Semiconductor structure and manufacturing method thereof
By introducing holes into the device isolation structure, the capacitance value is reduced to increase the critical voltage of the field device, thus solving the electrical problem caused by the opening of the gate and substrate doped regions and ensuring the normal operation of the semiconductor device.
Patent Information
- Application Number
- CN202411054748.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-07-19
- Filing Date
- 2024-08-02
- Publication Date
- 2026-01-23
AI Technical Summary
In semiconductor devices, the field elements formed by the gate on the device isolation structure and the doped regions in the substrate on both sides are easily turned on when a voltage is applied, affecting the normal electrical performance of the device.
Holes are introduced into the element isolation structure. The low dielectric constant of holes reduces the capacitance value, thereby increasing the critical voltage of the field element and preventing the field element from turning on.
By reducing the capacitance value and increasing the critical voltage of the field element, the component is ensured to maintain normal electrical performance during operation without being affected by the field element.
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Figure CN121398569A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present invention relates to a semiconductor structure and a method of manufacturing the same, and particularly to a semiconductor structure having a cavity in a device isolation structure and a method of manufacturing the same. BACKGROUND
[0002] In some semiconductor devices, a gate can be formed on a device isolation structure, and the gate and the doped regions in the substrate on both sides of the gate form a so-called field device. Thus, when the gate is applied with a voltage, the field device is turned on. As a result, the final formed device cannot have a normal electrical performance due to the turned-on field device. SUMMARY
[0003] The present invention provides a semiconductor structure and a method of manufacturing the same, wherein a cavity is formed in a device isolation structure.
[0004] The semiconductor structure of the present invention includes a substrate, a device isolation structure, and a gate. The device isolation structure is disposed in the substrate to define an active area. The gate is disposed on the device isolation structure. The device isolation structure includes a first portion and a second portion connected to each other. The first portion is located in the substrate. The second portion is located below the first portion. The width of the second portion is greater than the width of the first portion. The second portion includes a cavity therein. The cavity extends in the extension direction of the second portion.
[0005] In an embodiment of the semiconductor structure of the present invention, the top surface of the cavity is not higher than the top surface of the second portion, and the bottom surface of the cavity is higher than the bottom surface of the second portion.
[0006] In an embodiment of the semiconductor structure of the present invention, the second portion extends into the active area.
[0007] In an embodiment of the semiconductor structure of the present invention, a transistor is disposed in the substrate in the active area on both sides of the device isolation structure, wherein the transistors on both sides of the device isolation structure have the same conductivity type.
[0008] In an embodiment of the semiconductor structure of the present invention, the material of the device isolation structure includes silicon oxide.
[0009] In an embodiment of the semiconductor structure of the present invention, the width of the cavity in the extension direction of the second portion is greater than the thickness of the cavity.
[0010] The method for manufacturing a semiconductor structure includes the following steps. A substrate is provided. An element isolation structure is formed in the substrate to define an active region. A gate is formed on the element isolation structure. The element isolation structure includes a first portion and a second portion connected to each other. The first portion is located in the substrate. The second portion is located below the first portion. The second portion has a width greater than that of the first portion. A cavity is included in the second portion. The cavity extends in an extension direction of the second portion.
[0011] In one embodiment of the method for manufacturing a semiconductor structure, a top surface of the cavity is not higher than a top surface of the second portion, and a bottom surface of the cavity is higher than a bottom surface of the second portion.
[0012] In one embodiment of the method for manufacturing a semiconductor structure, the second portion extends into the active region.
[0013] In one embodiment of the method for manufacturing a semiconductor structure, the substrate at the active regions on opposite sides of the element isolation structure is also included, wherein the transistors located on opposite sides of the element isolation structure have the same conductivity type.
[0014] In one embodiment of the method for manufacturing a semiconductor structure, the method for forming the transistor and the gate includes the following steps. After the element isolation structure is formed, a gate insulating material layer is formed on the substrate in the active regions on opposite sides of the element isolation structure. A gate material layer is formed on the gate insulating material layer and the element isolation structure. The gate material layer and the gate insulating material layer are patterned to form the gate and a gate structure of the transistor. Doped regions are formed in the substrate on both sides of the gate structure of the transistor.
[0015] In one embodiment of the method for manufacturing a semiconductor structure, a width of the cavity in the extension direction of the second portion is greater than a thickness of the cavity.
[0016] Based on the above, in the method for manufacturing a semiconductor structure, the element isolation structure has a cavity, so that the element isolation structure can have a lower capacitance value, thereby improving the threshold voltage of the field element. In this way, the field element can be prevented from being turned on during the operation of the finally formed element, and the electrical performance of the finally formed element can be prevented from being affected. BRIEF DESCRIPTION OF DRAWINGS
[0017] Figures 1A-1E The figure is a cross-sectional schematic view of a manufacturing process of a semiconductor structure according to an embodiment of the present application.
[0018] SYMBOL DESCRIPTION
[0019] 10: semiconductor structure
[0020] 100: substrate
[0021] 102: hard mask layer
[0022] 104: insulating layer
[0023] 106: element isolation structure
[0024] 108: gate insulating material layer
[0025] 110: gate material layer
[0026] 112: doped region
[0027] 114: transistor
[0028] AA: active region
[0029] CA: hole
[0030] G1, G2: gate
[0031] GI: gate insulating layer
[0032] P1: first portion
[0033] P2: second portion
[0034] T: maximum thickness
[0035] TR: trench
[0036] TR1: first trench
[0037] TR2: second trench DETAILED DESCRIPTION
[0038] Embodiments are described below with reference to the accompanying drawings, but the embodiments provided are not intended to limit the scope of the present application. In addition, the drawings are merely intended to illustrate and not to limit the scope of the present application. For ease of understanding, the same elements will be identified by the same reference numerals in the following description.
[0039] The terms "comprise", "include", "have" and their conjugates, as used herein, are open-ended transitional phrases, terms, or words that encompass the items listed after these phrases, terms, or words and do not exclude additional items.
[0040] Figures 1A-1E A manufacturing flow cross-sectional schematic view of a semiconductor structure according to an embodiment of the present application.
[0041] First, refer to FIG. 1, which shows a manufacturing flow cross-sectional schematic view of a semiconductor structure according to an embodiment of the present application. Figure 1A, a substrate 100 is provided. In this embodiment, the substrate 100 is a silicon substrate. Thereafter, a hard mask layer 102 is formed on the substrate 100. The material of the hard mask layer 102 is, for example, silicon nitride, but the present application is not limited thereto.
[0042] Next, please refer to Figure 1B The hard mask layer 102 is subjected to a patterning process so that the hard mask layer 102 exposes a region where an element isolation structure is to be formed. In this embodiment, the element isolation structure to be formed is a shallow trench isolation (STI) structure. Thereafter, an etching process is performed to remove part of the substrate 100 to form a trench TR in the substrate 100, with the hard mask layer 102 as an etching mask. The trench TR formed defines an active area AA. The active area AA is a region where various semiconductor elements are to be formed on the substrate 100 in subsequent processes. In particular, in this embodiment, the active area AA can be a region where high-voltage elements are to be formed. Generally, high-voltage elements refer to elements with an operating voltage of 200 V or above, but the present application is not limited thereto.
[0043] In this embodiment, the trench TR formed includes a first trench TR1 and a second trench TR2. The second trench TR2 is formed below the first trench TR1 and communicates with the first trench TR1. In addition, the second trench TR2 extends below the first trench TR1 and into the active area AA. Thus, the width of the second trench TR2 is greater than that of the first trench TR1. Depending on actual needs, the first trench TR1 and the second trench TR2 can each have a desired depth, and the present application does not limit this. The trench TR can be formed in any known manner. For example, a TEL 88DD machine can be used to form the trench TR by adjusting the magnetic field, but the present application is not limited thereto.
[0044] In addition, in this embodiment, the profile of the trench TR is inverted T-shaped, but the present application is not limited thereto. In other embodiments, the profile of the trench TR can be trapezoidal with the top narrow and the bottom wide, i.e., the sidewall of the first trench TR1 and the sidewall of the second trench TR2 can be continuous.
[0045] Next, please refer to Figure 1C An insulating layer 104 is formed on the substrate 100 so that the insulating layer 104 covers the hard mask layer 102 and fills the trench TR. The material of the insulating layer 104 is silicon oxide. The insulating layer 104 can be formed, for example, by a chemical vapor deposition process. Thereafter, a chemical mechanical polishing (CMP) process can be performed to remove part of the insulating layer 104 until the top surface of the hard mask layer 102 is exposed, so that the top surface of the insulating layer 104 is coplanar with the top surface of the hard mask layer 102.
[0046] In the present embodiment, since the trench TR includes the first trench TR1 with a smaller width and the second trench TR2 with a larger width, and the first trench TR1 is located above the second trench TR2, the insulating layer 104 can easily fill the first trench TR1 and not fill the second trench TR2 in the process of filling the insulating layer 104. That is, after the insulating layer 104 is formed, a cavity CA can be formed inside the insulating layer 104 in the second trench TR2.
[0047] In addition, based on the characteristics of the chemical vapor deposition fabrication process itself and the profile of the second trench TR2, the formed cavity CA extends in the extension direction of the second trench TR2, so that the width of the cavity CA in the extension direction of the second trench TR2 is greater than the maximum thickness T of the cavity CA, the top surface of the cavity CA is not higher than the top surface of the second trench TR2, and the bottom surface of the cavity CA is higher than the bottom surface of the second trench TR2. That is, the cavity CA is embedded in the insulating layer 104 in the second trench TR2. In addition, by adjusting the parameters of the chemical vapor deposition fabrication process, the maximum thickness T of the formed cavity can be adjusted.
[0048] Next, referring to Figure 1D , the hard mask layer 102 is removed. After the hard mask layer 102 is removed, the insulating layer 104 outside the trench TR is removed to form the element isolation structure 106 of the present embodiment in the trench TR. At this time, the top surface of the element isolation structure 106 can be coplanar with the top surface of the substrate 100. The method of removing the insulating layer 104 outside the trench TR is, for example, to perform an etching-back fabrication process.
[0049] In the present embodiment, since the trench TR includes the first trench TR1 with a smaller width and the second trench TR2 with a larger width, and the first trench TR1 is located above the second trench TR2, the formed element isolation structure 106 corresponding to the profile of the trench TR can include a first portion P1 located in the first trench TR1 and a second portion P2 located in the second trench TR2, the first portion P1 and the second portion P2 are connected to each other, and the width of the second portion P2 is greater than the width of the first portion P1. The second portion P2 extends below the first portion P1 and extends into the active area AA. In addition, the cavity CA is embedded in the second portion P2 and extends in the extension direction of the second portion P2. The top surface of the cavity CA is not higher than the top surface of the second portion P2, and the bottom surface of the cavity CA is higher than the bottom surface of the second portion P2.
[0050] Then, a gate insulating material layer 108 is formed on the substrate 100 in the active areas AA. In this embodiment, the gate insulating material layer 108 is formed on the substrate 100 in the active areas AA on both sides of the element isolation structure 106. The material of the gate insulating material layer 108 is silicon oxide. The gate insulating material layer 108 is formed by, for example, an oxidation process. After the gate insulating material layer 108 is formed, a gate material layer 110 is formed on the substrate 100 so that the gate material layer 110 covers the gate insulating material layer 108 and the element isolation structure 106. The material of the gate material layer 110 is, for example, polysilicon.
[0051] In this embodiment, since the cavity CA is located in the second portion P2 of the element isolation structure 106, and the first portion PI of the element isolation structure 106 does not have a cavity, the gate material layer 110 can be effectively prevented from filling into the element isolation structure 106, which can affect the subsequent manufacturing process and the electrical properties of the final formed elements.
[0052] After that, please refer to Figure 1E The gate material layer 110 and the gate insulating material layer 108 are patterned to form a gate G1 on the element isolation structure 106, and a gate structure including a gate G2 and a gate insulating layer GI on the substrate 100 in the active areas AA on both sides of the element isolation structure 106. In this embodiment, the gate G1 is located only on the element isolation structure 106, but the present application is not limited thereto. In other embodiments, the gate G1 can extend into the active areas AA.
[0053] Then, a doped region 112 is formed in the substrate 100 on both sides of the gate structure. The gate G2, the gate insulating layer GI, and the doped region 112 constitute a transistor 114, in which the doped region 112 serves as a source / drain of the transistor 114. In this way, the semiconductor structure 10 of this embodiment is formed.
[0054] In the semiconductor structure 10 of this embodiment, the element isolation structure 106 is formed in the substrate 100, and the transistor 114 having the same conductivity type is formed on the substrate 100 in the active areas AA on both sides of the element isolation structure 106. In addition, the element isolation structure 106 and the gate G1 located thereon can constitute a field element known to those skilled in the art.
[0055] For the field element constituted by the element isolation structure 106 and the gate G1, the doped regions 112 having the same conductivity type are present in the substrate 100 on both sides of the field element, so that when the gate G1 is applied with a voltage, the field element can be turned on. In this way, the final formed element can be affected by the turned-on field element and cannot have a normal electrical property.
[0056] In this embodiment, since the second portion P2 of the element isolation structure 106 has the cavity CA and the air in the cavity CA is a low dielectric constant substance, the element isolation structure 106 has a lower capacitance value, thus increasing the threshold voltage (Vt) of the field element. Therefore, even if the gate G1 is applied with a voltage, since the field element has a higher threshold voltage, the field element will not be turned on, thus being able to avoid the electrical performance of the finally formed element being affected.
[0057] In addition, in this embodiment, by adjusting the maximum thickness of the cavity CA, the field element can be adjusted to have a required threshold voltage, so that the semiconductor structure 10 can be applied to various high-voltage elements.
[0058] For example, in a NOR type flash memory, since the word line extends across the element isolation structure, when a voltage is applied to the word line, the element isolation structure with the cavity embedded therein has a higher threshold voltage and can effectively avoid the field element between the bit line contact and the common source being turned on.
[0059] Although the present application has been disclosed in the above embodiments, it is not intended to limit the present application, and any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be defined by the appended claims.
Claims
1. A semiconductor structure, comprising: a substrate; a device isolation structure disposed in the substrate to define an active region; and a gate disposed on the device isolation structure, wherein: the device isolation structure comprises a first portion and a second portion connected to each other, the first portion is in the substrate, the second portion is below the first portion, the second portion has a width greater than a width of the first portion, the second portion includes a cavity therein, and the cavity extends in an extension direction of the second portion.
2. The semiconductor structure of claim 1, wherein a top surface of the cavity is not higher than a top surface of the second portion, and a bottom surface of the cavity is higher than a bottom surface of the second portion.
3. The semiconductor structure of claim 1, wherein the second portion extends into the active region.
4. The semiconductor structure of claim 1, further comprising transistors disposed in the substrate in the active region on opposite sides of the device isolation structure, wherein the transistors on opposite sides of the device isolation structure have a same conductivity type.
5. The semiconductor structure of claim 1, wherein a material of the device isolation structure comprises silicon oxide.
6. The semiconductor structure of claim 1, wherein a width of the cavity in the extension direction of the second portion is greater than a thickness of the cavity.
7. A method of fabricating a semiconductor structure, comprising: providing a substrate; forming a device isolation structure in the substrate to define an active region; and forming a gate on the device isolation structure, wherein: the device isolation structure comprises a first portion and a second portion connected to each other, the first portion is in the substrate, the second portion is below the first portion, the second portion has a width greater than a width of the first portion, the second portion includes a cavity therein, and the cavity extends in an extension direction of the second portion.
8. The method of fabricating a semiconductor structure of claim 7, wherein a top surface of the cavity is not higher than a top surface of the second portion, and a bottom surface of the cavity is higher than a bottom surface of the second portion.
9. The method of fabricating a semiconductor structure of claim 7, wherein the second portion extends into the active region.
10. The method of fabricating a semiconductor structure of claim 7, further comprising forming transistors in the substrate in the active region on opposite sides of the device isolation structure, wherein the transistors on opposite sides of the device isolation structure have a same conductivity type.
11. The method of fabricating a semiconductor structure of claim 10, wherein the forming of the transistors and the gate comprises: forming a gate insulating material layer on the substrate in the active region on opposite sides of the device isolation structure after the forming of the device isolation structure; forming a gate material layer on the gate insulating material layer and the device isolation structure; patterning the gate material layer and the gate insulating material layer to form the gate and gate structures of the transistors; and forming doped regions in the substrate on opposite sides of the gate structures of the transistors. 12. The method of manufacturing a semiconductor structure according to claim 7, wherein a width of the void in the extension direction of the second portion is greater than a thickness of the void.