Semiconductor packaging structure and electronic equipment

Abstract

The invention relates to a semiconductor packaging structure and electronic equipment, the semiconductor packaging structure comprises a substrate, a chip, a plugging structure and a heat conduction structure, the chip is arranged on the substrate, and the top wall, deviating from the substrate, of the chip is recessed downwards to form a heat exchange runner; the blocking structure is connected to the chip, and a cooling cavity communicating with the heat exchange runner is formed between the blocking structure and the chip; the heat-conducting structure is positioned in the cooling cavity and is in heat-conducting connection with the top wall of the chip; and the plugging structure is configured to enable a cooling medium to flow through the cooling cavity, the heat exchange runner and the heat conduction structure, so that the cooling medium exchanges heat with the chip. Through the above technical scheme, the semiconductor packaging structure provided by the invention can solve the problem that the heat dissipation effect on the chip is poor due to the fact that an existing packaging structure is limited by the arrangement form of multiple layers of heat transfer paths in the related technology, can meet the requirement for efficient cooling of the chip, and is beneficial to improving the performance and reliability of the chip.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor, and in particular, to a semiconductor packaging structure and an electronic device. BACKGROUND

[0002] In the related art, the demand for high-performance chips is also increasing, but as the performance of the chip improves, the power consumption of the chip also rises sharply. Due to the limitation of the arrangement form of the multi-layer heat transfer path, the existing packaging structure has the problem of poor heat dissipation effect of the chip, which affects the performance and reliability of the chip. SUMMARY

[0003] The purpose of the present disclosure is to provide a semiconductor packaging structure and an electronic device to improve the heat dissipation effect of the chip and improve the performance and reliability of the chip.

[0004] To achieve the above purpose, the first aspect of the present disclosure provides a semiconductor packaging structure, comprising: a substrate; a chip provided on the substrate, and a top wall of the chip facing away from the substrate is inwardly recessed to form a heat exchange flow channel; a blocking structure connected to the chip, and a cooling cavity communicated with the heat exchange flow channel is formed between the blocking structure and the chip; and a heat conduction structure located in the cooling cavity and heat-conductively connected to the top wall of the chip; wherein the blocking structure is configured to enable a cooling medium to flow through the cooling cavity, the heat exchange flow channel and the heat conduction structure, so that the cooling medium exchanges heat with the chip.

[0005] In some possible implementation manners, the heat exchange flow channel comprises a plurality of heat exchange flow channel segments arranged at intervals, and the heat conduction structure is arranged between any two adjacent heat exchange flow channel segments.

[0006] In some possible implementation manners, the heat conduction structure comprises a heat conduction protrusion connected to the top wall of the chip and extending towards a side facing away from the top wall; wherein a gap is formed between an end of the heat conduction protrusion facing away from the top wall of the chip and an inner wall of the blocking structure; and / or, an opening is arranged on the heat conduction protrusion.

[0007] In some possible implementation manners, the heat exchange flow channel comprises a plurality of heat exchange flow channel segments arranged at intervals along a first direction, and each heat exchange flow channel segment extends along a second direction perpendicular to the first direction; and / or, The heat-conducting structure comprises a plurality of heat-conducting protrusions arranged at intervals, the plurality of heat-conducting protrusions are arranged in a row along a first direction and / or arranged in a column along a second direction perpendicular to the first direction.

[0008] In some possible embodiments, a structural dimension of the heat exchange channel section along the first direction is 10 μm-20 μm; and / or, a structural dimension of the heat exchange channel section along the second direction is 10 mm-30 mm; and / or, a structural dimension of the heat exchange channel section along a third direction perpendicular to the plane in which the first direction and the second direction lie is 5 μm-200 μm.

[0009] In some possible embodiments, a structural dimension of the heat-conducting protrusion along the first direction is 10 μm-20 μm; and / or, a structural dimension of the heat-conducting protrusion along the second direction is 10 mm-30 mm; and / or, a structural dimension of the heat-conducting protrusion along a third direction perpendicular to the plane in which the first direction and the second direction lie is 100 μm-200 μm.

[0010] In some possible embodiments, the heat-conducting protrusion is configured in a cylindrical shape or a rectangular shape; and / or, a material of the heat-conducting protrusion is copper.

[0011] In some possible embodiments, a first structural layer is arranged on a top wall of the chip facing the heat-conducting structure, and the heat-conducting structure is connected to the chip through the first structural layer.

[0012] In some possible embodiments, a material of the first structural layer is titanium or titanium alloy.

[0013] In some possible embodiments, the blocking structure comprises a heat-dissipating cover and a second structural layer, the heat-dissipating cover is connected to the chip through the second structural layer, so that the heat-dissipating cover, the second structural layer, the heat-conducting structure and the chip jointly enclose the cooling cavity, and the heat-dissipating cover is provided with an inlet and an outlet communicating with the cooling cavity.

[0014] In some possible embodiments, the second structural layer is arranged between the heat-dissipating cover and the chip, and the second structural layer is arranged in a ring around an outer periphery of the chip, the heat-dissipating cover is provided with an inlet liquid flow channel and an outlet liquid flow channel, the inlet communicates with the cooling cavity through the inlet liquid flow channel, and the outlet communicates with the cooling cavity through the outlet liquid flow channel.

[0015] In some possible embodiments, the second structural layer is formed of sealant.

[0016] In some possible implementation manners, the material of the sealing glue is polydimethylsiloxane or epoxy-based negative photoresist.

[0017] In some possible implementation manners, the heat dissipation cover comprises a manifold plate and a cover plate arranged in a stacked manner along a third direction, and the cover plate is connected to the chip through the second structure layer, the cover plate is provided with a first fluid channel and a second fluid channel, the manifold plate is provided with the inlet, the outlet, a third fluid channel and a fourth fluid channel, the first fluid channel and the third fluid channel are arranged in communication to form the liquid inlet flow channel, and the second fluid channel and the fourth fluid channel are arranged in communication to form the liquid outlet flow channel.

[0018] In some possible implementation manners, the sealing structure further comprises a connecting structure, and the manifold plate and the cover plate are connected through the connecting structure.

[0019] In some possible implementation manners, the connecting structure comprises a first glue layer arranged between the manifold plate and the cover plate, the first glue layer is provided with a first channel communicating the first fluid channel and the third fluid channel, and a second channel communicating the second fluid channel and the fourth fluid channel; and / or, The connecting structure comprises a connecting bolt, and the manifold plate and the cover plate are threadedly connected through the connecting bolt.

[0020] In some possible implementation manners, the substrate is provided with an annular protrusion arranged around the chip, a second glue layer is arranged between the sealing structure and the annular protrusion, and the sealing structure is connected to the annular protrusion through the second glue layer.

[0021] In some possible implementation manners, the number of chips is one or more, and each chip is selected from one of a memory chip and a logic chip.

[0022] In some possible implementation manners, the semiconductor package structure further comprises an interposer arranged between the chip and the substrate, and the chip is connected to the substrate through the interposer.

[0023] The second aspect of the present disclosure provides an electronic device comprising the semiconductor package structure provided in the first aspect.

[0024] By the technical solution, the semiconductor packaging structure provided by the present disclosure is provided with the heat conduction structure connected to the chip in the cooling cavity formed between the blocking structure and the chip, and the heat exchange flow channel is directly formed on the top wall of the chip. Therefore, the heat exchange area between the cooling medium in the cooling cavity and the chip can be effectively increased by the heat exchange flow channel and the heat conduction structure. When the cooling medium flows through the cooling cavity, the heat exchange flow channel and the heat conduction structure, the chip can be efficiently cooled by the cooling medium, the heat dissipation effect of the cooling medium on the chip is effectively improved, the chip can be stably and high-performance operated at a safe temperature, and the chip performance and reliability are improved. In addition, the cooling medium is directly applied to the chip and the heat conduction structure connected to the top wall of the chip, which can effectively shorten the heat transfer path and improve the heat dissipation effect of the cooling medium on the chip. Therefore, the semiconductor packaging structure provided by the present disclosure can solve the problem of poor heat dissipation effect of the chip in the related art due to the limited arrangement form of the multi-layer heat transfer path of the existing packaging structure, and can efficiently cool the chip, which is beneficial to improve the chip performance and reliability.

[0025] Other features and advantages of the present disclosure will be described in detail in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0026] The accompanying drawings are included to provide a further understanding of the present disclosure and constitute a part of the specification, and are used together with the following specific embodiments to explain the present disclosure, but do not constitute a limitation on the present disclosure. In the drawings: Figure 1 is a schematic view of the semiconductor packaging structure provided in the exemplary embodiment of the present disclosure; Figure 2 is a schematic view of the semiconductor packaging structure provided in the exemplary embodiment of the present disclosure; Figure 1 is a cross-sectional view of the A-A position in the semiconductor packaging structure provided in the exemplary embodiment of the present disclosure; Figure 3 is a schematic view of the semiconductor packaging structure provided in the exemplary embodiment of the present disclosure; Figure 1 is a partial enlarged schematic view of the B position in the semiconductor packaging structure provided in the exemplary embodiment of the present disclosure; Figure 4 is a schematic view of the packaging structure provided in the related art.

[0027] BRIEF DESCRIPTION OF DRAWINGS 1 - substrate; 2 - chip; 210 - memory chip; 220 - logic chip; 3 - heat exchange channel; 310 - heat exchange channel section; 4 - blocking structure; 410 - heat dissipation cover; 411 - inlet; 412 - outlet; 413 - manifold plate; 414 - cover plate; 420 - second structure layer; 430 - first fluid cavity; 440 - second fluid cavity; 450 - third fluid cavity; 460 - fourth fluid cavity; 470 - connecting structure; 471 - first adhesive layer; 472 - first cavity; 473 - second cavity; 474 - connecting bolt; 5 - cooling cavity; 6 - heat conduction structure; 610 - heat conduction protrusion; 7 - gap; 8 - notch; 9 - first structure layer; 10 - annular protrusion; 11 - second adhesive layer; 12 - interlayer; 13 - underfill adhesive; 14 - heat conduction layer; 15 - liquid cooling plate. DETAILED DESCRIPTION

[0028] The specific embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely intended to illustrate and explain the present disclosure, and are not intended to limit the present disclosure.

[0029] In the present disclosure, the orientation words such as "upper" and "lower" generally refer to the upper and lower positions in the space of the semiconductor packaging structure when it is in use, unless otherwise specified. "Inner" and "outer" refer to the inner and outer positions relative to the outline of the component or structure itself. In addition, it should be noted that the terms such as "first", "second" and the like are used to distinguish one element from another element, and do not have sequential and important meanings. In addition, in the description with reference to the drawings, the same reference signs in different drawings represent the same elements.

[0030] In the related art, as shown in Figure 4 the chip 2 is thermally connected with the liquid cooling plate 15 through the heat conduction layer 14, so that the chip 2 can be indirectly cooled by the cooling medium in the liquid cooling plate 15. However, in this arrangement, the heat exchange between the chip 2 and the liquid cooling plate 15 needs to rely on, for example, a thermal interface material (TIM) at the heat conduction layer 14. As a result, due to the arrangement of the multi-layer heat transfer path of the overall packaging structure, the thermal interface resistance at the thermal interface material and other interfaces is significantly increased, resulting in poor heat dissipation effect of the chip 2, which leads to unprecedentedly high heat flux density in the chip 2, which is not conducive to the stable and high-performance operation of the chip 2 at a safe temperature, and affects the performance and reliability of the chip 2.

[0031] Therefore, according to a first aspect of the present disclosure, a semiconductor packaging structure is provided, as shown in Figures 1 to 3As shown, the semiconductor packaging structure includes a substrate 1, a chip 2, a blocking structure 4, and a heat conduction structure 6. The chip 2 is arranged on the substrate 1, and a heat exchange flow channel 3 is formed in the top wall of the chip 2 away from the substrate 1. The blocking structure 4 is connected to the chip 2, and a cooling cavity 5 is formed between the blocking structure 4 and the chip 2, which is communicated with the heat exchange flow channel 3. The heat conduction structure 6 is located in the cooling cavity 5 and is heat-conductively connected to the top wall of the chip 2. The blocking structure 4 is configured to enable the cooling medium to flow through the cooling cavity 5, the heat exchange flow channel 3, and the heat conduction structure 6, so that the cooling medium exchanges heat with the chip 2.

[0032] Through the above technical solution, that is, the semiconductor packaging structure provided by the present disclosure, the heat conduction structure 6 heat-conductively connected to the chip 2 is arranged in the cooling cavity 5 formed between the blocking structure 4 and the chip 2, and the heat exchange flow channel 3 is directly formed on the top wall of the chip 2. Therefore, the heat exchange area between the cooling medium in the cooling cavity 5 and the chip 2 can be effectively increased through the arrangement of the heat exchange flow channel 3 and the heat conduction structure 6. When the cooling medium flows through the cooling cavity 5, the heat exchange flow channel 3, and the heat conduction structure 6, the chip 2 can be efficiently cooled by the cooling medium. The heat dissipation effect of the cooling medium on the chip 2 is effectively improved, and the chip 2 can stably and efficiently operate at a safe temperature, which is beneficial to improving the performance and reliability of the chip 2.

[0033] In addition, since the cooling medium directly acts on the chip 2 and the heat conduction structure 6 heat-conductively connected to the top wall of the chip 2, the heat transfer path can be effectively shortened, and the heat dissipation effect of the cooling medium on the chip 2 can be improved. Therefore, the semiconductor packaging structure provided by the present disclosure can solve the problem of poor heat dissipation effect of the chip in the related art due to the limitation of the arrangement form of the multi-layer heat transfer path of the existing packaging structure, and can efficiently cool the chip, which is beneficial to improving the performance and reliability of the chip.

[0034] It should be noted that the above-mentioned cooling medium can include but is not limited to, for example, deionized water. Since the deionized water has weak conductivity and weak corrosion, it can safely and efficiently cool the chip 2. The present disclosure is not limited thereto, for example, the above-mentioned cooling medium can also include electronic fluorination liquid and other cooling liquids with weak conductivity and weak corrosion. The purpose is to enable the cooling medium to safely and efficiently cool the chip 2, and the person skilled in the art can adaptively design according to the actual application requirements.

[0035] In some possible implementation manners, reference can be made to Figures 1 to 3As shown, the heat exchange flow channel 3 can include a plurality of heat exchange flow channel segments 310 arranged at intervals, and a heat conduction structure 6 is arranged between two adjacent heat exchange flow channel segments 310. In this way, the heat exchange area between the cooling medium in the cooling cavity 5 and the chip 2 can be effectively increased. When the cooling medium flows through the cooling cavity 5, the heat exchange flow channel 3, and the heat conduction structure 6, the chip 2 can be efficiently cooled by the cooling medium, and the heat dissipation effect of the cooling medium on the chip 2 is effectively improved.

[0036] For example, in some possible implementation manners, the heat exchange flow channel 3 can be arranged on the top wall of the chip 2, and the heat exchange flow channel 3 can be arranged on the top wall of the chip 2 in a manner of directly penetrating through the top wall of the chip 2. Figures 1 to 3 As shown, the heat conduction structure 6 can include a heat conduction protrusion 610 connected to the top wall of the chip 2 and extending away from the side where the top wall is located. In this way, the heat generated by the chip 2 can be transferred to the heat conduction protrusion 610, and the cooling medium in the cooling cavity 5 can directly act on the heat conduction protrusion 610, so that the heat can be taken away, thereby achieving the purpose of cooling the chip 2. In combination with the heat exchange flow channel 3 directly formed on the top wall of the chip 2, the chip 2 can be efficiently cooled by the cooling medium, which helps to ensure that the chip 2 operates stably and with high performance at a safe temperature, and achieves the purpose of improving the performance and reliability of the chip 2.

[0037] It should be noted that, by connecting the heat conduction protrusion 610 to the top wall of the chip 2 away from the substrate 1, the heat exchange area between the cooling medium in the cooling cavity 5 and the chip 2 can be increased, and the total heat exchange efficiency can be improved. For example, in some possible implementation manners, the heat conduction protrusion 610 can extend away from the side where the top wall of the chip 2 is located and abut against the inner wall surface of the sealing structure 4 (for example, the inner wall surface of the heat dissipation cover 410 away from the chip 2). In this way, the heat exchange area between the cooling medium in the cooling cavity 5 and the chip 2 can be increased, and the heat dissipation effect of the chip 2 can be improved.

[0038] In addition, in some implementation manners, the heat conduction protrusion 610 can be arranged on the top wall of the chip 2. Figures 1 to 3 As shown, the heat conduction protrusion 610 can be provided with an opening 8, for example, the heat conduction protrusion 610 can be provided with an opening 8 on the top wall of the sealing structure 4, and the heat conduction protrusion 610 can also be provided with an opening 8 on the side wall. In this way, the cooling medium in the cooling cavity 5 can flow through the plurality of heat conduction protrusions 610 through the opening 8, which helps to improve the heat dissipation efficiency.

[0039] It can be understood that the specific embodiment that the heat-conducting protrusions 610 extend towards the side away from the top wall of the chip 2 and abut against the inner wall surface of the blocking structure 4 (for example, the inner wall surface of the heat dissipation cover 410 towards the chip 2) is exemplary, for example, in another alternative embodiment, the end of the heat-conducting protrusions 610 away from the top wall of the chip 2 can also have a gap 7 with the inner wall of the blocking structure 4, and the present disclosure does not specifically limit such a transformed mode, and a person skilled in the art can adaptively design according to the actual application requirements, and the purpose is to be able to improve the heat dissipation effect of the chip 2.

[0040] In addition, the plurality of heat-conducting protrusions 610 can be arranged in rows and spaced apart along the first direction, and / or arranged in columns and spaced apart along the second direction perpendicular to the first direction. In this way, by arranging the plurality of heat-conducting protrusions 610, a higher heat exchange area between the cooling medium in the cooling cavity 5 and the chip 2 can be ensured, which is beneficial to improve the heat dissipation effect of the chip 2. In addition, when the number of heat-conducting protrusions 610 is arranged to be multiple, the gap between the adjacent two heat-conducting protrusions 610 can also be realized so that the cooling medium flows through the plurality of heat-conducting protrusions 610, achieving the purpose of efficiently cooling the chip 2 by the cooling medium.

[0041] Wherein, the interval between any two adjacent heat-conducting protrusions 610 is not specifically limited by the present disclosure, and a person skilled in the art can adaptively design according to the actual application requirements, for example, the interval between the adjacent two heat-conducting protrusions 610 can be 1.5 times the thickness dimension of the heat-conducting protrusions 610 along the first direction or the second direction. In addition, the plurality of heat-conducting protrusions 610 can be arranged in an array, that is, the plurality of heat-conducting protrusions 610 can be arranged at equal intervals, or alternatively, the plurality of heat-conducting protrusions 610 can also be arranged at unequal intervals, for example, the heat-conducting protrusions 610 at the area with higher heat on the chip 2 can be arranged more densely (that is, the interval between the adjacent two heat-conducting protrusions 610 is smaller), and the heat-conducting protrusions 610 at the remaining area with lower heat on the chip 2 can be arranged more sparsely (that is, the interval between the adjacent two heat-conducting protrusions 610 is larger), and the present disclosure does not specifically limit this.

[0042] In addition, the specific shape structure, arrangement number, arrangement position and structure size of the heat-conducting protrusions 610 are not specifically limited by the present disclosure, and a person skilled in the art can adaptively design according to the actual application requirements, and the purpose is to be able to ensure that the cooling medium in the cooling cavity 5 has a higher heat exchange contact area with the heat-conducting protrusions 610, so as to achieve the purpose of quickly cooling the chip 2.

[0043] In addition, the specific shape and size of the plurality of heat-conducting protrusions 610 can be the same, so as to facilitate on-site processing and preparation. It can be understood that the specific shape and size of the plurality of heat-conducting protrusions 610 can also be adaptively configured to be different according to actual application requirements, for example, the shape and size of the heat-conducting protrusions 610 at the region with higher heat on the chip 2 can be configured to be larger than the heat-conducting protrusions 610 at the remaining region of the chip 2, so as to ensure a higher heat dissipation effect on the chip 2, and the present disclosure does not make a specific limitation in this regard.

[0044] Exemplarily, in some embodiments, with reference to Figures 1 to 3 , the structure size of the heat-conducting protrusions 610 along the first direction (which can refer to the left-right direction of the figure in Figure 1 ) can be 10 μm-20 μm, for example, the structure size of the heat-conducting protrusions 610 along the first direction (which can refer to the left-right direction of the figure in Figure 1 ) can be 10 μm, 13 μm, 15 μm, 18 μm, 20 μm, etc. The present disclosure is not limited thereto.

[0045] In addition, in some embodiments, with reference to Figures 1 to 3 , the structure size of the heat-conducting protrusions 610 along the second direction (which can refer to the direction perpendicular to Figure 1 the figure) can be 10 mm-30 mm, for example, the structure size of the heat-conducting protrusions 610 along the second direction (which can refer to the direction perpendicular to Figure 1 the figure) can be 10 mm, 15 mm, 20 mm, 25 mm, 30 mm, etc. The present disclosure is not limited thereto.

[0046] In addition, in some embodiments, with reference to Figures 1 to 3 , the structure size of the heat-conducting protrusions 610 along the third direction (which can refer to the up-down direction of the figure in Figure 1 ) perpendicular to the first direction and the second direction can be 100 μm-200 μm, for example, the structure size of the heat-conducting protrusions 610 along the third direction (which can refer to the up-down direction of the figure in Figure 1 ) perpendicular to the first direction and the second direction can be 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 170 μm, 180 μm, 190 μm, 200 μm, etc. The present disclosure is not limited thereto.

[0047] In some possible embodiments, with reference to Figures 1 to 3As shown, the specific shape of the heat-conducting protrusions 610 can be configured, for example, in a rectangular shape, so as to ensure a high heat exchange contact area between the cooling medium in the cooling cavity 5 and the heat-conducting protrusions 610, so as to achieve the purpose of rapidly cooling the chip 2, and has the advantages of simple overall structure and easy processing and preparation.

[0048] Alternatively, in other alternative embodiments, the specific shape of the heat-conducting protrusions 610 can also be configured, for example, in a cylindrical shape or other shapes, which are not specifically limited in the present disclosure, and can be designed by those skilled in the art according to actual application requirements. The purpose is to ensure a high heat exchange contact area between the cooling medium in the cooling cavity 5 and the heat-conducting protrusions 610, so as to achieve the purpose of rapidly cooling the chip 2.

[0049] In order to ensure that the heat-conducting protrusions 610 have high heat conduction performance, so as to rapidly transfer the heat generated at the chip 2 to the heat-conducting protrusions 610 and rapidly remove the heat through the cooling medium, in some possible embodiments, the material of the heat-conducting protrusions 610 can be copper. In this arrangement, the heat-conducting protrusions 610 can have high heat conduction performance, so as to rapidly transfer the heat generated at the chip 2 to the heat-conducting protrusions 610 and rapidly remove the heat through the cooling medium, which is beneficial to improve the cooling effect of the chip 2. In addition, the heat-conducting protrusions 610 prepared by using copper are also easy to process and have high reliability.

[0050] It can be understood that, in other alternative embodiments, the material of the heat-conducting protrusions 610 can also be a material having heat conduction performance, such as aluminum or aluminum alloy, which is not specifically limited in the present disclosure. Those skilled in the art can design it according to actual application requirements. The purpose is to enable the heat generated at the chip 2 to be transferred to the heat-conducting protrusions 610 and directly act on the heat-conducting protrusions 610 through the cooling medium in the cooling cavity 5, so as to remove the heat, thereby achieving the purpose of cooling the chip 2.

[0051] In some possible embodiments, referring to Figure 1 As shown, the chip 2 can be provided with a first structure layer 9 facing the top wall of the heat-conducting structure 6. The heat-conducting structure 6 is connected to the chip 2 through the first structure layer 9. In this arrangement, the heat-conducting protrusions 610 can be stably connected to the chip 2, which is easy to process and has high reliability, and is beneficial to ensure efficient and stable cooling of the chip 2, which is helpful to improve the performance and reliability of the chip 2.

[0052] Exemplarily, the first structure layer 9 can be, for example, a coating structure coated on the top wall of the chip 2, or alternatively, the first structure layer 9 can also be, for example, a connecting film structure arranged on the top wall of the chip 2, and the present disclosure does not make specific limitations thereon, and those skilled in the art can adaptively design according to actual application requirements.

[0053] It should be noted that the present disclosure does not make specific limitations on the thickness dimension of the first structure layer 9 along the third direction (which can refer to the up-down direction of the plane of FIG. 6), and those skilled in the art can adaptively design according to actual application requirements, and the purpose is to be able to ensure that the heat-conducting protrusion 610 can be stably connected to the chip 2, and at the same time, it is also possible to quickly transfer the heat generated at the chip 2 to the heat-conducting protrusion 610 and quickly take away the heat through the cooling medium. Figure 1

[0054] In addition, the specific preparation process of the first structure layer 9 configured as, for example, a coating structure coated on the top wall of the chip 2 or a connecting film structure arranged on the top wall of the chip 2 can be adaptively designed with reference to the existing processing and preparation process, and the present disclosure does not make too much redundant description thereon.

[0055] In addition, since the cooling medium can be directly exchanged with the heat-conducting protrusion 610 arranged in the cooling cavity 5 after flowing through the cooling cavity 5, and since the thickness dimension of the first structure layer 9 is thinner than the thickness of the heat-conducting layer 14 and the plate body of the liquid cooling plate 15 in the related art, compared with the cooling mode of the multi-layer heat transfer path in the related art, the present disclosure can effectively shorten the heat transfer path, and achieve the purpose of improving the heat dissipation effect of the cooling medium on the chip 2.

[0056] In some possible implementations, the material of the first structure layer 9 can adopt titanium, and such arrangement can make the first structure layer 9 prepared from titanium arranged on the chip 2, so as to facilitate the subsequent electroplating of the heat-conducting protrusion 610 on the chip 2, to ensure that the heat-conducting protrusion 610 can be stably connected to the chip 2, and at the same time, it is also possible to quickly transfer the heat generated at the chip 2 to the heat-conducting protrusion 610 and quickly take away the heat through the cooling medium, to achieve the purpose of efficiently and stably cooling the chip 2.

[0057] It can be understood that in other alternative implementations, the material of the first structure layer 9 can also adopt, for example, titanium alloy, and the present disclosure does not make specific limitations thereon, and those skilled in the art can adaptively design according to actual application requirements, and the purpose is to be able to ensure that the heat-conducting protrusion 610 can be stably connected to the chip 2, and at the same time, it is also possible to efficiently and stably cool the chip 2.

[0058] ​It should be noted that, for example, when both heat exchange channels 3 and thermally conductive bumps 610 are provided on chip 2, the aforementioned first structural layer 9 can be provided on chip 2 in advance, and then the aforementioned heat exchange channels 3 and thermally conductive bumps 610 can be provided on chip 2 to facilitate on-site processing and fabrication.

[0059] The heat exchange channel section 310 can be adaptively designed according to actual application requirements. For example, in some possible implementations, refer to... Figures 1 to 3 As shown, the number of heat exchange channel sections 310 can be multiple, and they are along the first direction (refer to...). Figure 1 The heat exchanger channels 310 are arranged at intervals along the left and right directions of the central image, and each heat exchanger channel section 310 is along a second direction perpendicular to the first direction (refer to the direction perpendicular to the first direction). Figure 1 The arrangement extends in the direction shown in the figure. This arrangement helps to ensure a high heat exchange area between the cooling medium in the cooling cavity 5 and the chip 2, while the overall structure is also relatively simple and easy to process and prepare the heat exchange channel section 310 on site.

[0060] It should be noted that the specific shape, structure and dimensions of each heat exchange channel section 310 are not specifically limited in this disclosure. Those skilled in the art can design them adaptively according to actual application needs. The purpose is to ensure that there is a high heat exchange area between the cooling medium in the cooling cavity 5 and the chip 2.

[0061] In addition, the specific shape and size of each heat exchange channel section 310 can be the same to facilitate on-site processing and fabrication. It is understood that those skilled in the art can also adapt the specific shape and size of each heat exchange channel section 310 to be different according to actual application needs. For example, the shape and size of some heat exchange channel sections 310 in the high heat area of ​​the chip 2 can be made larger than those of some heat exchange channel sections 310 in the remaining area of ​​the chip 2, so as to ensure a higher heat dissipation effect on the chip 2. This disclosure does not make specific limitations in this regard.

[0062] Exemplarily, in some implementations, reference is made to Figures 1 to 3 As shown, the heat exchange channel section 310 is along the first direction (refer to...). Figure 1 The structural dimensions (in the left-right direction of the middle image) can be 10μm-20μm. For example, the heat exchange channel section 310 along the first direction (refer to...) Figure 1 The structural dimensions (in the left-right direction of the middle image) can be 10μm, 13μm, 15μm, 18μm, 20μm, etc. This disclosure is not limited thereto.

[0063] Additionally, in some implementations, references Figures 1 to 3 As shown, the heat exchange channel section 310 is along the second direction (which can be referenced as perpendicular to the direction of the second direction).Figure 1 The structural size of the heat exchange flow channel segment 310 along the third direction (may refer to the up-down direction of the figure plane) can be 5 pm-200 pm, for example, the structural size of the heat exchange flow channel segment 310 along the third direction (may refer to the up-down direction of the figure plane) can be 5 pm, 20 pm, 50 pm, 80 pm, 100 pm, 120 pm, 150 pm, 180 pm, 200 pm, etc. The present disclosure is not limited thereto. Figure 1 The structural size of the heat exchange flow channel segment 310 along the third direction (may refer to the up-down direction of the figure plane) can be 5 pm-200 pm, for example, the structural size of the heat exchange flow channel segment 310 along the third direction (may refer to the up-down direction of the figure plane) can be 5 pm, 20 pm, 50 pm, 80 pm, 100 pm, 120 pm, 150 pm, 180 pm, 200 pm, etc. The present disclosure is not limited thereto.

[0064] In addition, in some embodiments, referring to FIG. 3, the specific shape structure of each heat exchange flow channel segment 310 can be designed to be, for example, a rectangular groove, and the overall structure is simple and easy to process and manufacture. It can be understood that the specific shape structure of each heat exchange flow channel segment 310 can also be designed to be, for example, a “V”-shaped groove or a semicircular groove, and the present disclosure does not make specific limitations thereto, and those skilled in the art can adaptively design according to the actual application requirements. Figures 1 to 3 Figure 1 The structural size of the heat exchange flow channel segment 310 along the third direction (may refer to the up-down direction of the figure plane) can be 5 pm-200 pm, for example, the structural size of the heat exchange flow channel segment 310 along the third direction (may refer to the up-down direction of the figure plane) can be 5 pm, 20 pm, 50 pm, 80 pm, 100 pm, 120 pm, 150 pm, 180 pm, 200 pm, etc. The present disclosure is not limited thereto. Figure 1 The structural size of the heat exchange flow channel segment 310 along the third direction (may refer to the up-down direction of the figure plane) can be 5 pm-200 pm, for example, the structural size of the heat exchange flow channel segment 310 along the third direction (may refer to the up-down direction of the figure plane) can be 5 pm, 20 pm, 50 pm, 80 pm, 100 pm, 120 pm, 150 pm, 180 pm, 200 pm, etc. The present disclosure is not limited thereto.

[0065] It should be noted that the specific structural size of the heat exchange flow channel segment 310 formed on the chip 2 can also be adaptively designed according to different types of chips 2, for example, when the number of chips 2 is multiple and includes a storage chip 210 and a logic chip 220, the specific structural size of the corresponding heat exchange flow channel segment 310 on the storage chip 210 and the logic chip 220 can be adaptively designed according to the actual application requirements of different chips 2, and the present disclosure does not make too much repetition here.

[0066] In addition, in some embodiments, referring to FIG. 3, the specific shape structure of each heat exchange flow channel segment 310 can be designed to be, for example, a rectangular groove, and the overall structure is simple and easy to process and manufacture. It can be understood that the specific shape structure of each heat exchange flow channel segment 310 can also be designed to be, for example, a “V”-shaped groove or a semicircular groove, and the present disclosure does not make specific limitations thereto, and those skilled in the art can adaptively design according to the actual application requirements. Figure 1 In addition, each heat exchange flow channel segment 310 can be processed and manufactured by, for example, any suitable etching or laser micromachining process in the art, and the present disclosure does not make too much repetition here.

[0067]

[0068] ​​Optionally, in some embodiments, the plurality of heat exchange channel segments 310 arranged at intervals along the first direction can be arranged at equal intervals. Such an arrangement can improve the uniformity of heat dissipation of the cooling medium to the chip 2 within the cooling cavity 5, ensuring a higher heat dissipation effect. Alternatively, the plurality of heat exchange channel segments 310 arranged at intervals along the first direction can also be arranged at unequal intervals. For example, some heat exchange channel segments 310 in the areas with higher heat on the chip 2 can be arranged more densely (i.e., the distance between two adjacent heat exchange channel segments 310 is smaller), while some heat exchange channel segments 310 in the remaining areas with lower heat on the chip 2 can be arranged more dispersedly (i.e., the distance between two adjacent heat exchange channel segments 310 is larger). This disclosure does not specifically limit this arrangement.

[0069] Additionally, it should be noted that the specific embodiment in which the heat exchange channel 3 includes a plurality of heat exchange channel segments 310 arranged at intervals along the first direction, and each heat exchange channel segment 310 extends along the second direction, is exemplary. In other alternative embodiments not shown, the heat exchange channel 3 may also be constructed as, for example, multiple branch channel segments formed on the top wall of the chip 2 and arranged in a "well" shape. This disclosure is not limited to this. The purpose is to ensure that the cooling medium located in the cooling cavity 5 and the chip 2 have a high heat exchange area through the arrangement of the heat exchange channel 3. Those skilled in the art can design it adaptively according to actual application requirements.

[0070] In some possible implementations, refer to Figure 1 As shown, the sealing structure 4 may include a heat dissipation cover 410 and a second structural layer 420. The heat dissipation cover 410 is connected to the chip 2 through the second structural layer 420, so that the heat dissipation cover 410, the second structural layer 420, the heat-conducting structure 6, and the chip 2 together form a cooling cavity 5. The heat dissipation cover 410 is provided with an inlet 411 and an outlet 412 communicating with the cooling cavity 5. This arrangement facilitates the replenishment and discharge of cooling medium, for example, within the cooling cavity 5. For example, the inlet 411 and outlet 412 of the heat dissipation cover 410 may be connected to a cooling medium supply device (not shown), thereby achieving the purpose of replenishing and discharging cooling medium within the cooling cavity 5. The cooling medium supply device (not shown) can be adaptively designed with reference to any suitable cooling medium supply device in the art, and will not be described in detail here.

[0071] Additionally, in some possible implementations, refer to Figure 1As shown, the second structural layer 420 is arranged between the heat dissipation cover 410 and the chip 2, and the second structural layer 420 is arranged in a ring around the outer periphery of the chip 2. The heat dissipation cover 410 is provided with an inlet flow channel and an outlet flow channel. The inlet 411 is connected to the cooling cavity 5 through the inlet flow channel, and the outlet 412 is connected to the cooling cavity 5 through the outlet flow channel. In this way, the inlet and outlet of the cooling medium in the cooling cavity 5 are facilitated by the arrangement of the inlet flow channel and the outlet flow channel. Since the second structural layer 420 is arranged in a ring around the outer periphery of the chip 2, the cooling cavity 5 formed between the heat dissipation cover 410, the second structural layer 420, the heat-conducting protrusion 610, and the chip 2 has high sealing and reliability, which is conducive to ensuring that the cooling medium in the cooling cavity 5 can efficiently and stably cool the chip 2.

[0072] In addition, in some possible embodiments, the second structural layer 420 can be formed of sealing glue. In this way, since the sealing glue can be compressed and stretched, the influence of warping during packaging of the chip 2 can be covered, which not only improves the overall reliability of the packaging structure, but also ensures that the heat dissipation cover 410 is stably connected to the chip 2 and that the cooling cavity 5 has high sealing, thereby achieving efficient and stable cooling of the chip 2.

[0073] The sealing glue can be adaptively designed according to actual application requirements. For example, in some possible embodiments, the material of the sealing glue can be polydimethylsiloxane (PDMS) or epoxy-based negative photoresist (SU-8). In this way, the heat dissipation cover 410 can be stably connected to the chip 2 while ensuring that the cooling cavity 5 has high sealing, thereby achieving the purpose of stable and efficient cooling of the chip 2. The present disclosure is not limited thereto.

[0074] In addition, the thickness of the sealing glue along the first direction or the second direction can be not less than 500 μm, and the height of the sealing glue along the third direction can be, for example, 250 μm-300 μm, so as to ensure that the sealing glue has high structural strength while improving the overall reliability of the packaging structure.

[0075] The heat dissipation cover 410 can be adaptively designed according to actual application requirements. For example, in some possible embodiments, referring to FIG. 4A, Figure 1 As shown, the heat dissipation cover 410 can include a third direction (which can be referred to as the height direction of the heat dissipation cover 410) along the third direction (which can be referred to as the height direction of the heat dissipation cover 410). Figure 1The manifold plate 413 and the cover plate 414 are arranged in a stacked manner in the up-down direction of the middle plane, and the cover plate 414 is connected to the chip 2 through the second structure layer 420, the cover plate 414 is provided with a first fluid cavity 430 and a second fluid cavity 440, the manifold plate 413 is provided with an inlet 411, an outlet 412, a third fluid cavity 450, and a fourth fluid cavity 460, the first fluid cavity 430 and the third fluid cavity 450 are arranged in communication to form a liquid inlet flow channel, and the second fluid cavity 440 and the fourth fluid cavity 460 are arranged in communication to form a liquid outlet flow channel, that is, the inlet 411 is in communication with the cooling cavity 5 through the first fluid cavity 430 and the third fluid cavity 450 arranged in communication, and the outlet 412 is in communication with the cooling cavity 5 through the second fluid cavity 440 and the fourth fluid cavity 460 arranged in communication, so as to facilitate the replenishment and discharge of the cooling medium in the cooling cavity 5, and since the heat dissipation cover 410 is configured to include the manifold plate 413 and the cover plate 414 arranged in a stacked manner, and the fluid cavities arranged in communication are machined on the manifold plate 413 and the cover plate 414 respectively, the overall structure of the heat dissipation cover 410 can be simplified, the complexity of the heat dissipation cover 410 is reduced, and the machining and preparation of the heat dissipation cover 410 (such as the manifold plate 413 and the cover plate 414) on site is facilitated.

[0076] In the present disclosure, the specific arrangement of the fluid cavities (such as the first fluid cavity 430, the second fluid cavity 440, the third fluid cavity 450, and the fourth fluid cavity 460) on the manifold plate 413 and the cover plate 414 is not specifically limited, and those skilled in the art can adaptively design according to the actual application requirements, and the purpose is to facilitate the replenishment and discharge of the cooling medium in the cooling cavity 5.

[0077] In addition, in order to ensure that the manifold plate 413 and the cover plate 414 have high connection reliability, in some possible embodiments, referring to FIG. 4B, Figure 1 As shown, the sealing structure 4 can also include a connecting structure 470, and the manifold plate 413 and the cover plate 414 are connected through the connecting structure 470, so that the manifold plate 413 and the cover plate 414 are stably connected through the connecting structure 470, and the reliability is high, and the assembly and connection operation of the manifold plate 413 and the cover plate 414 on site is facilitated.

[0078] The connecting structure 470 can be arranged in any suitable manner, for example, in some possible embodiments, referring to FIG. 4B, Figures 1 to 3As shown, the connecting structure 470 can include a first glue layer 471 arranged between the manifold plate 413 and the cover plate 414, the first glue layer 471 is provided with a first cavity 472 communicating the first fluid cavity 430 and the third fluid cavity 450, and a second cavity 473 communicating the second fluid cavity 440 and the fourth fluid cavity 460, in this way, through the arrangement of the first glue layer 471, the stable connection between the manifold plate 413 and the cover plate 414 can be realized, and at the same time, the higher sealing between the first fluid cavity 430 and the third fluid cavity 450 arranged in communication through the first cavity 472, and the second fluid cavity 440 and the fourth fluid cavity 460 arranged in communication through the second cavity 473 can be ensured, the risk of cooling medium leakage is reduced, and the cooling medium in the cooling cavity 5 is conveniently replenished and discharged.

[0079] Alternatively, in some embodiments, with reference to Figure 2 As shown, the connecting structure 470 can also include a connecting bolt 474, the manifold plate 413 and the cover plate 414 are threadedly connected through the connecting bolt 474, in this way, the stable connection between the manifold plate 413 and the cover plate 414 can be achieved, and the overall structure is simple and convenient for on-site assembly operation.

[0080] It should be noted that the above-mentioned connecting structure 470 can be configured to include only the above-mentioned first glue layer 471, or alternatively, the above-mentioned connecting structure 470 can also be configured to include only the above-mentioned connecting bolt 474, or alternatively, the above-mentioned connecting structure 470 can also include the above-mentioned first glue layer 471 and the connecting bolt 474, the present disclosure does not make specific limitations on such modification methods, and those skilled in the art can adaptively design according to the actual application requirements, the purpose is to be able to realize the stable connection and fixation between the manifold plate 413 and the cover plate 414.

[0081] In addition, the present disclosure does not make specific limitations on the specific structures of the above-mentioned first glue layer 471 and the connecting bolt 474, for example, the above-mentioned first glue layer 471 can be formed by, for example, any suitable sealant or structural adhesive in the art, and the purpose is to be able to ensure that the manifold plate 413 and the cover plate 414 are stably connected through the first glue layer 471, in addition, the above-mentioned connecting bolt 474 can be adaptively designed by, for example, any suitable bolt structure in the art, and the purpose is to be able to ensure that the manifold plate 413 and the cover plate 414 are stably connected through the connecting bolt 474. The present disclosure is not limited thereto.

[0082] In addition, it should be noted that the specific embodiment that the heat dissipation cover 410 can include the manifold plate 413 and the cover plate 414 arranged in the third direction in layers is exemplary, for example, in another alternative embodiment not shown, the heat dissipation cover 410 can also be configured as, for example, a whole cover plate structure not shown, and the whole cover plate structure can jointly enclose the cooling cavity 5 with the second structure layer 420 and the chip 2, and the whole cover plate structure can also be respectively provided with the inlet 411, the outlet 412, the fluid cavity (liquid inlet flow channel) for enabling the inlet 411 to communicate with the cooling cavity 5, and the fluid cavity (liquid outlet flow channel) for enabling the outlet 412 to communicate with the cooling cavity 5, so as to achieve efficient cooling of the chip 2. The present disclosure does not specifically limit such a variant, and those skilled in the art can adaptively design according to actual application requirements.

[0083] In some possible embodiments, referring to Figure 1 As shown, the substrate 1 can be provided with an annular protrusion 10 arranged around the chip 2, and the second adhesive layer 11 is arranged between the sealing structure 4 and the annular protrusion 10. The sealing structure 4 is connected to the annular protrusion 10 through the second adhesive layer 11. In this arrangement, by connecting the heat dissipation cover 410 (for example, the cover plate 414) to the annular protrusion 10 connected to the substrate 1, not only the connection reliability of the heat dissipation cover 410 can be improved, but also the structural strength of the substrate 1 can be enhanced, and the risk of warping of the substrate 1 due to the difference in the thermal expansion coefficient during, for example, packaging can be reduced, which helps to improve the packaging yield and improve the overall reliability of the packaging structure.

[0084] In the present disclosure, the specific shape, size, and material of the substrate 1, the specific structure, size, and material of the annular protrusion 10, and the connection and fixing manner between the substrate 1 and the annular protrusion 10 are not specifically limited, and those skilled in the art can adaptively design according to actual application requirements, which will not be described in detail herein. For example, the substrate 1 and the annular protrusion 10 can be fixedly connected through a third adhesive layer.

[0085] In addition, in some possible embodiments, referring to ​ As shown, the number of chips 2 can be one or more, and each chip 2 is selected from one of a storage chip 210 and a logic chip 220. In this arrangement, the number and type of chips 2 can be adaptively designed according to the application requirements of the packaging structure, so as to meet the application arrangement requirements in complex scenarios of the packaging structure, which is beneficial to improve the performance and applicability of the packaging structure. In addition, the chip 2 can be safely and efficiently cooled by the cooling medium in the cooling cavity 5, which can ensure that the chip 2 can still operate stably and with high performance at a safe temperature under, for example, high power consumption, and the reliability is high.

[0086] The chip 2 can include a silicon chip, that is, it can be understood that the chip 2 can be prepared from, but is not limited to, for example, silicon, so that the heat exchange channel 3 is opened on the chip 2 prepared from silicon, and the chip 2 can be cooled by the cooling medium, which helps to ensure that the chip 2 operates stably and with high performance at a safe temperature, and achieves the purpose of improving the performance and reliability of the chip 2.

[0087] It can be understood that, as shown in FIG. 1, ​ The chip 2 can be arranged in a plurality of rows along the first direction, or, alternatively, the chip 2 can also be arranged in a plurality of columns along the second direction, or, alternatively, the chip 2 can also be arranged in a plurality of rows along the first direction and in a plurality of columns along the second direction at the same time, and the present disclosure does not specifically limit such a transformation mode, and a person skilled in the art can adaptively design according to the actual application requirements.

[0088] It should be noted that the present disclosure does not specifically limit the specific structure of the chip 2 (for example, the storage chip 210 and the logic chip 220), the specific arrangement position on the substrate 1, and the specific arrangement number, and the like, and a person skilled in the art can adaptively design according to the actual application requirements, for example, the storage chip 210 can include, but is not limited to, for example, a high bandwidth memory chip (HBM), and the logic chip 220 can include, but is not limited to, for example, a system on chip (SOC), and the present disclosure is not limited thereto, and the purpose is to be able to meet the application arrangement requirements in a complex packaging structure scenario, and to improve the performance and applicability of the packaging structure.

[0089] Furthermore, in some embodiments not shown, when the number of chips 2 is, for example, one, the heat sink 410 may be provided with one of the aforementioned inlet 411 and outlet 412. And when the heat sink 410 is connected to the chip 2 via the second structural layer 420, so that the aforementioned cooling cavity 5 is formed between the heat sink 410, the second structural layer 420, and the chip 2, the fluid channels provided on the heat sink 410 (e.g., the first fluid channel 430, the second fluid channel 440, the third fluid channel 450, and the fourth fluid channel 460, etc.) can be adaptively designed as one or more, i.e. Each inlet 411 can be connected to the cooling chamber 5 through a corresponding fluid channel, or each inlet 411 can be connected to the cooling chamber 5 simultaneously through multiple fluid channels. Similarly, each outlet 412 can be connected to the cooling chamber 5 through a corresponding fluid channel, or each outlet 412 can be connected to the cooling chamber 5 simultaneously through multiple fluid channels. This disclosure does not make specific limitations in this regard. Those skilled in the art can design it adaptively according to actual application needs. The purpose is to enable the replenishment and discharge of the cooling medium in the cooling chamber 5 so as to achieve cooling and temperature reduction of the chip 2.

[0090] Furthermore, in some possible implementations, when the number of chips 2 is arranged in multiples, the heat sink 410 may also be provided with one of the aforementioned inlet 411 and outlet 412. Multiple second structural layers 420 may be adaptively arranged corresponding to the number of chips 2, and each second structural layer 420 may be arranged in a ring around the outer periphery of the corresponding chip 2 between the chip 2 and the heat sink 410. This allows a cooling cavity 5 to be formed between each chip 2, each second structural layer 420, and the heat sink 410 for the cooling medium to flow through and exchange heat with the corresponding chip 2. When multiple cooling cavities 5 are designed, the heat sink 410 is provided with... When the inlet 411 is connected to one of the multiple cooling chambers 5, the inlet 411 can be connected to one of the multiple cooling chambers 5 through one or more fluid channels on the heat sink 410. Similarly, when the outlet 412 on the heat sink 410 is connected to one of the multiple cooling chambers 5, the outlet 412 can be connected to one of the multiple cooling chambers 5 through one or more fluid channels on the heat sink 410. This disclosure is not limited to this. Its purpose is to enable the simultaneous replenishment and discharge of cooling medium in multiple cooling chambers 5, so as to simultaneously cool and reduce the temperature of multiple chips 2.

[0091] In some possible implementations, refer to ​As shown, the semiconductor package structure can further include an interposer 12 disposed between the chip 2 and the substrate 1, and the chip 2 is connected to the substrate 1 through the interposer 12. In this way, by integrating one or more chips 2 on the interposer 12, high-bandwidth and low-latency data interconnection can be achieved, and the purpose of high-density interconnection of the overall package structure is achieved, which is conducive to meeting the design requirements of high performance of the package structure.

[0092] It should be noted that one or more chips 2 can be integrated on the interposer 12 by, for example, a face-up or flip-chip method, and the micro-bumps on the chip 2 can form a signal connection with the corresponding pads on the interposer 12. The present disclosure does not make specific limitations thereon, and those skilled in the art can adaptively design it according to actual application requirements, and the purpose is to be able to realize the signal connection between the chip 2 and the interposer 12. In addition, the specific design form of the chip 2 integrated on the interposer 12 can be adaptively designed with reference to existing, for example, CoWoS (Chip-on-Wafer-on-Substrate) package structure technology, and the present disclosure does not make too much repetition here.

[0093] In addition, the above-mentioned interposer 12 can include, but is not limited to, for example, a silicon interposer, so that when one or more chips 2 are integrated on the interposer 12, high-bandwidth and low-latency data interconnection can be achieved, and the purpose of high-density interconnection of the overall package structure is achieved.

[0094] In addition, the interposer 12 and the substrate 1 can be provided with an underfill 13 (underfill) to enable the gap between the interposer 12 and the substrate 1 to be filled by the underfill 13. In this way, the connection reliability of the interposer 12 and the substrate 1 can be improved, and air can also be isolated to reduce the risk of surface oxidation, which is conducive to prolonging the service life of the overall package structure. The present disclosure is not limited thereto.

[0095] According to a second aspect of the present disclosure, an electronic device is provided, which includes the semiconductor package structure provided by the first aspect. In addition, the electronic device also has all the beneficial effects of the above semiconductor package structure, and the present disclosure does not make further repetition here.

[0096] In some possible implementations, the above-mentioned electronic device can include, but is not limited to, a general-purpose computing device or a professional computing device, such as a computer, a mobile phone, a tablet, a workstation, a smart watch, an AI server, a cloud computing server, a data center device, etc.

[0097] The preferred embodiments of the present disclosure are described in detail above with reference to the drawings, but the present disclosure is not limited to the specific details in the above-described embodiments. Various simple modifications can be made to the technical solutions of the present disclosure within the technical concept of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure.

[0098] In addition, it should be noted that each specific technical feature described in the above specific embodiments can be combined in any appropriate manner without contradiction. In order to avoid unnecessary repetition, various possible combinations are not described again in the present disclosure.

[0099] In addition, various different embodiments of the present disclosure can also be combined in any appropriate manner, as long as they do not deviate from the idea of the present disclosure, and they should also be considered as disclosed by the present disclosure.

Claims

1. A semiconductor packaging structure, characterized in that, include: substrate; A chip is disposed on the substrate, and the chip is recessed downward from the top wall of the substrate to form a heat exchange channel. A sealing structure is connected to the chip, and a cooling cavity communicating with the heat exchange channel is formed between the sealing structure and the chip; as well as A thermally conductive structure is located within the cooling cavity and is thermally connected to the top wall of the chip; The sealing structure is configured to allow the cooling medium to flow through the cooling cavity, the heat exchange channel, and the heat conduction structure, so that the cooling medium can exchange heat with the chip.

2. The semiconductor packaging structure according to claim 1, characterized in that, The heat exchange channel includes multiple heat exchange channel segments arranged at intervals, and the heat conduction structure is provided between two adjacent heat exchange channel segments.

3. The semiconductor packaging structure according to claim 1, characterized in that, The thermally conductive structure includes a thermally conductive protrusion, which is connected to the top wall of the chip and extends toward the side away from the top wall. Wherein, the end of the thermally conductive protrusion facing away from the top wall of the chip has a gap with the inner wall of the sealing structure; and / or, The heat-conducting protrusion has a notch.

4. The semiconductor packaging structure according to claim 1, characterized in that, The heat exchange channel includes a plurality of heat exchange channel segments arranged at intervals along a first direction, and each heat exchange channel segment extends along a second direction perpendicular to the first direction; and / or, The heat-conducting structure includes a plurality of heat-conducting protrusions arranged at intervals, the plurality of heat-conducting protrusions being arranged in a row along a first direction and / or arranged in a column along a second direction perpendicular to the first direction.

5. The semiconductor packaging structure according to claim 4, characterized in that, The structural dimensions of the heat exchange channel section along the first direction are 10μm-20μm; and / or, The structural dimensions of the heat exchange channel section along the second direction are 10mm-30mm; and / or, The structural dimensions of the heat exchange channel section along a third direction perpendicular to the plane containing the first and second directions are 5μm-200μm.

6. The semiconductor packaging structure according to claim 4, characterized in that, The thermally conductive protrusion has a structural dimension of 10μm-20μm along the first direction; and / or, The thermally conductive protrusion has a structural dimension of 10mm-30mm along the second direction; and / or, The thermally conductive protrusion has a structural dimension of 100μm-200μm along a third direction perpendicular to the plane containing the first and second directions.

7. The semiconductor packaging structure according to claim 4, characterized in that, The thermally conductive protrusions are cylindrical or rectangular; and / or, The thermally conductive protrusion is made of copper.

8. The semiconductor packaging structure according to claim 1, characterized in that, A first structural layer is provided on the top wall of the chip facing the thermal conductive structure, and the thermal conductive structure is connected to the chip through the first structural layer.

9. The semiconductor packaging structure according to claim 8, characterized in that, The first structural layer is made of titanium or a titanium alloy.

10. The semiconductor packaging structure according to any one of claims 1-9, characterized in that, The sealing structure includes a heat dissipation cover and a second structural layer. The heat dissipation cover is connected to the chip through the second structural layer, so that the heat dissipation cover, the second structural layer, the heat-conducting structure and the chip together form the cooling cavity. The heat dissipation cover is provided with an inlet and an outlet communicating with the cooling cavity.

11. The semiconductor packaging structure according to claim 10, characterized in that, The second structural layer is disposed between the heat sink and the chip, and the second structural layer is arranged in a circle around the outer periphery of the chip. The heat sink is provided with an inlet channel and an outlet channel. The inlet is connected to the cooling cavity through the inlet channel, and the outlet is connected to the cooling cavity through the outlet channel.

12. The semiconductor packaging structure according to claim 11, characterized in that, The second structural layer is formed of sealant.

13. The semiconductor packaging structure according to claim 12, characterized in that, The sealant is made of polydimethylsiloxane or epoxy-negative photoresist.

14. The semiconductor packaging structure according to claim 11, characterized in that, The heat dissipation cover includes a manifold plate and a cover plate stacked in a third direction, and the cover plate is connected to the chip through the second structural layer. The cover plate is provided with a first fluid channel and a second fluid channel. The manifold plate is provided with an inlet, an outlet, a third fluid channel and a fourth fluid channel. The first fluid channel and the third fluid channel are connected to form the liquid inlet channel, and the second fluid channel and the fourth fluid channel are connected to form the liquid outlet channel.

15. The semiconductor packaging structure according to claim 14, characterized in that, The sealing structure also includes a connecting structure, through which the manifold plate and the cover plate are connected.

16. The semiconductor packaging structure according to claim 15, characterized in that, The connection structure includes a first adhesive layer disposed between the manifold plate and the cover plate, the first adhesive layer having a first cavity communicating with the first fluid cavity and the third fluid cavity, and a second cavity communicating with the second fluid cavity and the fourth fluid cavity; and / or, The connection structure includes connecting bolts, and the manifold plate and the cover plate are threadedly connected by the connecting bolts.

17. The semiconductor packaging structure according to claim 1, characterized in that, The substrate has an annular protrusion arranged around the chip, and a second adhesive layer is disposed between the sealing structure and the annular protrusion. The sealing structure is connected to the annular protrusion through the second adhesive layer.

18. The semiconductor packaging structure according to claim 1, characterized in that, The number of chips is one or more, and each chip is selected from either memory chips or logic chips.

19. The semiconductor packaging structure according to claim 1 or 18, characterized in that, The semiconductor packaging structure further includes an intermediary layer disposed between the chip and the substrate, through which the chip is connected to the substrate.

20. An electronic device, characterized in that, Includes the semiconductor packaging structure described in any one of claims 1-19.

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