Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor with which it is possible to improve resistance to electrostriction when a high electric field is applied. A multilayer ceramic capacitor according to the present invention is provided with: a multilayer body including a plurality of dielectric layers that are laminated, the first main surface and the second main surface are opposite to each other in the stacking direction of the dielectric layers, the first side surface and the second side surface are opposite to each other in the width direction orthogonal to the stacking direction, and the first end surface and the second end surface are opposite to each other in the length direction orthogonal to the stacking direction and the width direction. A first internal electrode layer disposed on the plurality of dielectric layers and exposed on the first end surface; a second internal electrode layer disposed on the plurality of dielectric layers and exposed on the second end surface; a first external electrode having a base electrode layer disposed on the first end surface and a plating layer disposed on the base electrode layer; and a second external electrode having a base electrode layer disposed on the second end surface, and a plating layer disposed on the base electrode layer. The orientation of crystallites in dielectric particles included in the dielectric layer is oriented on the C-axis.

Description

TECHNICAL FIELD

[0001] The present application relates to a multilayer ceramic capacitor. BACKGROUND

[0002] Conventionally, a multilayer ceramic capacitor is known. Generally, a multilayer ceramic capacitor is provided with a ceramic sintered body containing a dielectric ceramic such as barium titanate (BaTi03). A plurality of internal electrodes are arranged inside the ceramic sintered body so as to overlap each other with a dielectric layer interposed therebetween. Further, external electrodes are formed on one end surface and the other end surface of the ceramic sintered body so as to be electrically connected to the internal electrodes (for example, Patent Document 1).

[0003] PRIOR ART DOCUMENTS

[0004] PATENT DOCUMENTS

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 8-306580 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] However, in a general multilayer ceramic capacitor such as that of Patent Document 1, the following problem occurs. That is, in a case where a high electric field is applied to the multilayer ceramic capacitor, the dielectric particles contained in the dielectric layer are greatly displaced in the direction of the electric field application (C-axis), and it is likely that electrostriction occurs to cause a failure.

[0008] Therefore, the main object of the present application is to provide a multilayer ceramic capacitor in which the resistance to electrostriction in a case where a high electric field is applied is improved.

[0009] TECHNICAL SOLUTION FOR SOLVING THE PROBLEMS

[0010] The multilayer ceramic capacitor according to the present application is provided with: a laminate body containing a plurality of dielectric layers laminated, and having a first main surface and a second main surface opposed in the direction of lamination of the plurality of dielectric layers, a first side surface and a second side surface opposed in a width direction orthogonal to the direction of lamination, and a first end surface and a second end surface opposed in a length direction orthogonal to the direction of lamination and the width direction; a first internal electrode layer arranged on the plurality of dielectric layers and exposed at the first end surface; a second internal electrode layer arranged on the plurality of dielectric layers and exposed at the second end surface; a first external electrode having a base electrode layer arranged on the first end surface, and a plating layer arranged on the base electrode layer; and a second external electrode having a base electrode layer arranged on the second end surface, and a plating layer arranged on the base electrode layer, the orientation of crystallites in the dielectric particles contained in the dielectric layers being oriented in the C-axis.

[0011] According to the present application, in a laminated ceramic capacitor, the resistance to electrostriction under application of a high electric field can be improved.

[0012] Effects of the Invention

[0013] According to the present application, in a laminated ceramic capacitor, the resistance to electrostriction under application of a high electric field can be improved.

[0014] The above objects, other objects, features and advantages of the present application will become more fully understood from the following detailed description, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is an appearance perspective view showing one example of a laminated ceramic capacitor to which an embodiment of the present application pertains.

[0016] Figure 2 is a front view showing one example of a laminated ceramic capacitor to which an embodiment of the present application pertains.

[0017] Figure 3 is a plan view showing one example of a laminated ceramic capacitor to which an embodiment of the present application pertains.

[0018] Figure 4 is Figure 1 a cross-sectional view at line IV-IV.

[0019] Figure 5 is Figure 1 a cross-sectional view at line V-V.

[0020] Figure 6 is Figure 4 a cross-sectional view at line VI-VI.

[0021] Figure 7 (a) of FIG. 1 is a cross-sectional view at line II-II showing a configuration in which the opposing electrode portion of the internal electrode layer of a laminated ceramic capacitor to which an embodiment of the present application pertains is divided into 2. Figure 1 (a) of FIG. 1 is a cross-sectional view at line II-II showing a configuration in which the opposing electrode portion of the internal electrode layer of a laminated ceramic capacitor to which an embodiment of the present application pertains is divided into 2. Figure 7 (b) of FIG. 1 is a cross-sectional view at line II-II showing a configuration in which the opposing electrode portion of the internal electrode layer of a laminated ceramic capacitor to which an embodiment of the present application pertains is divided into 3. Figure 1 (b) of FIG. 1 is a cross-sectional view at line II-II showing a configuration in which the opposing electrode portion of the internal electrode layer of a laminated ceramic capacitor to which an embodiment of the present application pertains is divided into 3. Figure 7 (c) of FIG. 1 is a cross-sectional view at line II-II showing a configuration in which the opposing electrode portion of the internal electrode layer of a laminated ceramic capacitor to which an embodiment of the present application pertains is divided into 4. Figure 1 (c) of FIG. 1 is a cross-sectional view at line II-II showing a configuration in which the opposing electrode portion of the internal electrode layer of a laminated ceramic capacitor to which an embodiment of the present application pertains is divided into 4. DETAILED DESCRIPTION

[0022] Hereinafter, an example of the multilayer ceramic capacitor according to the embodiment of the present application will be described.

[0023] 1. A multilayer ceramic capacitor

[0024] Hereinafter, an example of the multilayer ceramic capacitor according to the embodiment of the present application will be described. Figure 1 is an appearance perspective view showing an example of the multilayer ceramic capacitor according to the embodiment of the present application. Figure 2 is a front view showing an example of the multilayer ceramic capacitor according to the embodiment of the present application. Figure 3 is a plan view showing an example of the multilayer ceramic capacitor according to the embodiment of the present application. Figure 4 is Figure 1 is a cross-sectional view taken along line IV-IV. Figure 5 is Figure 1 is a cross-sectional view taken along line V-V. Figure 6 is Figure 4 is a cross-sectional view taken along line VI-VI. Figure 4 is Figure 1 is a cross-sectional view taken along line VI-VII.

[0025] The multilayer ceramic capacitor 10 has a multilayer body 12 and external electrodes 30. The multilayer body 12 is composed of a plurality of dielectric layers 14 and a plurality of internal electrode layers 16 alternately laminated and exhibits an inner layer portion 15a exhibiting a capacitance, and a first outer layer portion 15b1 and a second outer layer portion 15b2 arranged to sandwich the inner layer portion 15a from upper and lower main surface sides.

[0026] Hereinafter, each structure will be described in the order of the multilayer body 12, the internal electrode layer 16, and the external electrode 30.

[0027] (Multilayer body)

[0028] The multilayer body 12 has a plurality of dielectric layers 14 and a plurality of internal electrode layers 16 laminated. Further, the multilayer body 12 includes a first main surface 12a and a second main surface 12b opposed in a height direction x of the laminating direction of the plurality of dielectric layers 14, a first side surface 12c and a second side surface 12d opposed in a width direction y orthogonal to the height direction x, and a first end surface 12e and a second end surface 12f opposed in a length direction z orthogonal to the height direction x and the width direction y. In addition, the length direction z is also defined as an L direction which connects the first end surface 12e and the second end surface 12f. The width direction y is also defined as a W direction which connects the first side surface 12c and the second side surface 12d. The height direction x is also defined as a T direction which connects the first main surface 12a and the second main surface 12b.

[0029] The laminate 12 is a rectangular parallelepiped shape. It is a rectangular parallelepiped in which the corner portions and the ridge line portions are rounded. In addition, the corner portion is a portion where three adjacent faces of the laminate 12 intersect, and the ridge line portion is a portion where two adjacent faces of the laminate 12 intersect. That is, the member of the "rectangular parallelepiped shape" means all members having the first main face 12a and the second main face 12b, the first side face 12c and the second side face 12d, and the first end face 12e and the second end face 12f.

[0030] A concave-convex or the like can be formed in part or all of the first main face 12a and the second main face 12b, the first side face 12c and the second side face 12d, and the first end face 12e and the second end face 12f.

[0031] As shown in Figs. 1 and 2, the laminate 12 has the first main face 12a and the second main face 12b, the first side face 12c and the second side face 12d, and the first end face 12e and the second end face 12f. Figure 4 Figure 5 As shown in Figs. 1 and 2, the laminate 12 has the first main face 12a and the second main face 12b, the first side face 12c and the second side face 12d, and the first end face 12e and the second end face 12f.

[0032] The first outer layer portion 15b1 is located on the first main face 12a side of the laminate 12, and is a collection of the plurality of dielectric layers 14 located between the first main face 12a and the internal electrode layer 16 closest to the first main face 12a.

[0033] The second outer layer portion 15b2 is located on the second main face 12b side of the laminate 12, and is a collection of the plurality of dielectric layers 14 located between the second main face 12b and the internal electrode layer 16 closest to the second main face 12b.

[0034] Furthermore, the region sandwiched by the first outer layer portion 15b1 and the second outer layer portion 15b2 is the inner layer portion 15a.

[0035] The number of stacked dielectric layers 14 is not particularly limited, but is preferably 50 or more and 2000 or less including the first outer layer portion 15b1 and the second outer layer portion 15b2. In addition, the thickness of the dielectric layer 14 is, for example, preferably 0.5 μm or more and 10 μm or less.

[0036] ​As the ceramic material constituting the dielectric layer 14, for example, a dielectric material can be formed. In particular, in the present embodiment, as the dielectric material, a dielectric ceramic in which barium titanate (BaTiO3) is a main component is preferably used. Further, depending on the characteristics of the desired multilayer body, for example, a material in which a subcomponent is added in a smaller amount than the main component, such as a Mn compound, a Fe compound, a Cr compound, a Co compound, a Ni compound, or the like, can also be used.

[0037] Further, in the present embodiment, the orientation of the crystallite in the dielectric particle included in the dielectric layer 14 is oriented on the C-axis.

[0038] That is, the dielectric particle included in the dielectric layer 14 is displaced in the direction of the electric field application (C-axis) in a state in which a high electric field is applied, which causes electrostriction. In this regard, by orienting the orientation of the crystallite in the dielectric particle in advance on the C-axis as described above, the amount of displacement of the dielectric particle included in the dielectric layer 14 in the direction of the electric field application (C-axis) when a high electric field is applied to the multilayer ceramic capacitor 10 is reduced. Therefore, the resistance to electrostriction of the multilayer ceramic capacitor 10 is improved.

[0039] Further, the degree of orientation of the orientation of the crystallite in the dielectric particle included in the dielectric layer 14 on the C-axis (C-axis orientation degree) is preferably 1.6 or more and 2.2 or less.

[0040] Thereby, the resistance to electrostriction of the multilayer ceramic capacitor 10 can be further improved.

[0041] The C-axis orientation degree can be obtained based on the diffraction intensity measurement using transmission XRD of SPring-8. Specifically, the relative intensity ratio of the peak intensity of the plane orientation (400) and (040) obtained by Rietveld analysis to the ICDD card inclusion data is calculated and obtained as a measured intensity ratio. Then, the ratio of the measured intensity ratio to the theoretical intensity ratio of the plane orientation (400) and (040) of BaTiO3 is calculated and determined as the C-axis orientation degree.

[0042] Since the theoretical intensity ratio of the plane orientation (400) and (040) of BaTiO3 is 2:1, if the measured intensity ratio is 2:1, the measured intensity ratio and the theoretical intensity ratio are the same, the C-axis orientation degree is 1, that is, the crystallite in the dielectric particle is not oriented. On the other hand, in a case where the intensity of the plane orientation (400) when the intensity of the plane orientation (040) of BaTiO3 is set to 1 is greater than 2, the C-axis orientation degree becomes greater than 1, that is, the crystallite is oriented.

[0043] Further, in the present embodiment, the relative dielectric constant of the dielectric particle is preferably 1000 or more.

[0044] This is based on the following reasoning. Specifically, when the relative permittivity of the dielectric particles is 1000 or higher, the displacement of the dielectric particles is large when a voltage is applied to the dielectric layer 14. Therefore, for such dielectric particles, as in this embodiment, by pre-orienting the dielectric particles along the C-axis, the effect of reducing the displacement of the dielectric layer 14 when a voltage is applied to the multilayer ceramic capacitor 10 can be made more significant.

[0045] (Internal electrode layer)

[0046] like Figure 4 as well as Figure 5 As shown, the internal electrode layer 16 has a first internal electrode layer 16a and a second internal electrode layer 16b. The first internal electrode layer 16a and the second internal electrode layer 16b are stacked alternately with a dielectric layer 14 in between.

[0047] The first internal electrode layer 16a is disposed on the surface of the dielectric layer 14. The first internal electrode layer 16a has a first opposing electrode portion 18a opposite to the second internal electrode layer 16b, and a first lead-out electrode portion 20a located at one end of the first internal electrode layer 16a and extending from the first opposing electrode portion 18a to the first end face 12e of the laminate 12. The end of the first lead-out electrode portion 20a extends to and is exposed on the first end face 12e. Specifically, the end of the first lead-out electrode portion 20a is slightly recessed from the second end face 12f.

[0048] The shape of the first opposing electrode portion 18a of the first internal electrode layer 16a is not particularly limited, but it is preferably rectangular in plan view. However, the corner portion in plan view can be rounded, or the corner portion can be formed into a tapered shape in plan view.

[0049] The shape of the first lead-out electrode portion 20a of the first internal electrode layer 16a is not particularly limited, but it is preferably rectangular in plan view. However, the corner portion in plan view can be rounded, or the corner portion can be formed into a plan view that is inclined (conical). Alternatively, it can be a plan view cone shape that is inclined in any direction.

[0050] The second internal electrode layer 16b is disposed on the surface of a dielectric layer 14 different from the dielectric layer 14 on which the first internal electrode layer 16a is disposed. It has a second opposing electrode portion 18b opposite to the first internal electrode layer 16a, and a second lead-out electrode portion 20b located at one end of the second internal electrode layer 16b and extending from the second opposing electrode portion 18b to the second end face 12f of the laminate 12. The end of the second lead-out electrode portion 20b extends to and is exposed on the second end face 12f. Specifically, the end of the second lead-out electrode portion 20b is slightly recessed from the first end face 12e.

[0051] The shape of the second opposing electrode portion 18b of the second inner electrode layer 16b is not particularly limited, but it is preferably rectangular in plan view. However, the corner portions in plan view can be rounded, or the corner portions can be formed into a plan view that is inclined (conical).

[0052] The shape of the second lead-out electrode portion 20b of the second inner electrode layer 16b is not particularly limited, but it is preferably rectangular in plan view. However, the corner portion in plan view can be rounded, or the corner portion can be formed into a plan view that is inclined (conical). Alternatively, it can be a plan view cone shape that is inclined in any direction.

[0053] The laminate 12 includes a side portion (hereinafter referred to as "W gap") 22a formed between one end of the first opposing electrode portion 18a and the second opposing electrode portion 18b in the width direction y and the first side surface 12c, and between the other end of the first opposing electrode portion 18a and the second opposing electrode portion 18b in the width direction y and the second side surface 12d. Furthermore, the laminate 12 includes an end portion (hereinafter referred to as "L gap") 22b formed between the end of the first inner electrode layer 16a opposite to the first lead-out electrode portion 20a and the second end surface 12f, and between the end of the second inner electrode layer 16b opposite to the second lead-out electrode portion 20b and the first end surface 12e.

[0054] The number of stacked internal electrode layers 16 is not particularly limited, but is preferably 50 or more and 2000 or less. Furthermore, the thickness of the internal electrode layers 16 is preferably 0.2 μm or more and 2.0 μm or less.

[0055] The internal electrode layer 16 can be made of a suitable conductive material, such as a metal like Ni, Cu, Ag, Pd, Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy.

[0056] In addition, such as Figure 7 As shown, Figure 1 The stacked body 12 shown can also be configured such that, in addition to the first internal electrode layer 16a and the second internal electrode layer 16b, a floating internal electrode layer 16c is provided that is not led out to either the first end face 12e or the second end face 12f, and the opposing electrode portion 26c is divided into multiple parts by the floating internal electrode layer 16c. For example, Figure 7 The two-connected structure shown in (a) Figure 7 The 3-connected structure shown in (b) Figure 7The four-connection structure shown in (c) can, of course, be a structure with more than four connections. By dividing the opposing electrode section 26c into multiple components, multiple capacitor components are formed between the opposing first inner electrode layer 16a, second inner electrode layer 16b, and floating inner electrode layer 16c, and these capacitor components are connected in series. Therefore, the voltage applied to each capacitor component is lower, and a high withstand voltage of the multilayer ceramic capacitor 10 can be achieved.

[0057] Furthermore, the floating internal electrode layer 16c, like the first internal electrode layer 16a and the second internal electrode layer 16b, can be made of suitable conductive materials, such as metals like Ni, Cu, Ag, Pd, Au, or alloys containing at least one of these metals, such as Ag-Pd alloys.

[0058] like Figures 1 to 3 As shown, external electrodes 30 are disposed on the first end face 12e side and the second end face 12f side of the laminate 12.

[0059] The external electrode 30 includes a base electrode layer 32 comprising a metal component and glass, and a plating layer 34 disposed on the surface of the base electrode layer 32.

[0060] The external electrode 30 has a first external electrode 30a and a second external electrode 30b.

[0061] The first external electrode 30a is connected to the first internal electrode layer 16a and is disposed at least on the surface of the first end face 12e. Furthermore, the first external electrode 30a extends from the first end face 12e of the laminate 12 and is also disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the first external electrode 30a is electrically connected to the first lead-out electrode portion 20a of the first internal electrode layer 16a.

[0062] The second external electrode 30b is connected to the second internal electrode layer 16b and is disposed at least on the surface of the second end face 12f. Furthermore, the second external electrode 30b extends from the second end face 12f of the laminate 12 and is also disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the second external electrode 30b is electrically connected to the second lead-out electrode portion 20b of the second internal electrode layer 16b.

[0063] Within the laminate 12, a static capacitance is formed by the first opposing electrode portion 18a of the first inner electrode layer 16a and the second opposing electrode portion 18b of the second inner electrode layer 16b being opposed to each other across the dielectric layer 14. Therefore, a static capacitance can be obtained between the first outer electrode 30a connected to the first inner electrode layer 16a and the second outer electrode 30b connected to the second inner electrode layer 16b, exhibiting the characteristics of a capacitor.

[0064] The base electrode layer 32 has a first base electrode layer 32a and a second base electrode layer 32b.

[0065] The first base electrode layer 32a is connected to the first inner electrode layer 16a and disposed on the surface of the first end face 12e. Furthermore, the first base electrode layer 32a extends from the first end face 12e and is also disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the first base electrode layer 32a is electrically connected to the first lead-out electrode portion 20a of the first inner electrode layer 16a.

[0066] The second base electrode layer 32b is connected to the second inner electrode layer 16b and disposed on the surface of the second end face 12f. Furthermore, the second base electrode layer 32b extends from the second end face 12f and is also disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the second base electrode layer 32b is electrically connected to the second lead-out electrode portion 20b of the second inner electrode layer 16b.

[0067] The substrate electrode layer 32 includes at least one selected from sintered layers, conductive resin layers, and thin film layers.

[0068] The following describes the structures when the base electrode layer 32 is configured as the above-described sintered layer, conductive resin layer, and thin film layer.

[0069] (The situation of burning the attached layer)

[0070] The sintered layer comprises a metallic component and glass. The metallic component of the sintered layer may include, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloys, Au, etc. The sintered layer is formed by applying a conductive paste comprising glass and metal to a laminate and then sintering it. The sintered layer is formed by simultaneously sintering a chip having an internal electrode layer 16 and a dielectric layer 14 and the conductive paste applied to the chip, but it can also be sintered after the chip having the internal electrode layer 16 and the dielectric layer 14 has been sintered. The sintered layer may also consist of multiple layers.

[0071] The thickness of the length direction z connecting the first end face 12e and the second end face 12f at the center of the height direction x of the first base electrode layer 32a located on the first end face 12e is preferably, for example, 10 μm or more and 150 μm or less.

[0072] The thickness of the length direction z connecting the first end face 12e and the second end face 12f at the center of the second base electrode layer 32b in the height direction x of the second end face 12f is preferably, for example, 10 μm or more and 150 μm or less.

[0073] The thickness of the first base electrode layer 32a, located in a portion of the first main surface 12a and the second main surface 12b, in the length direction z connecting the first end surface 12e and the second end surface 12f, in the height direction x connecting the first main surface 12a and the second main surface 12b, is preferably, for example, 10 μm or more and 100 μm or less.

[0074] Furthermore, the thickness of the second base electrode layer 32b, located at the center of the length direction z connecting the first end face 12e and the second end face 12f, which is part of the first main surface 12a and the second main surface 12b, in the height direction x connecting the first main surface 12a and the second main surface 12b, is preferably, for example, 10 μm or more and 100 μm or less.

[0075] The thickness of the first base electrode layer 32a, located in a portion of the first side surface 12c and the second side surface 12d, in the length direction z at the center of the first end face 12e and the second end face 12f, and in the width direction y connecting the first side surface 12c and the second side surface 12d, is preferably, for example, 10 μm or more and 100 μm or less.

[0076] Furthermore, the thickness of the second base electrode layer 32b, located in a portion of the first side surface 12c and the second side surface 12d, in the length direction z at the center of the portion connecting the first end face 12e and the second end face 12f, and in the width direction y connecting the first side surface 12c and the second side surface 12d, is preferably, for example, 10 μm or more and 100 μm or less.

[0077] (In the case of conductive resin layer)

[0078] The conductive resin layer has a first conductive resin layer and a second conductive resin layer.

[0079] The first conductive resin layer, serving as the first base electrode layer 32a, is preferably configured to further cover other layers such as a sintered layer, and the second conductive resin layer, serving as the second base electrode layer 32b, is preferably configured to further cover other layers such as a sintered layer.

[0080] Specifically, the first conductive resin layer and the second conductive resin layer are preferably disposed on top of other layers such as the sintered layer on the first end face 12e and the second end face 12f, and are configured to extend to other layers such as the sintered layer on the first main surface 12a and the second main surface 12b, and the first side surface 12c and the second side surface 12d. However, the first conductive resin layer and the second conductive resin layer may also be disposed only on other layers such as the sintered layer on the first end face 12e and the second end face 12f.

[0081] The thicknesses of the first conductive resin layer and the second conductive resin layer are preferably, for example, 10 μm or more and 200 μm or less.

[0082] The first conductive resin layer and the second conductive resin layer contain thermosetting resin and metal components.

[0083] The first and second conductive resin layers, because they contain thermosetting resins, are more flexible than the base electrode layer 32 formed by firing, for example, a coated film or conductive paste. Therefore, even when the multilayer ceramic capacitor 10 is subjected to physical impacts, such as those caused by thermal cycling, the conductive resin layers can function as buffer layers to prevent cracks from forming in the multilayer ceramic capacitor 10.

[0084] Specific examples of thermosetting resins include various known thermosetting resins such as epoxy resins, phenolic resins, polyurethane resins, silicone resins, and polyimide resins. Among these, epoxy resins, with their excellent heat resistance, moisture resistance, and adhesion, are one of the most suitable resins.

[0085] In both the first and second conductive resin layers, a curing agent is preferably included together with the thermosetting resin. When using epoxy resin as the base resin, various known compounds such as phenolic, amine, anhydride, and imidazole compounds can be used as the curing agent for the epoxy resin.

[0086] Ag, Cu, or alloys thereof can be used as the metals contained in the first and second conductive resin layers. Furthermore, materials in which Ag has been applied to the surface of the metal powder can be used. When using materials in which Ag has been applied to the surface of the metal powder, Cu or Ni is preferred as the metal powder.

[0087] Furthermore, materials for which Cu has undergone oxidation prevention treatment can also be used. The reason for using metals coated with Ag is that the base metal can be made from an inexpensive metal while maintaining the aforementioned properties of Ag.

[0088] The metal contained in the first conductive resin layer and the second conductive resin layer preferably comprises 35 vol% or more and 75 vol% or less relative to the total volume of the conductive resin.

[0089] The shape of the metal contained in the first and second conductive resin layers is not particularly limited. The conductive filler can also be spherical, flat, etc.

[0090] The average particle size of the metals contained in the first and second conductive resin layers is not particularly limited. The average particle size of the conductive filler may, for example, be between 0.3 μm and 10 μm.

[0091] The metal contained in the first and second conductive resin layers primarily bears the responsibility for the electrical conductivity of the conductive resin layers. Specifically, conductive fillers are in contact with each other, thereby forming electrical pathways within the conductive resin layers.

[0092] The metal contained in the first conductive resin layer and the second conductive resin layer can be spherical, flat, or other types of metal, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0093] Alternatively, the conductive resin layer can be formed directly on the laminate without forming a sintered layer.

[0094] (The case of thin film layers)

[0095] In the case where the substrate electrode layer 32 is formed by a thin film layer, the thin film layer is formed by a thin film formation method such as sputtering or vapor deposition, and is a layer with metal particles deposited on it and a thickness of less than 10 μm.

[0096] Next, refer to Figure 2 as well as Figure 3 The plating layers 34 disposed on the substrate electrode layer 32, namely the first plating layer 34a and the second plating layer 34b, will be described.

[0097] The first plating layer 34a and the second plating layer 34b may include at least one material selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0098] The first plating layer 34a is configured to completely cover the first base electrode layer 32a.

[0099] The second plating layer 34b is configured to completely cover the second base electrode layer 32b.

[0100] The first plating layer 34a and the second plating layer 34b may also be formed from multiple layers. In this case, the plating layer 34 is preferably a two-layer structure consisting of a lower plating layer (Ni plating layer) formed on the substrate electrode layer 32 based on Ni plating and an upper plating layer (Sn plating layer) formed on the lower plating layer based on Sn plating.

[0101] That is, in this case, the first plating layer 34a has a first lower plating layer and a first upper plating layer located on the surface of the first lower plating layer.

[0102] Furthermore, the second plating layer 34b has a second lower plating layer and a second upper plating layer located on the surface of the second lower plating layer.

[0103] The lower plating layer based on Ni plating is used to prevent the base electrode layer 32 from being eroded by the solder when mounting the multilayer ceramic capacitor 10, and the upper plating layer based on Sn plating is used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, thereby making it easier to mount.

[0104] The thickness of each of the lower and upper plating layers is preferably 1.0 μm or more and 15.0 μm or less.

[0105] The dimension of the stacked ceramic capacitor 10, which includes the stacked body 12, the first external electrode 30a, and the second external electrode 30b, in the length direction z is set as dimension L. The dimension of the stacked ceramic capacitor 10, which includes the stacked body 12, the first external electrode 30a, and the second external electrode 30b, in the height direction x is set as dimension T. The dimension of the stacked ceramic capacitor 10, which includes the stacked body 12, the first external electrode 30a, and the second external electrode 30b, in the width direction y is set as dimension W.

[0106] Regarding the dimensions of the multilayer ceramic capacitor 10, the length dimension L in the z-direction is 0.2 mm or more and 10.0 mm or less, the width dimension W in the y-direction is 0.1 mm or more and 10.0 mm or less, and the height dimension T in the x-direction is 0.1 mm or more and 5.0 mm or less. Furthermore, the dimensions of the multilayer ceramic capacitor 10 can be measured using a microscope.

[0107] exist Figure 1 In the multilayer ceramic capacitor 10 of the embodiment shown, the microcrystals in the dielectric particles contained in the dielectric layer 14 of the laminate 12 are oriented along the C-axis. As a result, when a high electric field is applied to the multilayer ceramic capacitor 10, the amount of displacement of the dielectric particles contained in the dielectric layer 14 in the direction of electric field application (C-axis) is reduced, thereby improving the resistance to electrostriction.

[0108] Furthermore, in the multilayer ceramic capacitor 10, the orientation degree of the microcrystals in the dielectric particles contained in the dielectric layer 14 relative to the C-axis (C-axis orientation degree) is preferably 1.6 or more and 2.2 or less. This allows for further improvement in the electrostriction tolerance of the multilayer ceramic capacitor 10.

[0109] Furthermore, in the multilayer ceramic capacitor 10, the relative permittivity of the dielectric particles is preferably 1000 or higher. This makes the reduction in the displacement of the dielectric layer 14 when a voltage is applied in the multilayer ceramic capacitor 10 more significant.

[0110] 2. Manufacturing method of multilayer ceramic capacitors

[0111] Next, the manufacturing method of multilayer ceramic capacitors will be explained.

[0112] (1) Prepare a conductive paste for dielectric sheets and internal electrode layers. The conductive paste for dielectric sheets and internal electrode layers contains an adhesive (e.g., a known organic adhesive) and a solvent (e.g., a known organic adhesive).

[0113] (2) Next, conductive paste for the inner electrode layer is printed on the dielectric sheet in a given pattern, for example by screen printing or gravure printing, to prepare a dielectric sheet having a first inner electrode pattern corresponding to the first inner electrode layer and a dielectric sheet having a second inner electrode pattern corresponding to the second inner electrode layer. In addition, a dielectric sheet for the outer layer without the inner electrode pattern is also prepared.

[0114] (3) A given number of dielectric sheets for the outer layer without an internal electrode pattern are stacked to form a second outer layer. A dielectric sheet with a first internal electrode pattern and a dielectric sheet with a second internal electrode pattern are stacked sequentially on top of the outer layer to form an inner layer.

[0115] (4) Furthermore, a given number of dielectric sheets without printed internal electrode patterns are stacked on the internal electrode pattern corresponding to the internal electrode layer on the outermost surface of the inner layer to form a portion of the first outer layer, thereby producing a laminated sheet.

[0116] (5) A laminated block is made by pressing the laminated sheets in the lamination direction using methods such as isostatic pressing.

[0117] (6) Cut the stacked block to the given size to cut out stacked pieces. At this time, the corners and edges of the stacked pieces can also be rounded by roller grinding or the like.

[0118] (7) The laminate 12 is fabricated by firing the stacked small pieces. Although the firing temperature is also based on the ceramic and the material of the internal electrode layer 16, it is preferably 900°C or higher and 1400°C or lower. In addition, it is preferable that the oxygen concentration is 1000 ppm or higher and 5000 ppm or lower regarding the firing atmosphere, the heating rate is 100°C or higher from 800°C to the maximum temperature (1400°C), and the firing time is 4 seconds or higher and 8 seconds or lower. As a result, the orientation of the microcrystals in the dielectric particles contained in the dielectric layer can be aligned along the C-axis.

[0119] (8) Next, a base electrode layer is formed. In addition, the base electrode layer is set as a sintered layer. For the first base electrode layer and the second base electrode layer, a conductive paste containing glass and metal components is prepared respectively.

[0120] (9) For example, a conductive paste is applied to the first and second end faces of the laminate 12 by means of dipping, screen printing or other methods, and then a sintering process is performed to form the first base electrode layer and the second base electrode layer. In addition, the sintering temperature is preferably 700°C or higher and 900°C or lower.

[0121] (10) In addition, when the base electrode layer is formed from a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer can be formed on the surface of the sintered layer, or the conductive resin layer can be formed directly on the laminate in the form of a monomer without forming a sintered layer.

[0122] As a method for forming a conductive resin layer, a conductive resin paste comprising a thermosetting resin and a metal component is applied to a sintered layer or a laminate, and then heat-treated at a temperature of 250°C or higher and 550°C or lower to thermocure the resin and form a conductive resin layer. The atmosphere during this heat treatment is preferably N2 atmosphere. Furthermore, to prevent resin scattering and oxidation of the various metal components, the oxygen concentration is preferably suppressed to 100 ppm or lower.

[0123] In addition, as a method for applying conductive resin paste, it can be formed, for example, by using a process of extruding conductive resin paste from a slit and applying it, or by roller transfer printing.

[0124] (11) A plating layer is formed on the surface of the substrate electrode layer. In this embodiment, two plating layers are formed on the surfaces of the first substrate electrode layer and the second substrate electrode layer. Specifically, a Ni plating layer is formed on the first substrate electrode layer and the second substrate electrode layer, and a Sn plating layer is formed on the Ni plating layer. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by a roll plating method.

[0125] As described above, manufacturing Figure 1The embodiment shown relates to a multilayer ceramic capacitor 10.

[0126] 3. Experimental Example

[0127] Next, in order to confirm the effect of the multilayer ceramic capacitor involved in the present invention, as an experimental sample, a multilayer ceramic capacitor was manufactured according to the above manufacturing method as a sample in which the C-axis orientation was changed, and an experiment was conducted to confirm whether cracks caused by electrostriction test occurred.

[0128] (1) Specifications of the multilayer ceramic capacitor manufactured as an example

[0129] Multilayer ceramic capacitors, which are samples of Examples 1 to 5, were manufactured using the manufacturing method described in the above embodiments.

[0130] • Dimensions of the multilayer ceramic capacitor (design values): L×W×T = 1.19mm×0.68mm×0.68mm

[0131] Ceramic material: BaTiO3

[0132] • Capacitance: 10μF

[0133] • Material of the internal electrode layer: Ni

[0134] • Construction of external electrodes: conductive metal (Cu) and glass composition

[0135] · Coating layer

[0136] Two layers are formed: a Ni plating layer and a Sn plating layer.

[0137] Ni plating thickness: approximately 3μm

[0138] Sn plating thickness: approximately 5μm

[0139] (2) Specifications of the multilayer ceramic capacitor manufactured as a comparative example

[0140] A multilayer ceramic capacitor, serving as a comparative example, was manufactured using the manufacturing method described in the above embodiments. However, in the manufacturing process of the comparative example sample, the heating rate of step (7) of the manufacturing method was set to 5°C / min, the oxygen concentration was set to a lower level than that of the experimental example, and firing was performed. Other specifications were set to be the same as those of the sample in the embodiment.

[0141] (3) Method of electrostriction test

[0142] Electrostriction tests on the multilayer ceramic capacitors involved in each sample were conducted using a breakdown voltage measuring device. As detailed for the breakdown voltage measuring device, the voltage was boosted to DC 150V at a boost rate of 100V / sec.

[0143] (4) Crack detection methods

[0144] The detection of cracks in the samples was carried out using the following method: First, samples for which voltage was applied via the aforementioned electrostriction test were arranged with the main surface of the stacked ceramic capacitors facing upwards. Next, an ultrasonic probe was used to irradiate the upper surface of the stacked ceramic capacitors, and ultrasonic waves were irradiated to scan it. The reflected ultrasonic waves were observed, and the presence or absence of cracks was confirmed by detecting the reflected waves that returned earlier than the bottom surface waves.

[0145] Here, samples with confirmed cracks were counted as electrostrictive defects, and the crack incidence rate was calculated. For each embodiment and comparative example, 100 samples were prepared, and the crack incidence rate was measured. Then, the percentage of the total number of measurements (100 samples) to the number of cracks was defined as the crack incidence rate. In addition, regarding the criteria for judging the crack incidence rate, 0% or more and 4% or less was set as "〇", 5% or more and 80% or less was set as "△", and 81% or more and 100% or less was set as "×".

[0146] (5) Method for determining C-axis orientation

[0147] The C-axis orientation of the dielectric particles was obtained based on diffraction intensity measurements using SPring-8 transmission XRD. Specifically, as described above, the relative intensity ratios of the peak intensities of the plane orientations (400) and (040) obtained through Rietveld analysis to the data recorded on the ICDD card were calculated. This ratio was used as the measured intensity ratio, and then compared with the theoretical intensity ratio. The criteria for determining the C-axis orientation are as follows: When the C-axis orientation is 1, it is considered a random orientation, i.e., no C-axis orientation. When the C-axis orientation is greater than 1, it is considered a C-axis orientation.

[0148] (6) Results

[0149] Table 1 shows the C-axis orientation of dielectric particles, crack incidence, and determination results based on electrostriction tests for each sample of the multilayer ceramic capacitors according to Examples 1 to 5 and Comparative Example 1.

[0150] [Table 1]

[0151]

[0152] According to Table 1, in each sample of Examples 1 to 5, the dielectric particles in the dielectric layer were oriented on the C-axis, so the crack incidence rate was less than 5%, which yielded good results.

[0153] Furthermore, in each of the samples from Examples 2 to 5, the orientation degree of the C-axis was 1.6 or higher and 2.2 or lower, so the crack incidence rate was 0%, resulting in better results.

[0154] On the other hand, in the comparative example, the specimens were not oriented on the C-axis (C-axis orientation degree was 1), so the crack incidence rate was 93%.

[0155] Based on the above results, in this invention, by orienting the microcrystals in the dielectric particles contained in the dielectric layer along the C-axis, the amount of displacement of the dielectric layer is reduced when a high electric field is applied to the laminate. As a result, it is suggested that the electrostriction tolerance of the laminated ceramic capacitor can be improved.

[0156] Furthermore, as described above, embodiments of the present invention have been disclosed in the foregoing description, but the present invention is not limited thereto.

[0157] That is, without departing from the technical concept and scope of the present invention, various changes can be made to the above-described embodiments regarding the mechanism, shape, material, quantity, position or configuration, etc., and these are included in the present invention.

[0158] Explanation of reference numerals in the attached figures

[0159] 10: Multilayer ceramic capacitors;

[0160] 12: Layered body;

[0161] 12a: 1st main side;

[0162] 12b: 2nd main side;

[0163] 12c: First side view;

[0164] 12d: Second side view;

[0165] 12e: First end face;

[0166] 12f: Second end face;

[0167] 14: Dielectric layer;

[0168] 15a: Inner layer;

[0169] 15b1: First outer layer;

[0170] 15b2: Second outer layer;

[0171] 16: Internal electrode layer;

[0172] 16a: First internal electrode layer;

[0173] 16b: Second internal electrode layer;

[0174] 16c: Floating internal electrode layer;

[0175] 18a: First opposing electrode section;

[0176] 18b: Second opposing electrode section;

[0177] 20a: First lead-out electrode section;

[0178] 20b: Second lead-out electrode section;

[0179] 22a: Side;

[0180] 22b: End;

[0181] 26c: Opposing electrode section;

[0182] 30: External electrode;

[0183] 30a: First external electrode;

[0184] 30b: Second external electrode;

[0185] 32: Substrate electrode layer;

[0186] 32a: First base electrode layer;

[0187] 32b: Second base electrode layer;

[0188] 34: Plating layer;

[0189] 34a: First plating layer;

[0190] 34b: Second plating layer;

[0191] x: Height direction (stack direction);

[0192] y: width direction;

[0193] z: Length direction.

Claims

1. A multilayer ceramic capacitor, comprising: A laminate comprising a plurality of stacked dielectric layers, and having a first main surface and a second main surface opposite to each other in the stacking direction of the plurality of dielectric layers, a first side surface and a second side surface opposite to each other in a width direction orthogonal to the stacking direction, and a first end surface and a second end surface opposite to each other in a length direction orthogonal to the stacking direction and the width direction. A first internal electrode layer is disposed on the plurality of dielectric layers and exposed at the first end face; A second internal electrode layer is disposed on the plurality of dielectric layers and exposed at the second end face; The first external electrode has a base electrode layer disposed on the first end face and a plating layer disposed on the base electrode layer; and The second external electrode has a base electrode layer disposed on the second end face and a plating layer disposed on the base electrode layer. The microcrystals in the dielectric particles contained in the dielectric layer are oriented along the C-axis.

2. The multilayer ceramic capacitor according to claim 1, wherein, The orientation degree of the microcrystals in the dielectric particles relative to the C-axis, i.e., the C-axis orientation degree, is greater than 1.6 and less than 2.

2.

3. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein, The relative permittivity of the dielectric particles is above 1000.

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