Data readout structure, temperature sensor and electronic device
By employing data weighting averaging technology and dynamic element matching in the CMOS temperature sensor, the error problem caused by poor capacitor matching in the capacitor array is solved, thereby improving the measurement accuracy of the temperature sensor.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NINGBO AURA SEMICON CO LTD
- Filing Date
- 2025-12-29
- Publication Date
- 2026-05-15
AI Technical Summary
Existing CMOS temperature sensors based on bipolar junction transistors have shortcomings in measurement accuracy, especially due to large errors caused by poor capacitance matching in the capacitor array.
The Data Weighted Averaging (DWA) technique is employed, which selects different capacitor cells as the first and second sampling capacitors in each sampling clock cycle and cyclically selects all capacitor cells in the capacitor array for sampling. Combined with dynamic component matching technology, this ensures parameter matching between capacitor cells, thereby reducing mismatch errors.
By using DWA technology and dynamic component matching, mismatch errors in the capacitor array are reduced, improving the measurement accuracy of the temperature sensing system and achieving higher temperature measurement accuracy.
Smart Images
Figure CN121409433B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic circuit technology, and in particular to a data readout structure, a temperature sensor, and an electronic device. Background Technology
[0002] Temperature sensors are widely used in various electronic devices that require high-precision temperature monitoring, such as smartphones, wearable devices, industrial control systems, and automotive electronics. Among them, complementary metal-oxide-semiconductor (CMOS) temperature sensors have become the mainstream choice in the field of temperature measurement due to their high integration, low power consumption, and good compatibility.
[0003] The basic principle of CMOS temperature sensors based on bipolar junction transistors (BJTs, commonly known as triodes) is usually to use the temperature characteristics of transistors to sense temperature changes.
[0004] However, the measurement accuracy of CMOS temperature sensors in BJT temperature sensing devices in related technologies needs to be improved. Summary of the Invention
[0005] The purpose of this application is to provide a data readout structure, a temperature sensor, and an electronic device, at least to improve the measurement accuracy of a temperature sensing system.
[0006] This application provides a data readout structure for data readout from a sensing front-end 200 in a CMOS temperature sensor, comprising: a signal sampling module 101 configured to sample a first sensing voltage VBE1 output by the sensing front-end 200 to generate a first sampling voltage, and to sample the difference between a second sensing voltage VBE2 output by the sensing front-end 200 and the first sensing voltage VBE1 to generate a second sampling voltage; a data processing module 102 connected to the signal sampling module 101 configured to perform integration and quantization on the first sampling voltage and the second sampling voltage to read out the sensed temperature signal Dout; and a control module 103 connected to the signal sampling module 101 and... The data processing module 102 is configured to perform dynamic component matching on the signal sampling module 101 and the data processing module 102, and control the data processing module 102 to read out the sensed temperature signal Dout; wherein, the signal sampling module 101 includes at least a capacitor array; the process of the control module 103 performing the dynamic component matching includes: in each sampling clock cycle, selecting a first target capacitor from the capacitor array as a first sampling capacitor to sample the first sensed voltage VBE1, and selecting a second target capacitor from the capacitor array as a second sampling capacitor to sample the difference between the second sensed voltage VBE2 and the first sensed voltage VBE1.
[0007] The capacitor array includes multiple capacitor units (Cunits), and the multiple capacitor units (Cunits) are arranged in a common centroid manner.
[0008] The signal sampling module 101 includes: a first capacitor unit, which serves as the first sampling capacitor selected by the control module 103 to sample the first sensed voltage VBE1; the first capacitor unit includes a first capacitor Css1 and a second capacitor Css2; in the sampling phase, the first plate of the first capacitor Css1 receives the first sensed voltage VBE1, the second plate of the first capacitor Css1 serves as the inverting output terminal outn of the signal sampling module 101, the first plate of the second capacitor Css2 is grounded, and the second plate of the second capacitor Css2 serves as the non-inverting output terminal outp of the signal sampling module 101; the second capacitor unit, as... The second sampling capacitor selected by the control module 103 is used to sample the difference between the second sensed voltage VBE2 and the first sensed voltage VBE1; the second capacitor unit includes a first capacitor group kCsg1 and a second capacitor group kCsg2; in the sampling phase, the first plate of the first capacitor group kCsg1 is connected to the first plate of the first capacitor Css1, the second plate of the first capacitor group kCsg1 is connected to the second plate of the first capacitor Css1, the first plate of the second capacitor group kCsg2 receives the second sensed voltage VBE2, and the second plate of the second capacitor group kCsg2 is connected to the second plate of the second capacitor Css2.
[0009] In the integrating phase, the first plate of the first capacitor Css1 is grounded, and the second plate of the first capacitor Css1 serves as the inverting output terminal outn of the signal sampling module 101. The first plate of the second capacitor Css2 receives the first sensed voltage VBE1, and the second plate of the second capacitor Css2 serves as the non-inverting output terminal outp of the signal sampling module 101. In the integrating phase, the first plate of the first capacitor group kCsg1 receives the second sensed voltage VBE2, the second plate of the first capacitor group kCsg1 is connected to the second plate of the first capacitor Css1, the first plate of the second capacitor group kCsg2 is connected to the first plate of the second capacitor Css2, and the second plate of the second capacitor group kCsg2 is connected to the second plate of the second capacitor Css2.
[0010] The data processing module 102 includes at least a first integrator 301 and an integrating capacitor unit corresponding to the first integrator 301. The integrating capacitor unit includes a third capacitor Ci1 and a fourth capacitor Ci2. The first plate of the third capacitor Ci1 is connected to the non-inverting output terminal vop of the first integrator 301, and the second plate of the third capacitor Ci1 is connected to the inverting input terminal Vin of the first integrator 301 and the inverting output terminal outn of the signal sampling module 101 after passing through a first switch K1. The first plate of the fourth capacitor Ci2 is connected to the inverting output terminal von of the first integrator 301, and the second plate of the fourth capacitor Ci2 is connected to the non-inverting input terminal Vip of the first integrator 301 and the non-inverting output terminal outp of the signal sampling module 101 after passing through a second switch K2.
[0011] The process of the control module 103 performing the dynamic element matching also includes: selecting a third target capacitor from the capacitor array as the integrating capacitor unit in each sampling clock cycle.
[0012] The control module 103 includes: a first pointer sel_csg, a second pointer sel_css, and a third pointer sel_ci. The first pointer sel_csg is used to select the second target capacitor from the capacitor array, the second pointer sel_css is used to select the first target capacitor from the capacitor array, and the third pointer sel_ci is used to select the third target capacitor from the capacitor array. In the current sampling clock, the first pointer sel_csg is the sum of the first pointer sel_csg in the previous sampling clock and a first preset value, the second pointer sel_css is the sum of the first pointer sel_csg and a second preset value, and the third pointer sel_ci is the sum of the second pointer sel_css and a third preset value.
[0013] The data processing module 102 includes: a first integrator 301, with its input terminal connected to the output terminal of the signal sampling module 101, its non-inverting output terminal VOP connected to the boost terminal VFBP of the signal sampling module 101, and its inverting output terminal VON connected to the buck terminal VFBN of the signal sampling module 101; a second integrator 302, with its input terminal connected to the output terminal of the first integrator 301; an adder 303, with its first input terminal AP connected to the non-inverting output terminal VOP of the first integrator 301, its second input terminal BP connected to the non-inverting output terminal VOP of the second integrator 302, its third input terminal BN connected to the inverting output terminal VON of the first integrator 301, and its fourth input terminal An connected to the inverting output terminal VON of the second integrator 302; and a quantizer 304, with its input terminal connected to the output terminal of the adder 303.
[0014] This application also provides a temperature sensor, including: a sensing front end configured to sense the temperature of a measured object to output a first sensing voltage and a second sensing voltage; and a reading back end connected to the sensing front end configured to generate a sensing temperature signal based on the first sensing voltage and the second sensing voltage; wherein the reading back end includes the data readout structure described above.
[0015] This application also provides an electronic device, including the temperature sensor described above.
[0016] The technical solution provided in this application has at least the following advantages: By configuring a capacitor array for the signal sampling module, and by cyclically selecting different capacitor units as the first and second sampling capacitors in each sampling clock cycle, after a certain period, all capacitor units in the capacitor array can be selected for sampling (Data Weighted Averaging, DWA). Through this mechanism, the average value of the ADC error after one complete cycle is 0. That is, after one complete cycle, the mismatch error between the ADCs can be averaged by the first order, and then the remaining high-frequency error components are filtered out by the subsequent filter. Alternatively, DWA can shift the ADC error to the high-frequency range, perform noise-shaping-like processing on the ADC error, and then filter it out by a digital filter, reducing the mismatch between the first and second sampling capacitors in a simpler way, thereby improving the measurement accuracy of the temperature sensing system. Attached Figure Description
[0017] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.
[0018] Figure 1 This is a schematic diagram of the structure of a traditional CMOS temperature sensor;
[0019] Figure 2 This is a schematic diagram of the specific structure of the sensing front-end circuit, sampling interface circuit, and integration circuit in a traditional CMOS temperature sensor.
[0020] Figure 3 This is a schematic diagram of the module structure of a data readout structure provided in an embodiment of this application;
[0021] Figure 4 This is a schematic diagram of the specific circuit connection of the signal sampling module under the sampling phase according to an embodiment of this application;
[0022] Figure 5This is a schematic diagram of the specific circuit connection of the signal sampling module in the integrating phase according to an embodiment of this application;
[0023] Figure 6 This is a schematic diagram of the first part of the structure of a data processing module provided in an embodiment of this application;
[0024] Figure 7 This is a schematic diagram of the second part of the structure of the data processing module provided in one embodiment of this application;
[0025] Figure 8 This is a schematic diagram of the specific circuit of the first integrator provided in an embodiment of this application;
[0026] Figure 9 This is a schematic diagram of the specific circuit of the second integrator provided in one embodiment of this application. Detailed Implementation
[0027] As can be seen from the background technology, the measurement accuracy of complementary metal-oxide-semiconductor (CMOS) temperature sensors for bipolar junction transistor (BJT) temperature sensing devices needs to be improved.
[0028] In one example, such as Figure 1 As shown, the CMOS temperature sensing system 10 includes a front-end sensing circuit 11, a conversion circuit 12, and a digital back-end processing circuit 13.
[0029] refer to Figure 1 and Figure 2 For the front-end sensing circuit 11, in the field of temperature sensor technology based on CMOS technology, BJT-based temperature sensors are a common type. These sensors typically utilize the characteristics of the base-emitter voltage VBE of a BJT changing with temperature, and the characteristics of the base-emitter voltage difference ΔVBE of two BJTs changing with temperature under specific operating conditions, to measure temperature.
[0030] Taking a PNP type BJT as an example, its basic principle is: two identical PNP transistors Q L and Q R With 1:P ( Figure 2 For example, a current ratio of 1:5 is used for biasing, Q L The base-emitter voltage VBE1 exhibits temperature-to-absolute (CTAT) complementary characteristics, while Q... L and Q R The base-emitter voltage difference ΔVBE = VBE²(Q) RThe base-emitter voltage (VBE1) is proportional to the absolute temperature (PTAT), which can be expressed by the following formulas 1 and 2:
[0031] Formula 1
[0032] Formula 2
[0033] Where η is a process-related non-ideal factor, k is the Boltzmann constant, q is the electron charge, T is the Kelvin temperature, Ic is the collector current, Is is the saturation current of the PNP, and p = Ic / Is.
[0034] In some examples, VBE1 and ΔVBE are linearly combined to generate a reference voltage VREF, VREF = VBE1 + α × ΔVBE, where α is the gain coefficient.
[0035] Next, the ratio of α×ΔVBE to the reference voltage VREF is digitized using an analog-to-digital converter (ADC) (as shown in Formula 3 below). The resulting digital ratio μ is a linear function of temperature.
[0036] Formula 3
[0037] In other examples, the ratio X of VBE1 to ΔVBE is further generated in the conversion circuit 12, and the ADC is used to convert X from analog to digital to obtain the value μ, as shown in Formula 4 below:
[0038] Formula 4
[0039] Regardless of the conversion scheme, it can be understood that the ADC converts the analog quantities (VBE1, ΔVBE, X, etc.) representing temperature information into corresponding digital quantities.
[0040] For the conversion circuit 12 and the digital back-end processing circuit 13, the conversion circuit 12 generates a voltage proportional to absolute temperature (PTAT) and a reference voltage by combining VBE (the aforementioned VBE1) and ΔVBE in a specific manner, and then uses an analog-to-digital converter (ADC) to convert them into an analog quantity representing temperature information; the digital back-end processing circuit 13 processes the analog quantity accordingly and outputs the sensed temperature signal Dout.
[0041] Specifically, the conversion circuit 12 utilizes the negative temperature coefficient (CTAT) characteristic of VBE and the PTAT characteristic of ΔVBE to make the reference voltage VREF approximately constant within a certain temperature range by adjustment. The conversion circuit 12 converts the voltage ratio into an analog quantity μ according to the following formula 5, where X = VBE / ΔVBE.
[0042] Formula 5
[0043] The digital back-end processing circuit 13 converts the analog quantity μ into a sensed temperature signal Dout in degrees Celsius based on the following formula 6, where A and B are constants.
[0044] Formula 6
[0045] against Figure 1 The CMOS temperature sensing system 10 shown typically employs a series of techniques to improve its measurement accuracy. For example, to reduce the offset voltage of the operational amplifier in the circuit, chopping technology is used in the front-end sensing circuit 11 and the conversion circuit 12 of the CMOS temperature sensing system 10 to improve accuracy; to reduce the mismatch between circuit components, the current branch in the front-end sensing circuit 11 and the capacitor array in the conversion circuit 12 are dynamically matched using Dynamic Elements Matching (DEM) technology.
[0046] If the conversion circuit 12 is a zoom-adc architecture, the power efficiency of the formed CMOS temperature sensing system 10 can be improved. Specifically, with the zoom-adc architecture, it is not necessary to generate an analog reference voltage VREF in the front-end sensing circuit 11. Instead, a sampling integration method is used in the sampling interface circuit between the front-end sensing circuit 11 and the conversion circuit 12 to sample VBE and ΔVBE and calculate X=VBE / ΔVBE. This architecture avoids the need for a high-precision analog bias circuit to generate the reference voltage VREF.
[0047] like Figure 1 and Figure 2 As shown [ Figure 2 (a) in the diagram is a circuit diagram of the sampling phase. Figure 2 [In diagram (b), which is a circuit diagram of the integrating phase], Cs capacitor refers to the capacitance value of the capacitor being Cs, 2Cs capacitor refers to the capacitance value of the capacitor being 2Cs, and KCs refers to the overall capacitance composed of K Cs capacitors, with a capacitance value of KCs. The output terminal of the front-end sensing circuit 11 is connected to the sampling interface circuit 14, and the output terminal of the sampling interface circuit 14 is connected to the integrating circuit 15. The integrating circuit 15 is the integrator in the conversion circuit 12, and Vint is the integrated voltage output by the integrating circuit 15. The conversion circuit 12 then quantizes the integrated voltage Vint to generate an analog quantity.
[0048] based on Figure 2 As shown in the circuit example, the principle by which the sampling interface circuit 14 calculates VBE=X×△VBE is as follows:
[0049] The amount of charge Q sampled in the sampling phase 1s_diff Obtained based on the following formula 7.
[0050] Formula 7
[0051] The charge Q sampled in the integrating phase 2s_diff Obtained based on the following formula 8.
[0052] Formula 8
[0053] During the later stage of integration, the current integral output voltage increment ΔV out_diff If the reference voltage VREF of the SDM conversion is taken as the lower boundary j×△VBE, the derivation is as follows: Formula 9.
[0054] Formula 9
[0055] Similarly, when the reference voltage Vref of the SDM conversion is taken as the upper boundary (j+1)×△VBE, the derivation is as follows: Formula 10.
[0056] Formula 10
[0057] Where j represents an intermediate variable in the analog-to-digital conversion process, and the average value of j eventually converges to the value of X; in the SDM conversion, VBE1 can be considered as the input signal, X×△VBE as the first reference voltage signal Vref-, (X+1)×△VBE as the second reference voltage signal Vref+, and the first reference voltage signal Vref- and the second reference voltage signal Vref+ constitute the reference voltage Vref.
[0058] Analysis revealed that although the CMOS temperature sensing system 10 based on the zoom-adc architecture achieves a certain degree of high temperature measurement accuracy, the Cs capacitor and the overall KCs capacitor in the sampling interface circuit 14 both participate in the sampling and calculation of VBE and ΔVBE. As can be seen from the above formula, the accurate matching of the Cs capacitor and the overall KCs capacitor is extremely important. Due to the low-pass transmission characteristics in analog-to-digital conversion, any mismatch between the Cs capacitor and the overall KCs capacitor will directly enter the conversion circuit 12 and be converted into an error in the sensed temperature signal Dout.
[0059] In one example, to achieve a measurement accuracy of 0.05 degC, the capacitance matching between the K individual Cs capacitors in the overall KCs capacitance, as well as the capacitance matching between the Cs capacitors and the overall KCs capacitance, needs to achieve a matching accuracy of 0.0375%.
[0060] To address the stringent requirements for improving sensing accuracy in temperature sensing systems, this application provides a data readout structure for data readout from the sensing front end of a CMOS temperature sensor. The structure includes: a signal sampling module configured to sample a first sensing voltage output from the sensing front end to generate a first sampling voltage, and to sample the difference between a second sensing voltage output from the sensing front end and the first sensing voltage to generate a second sampling voltage; a data processing module connected to the signal sampling module, configured to integrate and quantize the first and second sampling voltages to read out the sensed temperature signal; and a control module connected to the signal sampling module and the data processing module, configured to perform dynamic component matching on the signal sampling module and the data processing module, and control the data processing module to read out the sensed temperature signal. The signal sampling module includes at least a capacitor array. The dynamic component matching process performed by the control module includes: in each sampling clock cycle, selecting a first target capacitor from the capacitor array as the first sampling capacitor to sample the first sensing voltage, and selecting a second target capacitor from the capacitor array as the second sampling capacitor to sample the difference between the second and first sensing voltages.
[0061] This embodiment configures a capacitor array for the signal sampling module. By cyclically selecting different capacitor units as the first and second sampling capacitors in each sampling clock cycle, after a certain period, all capacitor units in the array can be selected for sampling (Data Weighted Averaging, DWA). Through this mechanism, the average error of the ADC after one complete cycle is 0. That is, after one complete cycle, the mismatch error between the ADCs can be averaged using a first-order method, and then the remaining high-frequency error components are filtered out by a subsequent filter. Alternatively, DWA can be said to shift the ADC error to a higher frequency range, performing a noise-shaping-like process on the ADC error before filtering it out by a digital filter. This reduces the mismatch between the first and second sampling capacitors in a relatively simple way, thereby improving the measurement accuracy of the temperature sensing system.
[0062] Specifically, dynamic component matching techniques also include: single-stage averaging, clock averaging, randomization, and data weight averaging (DWA). In SD (Sigma-Delta) ADCs, especially multi-bit SD ADCs, DWA is commonly used. DWA's error handling process for the ADC manifests as first-order noise shaping. Mathematically, the original analog signal is correctly encoded and decoded; however, the mismatch noise undergoes first-order noise shaping over a long period. After DWA, the ADC error expression is as follows: Equation 11.
[0063] Formula 11
[0064] Where △Ci represents the difference between Ci and E(Ci), and E(Ci) is the average value of the selected capacitors in the corresponding period. The summation in Formula 11 is called the integral mismatch term.
[0065] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the various embodiments of this application to help readers better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments. The division of the various embodiments below is for the convenience of description and should not constitute any limitation on the specific implementation of this application. The various embodiments can be combined with and referenced by each other without contradiction.
[0066] One embodiment of this application relates to a data readout structure 100, such as... Figure 3 As shown, the data readout structure 100 is used for data readout from the sensing front end 200 in the CMOS temperature sensor. The sensing front end 200 is the same as the aforementioned front-end sensing circuit 11, and will not be described again in this embodiment.
[0067] The data readout structure 100 includes a signal sampling module 101, a data processing module 102, and a control module 103. The signal sampling module 101 is configured to sample the first sensing voltage VBE1 output by the sensing front end 200 to generate a first sampling voltage, and to sample the difference ΔVBE between the second sensing voltage VBE2 output by the sensing front end 200 and the first sensing voltage VBE1 to generate a second sampling voltage.
[0068] The data processing module 102 is connected to the signal sampling module 101. The data processing module 102 is configured to perform integration and quantization on the first sampling voltage and the second sampling voltage to read out the sensed temperature signal Dout.
[0069] The control module 103 is connected to the signal sampling module 101 and the data processing module 102. The control module 103 is configured to perform dynamic component matching on the signal sampling module 101 and the data processing module 102, and control the data processing module 102 to read out the sensed temperature signal Dout.
[0070] The signal sampling module 101 includes at least a capacitor array, which includes multiple capacitor units (Cunit). The dynamic component matching process performed by the control module 103 includes: selecting a corresponding capacitor unit (Cunit) from the capacitor array as a first target capacitor in each sampling clock cycle, using the first target capacitor as the first sampling capacitor in the signal sampling module 101 to sample the first sense voltage; and selecting a corresponding capacitor unit (Cunit) from the capacitor array as a second target capacitor, using the second target capacitor as the second sampling capacitor in the signal sampling module 101 to sample the difference ΔVBE between the second sense voltage VBE2 and the first sense voltage VBE1.
[0071] This embodiment configures a capacitor array for the signal sampling module 101. In each sampling clock cycle, different capacitor units (Cunits) are cyclically selected as the first and second sampling capacitors. After a certain period, all capacitor units (Cunits) in the array can be selected for sampling. Through this mechanism, the average error of the ADC after one complete cycle is 0. That is, after one complete cycle, the mismatch error between the ADCs can be averaged using a first-order method, and then the remaining high-frequency error components are filtered out by a subsequent filter. Alternatively, DWA can shift the ADC error to a higher frequency range, performing noise-shaping-like processing on the ADC error before filtering it out by a digital filter. This reduces the mismatch between the first and second sampling capacitors in a simpler way, thereby improving the measurement accuracy of the temperature sensing system.
[0072] For the data processing module 102, in one example, the data processing module 102 is configured as a zoom-adc, and its analog-to-digital conversion workflow includes: SAR conversion process and SDM conversion process. Generally, the SAR conversion process is performed first. The Mbits data (M is the number of capacitor units in the capacitor array) output by the SAR conversion process serves as both the MSB of the overall output of the zoom-adc and the reference voltage Vref required for the SDM conversion process is obtained through the value of M. Then, the SDM conversion process is performed. The SDM conversion process can be referred to the relevant descriptions in Formulas 7 to 10 above, which will not be repeated in this embodiment.
[0073] It should be noted that the entire conversion process of the data processing module 102 is performed under the control of the control module 103. In some embodiments, the control module 103 includes an SAR timing control unit, an SDM timing control unit, and a CIC filtering unit, etc.
[0074] Since the first and second sampling capacitors need to maintain parameter matching, otherwise the analog signal converted by the ADC will have errors. Therefore, in some embodiments, multiple capacitor units (Cunits) in the capacitor array are arranged in a common centroid manner to ensure parameter matching between the selected first and second sampling capacitors, thereby ensuring the temperature readout accuracy of the data readout structure 100.
[0075] For signal sampling module 101, refer to Figure 4 The signal sampling module 101 includes: a first capacitor unit, which serves as the first sampling capacitor selected by the control module 103 to sample the first sense voltage VBE1; the first capacitor unit includes a first capacitor Css1 and a second capacitor Css2; in the sampling phase, the first plate of the first capacitor Css1 receives the first sense voltage VBE1, the second plate of the first capacitor Css1 serves as the inverting output terminal outn of the signal sampling module 101, the first plate of the second capacitor Css2 is grounded, and the second plate of the second capacitor Css2 serves as the non-inverting output terminal outp of the signal sampling module 101.
[0076] Specifically, the control module 103 selects a first target capacitor as the first capacitor Css1 in the capacitor array and selects a first target capacitor as the second capacitor Css2 in the capacitor array, thereby realizing the sampling of the first sensing voltage VBE1.
[0077] The signal sampling module 101 further includes: a second capacitor unit, which serves as the second sampling capacitor selected by the control module 103 to sample the difference between the second sensing voltage VBE2 and the first sensing voltage VBE1; the second capacitor unit includes a first capacitor group kCsg1 and a second capacitor group kCsg2; in the sampling phase, the first plate of the first capacitor group kCsg1 is connected to the first plate of the first capacitor Css1, the second plate of the first capacitor group kCsg1 is connected to the second plate of the first capacitor Css1, the first plate of the second capacitor group kCsg2 receives the second sensing voltage VBE2, and the second plate of the second capacitor group kCsg2 is connected to the second plate of the second capacitor Css2.
[0078] Specifically, the control module 103 selects k second target capacitors in the capacitor array as the first capacitor group kCsg1, and selects k second target capacitors in the capacitor array as the second capacitor group kCsg2, thereby realizing the sampling of the difference between the second sensing voltage VBE2 and the first sensing voltage VBE1.
[0079] Combination Figure 4 And refer to Figure 5In the integrating phase, the first plate of the first capacitor Css1 is grounded, and the second plate of the first capacitor Css1 serves as the inverting output terminal outn of the signal sampling module 101. The first plate of the second capacitor Css2 receives the first sensing voltage VBE1, and the second plate of the second capacitor Css2 serves as the non-inverting output terminal outp of the signal sampling module 101. In the integrating phase, the first plate of the first capacitor group kCsg1 receives the second sensing voltage VBE2, and the second plate of the first capacitor group kCsg1 is connected to the second plate of the first capacitor Css1. The first plate of the second capacitor group kCsg2 is connected to the first plate of the second capacitor Css2, and the second plate of the second capacitor group kCsg2 is connected to the second plate of the second capacitor Css2.
[0080] like Figure 4 and Figure 5 As shown, the signal sampling module 101 acts as a signal bridge between the sensing front end 200 and the data processing module 102 in the data readout structure 100. In some embodiments, since the first capacitor unit and the second capacitor unit are selected based on the capacitor unit Cunit in the same capacitor array, and the capacitor units Cunit in the same capacitor array are set with a common centroid, the parameters between the capacitor units Cunit are more matched, and the error introduced into the ADC is smaller, so as to improve the temperature readout accuracy of the data readout structure 100.
[0081] Continue to refer to Figure 4 and Figure 5 In some embodiments, the data processing module 102 includes at least a first integrator 301 and an integrating capacitor unit corresponding to the first integrator 301. The integrating capacitor unit includes a third capacitor Ci1 and a fourth capacitor Ci2. The first plate of the third capacitor Ci1 is connected to the non-inverting output terminal vop of the first integrator 301, and the second plate of the third capacitor Ci1 is connected to the inverting input terminal Vin of the first integrator 301 and the inverting output terminal outn of the signal sampling module 101 through a first switch K1. That is, the inverting input terminal Vin of the first integrator 301 is connected to the inverting output terminal outn of the signal sampling module 101. The first plate of the fourth capacitor Ci2 is connected to the inverting output terminal von of the first integrator 301, and the second plate of the fourth capacitor Ci2 is connected to the non-inverting input terminal Vip of the first integrator 301 and the non-inverting output terminal outp of the signal sampling module 101 through a second switch K2. That is, the non-inverting input terminal Vip of the first integrator 301 is connected to the non-inverting output terminal outp of the signal sampling module 101.
[0082] refer to Figure 4During the sampling phase, the first switch K1 and the second switch K2 are open. At this time, the node between the third capacitor Ci1 and the first switch K1 stores the charge of the first integrator 301 in the previous cycle, and the node between the fourth capacitor Ci2 and the second switch K2 stores the charge of the integrator in the previous cycle. (Reference) Figure 5 During the integration phase, the first switch K1 and the second switch K2 are closed, and the stored charge is added to the charge obtained from the current sampling, thus realizing the charge accumulation, which is the integration behavior.
[0083] To ensure parameter matching between the integrating capacitor unit and the first and second capacitor units, the dynamic component matching process of the control module 103 further includes selecting a third target capacitor from the capacitor array as the integrating capacitor unit in each sampling clock cycle. By selecting a capacitor unit Cunit from the capacitor array as the integrating capacitor unit, the consistency of the capacitor parameters in the signal sampling module 101 is further ensured, thereby improving the temperature readout accuracy of the data readout structure 100.
[0084] Specifically, the control module 103 selects a third target capacitor in the capacitor array as the third capacitor Ci1, and selects a third target capacitor in the capacitor array as the fourth capacitor Ci2, thereby realizing the capacitor component corresponding to the first integrator 301.
[0085] In addition, for Figure 4 and Figure 5 For example, mode switches are connected in parallel across the terminals of the third capacitor Ci1 and the fourth capacitor Ci2. When the mode switches are closed, the third capacitor Ci1 and the fourth capacitor Ci2 are short-circuited, i.e., the integrating capacitor unit is short-circuited, and the signal sampling module 101 is in the sampling phase. When the mode switches are open, the third capacitor Ci1 and the fourth capacitor Ci2 are connected to the signal path between the sensing front end 200 and the first integrator 301, i.e., the integrating capacitor unit is connected to the circuit, and the signal sampling module 101 is in the integrating phase.
[0086] Regarding the selection of the first target capacitor, the second target capacitor, and the third target capacitor by the control module 103, in some embodiments, the control module includes a first pointer sel_csg, a second pointer sel_css, and a third pointer sel_ci, wherein the first pointer sel_csg is used to select the second target capacitor from the capacitor array, the second pointer sel_css is used to select the first target capacitor from the capacitor array, and the third pointer sel_ci is used to select the third target capacitor from the capacitor array.
[0087] In the current sampling clock, the second pointer sel_css is the sum of the first pointer sel_csg and the first preset value, and the third pointer sel_ci is the sum of the second pointer sel_css and the second preset value; in the next sampling clock, the first pointer sel_csg is the sum of the third pointer sel_ci and the third preset value in the current sampling clock.
[0088] Specifically, the core of the DWA algorithm is as follows: the first target capacitor, the second target capacitor, and the third target capacitor each have an independent pointer: a second pointer sel_css, a first pointer sel_csg, and a third pointer sel_ci. Each pointer determines the position of the capacitor cell it points to in the current sampling clock based on its initial state, the pointer state under the previous sampling clock, and the state of Din under the previous sampling clock.
[0089] In one example, using a 35-bit first pointer sel_csg, second pointer sel_css, and third pointer sel_ci, the Css capacitor used for sampling VBE1 will select one capacitor cell starting from the position next to the position occupied by the Csg capacitor for sampling VBE1. The Ci capacitor used for integration will select two capacitor cells starting from the position next to the position occupied by the Css capacitor, taking the integration capacitor of the first-stage integrator as an example.
[0090] Specifically, sel_csg<34:0>=Din_q<4:0>+sel_csg<34:0>+3, sel_css<34:0>=sel_csg<3 4:0>+Din<4:0>; sel_ci<34:0>=sel_css<34:0>+Din<4:0>+1, Din_q<4:0>=Din<4:0>.
[0091] Din<4:0> and Din_q<4:0> are used to determine the first preset value, the second preset value, and the third preset value, wherein the first preset value is Din_q<4:0>+3, the second preset value is Din<4:0>, and the third preset value is Din<4:0>+1.
[0092] The pointer values of the first, second, and third pointers under some sampling clocks in this example are shown in Table 1 below.
[0093] Table 1
[0094]
[0095] The first target capacitor, second target capacitor, and third target capacitor selected by the first, second, and third pointers are shown in Table 2 below.
[0096] Table 2
[0097]
[0098] In this symbol, "##" represents the current position of the first pointer, and "#" and "##" represent the second target capacitor selected by the first pointer; "$$" represents the current position of the second pointer and the first target capacitor selected by the second pointer; "&&" represents the current position of the third pointer, and "&&" and "&" represent the third target capacitor selected by the third pointer.
[0099] It should be noted that the above examples are only for those skilled in the art to understand the setting methods of the first, second, and third pointers, and do not constitute a limitation on the first, second, and third preset values. In specific applications, the relative relationship between the first, second, and third pointers can be flexibly set according to the number of capacitor units introduced as required.
[0100] refer to Figure 6 and Figure 7 For the signal sampling module 101, one input terminal of the signal sampling module 101 receives the first sensing voltage VBE1 output by the sensing front end, and another input terminal receives the second sensing voltage VBE2 output by the sensing front end. Other input signals, such as ph2, ph1d, chop_sel, adc_test_en, sel_css, sel_csg, sel_ci and rstb, are used for switching the sampling phase / integration phase in the signal sampling module 101, selecting capacitor units in the capacitor array, chopping selection and resetting, etc., so as to control the working mode of the signal sampling module 101 based on the control module 103.
[0101] The data processing module 102 includes a first integrator 301, a second integrator 302, an adder 303, and a quantizer 304.
[0102] The input terminal of the first integrator 301 is connected to the output terminal of the signal sampling module 101. Specifically, the non-inverting input terminal vip of the first integrator 301 is connected to the non-inverting output terminal outp of the signal sampling module 101 to receive the non-inverting sampled signal Integ1_inn, and the inverting input terminal vin of the first integrator 301 is connected to the inverting output terminal outn of the signal sampling module 101 to receive the inverting sampled signal Integ1_inp. In addition, the non-inverting output terminal vop of the first integrator 301 is connected to the boost terminal vfbp of the signal sampling module 101, and the inverting output terminal von of the first integrator 301 is connected to the buck terminal vfbn of the signal sampling module 101 to realize voltage feedback to the signal sampling module 101.
[0103] For the first integrator 301, refer to Figure 8 The first integrator 301 includes a first power amplifier Am1, a first switch, and a second switch. The first switch and the second switch are turned off or closed based on the ph1 received by the control terminal f1 of the first integrator. When the first switch and the second switch are closed, the input terminal and the output terminal of the first power amplifier Am1 are short-circuited, and the first integrator 301 is not connected to the data processing module 102 at this time. When the first switch and the second switch are turned off, the first integrator 301 is connected to the data processing module 102.
[0104] Continue to refer to Figure 7 and Figure 8 The input terminal of the second integrator 302 is connected to the output terminal of the first integrator 301. The non-inverting output terminal vop of the first integrator 301 is connected to the non-inverting input terminal vip of the second integrator 302 to transmit the first non-inverting integration signal Integ2_inp. The inverting output terminal von of the first integrator 301 is connected to the inverting input terminal vin of the second integrator 302 to transmit the first inverting integration signal Integ2_inn.
[0105] For the second integrator 302, refer to Figure 9 The second integrator 302 includes a second power amplifier Am2, a reset switch, a first switch group, a second switch group, a third switch group, a fourth switch group, a first sampling capacitor CS, and a second sampling capacitor CI. The first switch group controls whether PH2, connected to the control terminal f1 of the second integrator 302, is in an off or closed state; the second switch group controls whether PH1, connected to the control terminal f2 of the second integrator 302, is in an off or closed state; the third switch group controls whether PH2D, connected to the control terminal f3 of the second integrator 302, is in an off or closed state; and the fourth switch group controls whether PH1D, connected to the control terminal f4 of the second integrator 302, is in an off or closed state. The first, second, third, and fourth switch groups are used to determine the connection method of the first sampling capacitor CS. The reset switch group RSTB connects to the input and output terminals of the second power amplifier Am2 to determine whether the second power amplifier Am2 is connected to the data processing module 102.
[0106] For adder 303 and quantizer 304, adder 303 has its first input terminal ap connected to the non-inverting output terminal vop of the first integrator 301, its second input terminal bp connected to the non-inverting output terminal vop of the second integrator 302, its third input terminal bn connected to the inverting output terminal von of the first integrator 301, and its fourth input terminal an connected to the inverting output terminal von of the second integrator 302. Quantizer 304 has its input terminals connected to the output terminals of adder 303. Specifically, the non-inverting output terminal adop of adder 303 is connected to the non-inverting input terminal q_inp of quantizer 304, and the inverting output terminal adon of adder 303 is connected to the inverting input terminal q_inn of quantizer 304. Adder 303 accumulates the first positive-phase integral signal Integ2_inp received at the first input terminal ap and the second positive-phase integral signal Integ2_outp received at the second input terminal bp, and outputs q_inp through the first output terminal adop. Adder 303, controlled by switch sbp, accumulates the first negative-phase integral signal Integ2_inn received at the third input terminal bn and the second negative-phase integral signal Integ2_outn received at the fourth input terminal an, and outputs q_inn through the second output terminal adon.
[0107] Quantizer 304 quantizes based on q_inp and q_inn to generate q_outp and q_outn. Data processing module 102 then further processes q_outp and q_outn to generate the sensed temperature signal Dout.
[0108] In summary, the data readout structure 100 provided in this application configures a capacitor array for the signal sampling module 101. By cyclically selecting different capacitor units (Cunits) as the first and second sampling capacitors in each sampling clock cycle, after a certain period, all capacitor units (Cunits) in the capacitor array can be selected for sampling. Through this mechanism, the average error of the ADC after one complete cycle is 0. That is, after one complete cycle, the mismatch error between the ADCs can be averaged using a first-order method, and then the remaining high-frequency error components are filtered out by a subsequent filter. Alternatively, it can be said that DWA can shift the ADC error to a higher frequency range, perform noise-shaping-like processing on the ADC error, and then filter it out by a digital filter, reducing the mismatch between the first and second sampling capacitors in a simpler way, thereby improving the measurement accuracy of the temperature sensing system.
[0109] Another aspect of this application embodiment provides a temperature sensor, including: a sensing front end configured to sense the temperature of a measured object to output a first sensing voltage and a second sensing voltage; and a reading back end connected to the sensing front end configured to generate a sensing temperature signal based on the first sensing voltage and the second sensing voltage; wherein the reading back end includes a data readout structure as described in any of the above embodiments.
[0110] It is not difficult to see that this embodiment is a temperature sensor embodiment corresponding to the circuit embodiment, and this embodiment can be implemented in conjunction with the data readout structure embodiment. The relevant technical details mentioned in the data readout structure embodiment are still valid in this embodiment, and will not be repeated here to avoid repetition. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the circuit embodiment.
[0111] Furthermore, in order to highlight the innovative aspects of this application, no units that are not closely related to solving the technical problems proposed in this application are introduced in this embodiment, but this does not mean that there are no other units in this embodiment.
[0112] Another aspect of this application provides an electronic device, including: a temperature sensor as described in the above embodiment.
[0113] The above division of various components is only for clarity of description. In implementation, they can be merged into one component or some components can be split into multiple components. As long as they include the same logical relationship, they are all within the protection scope of this application.
[0114] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing this application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of this application.
Claims
1. A data readout structure (100) for data readout from the sensing front end (200) of a CMOS temperature sensor, characterized in that, include: The signal sampling module (101) is configured to sample the first sensing voltage (VBE1) output by the sensing front end (200) to generate a first sampling voltage, and to sample the difference between the second sensing voltage (VBE2) output by the sensing front end (200) and the first sensing voltage (VBE1) to generate a second sampling voltage. The data processing module (102), connected to the signal sampling module (101), is configured to perform integration and quantization on the first sampling voltage and the second sampling voltage to read out the sensed temperature signal (Dout). The control module (103), connected to the signal sampling module (101) and the data processing module (102), is configured to perform dynamic component matching on the signal sampling module (101) and the data processing module (102), and control the data processing module (102) to read out the sensed temperature signal (Dout). The signal sampling module (101) includes at least a capacitor array, which includes multiple capacitor units. The process of the control module (103) performing the dynamic element matching includes: in each sampling clock cycle, selecting different capacitor units from the capacitor array as first sampling capacitors to sample the first sense voltage (VBE1), and selecting different capacitor units from the capacitor array as second sampling capacitors to sample the difference between the second sense voltage (VBE2) and the first sense voltage (VBE1), and after a certain period, all the capacitor units in the capacitor array can be selected for sampling.
2. The data readout structure (100) according to claim 1, characterized in that, The multiple capacitor units are arranged in a common centroid manner.
3. The data readout structure (100) according to claim 1, characterized in that, The signal sampling module (101) includes: The first capacitor unit is selected by the control module (103) as the first sampling capacitor to sample the first sense voltage (VBE1). The first capacitor unit includes a first capacitor (Css1) and a second capacitor (Css2). In the sampling phase, the first plate of the first capacitor (Css1) receives the first sense voltage (VBE1), the second plate of the first capacitor (Css1) serves as the inverting output terminal (outn) of the signal sampling module (101), the first plate of the second capacitor (Css2) is grounded, and the second plate of the second capacitor (Css2) serves as the non-inverting output terminal (outp) of the signal sampling module (101). The second capacitor unit serves as the second sampling capacitor selected by the control module (103) to sample the difference between the second sensing voltage (VBE2) and the first sensing voltage (VBE1); The second capacitor unit includes a first capacitor group (kCsg1) and a second capacitor group (kCsg2); In the sampling phase, the first plate of the first capacitor group (kCsg1) is connected to the first plate of the first capacitor (Css1), the second plate of the first capacitor group (kCsg1) is connected to the second plate of the first capacitor (Css1), the first plate of the second capacitor group (kCsg2) receives the second sense voltage (VBE2), and the second plate of the second capacitor group (kCsg2) is connected to the second plate of the second capacitor (Css2).
4. The data readout structure (100) according to claim 3, characterized in that, include: In the integral phase, the first plate of the first capacitor (Css1) is grounded, the second plate of the first capacitor (Css1) serves as the inverting output terminal (outn) of the signal sampling module (101), the first plate of the second capacitor (Css2) receives the first sensed voltage (VBE1), and the second plate of the second capacitor (Css2) serves as the non-inverting output terminal (outp) of the signal sampling module (101). In the integral phase, the first plate of the first capacitor group (kCsg1) receives the second sensed voltage (VBE2), the second plate of the first capacitor group (kCsg1) is connected to the second plate of the first capacitor (Css1), the first plate of the second capacitor group (kCsg2) is connected to the first plate of the second capacitor (Css2), and the second plate of the second capacitor group (kCsg2) is connected to the second plate of the second capacitor (Css2).
5. The data readout structure (100) according to claim 3 or 4, characterized in that, The data processing module (102) includes at least a first integrator (301) and an integrating capacitor unit corresponding to the first integrator (301); The integrating capacitor unit includes a third capacitor (Ci1) and a fourth capacitor (Ci2). The first plate of the third capacitor (Ci1) is connected to the non-inverting output terminal (vop) of the first integrator (301), and the second plate of the third capacitor (Ci1) is connected to the inverting input terminal (Vin) of the first integrator (301) and the inverting output terminal (outn) of the signal sampling module (101) after passing through the first switch (K1). The first plate of the fourth capacitor (Ci2) is connected to the inverting output terminal (von) of the first integrator (301), and the second plate of the fourth capacitor (Ci2) is connected to the non-inverting input terminal (Vip) of the first integrator (301) and the non-inverting output terminal (outp) of the signal sampling module (101) after passing through the second switch (K2).
6. The data readout structure (100) according to claim 5, characterized in that, The process of the control module (103) performing the dynamic element matching also includes: selecting a third target capacitor from the capacitor array as the integrating capacitor unit in each sampling clock cycle.
7. The data readout structure (100) according to claim 6, characterized in that, The control module (103) includes: a first pointer (sel_csg), a second pointer (sel_css), and a third pointer (sel_ci). The first pointer (sel_csg) is used to select a second target capacitor from the capacitor array, the second pointer (sel_css) is used to select a first target capacitor from the capacitor array, and the third pointer (sel_ci) is used to select a third target capacitor from the capacitor array. In the current sampling clock, the first pointer (sel_csg) is the sum of the first pointer (sel_csg) and the first preset value in the previous sampling clock, the second pointer (sel_css) is the sum of the first pointer (sel_csg) and the second preset value, and the third pointer (sel_ci) is the sum of the second pointer (sel_css) and the third preset value.
8. The data readout structure (100) according to claim 1, characterized in that, The data processing module (102) includes: The first integrator (301) has its input terminal connected to the output terminal of the signal sampling module (101), its positive output terminal (vop) connected to the boost terminal (vfbp) of the signal sampling module (101), and its negative output terminal (von) connected to the buck terminal (vfbn) of the signal sampling module (101). The second integrator (302) has its input terminal connected to the output terminal of the first integrator (301); The adder (303) has a first input terminal (ap) connected to the non-inverting output terminal (vop) of the first integrator (301), a second input terminal (bp) connected to the non-inverting output terminal (vop) of the second integrator (302), a third input terminal (bn) connected to the inverting output terminal (von) of the first integrator (301), and a fourth input terminal (an) connected to the inverting output terminal (von) of the second integrator (302). The input of the quantizer (304) is connected to the output of the adder (303).
9. A temperature sensor, characterized in that, include: The sensing front end is configured to sense the temperature of the object being measured in order to output a first sensing voltage and a second sensing voltage. The reading backend, connected to the sensing frontend, is configured to generate a sensing temperature signal based on the first sensing voltage and the second sensing voltage; The reading backend includes the data reading structure described in any one of claims 1 to 8.
10. An electronic device, characterized in that, include: The temperature sensor as described in claim 9.