Fault diagnosis method, diagnosis device and fault diagnosis equipment

Abstract

The invention provides a fault diagnosis method, diagnosis device and fault diagnosis equipment, and relates to the technical field of fault diagnosis, and the fault diagnosis method comprises the steps: obtaining test firmware corresponding to the model of a to-be-measured force plate in response to the model selection of the to-be-measured force plate, and displaying a test interface corresponding to the to-be-measured force plate; and in response to a detection operation for the to-be-measured force plate, running the test firmware, and determining the working state of the to-be-measured force plate. According to the method, efficient fault diagnosis is realized through the automatic test process and the user interaction interface, the efficiency and accuracy can be improved, and manual dependence is reduced.

Description

Technical Field

[0001] This application relates to the field of fault diagnosis technology, and in particular to a fault diagnosis method, diagnostic device and fault diagnosis equipment. Background Technology

[0002] In the maintenance practice of blockchain servers, the maintenance process is highly dependent on manual operation. Maintenance personnel need to use special tools to manually inspect the computing boards with dense electronic components and complex structures, and check the fault points one by one. The inspection process is time-consuming and lacks positioning accuracy. Summary of the Invention

[0003] The main objective of this invention is to provide a fault diagnosis method that aims to improve fault diagnosis efficiency, reduce reliance on manual operation, and enhance diagnostic accuracy.

[0004] To achieve the above objectives, the present invention provides a fault diagnosis method applied to a fault diagnosis device, the fault diagnosis device including a connection interface for connecting a computing board under test, and the fault diagnosis method including: In response to the selection of the model of the computing board under test, the test firmware corresponding to the model of the computing board under test is obtained, and the test interface corresponding to the computing board under test is displayed. In response to the testing operation on the computing board under test, the test firmware is run to determine the working status of the computing board under test.

[0005] Optionally, the step of running the test firmware in response to a detection operation on the computing board under test to determine the working state of the computing board under test includes: In response to the detection operation, the test firmware is loaded and started running; Obtain the first detection signal from the test firmware and send the first detection signal to the computing board under test; The system monitors the response signal fed back by the computing board under test, compares the response signal with the preset normal response mode, determines the working status of the computing board under test, and displays the working status on the test interface.

[0006] Optionally, sending the first detection signal to the computing board under test specifically includes: Obtain the chip code sequence of each chip in the computing board under test; Based on the chip space layout topology order and signal transmission timing rules represented by the chip encoding sequence, the first detection signal is transmitted sequentially to the corresponding chip.

[0007] Optionally, sending the first detection signal to the computing board under test specifically includes: Obtain the chip array hardware topology of the computing board under test, and traverse and extract the physical address identification information of each chip in the chip array hardware topology. The first detection signal is transmitted in parallel to the corresponding chip according to the signal transmission path determined by the physical address identification information.

[0008] Optionally, the step of monitoring the response signal fed back by the computing board under test, comparing the response signal with a preset normal response mode to determine the working status of the computing board under test, and displaying the working status on the test interface includes: The response signal is subjected to timing analysis and level feature extraction to obtain the high and low level duration period and transition edge distribution of the response signal; The duration of the high and low levels and the distribution of the transition edges are matched one by one with the timing features in the preset normal response mode to generate corresponding matching results. If there are mismatches in the matching results, it is determined that the chip of the computing board under test is abnormal, and the location and fault type of the abnormal chip are determined according to the mismatches, and the location and fault type of the abnormal chip are displayed on the test interface. If the matching results are consistent, it is determined that the computing board under test is in normal working condition, and a normal operation indicator is displayed on the test interface.

[0009] Optionally, the connection interface has a control signal terminal for connecting to a controllable DC power supply, and the output terminal of the controllable DC power supply is connected to the power input terminal of the computing board under test. After responding to the selection of the model of the computing power board under test and displaying the test interface corresponding to the computing power board under test, the method further includes: In response to adjustment commands for electrical parameters, the supply voltage, supply current, and delay time of the controllable DC power supply are adjusted. The step of running the test firmware in response to a detection operation on the computing board under test includes: In response to the detection operation on the computing board under test, the controllable DC power supply is controlled to supply power to the computing board under test according to the adjusted supply voltage and supply current, and a corresponding first detection signal is sent to the computing board under test. Within the delay time after the computing board under test returns response data, the power supply connection between the controllable DC power supply and the computing board under test is disconnected.

[0010] Optionally, the fault diagnosis method further includes: Record the working status of each test, extract the test timing, chip operating status and test count from each record, and generate the corresponding test log; Obtain the computing board model data and corresponding test data for each test record in the test log; In response to a query command for the test log, the computing board model data and the test data are retrieved, arranged in the corresponding time order, and displayed on the test interface.

[0011] Optionally, the fault diagnosis method further includes: If the working state is abnormal, obtain the abnormal chip, abnormal location and fault type in the computing board; Display the rendering of the computing board corresponding to the computing board under test, and mark the abnormal locations on the rendering of the computing board; In response to the selection of an abnormal location on the computing board rendering, the fault type and suggested repair solution corresponding to the abnormal location are displayed.

[0012] In addition, to achieve the above objectives, the present invention also provides a diagnostic device, the diagnostic device comprising: a memory, a processor, and a fault diagnosis program stored in the memory and executable on the processor, the fault diagnosis program being configured to implement the fault diagnosis method as described above.

[0013] Furthermore, to achieve the above objectives, the present invention also provides a fault diagnosis device, the fault diagnosis device comprising: The display component is used to present the test interface and the working status of the computing board under test. A connection interface, wherein the connection interface is used to connect to the computing board under test; and The diagnostic device described above is electrically connected to both the display component and the connection interface. The diagnostic device is used to respond to the user's selection of the model of the computing board under test on the display component, obtain the test firmware corresponding to the model of the computing board under test, and display the test interface corresponding to the computing board under test on the display component. The diagnostic device is also used to run the test firmware in response to a user's detection operation on the display component for the computing board under test, and to determine the working status of the computing board under test.

[0014] The fault diagnosis method of this invention is applied to a fault diagnosis device, which includes a connection interface for connecting a computing board under test. The fault diagnosis method, in response to the selection of a model for the computing board under test, obtains test firmware corresponding to that model and displays a test interface corresponding to the computing board under test. In response to a detection operation on the computing board under test, the test firmware is run to determine the working status of the computing board under test. Thus, efficient fault diagnosis is achieved through an automated testing process and user interface, improving efficiency and accuracy while reducing reliance on manual labor. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0016] Figure 1 This is a schematic flowchart of a fault diagnosis method according to an embodiment of the present invention; Figure 2 for Figure 1 A flowchart illustrating the method of step S200; Figure 3 for Figure 2 A flowchart illustrating the method of step S220; Figure 4 This is a schematic flowchart of a fault diagnosis method according to another embodiment of the present invention; Figure 5 for Figure 2 A flowchart illustrating the method of step S230; Figure 6 This is a schematic flowchart of a fault diagnosis method according to another embodiment of the present invention; Figure 7 This is a schematic flowchart of a fault diagnosis method according to another embodiment of the present invention; Figure 8 This is a schematic flowchart of a fault diagnosis method according to an embodiment of the present invention.

[0017] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0018] In the maintenance practice of blockchain servers, the fault diagnosis process of existing computing boards relies heavily on manual operation. Maintenance personnel must manually locate chips based on circuit diagrams and use specialized tools such as multimeters to measure the voltage, signal, and other parameters of each chip. They then analyze the measurement data based on personal experience to determine if a fault exists. This operational mode results in extremely low testing efficiency, significantly extending the maintenance cycle when dealing with batches of faulty equipment, making it difficult to meet the demand for rapid response. Furthermore, the accuracy of fault location is severely limited by the operator's experience level. Due to the lack of standardized judgment criteria, misdiagnosis or omission occurs frequently, affecting the reliability of the diagnostic results. In addition, this method demands extremely high professional skills from operators, requiring long-term accumulation of circuit knowledge and practical experience to independently complete diagnostic tasks. This leads to lengthy and costly personnel training cycles, hindering the rapid formation and capacity building of maintenance teams. A more prominent problem is the lack of compatibility of existing testing tools. Dedicated equipment is usually only compatible with a single brand or a specific model of computing board. When faced with computing boards of different brands or types, it is necessary to frequently change tools and reconfigure the testing process. The operation steps are cumbersome and prone to errors, which further reduces the overall testing efficiency.

[0019] The main solution of this application embodiment is: in response to the selection of the model of the computing power board under test, the test firmware corresponding to the model of the computing power board under test is obtained, and the test interface corresponding to the computing power board under test is displayed. In response to the detection operation of the computing power board under test, the test firmware is run to determine the working status of the computing power board under test.

[0020] In this embodiment, for ease of description, the diagnostic device will be used as the subject of the explanation below.

[0021] This application provides a solution that achieves efficient fault diagnosis through automated testing processes and user interfaces, thereby improving efficiency and accuracy and reducing reliance on manual labor.

[0022] Therefore, the present invention proposes a fault diagnosis method; it is understood that the fault diagnosis equipment is equipped with a diagnostic device for storing and executing the following method. The diagnostic device can be implemented using a main controller, such as an MCU (Microcontroller Unit), a DSP (Digital Signal Processor), an FPGA (Field Programmable Gate Array), or a SOC (System On Chip).

[0023] In the process of diagnosing computing board faults, existing technologies rely on manual operation for parameter measurement. This process involves operators manually locating chip positions by referring to circuit diagrams, collecting voltage and signal data point by point using specialized testing tools, and then judging the fault status based on individual experience. The diagnostic efficiency is limited by the serial processing nature of manual operation, the accuracy of fault location is limited by the operator's mastery of circuit knowledge, the operational threshold is significantly increased due to the need for long-term experience accumulation, and the hardware compatibility mechanism of testing tools makes it impossible to universalize the diagnostic process across different brands or types of computing boards. This results in a longer overall system diagnostic cycle, reduced resource utilization, and decreased equipment availability.

[0024] For example, in the routine maintenance of data center server clusters, maintenance personnel need to test multiple faulty computing boards from different brands. This requires identifying the physical location of each chip according to circuit diagrams and using tools such as multimeters to measure the pin voltages and signal timing characteristics of each chip. When handling new models of computing boards, operators need to change to specialized testing tools and relearn their operating procedures, leading to frequent interruptions in the diagnostic process. Furthermore, due to subjective biases in manual data reading, voltage measurement results for the same chip can be inconsistent among different operators, resulting in misdiagnosis. In this scenario of manual data reading, the complexity of the chip spatial layout makes it difficult to accurately trace signal transmission paths, hindering operators from efficiently verifying the collaborative working status of multiple chips. Ultimately, this results in a lengthy diagnostic process and unreliable results.

[0025] If the above problems are not resolved, the diagnostic process for computing boards will remain constrained by the inherent defects of manual operation, resulting in a continuous increase in equipment downtime, inefficient use of maintenance resources, and a negative impact on the overall stability of the system. In addition, fluctuations in diagnostic results caused by differences in operator skills will increase the uncertainty of fault repair, hinder the standardized implementation of maintenance processes, thereby exacerbating the complexity of equipment management and driving up long-term operation and maintenance costs.

[0026] Therefore, referring to Figure 1 In one embodiment of the present invention, the fault diagnosis method is applied to a fault diagnosis device, the fault diagnosis device including a connection interface for connecting to the computing board under test, and the fault diagnosis method including steps S100-S200, wherein: S100: In response to the selection of the model of the computing board under test, obtain the test firmware corresponding to the model of the computing board under test, and display the test interface corresponding to the computing board under test. S200: In response to the testing operation on the computing board under test, runs the test firmware to determine the working status of the computing board under test.

[0027] In this context, fault diagnosis equipment refers to a hardware and software integrated system specifically designed to perform fault diagnosis methods. This equipment typically includes an interface for physical or logical connection to the device under test (DUT), as well as processing and display units for running diagnostic programs, processing data, and displaying results. The connection interface refers to the port or module on the fault diagnosis equipment used to establish a physical or logical connection with an external DUT (such as a computing board, power supply, or fan). This interface enables the transmission of data, signals, or power, serving as a bridge for information exchange between the fault diagnosis equipment and the DUT. The fault diagnosis equipment is configured with a connection interface designed for physical or logical connection to the DUT. For example, the connection interface could be a Universal Serial Bus (USB) interface, connecting different types of computing boards via an adapter; or it could be a multi-pin dedicated slot, requiring manual insertion of the DUT. The DUT refers to the computing power unit that needs fault diagnosis. This computing board typically contains multiple computing chips, storage units, and related circuits and interfaces; its proper functioning directly affects the performance of the entire blockchain server.

[0028] Model selection refers to the process by which the user or system identifies and matches the specific model of the computing board under test. Model selection ensures that subsequent diagnostic procedures and test parameters conform to the specifications of the computing board under test, improving diagnostic accuracy. Test firmware refers to a diagnostic program specifically designed and compiled for a particular model of computing board under test. This firmware is loaded into the fault diagnosis equipment and runs, sending specific detection signals to the computing board under test and receiving its responses to evaluate its various functions and performance. The test interface refers to the graphical user interface on the fault diagnosis equipment used to display the diagnostic process, real-time data, and diagnostic results to the user. This test interface typically provides operation buttons, status indicators, and information display areas to facilitate user interaction and access to diagnostic information.

[0029] The detection operation refers to the instruction or action by the user to initiate the fault diagnosis process through the test interface or automated program. This operation triggers the execution of the test firmware, thereby initiating a systematic test of the connected computing board under test. The operating status refers to the operational condition of the computing board under test after the detection operation. This status can be normal operation, partial anomaly, or complete failure, and is the final result determined by the fault diagnosis method.

[0030] During fault diagnosis, in response to the selection of the model of the computing board under test, the diagnostic device is configured to obtain the test firmware corresponding to the model of the computing board under test. Model selection can be achieved in several ways. For example, the user can manually enter the model code of the computing board under test on the fault diagnosis device, and the diagnostic device can retrieve the matching test firmware from local storage or a remote server based on this code; or the user can select the corresponding model option on the test interface and match the corresponding test firmware; or the diagnostic device can automatically read the identification information built into the computing board under test, such as the device serial number or model label, automatically identify it through a communication protocol, and retrieve the corresponding test firmware from the database. Alternatively, the diagnostic device can preset a firmware list, from which the user selects the firmware that matches the model of the computing board under test.

[0031] During the acquisition of the test firmware, the diagnostic device is configured to display a test interface corresponding to the computing board under test. This test interface can be a universal diagnostic interface, with the same layout and functions for all models of computing boards, only adapted when displaying specific data. Alternatively, the test interface can be a preset template interface, loading the corresponding interface elements and display area based on the computing board model selected by the user.

[0032] Subsequently, in response to the testing operation on the computing board under test, the diagnostic device is configured to run the test firmware. The testing operation can be triggered by the user by clicking the "Start Testing" button on the test interface. Upon receiving this instruction, the fault diagnosis device will load and execute the previously acquired test firmware. The execution of the test firmware can be a simple sequential execution process, sending test signals one by one according to a preset instruction set and waiting for a response.

[0033] Finally, after the test firmware completes its execution, the diagnostic device is configured to determine the operating status of the computing board under test. This determination can be achieved in several ways. For example, the test firmware collects response data from the computing board during operation and compares this data with preset normal thresholds. If all data is within the normal range, the operating status is considered normal; if any data exceeds the threshold, the operating status is considered abnormal. This determination result is then displayed on the test interface.

[0034] In one specific implementation of this embodiment, it is assumed that a batch of newly produced computing boards needs to undergo pre-shipment quality inspection on a production line to ensure their normal operating condition. The fault diagnosis method in this embodiment is applied to a fault diagnosis device placed next to the production line.

[0035] First, when a computing board to be tested is placed onto the fault diagnosis equipment by a production line worker, the board is connected via a connection interface on the equipment. For example, this interface could be a customized slot to ensure the board is physically connected correctly.

[0036] Subsequently, User A sees a prompt on the fault diagnosis device's display screen, requiring them to select the model of the computing board under test. Based on the markings on the computing board, User A selects "Model X" on the test interface. In response to this model selection, the processor inside the fault diagnosis device automatically retrieves the test firmware corresponding to "Model X" from its memory. Furthermore, a test interface specifically designed for "Model X" immediately appears on the display screen, which may include a layout diagram of the computing board for "Model X," key test point indicators, and a "Start Test" button.

[0037] Next, User A clicks the "Start Testing" button on the test interface, triggering a testing operation for the computing board under test. Upon receiving this command, the fault diagnosis device immediately activates the previously acquired "Model X" test firmware. This firmware begins sending a series of preset test signals to the computing board under test, such as initialization commands, data read / write commands, or functional test commands to various chips on the board via the connection interface. Upon receiving these commands, the computing board under test responds according to its internal logic and feeds back the response signals to the fault diagnosis device through the connection interface.

[0038] During the test firmware operation, the fault diagnosis equipment continuously monitors and collects the response signals from the computing board under test. The test firmware analyzes and processes these response signals in real time, comparing factors such as signal timing, level, and data content to ensure they conform to the normal operating mode of "Model X". Based on these comparison results, the fault diagnosis equipment ultimately determines the operating status of the computing board under test. For example, if all detection items conform to the normal mode, the operating status is determined to be "normal"; if a chip's response signal is abnormal, the operating status is determined to be "abnormal," and the type of abnormality may be indicated. Finally, the determined operating status (e.g., "normal operation" or "Chip A abnormal") is clearly displayed on the test interface for user A to view.

[0039] Through the above process, the fault diagnosis method of this embodiment realizes automated and standardized testing of computing boards, eliminating the need for manual point-by-point measurement and experience-based judgment, thereby improving testing efficiency and accuracy.

[0040] In the above-described implementation methods, the existing technology for testing computing boards heavily relies on the experience and manual operation of maintenance personnel. For example, it requires manually locating chip positions by referring to circuit diagrams and using tools such as multimeters to test voltages and signals point by point. This method is not only inefficient, resulting in long repair cycles for batches of faulty equipment, but also limited by the operator's experience level in terms of fault location accuracy.

[0041] In contrast, this embodiment improves diagnostic efficiency by introducing an automated process for model selection, firmware testing, and the testing interface. In the above implementation, user A simply selects the model and triggers the detection operation; the fault diagnosis device automatically acquires and runs the matching firmware, eliminating the need for complex manual intervention steps. This automated process avoids the time-consuming manual measurement and judgment steps of traditional methods, making rapid testing of a large number of computing boards possible.

[0042] Furthermore, this embodiment improves the accuracy of fault diagnosis through a pre-set test firmware and a standardized response signal comparison mechanism. The test firmware is designed for precise testing of specific computing board models, and its internal detection logic and normal response modes have been rigorously verified. This contrasts with existing technologies that rely on the personal experience of maintenance personnel for judgment, effectively reducing human error and ensuring the objectivity and consistency of diagnostic results.

[0043] Furthermore, this embodiment lowers the operational threshold. In the example above, user A does not need in-depth circuit knowledge or years of repair experience; they only need to follow the instructions on the test interface to complete the diagnosis by simply selecting the model and triggering the operation. This contrasts sharply with existing technologies that require repair personnel to accumulate years of industry experience to operate independently, shortening the personnel training cycle and reducing labor costs.

[0044] Finally, this embodiment improves the compatibility of the fault diagnosis equipment through a model selection mechanism. The fault diagnosis equipment can dynamically load the corresponding test firmware and test interface according to different computing board models. This means that one device can be adapted to multiple brands and models of computing boards without the need to replace special tools as required by existing technologies, thereby simplifying the operation process and improving the versatility of the equipment.

[0045] The fault diagnosis method in this embodiment effectively solves the problems of low efficiency, low accuracy, high operating threshold and low compatibility in the prior art through the technical concept of automation, standardization and intelligence, and provides a high-efficiency, high-accuracy and easy-to-operate solution for fault diagnosis of computing boards.

[0046] The fault diagnosis method of this embodiment is applied to a fault diagnosis device, which includes a connection interface for connecting a computing board under test. The fault diagnosis method, in response to the selection of a model for the computing board under test, obtains the test firmware corresponding to that model and displays a test interface corresponding to the computing board under test. In response to a detection operation for the computing board under test, the test firmware is run to determine the working status of the computing board under test. Thus, efficient fault diagnosis is achieved through an automated testing process and user interface, improving efficiency and accuracy while reducing reliance on manual labor.

[0047] Optionally, refer to Figure 2 Another embodiment of the present invention provides a fault diagnosis method, based on the above. Figure 1 The illustrated embodiment, in response to a testing operation on the computing board under test, runs test firmware to determine the operating state of the computing board under test, including steps S210-S230, wherein: S210, in response to the detection operation, loads the test firmware and starts running; S220: Obtain the first detection signal from the test firmware and send the first detection signal to the computing board under test; S230: Monitor the response signal fed back by the computing board under test, compare the response signal with the preset normal response mode, determine the working status of the computing board under test, and display the working status on the test interface.

[0048] In response to a testing operation, the system loads and starts the test firmware to ensure that it is activated when needed and begins the predetermined testing process. For example, a user can click the "Start Testing" button on the test interface to trigger the system to load and run the firmware; or, the diagnostic device can automatically load and start the firmware after receiving an external instruction (such as via an API call).

[0049] The test firmware acquires the first detection signal and sends it to the computing board under test (DUT). Its function is to generate specific excitation signals from the test firmware to probe the functionality and response of the DUT. The test firmware can pre-set a series of detection signals, which are generated sequentially or on demand during runtime and sent to the DUT via signal pins of the connection interface. Alternatively, the test firmware can dynamically generate or read the first detection signal from memory based on the DUT model and the current testing stage, and send it to the DUT via a specific communication protocol (e.g., SPI, I2C, JTAG).

[0050] Monitoring the response signal from the computing board under test (DUT) serves to capture the DUT's feedback to the first detection signal, which is fundamental to determining its operational status. The fault diagnosis equipment can monitor and acquire the electrical signals output by the DUT in real time via the receiving pin of the connection interface. Alternatively, the fault diagnosis equipment can be configured with a high-speed data acquisition module capable of synchronously monitoring the digital or analog signals returned by the DUT within a specific time window.

[0051] The comparison between the response signal and a preset normal response pattern aims to identify abnormal behavior by comparing it with known normal behavior patterns. For example, the waveform, timing, and level characteristics of the acquired response signal can be compared point-by-point or feature-by-feature with the normal response patterns of the same computing board model stored in a database. As an upgraded version, pattern recognition algorithms or machine learning models can be used to analyze the feature vector of the response signal and evaluate its matching degree with pre-trained normal patterns.

[0052] Determining the operating status of the computing board under test is crucial for concluding whether it is functioning normally or abnormally. This can be achieved directly by identifying any mismatches in the comparison results or determining if the matching degree is below a threshold. Alternatively, the final operating status can be determined by combining the response comparison results of multiple detection signals and using logical judgment or decision tree models for comprehensive evaluation.

[0053] The testing interface displays the working status, serving to intuitively present diagnostic results to the user. For example, it can display the results in a specific area of ​​the testing interface using text (e.g., "Normal" or "Abnormal") or color (e.g., green for normal, red for abnormal). Alternatively, it can display the real-time working status of the computing board under test through a graphical interface, such as a progress bar, status indicator icons, or a detailed diagnostic report.

[0054] The solution proposed in this application, upon responding to a detection operation on a computing board under test, first loads and starts the test firmware, which then generates and sends a first detection signal to the board. Next, it monitors the response signal from the board and compares it with a preset normal response mode to determine the board's operating status, which is then displayed on the test interface. In this way, the fault diagnosis equipment can accurately obtain the internal operating information of the computing board under test and determine its health status based on rigorous comparison logic. This transforms the diagnostic process from a black-box operation into one with clear inputs, outputs, and judgment criteria, greatly improving the accuracy and reliability of the diagnosis.

[0055] In one implementation of this embodiment, assuming the user selects the model of the connected computing board under test on the test interface of the fault diagnosis device, the diagnostic device immediately acquires and displays the corresponding test interface. When the user clicks the "Start Detection" button on the test interface, the fault diagnosis device responds to this detection operation by loading the test firmware matching the model of the computing board under test into its internal processor and starting its operation. The test firmware then generates a specific digital signal sequence as the first detection signal, such as a read / write test sequence for testing the integrity of the memory bus, and sends it to the corresponding pin of the computing board under test through the connection interface. The fault diagnosis device simultaneously monitors the feedback of the computing board under test to the read / write test sequence, i.e., the response signal, through the connection interface. The device compares the timing and level characteristics of the acquired response signal with the pre-stored response mode of the computing board under test in normal working condition. If the comparison result shows that the response signal is completely consistent with the normal mode, it is determined that the computing board under test is in normal working condition, and a "normal operation" indicator is displayed on the test interface. If there are inconsistencies in the comparison results, such as the data read back from a certain memory address not matching the expectation, it is determined that there is an anomaly in the computing board under test, and an "anomaly" label will be displayed on the test interface, along with the corresponding anomaly type.

[0056] The above technical solution refines the abstract steps of running test firmware and determining the working status during fault diagnosis into specific processes of signal interaction, data comparison, and result presentation. This enables the fault diagnosis equipment to perform more in-depth and accurate testing of the computing board. This detailed diagnostic process can effectively identify potential faults or abnormal behaviors of the computing board under test, improving the accuracy and reliability of fault diagnosis. Furthermore, the intuitive display of the working status on the test interface allows operators to quickly understand the diagnostic results, thereby improving the efficiency of fault diagnosis and the user experience.

[0057] In actual fault diagnosis, the computing board under test typically contains multiple chips. Ensuring that the initial detection signal is accurately and efficiently transmitted to each target chip on the board, while considering the complex connections and signal transmission characteristics between chips, is a key challenge for achieving accurate diagnosis. Improper signal transmission can lead to low detection efficiency or failure to accurately identify specific faulty chips.

[0058] Therefore, referring to Figure 3 Another embodiment of the present invention provides a fault diagnosis method, based on the above. Figure 2 In the embodiment shown, sending a first detection signal to the computing board under test is specifically done in steps S221-S222, wherein: S221. Obtain the chip code sequence of each chip in the computing board to be tested; S222. Based on the chip space layout topology order and signal transmission timing rules represented by the chip encoding sequence, the first detection signal is transmitted to the corresponding chip in sequence.

[0059] Obtaining the chip code sequence for each chip on the computing board under test refers to the fault diagnosis equipment identifying and acquiring the unique identification information of each chip on the board through a specific method. These chip code sequences may contain data such as the chip's model, batch number, production date, or internal unique ID. Their purpose is to provide accurate addressing for subsequent signal transmission, ensuring that the detection signal can be sent to the intended target chip. For example, the fault diagnosis equipment can obtain these code sequences by reading the chip information burned into a pre-installed storage unit (such as EEPROM or Flash) on the computing board under test; alternatively, the fault diagnosis equipment can communicate with the main control chip on the computing board under test, which will return the code sequences of each chip connected to it.

[0060] Among them, the chip spatial layout topology order and signal transmission timing rules represented by the chip encoding sequence refer to the fault diagnosis equipment's use of pre-stored or dynamically acquired information to understand the physical arrangement, interconnection method, and signal transmission timing characteristics of the chips on the computing power board under test. The chip spatial layout topology order describes the positional relationship of the chips on the board and the data flow, while the signal transmission timing rules specify timing parameters such as signal transmission delay, setup time, hold time, and clock synchronization. Its role is to provide path and timing guidance for the accurate transmission of the first detection signal, avoiding signal conflicts, data loss, or timing errors. For example, the fault diagnosis equipment can internally store detailed topology diagrams and timing rule databases of different models of computing power boards, and perform matching queries based on the model and chip encoding sequence of the computing power board under test; or, the fault diagnosis equipment can dynamically construct the inter-chip connection relationships and timing characteristics of the computing power board under test before detection through a specific detection mechanism.

[0061] The sequential transmission of the first detection signal to the corresponding chip refers to the fault diagnosis equipment sending the first detection signal one by one to each target chip on the computing power board under test, according to the chip encoding sequence, spatial layout topology order, and signal transmission timing rules obtained above, in a predetermined order and with precise timing. Its purpose is to ensure that each chip can independently and accurately receive the detection signal and respond according to its characteristics, thereby achieving accurate detection and fault location of individual chips. For example, the fault diagnosis equipment can use a multiplexer or serial communication interface to select target chips one by one according to the chip encoding sequence and topology order and send the first detection signal; or, it can use a JTAG chain or a similar daisy chain structure to serially transmit the first detection signal to each chip, with each chip receiving and processing it before passing it to the next chip.

[0062] In the fault diagnosis process, to achieve accurate detection of multi-chip computing boards under test, the solution of this application first obtains the chip encoding sequence of each chip in the computing board under test. These sequences provide a unique identifier for each chip. Subsequently, based on the chip spatial layout topology and signal transmission timing rules represented by these chip encoding sequences, the fault diagnosis equipment can accurately understand the physical arrangement of chips on the computing board, their interconnection relationships, and the time characteristics required for signal transmission over these connections. By comprehensively utilizing this information, the fault diagnosis equipment can sequentially transmit the first detection signal to each corresponding chip in the computing board under test according to a predetermined, precise timing and path. This orderly transmission method based on topology and timing rules ensures that each chip can independently and accurately receive the detection signal, thereby avoiding signal conflicts or transmission errors and laying the foundation for subsequent accurate monitoring of chip responses and determination of their working status. Compared to simply sending detection signals, this solution significantly improves the diagnostic accuracy and efficiency of complex multi-chip computing boards by finely managing the signal transmission path and timing.

[0063] As one implementation method, for example, when the fault diagnosis device is connected to the computing board under test, it first establishes communication with the main control chip of the computing board under test through the JTAG interface. The main control chip is programmed to recognize and return the chip code sequences of each computing chip (e.g., ASIC chip) connected to it. These sequences may contain the chip's physical address and function type. The fault diagnosis device has a pre-stored chip layout diagram and signal transmission protocol for this type of computing board, which defines in detail the serial data link and clock synchronization requirements between chips. This constitutes the chip spatial layout topology order and signal transmission timing rules. For example, if the chips are connected in a daisy chain, the fault diagnosis device will, according to the obtained chip code sequence, send the first detection signal (e.g., a specific test vector) sequentially to the first chip through the JTAG chain according to the chain topology. After the first chip processes the signal and passes the result to the next chip, the next chip receives and processes the signal, until all chips in the chain have been detected. This method ensures that each chip receives an independent detection instruction at the correct timing.

[0064] Through the above technical solution, the fault diagnosis equipment can accurately obtain the unique identifier of each chip on the computing board under test, and combine it with its physical arrangement and signal transmission characteristics on the board to achieve accurate and orderly transmission of the first detection signal. This transmission method, based on chip encoding sequence, spatial layout topology order, and signal transmission timing rules, effectively solves the problems of blindness and inefficiency in the transmission of detection signals in complex multi-chip computing boards. It ensures that each chip can receive an independent and correct detection signal, thereby greatly improving the detection accuracy and fault location capability of a single chip, avoiding misjudgment or missed judgment due to improper signal transmission, and thus improving the efficiency and reliability of the entire fault diagnosis process.

[0065] In actual fault diagnosis, if the computing board under test contains a large number of chips, and all chips need to be tested quickly and efficiently, the above-mentioned... Figure 3 The method of sending detection signals one by one or in sequence in the illustrated embodiment may lead to low detection efficiency and prolonged diagnosis time. This limitation of the transmission method is even more prominent, especially in scenarios where it is necessary to quickly locate the faulty chip.

[0066] Therefore, referring to Figure 4 Another embodiment of the present invention provides a fault diagnosis method, based on the above. Figure 2 In the embodiment shown, a first detection signal is sent to the computing board under test, specifically in steps S223-S224, wherein: S223. Obtain the chip array hardware topology of the computing board to be tested, and traverse and extract the physical address identification information of each chip in the chip array hardware topology. S224. The first detection signal is transmitted in parallel to the corresponding chip according to the signal transmission path determined by the physical address identification information.

[0067] The process of acquiring the chip array hardware topology of the computing board under test (TBT) involves obtaining information such as the physical arrangement, interconnection, and bus structure of the chips on the TBT. This architecture information can be pre-stored in the firmware or configuration data of the TBT, and the fault diagnosis equipment can retrieve it by reading this data; alternatively, the fault diagnosis equipment can scan and identify the interconnection relationships of the chips through interfaces such as the JTAG interface or boundary scan interface connected to the TBT, thereby dynamically constructing the hardware topology. Extracting the physical address identifier information of each chip in the chip array hardware topology involves identifying and recording the unique addressing information of each chip in the bus or interconnection network from the acquired hardware topology. This physical address identifier information can be the chip's PCIe bus address, SPI slave address, I2C device address, or device ID on a custom bus. This information can be obtained by parsing from a pre-loaded chip layout file or dynamically obtained by addressing the chip array using specific hardware scanning protocols (such as I2C, SPI, JTAG, etc.). Transmitting the first detection signal in parallel to the corresponding chip according to the signal transmission path determined by the physical address identification information refers to using the parallel communication mechanism supported by the computing board under test to send detection signals to multiple chips concurrently. This can be achieved by using the high-speed parallel bus (such as PCIe, AXI bus, etc.) inside the computing board under test, directly addressing and simultaneously sending detection signals to multiple chips through the physical address identification information; or, the fault diagnosis equipment can be configured with multiple independent signal transmission channels, each channel corresponding to the physical address of one or a group of chips, thereby realizing the parallel transmission of detection signals.

[0068] This embodiment first obtains the chip array hardware topology of the computing board under test, which provides the physical layout and interconnection information of the chips on the board. Next, it iterates and extracts the physical address identification information of each chip, which is crucial for uniquely identifying the chip's position in the hardware topology. Based on this physical address identification information, the diagnostic device can determine the signal transmission path to each chip. Unlike traditional sequential transmission, this embodiment utilizes these determined transmission paths to transmit the first detection signal in parallel to multiple corresponding chips. This parallel transmission mechanism significantly improves the transmission efficiency of the detection signal, allowing more chips to be tested within the same time frame, thereby accelerating the entire fault diagnosis process. In this way, this embodiment effectively solves the problem of low efficiency in serial sequential transmission of detection signals in computing boards containing a large number of chips, enabling rapid monitoring of response signals and determination of operating status.

[0069] In one embodiment of this invention, it is assumed that the computing board under test is a blockchain server computing board containing multiple ASIC chips. During fault diagnosis, the fault diagnosis device first obtains the hardware topology of its ASIC chip array by reading the firmware configuration of the computing board. For example, the chips are connected via an SPI bus or a custom parallel bus, forming a chain or matrix layout. Next, the diagnostic device traverses this topology to extract the unique physical address identification information of each ASIC chip, such as the SPI slave address or the device ID on the bus. When a first detection signal needs to be sent, the fault diagnosis device sends the detection signal simultaneously to multiple ASIC chips via a parallel bus interface or multiple independent SPI channels, based on this physical address identification information. For example, signals can be sent to the first group of chips simultaneously, instead of waiting for the previous chip to respond before sending to the next. This parallel transmission method greatly shortens the transmission time of the detection signal, enabling rapid completion of the detection of the entire chip array.

[0070] Through the above technical solution, the fault diagnosis equipment can efficiently acquire the chip array hardware topology and physical address identification information of each chip on the computing board under test. Based on this information, the first detection signal can be transmitted in parallel to the corresponding chip according to a determined signal transmission path. This parallel transmission method significantly improves the transmission efficiency of the detection signal and shortens the overall detection time, making it particularly suitable for complex computing boards containing a large number of chips. This makes the fault diagnosis process faster, enabling quicker location of potentially faulty chips, thereby improving the overall efficiency and accuracy of fault diagnosis.

[0071] Optionally, refer to Figure 5 In another embodiment of the present invention, a fault diagnosis method is provided, based on the above. Figure 2 The embodiment shown monitors the response signal fed back by the computing board under test, compares the response signal with a preset normal response mode to determine the working status of the computing board under test, and displays the working status on the test interface, including steps S231-S234, wherein: S231. Perform timing analysis and level feature extraction on the response signal to obtain the high and low level duration period and transition edge distribution of the response signal; S232. Match the duration period and transition edge distribution of high and low levels with the timing characteristics in the preset normal response mode one by one to generate the corresponding matching results. S233. If there are mismatches in the matching results, it is determined that the chip of the computing board under test is abnormal, and the location and fault type of the abnormal chip are determined according to the mismatches, and the location and fault type of the abnormal chip are displayed on the test interface. S234. If the matching results are consistent, it is determined that the computing board under test is working normally, and a normal operation indicator is displayed on the test interface.

[0072] The timing analysis and level feature extraction of the response signal refers to analyzing the raw response signal received from the computing board under test to identify its key characteristics in the time and voltage level dimensions. This can include capturing the signal waveform using high-speed sampling technology and using digital signal processing algorithms, such as identifying the rising and falling edges of the signal, to accurately measure the duration the signal is held at different voltage levels (high or low), and to record the precise time points when these level transitions (jump edges) occur. In this way, the raw, potentially complex response signal can be transformed into a series of quantifiable timing and level features.

[0073] Obtaining the duration and transition edge distribution of the high and low levels of the response signal refers to, after completing timing analysis and level feature extraction, explicitly quantifying the duration of each high and low level state of the signal, as well as the precise time sequence of all signal level changes. For example, for a digital signal, one can measure how many nanoseconds it lasts after transitioning from low to high, and then how many nanoseconds it lasts after transitioning from high to low, recording the specific time of each level change. This periodicity and distribution data are key indicators for evaluating the proper functioning of the internal digital logic circuits and clock system of the computing board.

[0074] Matching the duration of high and low levels and the distribution of transition edges with the timing characteristics in the preset normal response mode involves a detailed, point-to-point comparison of the specific timing characteristics extracted from the actual response signal (such as the duration of high and low levels and the timing of transition edges) with the corresponding timing characteristics in a pre-stored reference mode representing the normal operating state. This matching process can employ precise time window comparison, numerical range judgment, or rule-based logical judgment to identify any discrepancies between the two.

[0075] Generating corresponding matching results means that after completing the above-mentioned step-by-step matching process, the diagnostic device will output a structured data set that clearly indicates whether each compared temporal feature matches a preset normal pattern. For example, a list or report can be generated, which includes the comparison status of each feature (such as "match" or "mismatch"), as well as the specific deviation value when there is a mismatch.

[0076] If a mismatch is found in the matching results, it indicates that a chip on the computing board under test is malfunctioning. The diagnostic device then determines the location and type of the malfunctioning chip based on the mismatch. This means that if the matching results show any item that does not conform to the preset normal mode, the diagnostic device will immediately determine that one or more chips on the computing board under test are malfunctioning. Specifically, the diagnostic device will infer the specific chip location (e.g., a specific ASIC, memory chip, or interface chip) and the type of fault (e.g., clock signal error, open / short circuit in data lines, abnormal power supply voltage, excessive response delay, etc.) caused by the mismatch based on the specific nature of the mismatch (e.g., which signal's timing is abnormal, the degree of abnormality, and the pattern), combined with a preset fault diagnosis rule base or fault mode database.

[0077] Displaying the location and fault type of the abnormal chip on the test interface means presenting the diagnosed abnormal chip location and fault type information in an intuitive and easy-to-understand manner on the test interface of the fault diagnosis equipment. This can include highlighting the abnormal chip on the graphical layout diagram of the computing board, or clearly listing the fault description in text form, so that operators can quickly understand and take subsequent measures.

[0078] If the matching results are consistent, it means that the computing board under test is in normal working condition. This means that if all extracted timing features completely match the timing features in the preset normal response mode, or match within an acceptable error range, the system judges that the computing board under test is currently in normal working condition and has no obvious fault.

[0079] Displaying a normal operation indicator on the test interface means that when the computing board under test is determined to be in normal working condition, a clear indication, such as "normal operation," "PASS," or a green indicator light icon, will be displayed on the test interface of the fault diagnosis equipment to inform the operator that the computing board has passed the test.

[0080] The proposed solution, upon receiving the response signal from the computing board under test, first performs refined timing analysis and level feature extraction on the response signal. This process accurately obtains the duration of the response signal in high and low level states, as well as the specific distribution of signal transition edges. These detailed timing and level features are key indicators reflecting the operating status of the chips inside the computing board. Subsequently, the extracted duration of the high and low levels and the distribution of transition edges are meticulously matched one by one with the corresponding timing features in a preset normal response mode. This one-by-one matching method can accurately identify any subtle differences in the response signal that do not conform to the normal mode, thereby generating detailed matching results. If any mismatch exists in the matching results, it indicates that a specific chip on the computing board under test may be abnormal. Based on the nature and location of these mismatches, the diagnostic device can infer the location of the abnormal chip and the type of fault, such as clock signal abnormality, data line level error, or response delay of a specific chip. Finally, these detailed diagnostic results, including the location and type of abnormal chip and normal operation indicators, are clearly displayed on the test interface. In this way, the solution refines the general "abnormal" state into specific fault information, which greatly improves the accuracy and efficiency of fault diagnosis, enabling maintenance personnel to quickly locate the problem and take targeted measures, thus solving the problem that traditional methods have difficulty in accurately identifying the location and type of fault.

[0081] In one embodiment of this invention, when the fault diagnosis device receives a response signal from the computing board under test, it can use its built-in high-speed analog-to-digital converter (ADC) to digitally sample the analog response signal, or directly process the digital response signal. Subsequently, the signal processing module running on the processor performs timing analysis on the sampled data, for example, identifying the rising and falling edges of the signal and accurately measuring the duration of each high or low level, thereby obtaining the high and low level duration periods of the response signal. Furthermore, the time points of each transition edge can be recorded to form a transition edge distribution. For example, if the preset normal response mode requires a signal to complete a high-low level transition within 100ns, with the high level lasting 50ns and the low level lasting 50ns, then the diagnostic device will accurately measure these parameters of the actual response signal. Next, the diagnostic device will compare these extracted high and low level duration periods and transition edge distributions one by one with the standard timing features stored in the preset normal response mode. For example, if the duration of a high-level signal is 20ns shorter than a preset value, or if a transition edge is 15ns delayed beyond the expected time, these will be marked as mismatches. Based on these mismatches, the system can use a pre-established fault diagnosis rule base. For instance, if a specific bit line of a data bus remains low, it may indicate a fault in the corresponding driver or receiver chip. The diagnostic device will then determine the location of the faulty chip, such as "pin 3 of chip A," and identify the fault type, such as "data line short circuit" or "insufficient drive capability." Ultimately, this detailed information on the location of the faulty chip and the fault type, or the "normal operation" indicator displayed when all matches are consistent, will be visually presented on the test interface of the fault diagnosis device for operator reference.

[0082] Through the above technical solution, this embodiment can perform timing analysis and level feature extraction on the received response signal, thereby obtaining key timing features such as the duration period of high and low levels and the distribution of transition edges. This detailed feature extraction and one-to-one matching with preset normal response patterns enable the diagnostic device to accurately identify any subtle anomalies in the response signal. When mismatches exist, this embodiment can accurately determine the specific location and fault type of the abnormal chip in the computing board under test based on the characteristics of these mismatches, rather than simply providing a general anomaly message. This greatly improves the accuracy and efficiency of fault diagnosis, enabling maintenance personnel to obtain specific and actionable fault information, thereby quickly locating the problem and performing targeted repairs, significantly shortening troubleshooting time and reducing maintenance costs. When all features match, the diagnostic device can also clearly display a normal operation indicator, avoiding misjudgment.

[0083] The above methods mainly focus on high-precision timing analysis of the digital level response signals generated during the operation of the test firmware. However, the lack of control over the power supply may prevent the simulation of the actual working conditions of the computing board under different power supply conditions during the diagnostic process. This makes it difficult to discover potential faults that are sensitive to voltage and current fluctuations or only appear under specific power supply timing, thus affecting the comprehensiveness and accuracy of fault diagnosis.

[0084] Therefore, referring to Figure 6 Another embodiment of the present invention provides a fault diagnosis method, based on the above. Figure 1 In the embodiment shown, the connection interface has a control signal terminal for connecting a controllable DC power supply, and the output terminal of the controllable DC power supply is connected to the power input terminal of the computing board under test.

[0085] The connection interface is designed to include a control signal terminal specifically for communicating and controlling a controllable DC power supply. The output of the controllable DC power supply is directly connected to the power input of the computing board under test (DUT). This configuration allows the fault diagnosis equipment to directly manage and regulate the power supplied to the DUT. For example, the control signal terminal could be a digital communication interface through which commands are sent to the controllable DC power supply; alternatively, it could be an analog control interface that regulates the power output via voltage or current signals. Through this connection, the fault diagnosis equipment can achieve precise control of the power supply to the computing board, rather than relying solely on a fixed external power source.

[0086] In response to the selection of the model of the computing power board under test, after displaying the test interface corresponding to the computing power board under test, the process further includes step S300, wherein: S300, in response to adjustment commands for electrical parameters, adjusts the supply voltage, supply current and delay time of the controllable DC power supply output.

[0087] Step S300 refers to the diagnostic device adjusting the output parameters of the controllable DC power supply according to specific instructions before fault diagnosis. These instructions can be manually input by the user on the test interface or from a preset automated test script. Adjustable electrical parameters include supply voltage, supply current, and delay time. Adjusting the supply voltage allows testing the stability of the computing board under different voltage conditions (such as undervoltage, overvoltage, or nominal voltage); adjusting the supply current can simulate different load conditions or test current limits; and the delay time controls the duration of power supply or the waiting time after power failure following a specific event (such as data return), which is crucial for testing transient response or ensuring the stability of the test environment. For example, adjustments can be made by sending specific digital commands to the controllable DC power supply or by adjusting the analog control input of the power supply.

[0088] In response to the testing operation on the computing board under test, the test firmware is run, including step S240, wherein: S240. In response to the detection operation on the computing power board under test, the controllable DC power supply is controlled to supply power to the computing power board under test according to the adjusted supply voltage and supply current, and a corresponding first detection signal is sent to the computing power board under test. Within the delay time after the computing power board under test returns response data, the power supply connection between the controllable DC power supply and the computing power board under test is disconnected.

[0089] Step S240 describes how the fault diagnosis equipment coordinates the control of the power supply and detection signals during the actual testing process. When the detection operation is triggered, the fault diagnosis equipment instructs the controllable DC power supply to provide power to the computing board under test according to the pre-adjusted supply voltage and current. Simultaneously, the diagnostic device sends a first detection signal to the computing board under test. This synchronous operation ensures that the detection signal is applied under precisely controlled power conditions. More importantly, after the computing board under test returns response data, the fault diagnosis equipment quickly disconnects the power supply connection between the controllable DC power supply and the computing board within a preset delay time. This power timing control ensures the testing of the computing board's startup and shutdown behavior, transient response, and that each test is performed in a consistent initial state. For example, control can be implemented using a microcontroller or field-programmable gate array (FPGA) within the diagnostic equipment, which can precisely manage the switching of the power supply and the transmission of detection signals.

[0090] This embodiment significantly enhances the depth and flexibility of fault diagnosis by introducing the integration and management of a controllable DC power supply. The connection interface is designed to accept a controllable DC power supply, and the power supply can be commanded and controlled via a control signal terminal, directly connecting the power output to the power input of the computing board under test (DUT). After the user selects the DUT model and the test interface is displayed, the diagnostic device allows the user or automated program to adjust the output parameters of the controllable DC power supply according to diagnostic needs. These adjusted electrical parameters include the supply voltage, supply current, and supply delay time. Adjusting these parameters allows the diagnostic device to simulate the power environment of the computing board under various extreme or specific operating conditions. When the actual testing operation is initiated, the fault diagnosis device precisely controls the controllable DC power supply, ensuring it supplies power to the DUT according to the preset adjustment parameters. During this power supply process, the diagnostic device sends a first detection signal to the computing board, ensuring the signal is applied under stable and controlled power conditions. More importantly, after the DUT returns response data, the fault diagnosis device quickly and accurately disconnects the power connection within a preset delay time. This power timing control, including the adjustment of power supply parameters and the timely disconnection of power supply, enables the diagnostic process to comprehensively evaluate the performance, stability and transient response of the computing board under different power conditions. This allows for the discovery of potential faults that are difficult to expose under traditional fixed power supply testing, greatly improving the accuracy and reliability of fault diagnosis.

[0091] In one embodiment of this invention, when diagnosing a fault in a certain model of computing board under test, it is first connected to the fault diagnosis device via a connection interface. On the test interface, the user can input adjustment commands according to the characteristics of the computing board or specific test requirements. For example, the user can set the supply voltage of the controllable DC power supply to 1.05V (lower than the nominal voltage, used to test undervoltage stability), limit the supply current to 8A, and set a 150-millisecond delay to disconnect the power supply after the computing board returns response data.

[0092] When a user initiates a testing operation, the fault diagnosis device sends a command to a controllable DC power supply (e.g., a programmable precision power module) via its control signal terminal, instructing it to output 1.05V and limit the maximum current to 8A. This power supply output is then connected to the computing board under test (DUT). The moment the power supply stabilizes, the fault diagnosis device sends a preset first detection signal (e.g., a specific data sequence used to test the functionality of the computing board's internal registers or logic units) to the DUT. The DUT executes the corresponding operation and returns response data. Once the fault diagnosis device receives and parses this response data, it immediately starts a timer and, after a 150-millisecond delay, sends a power-off command to the controllable DC power supply, thus quickly cutting off power to the computing board. This power control and timing management allows the diagnostic device to simulate various power conditions that the computing board might encounter in a real-world operating environment, thereby more effectively identifying potential faults.

[0093] Through the above technical solution, this embodiment can precisely control the power supply voltage, current, and duration provided by the fault diagnosis equipment to the computing board under test. This allows the diagnostic process to simulate the operating environment of the computing board under test under different electrical parameters, such as under-voltage, over-voltage, or specific load conditions. By sending detection signals and monitoring responses under controlled power conditions, the performance and stability of the computing board can be more comprehensively evaluated, thereby effectively identifying potential faults that are sensitive to power fluctuations or only manifest under specific electrical parameters. In addition, the power disconnection sequence helps test the transient response and reset behavior of the computing board, improving the depth and accuracy of fault diagnosis and avoiding missed or misdiagnosed cases due to uncertain power conditions.

[0094] In practical applications, simply displaying the current operating status of the computing board under test may not be sufficient to meet complex fault diagnosis needs. For example, users may need to understand the historical operating status of the computing board, the frequency of fault occurrence, the trend of fault types over time, or evaluate its stability after multiple repairs. The lack of effective management and presentation of historical diagnostic data makes it difficult for users to conduct in-depth fault analysis and long-term performance evaluation.

[0095] Optionally, refer to Figure 7 Another embodiment of the present invention provides a fault diagnosis method, based on the above. Figure 1 The illustrated embodiment further includes steps S400-S600, wherein: S400: Record the working status of each test, extract the test timing, chip running status and test count from each record, and generate the corresponding test log; S500: Obtain the computing board model data and corresponding test data for each test record in the test log; S600, in response to a query command for the test log, retrieves the computing board model data and test data, arranges them sequentially according to the corresponding time order, and displays them on the test interface.

[0096] Step S400 aims to build a comprehensive historical diagnostic data storage mechanism. The detection log can be a structured database (e.g., a relational database or a NoSQL database) or a specific format file (e.g., JSON, XML, or CSV) stored in a file system. Recording the detection status refers to saving the final working status of the computing board under test (e.g., "Normal," "Abnormal: Chip A01 overheating," "Abnormal: Communication error") determined by the test firmware after each diagnostic operation. This can be achieved by the processor in the fault diagnosis device performing a data write operation at the end of the diagnostic process. Extracting the detection timing refers to acquiring and recording the exact time point of each detection, typically accurate to the second or millisecond, which can be achieved using the timestamp information provided by the system clock module. Extracting the operating status of each chip refers to recording in detail the specific performance of each chip on the computing board under test during the detection process, such as the response status, error code, performance parameters, etc. of each chip. This information can be obtained by parsing the detailed diagnostic report returned by the test firmware. Extracting the number of detections refers to the cumulative count of diagnostics performed on a specific computing board under test or a specific test item. This can be dynamically calculated by maintaining a counter variable or querying historical records. Generating the corresponding detection log involves integrating all the extracted information and storing it in a predefined format to ensure data integrity and traceability.

[0097] Step S500 aims to associate the diagnostic results with the specific computing board model and test conditions. The computing board model data refers to the unique identifier or product model information of the computing board under test. This data is typically captured by the system when the user selects the model and stored along with subsequent test records. Test data refers to the specific parameters and environmental information related to each test operation, such as the test firmware version used, the test mode (e.g., full-function test, partial test), the characteristics of the input signals, and the test duration. This data is crucial for understanding the context of the diagnostic results and reproducing the test conditions; it can be collected before or during the test and saved along with the test records.

[0098] Step S600 aims to provide a user-friendly historical data query and display function. The query command for the detection log is a request issued by the user through the test interface. For example, the user might select a specific computing board model or specify a time range to view its historical diagnostic records. This query command can be triggered through interactive elements on the user interface such as buttons, input boxes, left and right screen swipes, or drop-down menus. Retrieving computing board model data and test data means that the fault diagnosis device retrieves all records that meet the conditions from the stored detection logs according to the query command. This can be achieved through database query languages ​​or file parsing algorithms. Arranging in chronological order means sorting the retrieved historical records in ascending or descending order according to their detection time sequence (timestamp) to present a clear timeline. Displaying on the test interface means displaying the sorted historical diagnostic data on the user interface, such as in the form of lists, tables, or charts, allowing users to intuitively view and analyze the long-term performance and fault evolution of the computing board.

[0099] This embodiment systematically records the working status, detection sequence, operating status of each chip, and number of tests of the computing board under test after each fault diagnosis operation. Combined with the computing board model data and test data, it generates a detailed detection log. When the user needs to review historical diagnostic information, the fault diagnosis device can respond to query commands, efficiently retrieve relevant data from the detection log, arrange it chronologically, and finally present it intuitively to the user on the test interface. This mechanism allows fault diagnosis to go beyond the immediate results of a single test, providing a comprehensive, time-series-based diagnostic view. In this way, users can clearly track performance changes of the computing board, the frequency of fault occurrence, the evolution of fault types, and the effectiveness evaluation after repair, thereby greatly improving the depth and breadth of fault diagnosis and providing a more solid data foundation for computing board maintenance, fault analysis, and lifespan prediction.

[0100] In one embodiment of this example, a fault diagnosis device is connected to a computing board under test. First, the user selects the model of the computing board on the test interface, and the diagnostic device loads the corresponding test firmware. Then, the user initiates a test operation, the test firmware runs, and the computing board's operating status is determined; for example, the test result displays "Abnormal: Chip A01 temperature too high." At this time, the fault diagnosis device automatically records detailed information about the test, including the timestamp of the test (e.g., "2023-10-27 10:35:12"), the abnormal temperature state of chip A01, the operating status of other chips, that this is the 5th test for this computing board, and the test firmware version and test mode used. This data is structured and stored in the fault diagnosis device's internal database as part of the test log. When an engineer needs to view the historical diagnostic records of the computing board, they can select the "historical query" function on the test interface, or use the drop-down or left / right swipe function on the test interface. The diagnostic device will immediately retrieve all historical records related to this model from the test log and sort them from earliest to latest according to the test time. The test interface will then display a list, for example: 2023-10-26 09:00:00 - Running normally; 2023-10-26 15:30:00 - Error: Communication error in chip C03; 2023-10-27 10:35:12 - Anomaly: Chip A01 temperature is too high.

[0101] Engineers can click on any record to view more detailed chip operating status and test data, thereby gaining a comprehensive understanding of the health status evolution of the computing board.

[0102] Through the above technical solution, the fault diagnosis equipment can systematically record the results of each test on the computing board, including detailed test timing, the operating status of each chip, and the number of tests, and integrate this into a traceable test log. When it is necessary to review or analyze historical data, users can easily query and view all diagnostic records for a specific computing board in chronological order. This allows users not only to understand the current operating status of the computing board, but also to track its performance change trends, identify intermittent failure modes, or evaluate the effectiveness of maintenance, thereby significantly improving the depth and efficiency of fault diagnosis and providing more comprehensive and reliable data support for the maintenance, fault analysis, and lifespan prediction of the computing board.

[0103] When the working status of the computing board under test is determined to be abnormal, simply knowing its abnormal status cannot directly guide the user to effectively locate and repair the fault. The user still needs to spend a lot of time troubleshooting, and may not be able to accurately determine the fault point and repair method due to a lack of professional knowledge, thus affecting the efficiency of fault diagnosis and the convenience of repair.

[0104] Therefore, referring to Figure 8 The present invention provides a fault diagnosis method based on the above. Figure 1 The embodiment shown further includes steps S700-S900, wherein: S700: If the working status is abnormal, obtain the abnormal chip in the computing board, the abnormal location and the fault type. S800 displays the effect diagram of the computing board corresponding to the computing board under test, and marks the abnormal locations on the computing board effect diagram; S900: In response to the selection of an abnormal location on the computing board rendering, it displays the fault type and suggested repair solution corresponding to the abnormal location.

[0105] When the operating status of the computing board under test is determined to be abnormal, specific fault information needs to be obtained. This includes: an abnormal chip (integrated circuit or functional module detected as malfunctioning on the board); an abnormal location (the physical coordinates or marked area of ​​the abnormal chip on the board); and a fault type (the specific fault mode exhibited by the abnormal chip, such as short circuit, open circuit, overheating, or data transmission error). This information can be obtained by parsing detailed diagnostic data collected during the test firmware's operation. For example, the test firmware can send specific detection signals to each chip on the computing board and receive responses. By comparing the response signals with preset normal patterns, it can identify the abnormal chip and its physical address on the board, and match the characteristic patterns of the abnormal response to a preset fault database to determine the specific fault type. Alternatively, if the test firmware finds that a specific register value, status bit, or output waveform of a chip deviates from the normal range during testing, it can directly locate the abnormal location of the chip according to a preset mapping relationship and classify it into the corresponding fault type based on the nature of the deviation.

[0106] The computing board rendering is a graphical representation of the computing board under test, typically a two-dimensional or three-dimensional view of its physical layout, used to visually demonstrate the board's structure and component distribution. This rendering can be pre-stored in the fault diagnosis equipment's memory and loaded and displayed according to the model of the computing board under test. After acquiring anomaly location information, the fault diagnosis equipment will visually highlight or mark the anomaly location on the computing board rendering. For example, it can be marked by changing the color of the anomaly area, flashing it, adding arrow indicators, or overlaying text labels above the anomaly chip, allowing users to quickly and accurately identify the specific physical location of the fault. The selection operation refers to the user's action of selecting the anomaly location marked on the computing board rendering through the human-computer interaction interface. This can be achieved in various ways, such as using a mouse click, touchscreen control, or keyboard navigation to select the marked anomaly location. Once the user completes the selection operation, the fault diagnosis equipment will immediately display a detailed fault type description associated with the anomaly location and the corresponding repair plan on the test interface. Repair solutions can be differentiated based on the user's level of experience. For example, for novice users, detailed and simple instructions can be provided, such as "check if the connection cable is loose"; for experienced users, more professional and in-depth advice can be provided, such as "replace the capacitor of a specific model" or "check the impedance of a specific signal line".

[0107] This embodiment significantly improves the practicality of fault diagnosis and user experience by providing detailed fault location and repair guidance after determining that the working state of the computing board under test is abnormal. Specifically, when the fault diagnosis device determines that the working state of the computing board under test is abnormal by running the test firmware, it no longer stops at the general conclusion of "abnormal," but deeply analyzes the diagnostic data returned by the test firmware to accurately obtain the specific chip causing the abnormality, the physical location of the chip on the computing board, and the type of fault. Subsequently, to intuitively present this complex fault information to the user, the diagnostic device loads and displays a rendering of the computing board matching the model of the computing board under test, and marks the abnormal location in a prominent manner on the rendering. This visualization method allows users to quickly locate the fault point without having in-depth professional knowledge. Furthermore, to provide actionable solutions, the diagnostic device allows users to interact with the abnormal location on the rendering by selecting an operation. Once selected, the diagnostic device immediately displays a detailed description of the fault type corresponding to that abnormal location and provides suggested repair solutions for different levels of users, such as novices and experienced users, based on preset rules or user configuration. This complete process, from fault discovery and location to providing personalized repair guidance, enables fault diagnosis equipment to transform from a simple "detection tool" into an "intelligent repair assistant," greatly lowering the threshold for fault diagnosis and repair and improving repair efficiency and accuracy.

[0108] In one implementation, when the fault diagnosis device detects an abnormal operating status of the computing board under test by running test firmware, for example, the test firmware reports a data transmission error for a specific chip, the fault diagnosis device will identify the abnormal chip as an "ASIC chip" based on the diagnostic results of the test firmware. The abnormal location is located in the upper left corner of the computing board, and the fault type is "data bus error." Subsequently, the fault diagnosis device will load and display a two-dimensional planar image of the computing board model on its display component. On this image, the "ASIC chip" area will be highlighted, possibly accompanied by a flashing red border, with the word "Abnormal" displayed above the chip, or the corresponding computing power value displayed above the chip. The user can trigger a selection operation by touching or long-pressing the highlighted area on the display component. In response to this operation, the display component will pop up a dialog box, which details "Fault type: ASIC chip data bus error, possible causes: poor soldering of pads or internal logic error of the chip." In addition, the dialog box will provide two types of suggested repair solutions: For novice users, the suggested solutions may be "1. Check if the solder joints around the ASIC chip are obviously loose or oxidized; 2. Try reseating the computing board to ensure a secure connection"; For experienced users, the suggested solutions may be "1. Use a multimeter to measure the impedance to ground of the ASIC chip's data bus pins to check for short circuits or open circuits; 2. Use a hot air gun to repair or replace the ASIC chip using BGA".

[0109] Through the above technical solution, when the operating status of the computing board under test is determined to be abnormal, the fault diagnosis equipment can provide more detailed and intuitive fault information. Users can not only be aware of the fault's existence but also visually locate the specific abnormal chip and its location through the computing board's diagram, significantly shortening troubleshooting time. Furthermore, the diagnostic device provides detailed fault type descriptions based on the abnormal location and suggested repair solutions tailored to users with different experience levels, enabling repair personnel to quickly understand the nature of the fault and obtain actionable repair guidance. This effectively lowers the professional threshold and trial-and-error costs of repair, thereby significantly improving the efficiency of fault diagnosis and the success rate of repairs.

[0110] The present invention also proposes a diagnostic device, which includes: a memory, a processor, and a fault diagnosis program stored in the memory and executable on the processor, the fault diagnosis program being configured to implement the fault diagnosis method described above.

[0111] In this context, a diagnostic device refers to a hardware system specifically designed to perform fault diagnosis tasks, aiming to provide a stable, efficient, and user-friendly diagnostic environment. Memory is a hardware component used to store data and instructions, providing the processor with program code and the data required for runtime. Memory can include, but is not limited to, Random Access Memory (RAM), Read-Only Memory (ROM), Flash Memory, or Hard Disk Drive (HDD). The processor is the core computing unit of the diagnostic device, responsible for executing instructions in memory, performing data operations, and controlling the entire diagnostic process. The processor can be a Central Processing Unit (CPU), Microcontroller (MCU), Field-Programmable Gate Array (FPGA), or Application-Specific Integrated Circuit (ASIC). A fault diagnosis program is a pre-written set of instructions that guides the processor to execute fault diagnosis methods according to specific logic and steps. Fault diagnosis programs can exist in the form of firmware, applications within the operating system, or scripts. The fault diagnosis program is stored in memory, meaning the program code is persistently or temporarily loaded into the storage medium so that the processor can access and read these instructions. The fault diagnosis program can run on the processor, indicating that the processor can parse and execute the program instructions in memory, thereby driving the diagnostic device to complete its various functions. The fault diagnosis program is configured to implement the above fault diagnosis method, meaning that the program's design and coding fully follow the logic and steps of the above fault diagnosis method, ensuring that the diagnostic device can accurately and completely execute all aspects of the method.

[0112] It is worth noting that since the diagnostic device of the present invention is based on the above-described fault diagnosis method, the embodiments of the diagnostic device of the present invention include all the technical solutions of all embodiments of the above-described fault diagnosis method, and the technical effects achieved are exactly the same, so they will not be repeated here.

[0113] The present invention also proposes a fault diagnosis device, which includes a display component, a connection interface, and a diagnostic device as described in all the embodiments above, wherein: The display component is used to present the test interface and the working status of the computing board under test; the connection interface is used to connect the computing board under test; the diagnostic device is electrically connected to the display component and the connection interface respectively; the diagnostic device is used to respond to the user's selection of the model of the computing board under test on the display component, obtain the test firmware corresponding to the model of the computing board under test, and display the test interface corresponding to the computing board under test on the display component; the diagnostic device is also used to respond to the user's detection operation on the display component for the computing board under test, run the test firmware, and determine the working status of the computing board under test.

[0114] The core innovation of this embodiment lies in the integrated design of the display component, connection interface, and diagnostic device, thereby achieving an automated fault diagnosis process for different models of computing boards. In practice, the user only needs to select the model of the computing board under test through the display component; the diagnostic device automatically acquires the matching test firmware and displays a dedicated test interface. When the user triggers a detection operation, the diagnostic device runs the test firmware to complete the diagnosis, eliminating the need for manual chip location based on circuit diagrams or point-by-point voltage signal testing with a multimeter. This design avoids the drawbacks of traditional methods that rely on the experience of maintenance personnel for manual operation, significantly improving diagnostic efficiency and accuracy. Furthermore, since the test firmware can be dynamically loaded according to the model, the device is compatible with various brands and models of computing boards, solving the problem of poor compatibility with specialized tools. Through the above technical solution, this application effectively lowers the operational threshold, shortens the maintenance cycle, and increases the fault location accuracy to over 95%, providing an efficient and reliable solution for the batch testing of computing boards.

[0115] It is worth noting that since the fault diagnosis device of the present invention is based on the above-mentioned diagnostic device, the embodiments of the fault diagnosis device of the present invention include all the technical solutions of all the embodiments of the above-mentioned diagnostic device, and the technical effects achieved are exactly the same, so they will not be repeated here.

[0116] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A fault diagnosis method, applied to a fault diagnosis device, the fault diagnosis device including a connection interface for connecting a computing board under test, characterized in that, The fault diagnosis method includes: In response to the selection of the model of the computing board under test, the test firmware corresponding to the model of the computing board under test is obtained, and the test interface corresponding to the computing board under test is displayed. In response to the testing operation on the computing board under test, the test firmware is run to determine the working status of the computing board under test.

2. The fault diagnosis method as described in claim 1, characterized in that, The step of running the test firmware in response to a detection operation on the computing board under test and determining the working state of the computing board under test includes: In response to the detection operation, the test firmware is loaded and started running; Obtain the first detection signal from the test firmware and send the first detection signal to the computing board under test; The system monitors the response signal fed back by the computing board under test, compares the response signal with the preset normal response mode, determines the working status of the computing board under test, and displays the working status on the test interface.

3. The fault diagnosis method as described in claim 2, characterized in that, The step of sending the first detection signal to the computing board under test specifically involves: Obtain the chip code sequence of each chip in the computing board under test; Based on the chip space layout topology order and signal transmission timing rules represented by the chip encoding sequence, the first detection signal is transmitted sequentially to the corresponding chip.

4. The fault diagnosis method as described in claim 2, characterized in that, The step of sending the first detection signal to the computing board under test specifically involves: Obtain the chip array hardware topology of the computing board under test, and traverse and extract the physical address identification information of each chip in the chip array hardware topology. The first detection signal is transmitted in parallel to the corresponding chip according to the signal transmission path determined by the physical address identification information.

5. The fault diagnosis method as described in claim 2, characterized in that, The process of monitoring the response signal fed back by the computing board under test, comparing the response signal with a preset normal response mode to determine the working status of the computing board under test, and displaying the working status on the test interface includes: The response signal is subjected to timing analysis and level feature extraction to obtain the high and low level duration period and transition edge distribution of the response signal; The duration of the high and low levels and the distribution of the transition edges are matched one by one with the timing features in the preset normal response mode to generate corresponding matching results. If there are mismatches in the matching results, it is determined that the chip of the computing board under test is abnormal, and the location and fault type of the abnormal chip are determined according to the mismatches, and the location and fault type of the abnormal chip are displayed on the test interface. If the matching results are consistent, it is determined that the computing board under test is in normal working condition, and a normal operation indicator is displayed on the test interface.

6. The fault diagnosis method as described in claim 1, characterized in that, The connection interface has a control signal terminal for connecting to a controllable DC power supply, and the output terminal of the controllable DC power supply is connected to the power input terminal of the computing board under test. After responding to the selection of the model of the computing power board under test and displaying the test interface corresponding to the computing power board under test, the method further includes: In response to adjustment commands for electrical parameters, the supply voltage, supply current, and delay time of the controllable DC power supply are adjusted. The step of running the test firmware in response to a detection operation on the computing board under test includes: In response to the detection operation on the computing board under test, the controllable DC power supply is controlled to supply power to the computing board under test according to the adjusted supply voltage and supply current, and a corresponding first detection signal is sent to the computing board under test. Within the delay time after the computing board under test returns response data, the power supply connection between the controllable DC power supply and the computing board under test is disconnected.

7. The fault diagnosis method as described in claim 1, characterized in that, The fault diagnosis method further includes: Record the working status of each test, extract the test timing, chip operating status and test count from each record, and generate the corresponding test log; Obtain the computing board model data and corresponding test data for each test record in the test log; In response to a query command for the test log, the computing board model data and the test data are retrieved, arranged in the corresponding time order, and displayed on the test interface.

8. The fault diagnosis method as described in claim 1, characterized in that, The fault diagnosis method further includes: If the working state is abnormal, obtain the abnormal chip, abnormal location and fault type in the computing board; Display the rendering of the computing board corresponding to the computing board under test, and mark the abnormal locations on the rendering of the computing board; In response to the selection of an abnormal location on the computing board rendering, the fault type and suggested repair solution corresponding to the abnormal location are displayed.

9. A diagnostic device, characterized in that, The diagnostic device includes: a memory, a processor, and a fault diagnosis program stored in the memory and executable on the processor, the fault diagnosis program being configured to implement the fault diagnosis method as described in any one of claims 1 to 8.

10. A fault diagnosis device, characterized in that, The fault diagnosis equipment includes: The display component is used to present the test interface and the working status of the computing board under test. A connection interface, wherein the connection interface is used to connect to the computing board under test; and The diagnostic device as claimed in claim 9, wherein the diagnostic device is electrically connected to the display component and the connection interface, respectively; The diagnostic device is used to respond to the user's selection of the model of the computing board under test on the display component, obtain the test firmware corresponding to the model of the computing board under test, and display the test interface corresponding to the computing board under test on the display component. The diagnostic device is also used to run the test firmware in response to a user's detection operation on the display component for the computing board under test, and to determine the working status of the computing board under test.

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