A Hotspot Detection Method for Integrated Circuit Layout Based on R-tree Graph Construction

Abstract

This invention discloses a hotspot detection method for integrated circuit layouts based on R-tree graph construction. First, each independent and continuous polygon in the integrated circuit layout file is created as a node in the graph structure. An R-tree is used to establish spatial adjacency relationships, and polygon contour expansion technology is employed to determine node connectivity. When the expanded polygons have overlapping areas, connecting edges are established, thus constructing the graph structure. This graph structure is then input into a graph neural network model to obtain the hotspot prediction results for each node. This invention achieves an innovative solution that accurately preserves the geometric features of the layout while efficiently constructing the graph structure, completely avoiding rectangular segmentation. This effectively improves the model's representation ability and detection efficiency for complex real-world layouts.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a method for detecting hotspots in integrated circuit layouts based on R-tree graph construction. Background Technology

[0002] In advanced photolithography, when the exposure wavelength is on the same order of magnitude as or even longer than the design pattern size, light diffraction becomes extremely significant. This causes a severe deviation between the pattern projected onto the photoresist and the design intent on the mask. For example, a right angle designed in the original design might be printed as a rounded corner, the ends of dense lines might shrink, and the width of isolated lines might differ from that of dense lines. This optical distortion caused by the interaction of adjacent patterns is one of the main causes of hot spots, which can easily lead to bridging or open circuits. The essence of a hot spot is a mismatch between design and process: certain combinations of patterns, topologies, or environmental contexts in the layout, after undergoing a series of non-ideal manufacturing steps, result in insufficient robustness, thus "resonating" and amplifying within a specific process window, evolving into a deterministic manufacturing defect point, i.e., a hot spot.

[0003] Currently, mainstream hotspot detection methods mainly fall into three categories: lithography simulation, pattern matching, and machine learning. Lithography simulation methods, by accurately modeling the lithography process, can identify potential hotspots relatively accurately; however, they consume enormous computational resources, especially at advanced process nodes, significantly extending the overall design cycle as design scale rapidly increases. Pattern matching methods rely on known hotspot libraries, achieving rapid detection by searching the layout for regions with similar patterns to those in the library. While highly efficient, their detection capability is limited by the completeness of the existing hotspot library, and they lack the ability to identify novel or unknown hotspots. In recent years, machine learning technology has shown significant potential in the field of hotspot detection, making positive progress in improving detection speed and predicting unknown hotspots. Existing machine learning-based hotspot detection methods mostly borrow from mature models in computer vision, such as convolutional neural networks (CNNs) and Transformers, and improve model recognition accuracy by introducing attention mechanisms or Inception modules. However, such methods typically convert the layout into an image representation, which has several inherent limitations: image representation introduces a large amount of background information unrelated to hotspots, interfering with model judgment; the geometric accuracy of the layout is inevitably lost during the rasterization process; and it is limited by a fixed input size, making it difficult to flexibly adapt to layout areas of different sizes.

[0004] While other methods exist for hotspot detection, such as constructing a graph representation of the map using a rectangular segmentation strategy and leveraging graph neural networks (GNNs) for hotspot detection, these methods effectively reduce computational overhead while maintaining high-precision geometric information of the map, achieving a good balance between detection accuracy and computational efficiency. However, the rectangular segmentation step not only incurs significant computational costs, increasing the overall complexity and time cost of the process, but also increases the number of nodes and edges in the graph, thus limiting the model's ability to accurately model and generalize to complex real-world maps. Furthermore, rectangular segmentation is only applicable to Manhattan polygons, limiting its application in hotspot detection.

[0005] Therefore, there is still an urgent need for a detection solution that can simultaneously achieve high detection speed and strong ability to predict unknown hotspots. Summary of the Invention

[0006] The purpose of this invention is to address the shortcomings of existing technologies by providing a hotspot detection method for integrated circuit layouts based on R-tree graph construction. This method transforms the original, continuous layout data into a discrete, semantically rich graph data structure G = (V, E), where V is the set of nodes and E is the set of edges. Its core lies in completely bypassing rectangular partitioning and directly constructing the graph based on the polygonal geometric entities of the layout. This method fully preserves the geometric accuracy and topological information of the layout, thereby significantly improving the accuracy and generalization ability of hotspot detection.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] In a first aspect, the present invention provides a method for detecting hotspots in integrated circuit layout based on R-tree graph construction, comprising the following steps:

[0009] Traverse the layout file, create each independent and continuous polygon as a node in the graph structure, and extract the geometric information of the polygon as node features;

[0010] Calculate the minimum bounding rectangle (MBR) of each node, organize all the minimum bounding rectangles (MBR) into an R-tree structure to construct the R-tree spatial index, and perform a neighborhood search on each node through the R-tree spatial index to form a candidate neighbor node set;

[0011] For each candidate node pair in the candidate neighbor set, determine whether there is an interaction between them. If there is, establish an undirected edge between the two nodes and use the strength value of the interaction as the edge feature.

[0012] Construct a layout graph structure based on all nodes, edges, node features, and edge features;

[0013] The graph structure is input into a pre-trained graph neural network model, which outputs the hotspot prediction results for each node.

[0014] Furthermore, the neighborhood search specifically involves: for any node Using its minimum bounding rectangle (MBR) as the center, a preset neighborhood search radius is expanded outward to form a query window. The R-tree spatial index is then used to retrieve all nodes where the minimum bounding rectangle intersects with the query window. To form the candidate node set .

[0015] Furthermore, determining whether there is an interaction between them specifically involves:

[0016] For each node and nodes The corresponding polygonal outline is expanded equidistantly. A Boolean intersection operation is performed on the expanded two polygons to calculate the area of ​​the overlapping region. If the area of ​​the overlapping region is greater than 0, then at the node... and nodes Establish an undirected edge between them The area of ​​the overlapping region is used as the edge feature.

[0017] Furthermore, when performing equidistant expansion, the expansion distance d is defined as the error tolerance in the photolithography process or the critical distance at which bridging may occur.

[0018] Furthermore, the geometric information of the polygon includes a sequence of vertex coordinates of the polygon, and the vertex coordinate sequence is normalized before being input into the graph neural network.

[0019] Furthermore, the graph neural network model employs a graph convolutional network (GCN), a graph sample and aggregate network (GraphSAGE), or a graph attention network (GAT), and the hotspot prediction result is a classification label or a regression value representing the probability of a node becoming a hotspot.

[0020] Secondly, the present invention provides an integrated circuit layout hotspot detection system for implementing the above method, comprising:

[0021] The layout acquisition module acquires the integrated circuit layout file and creates each independent and continuous polygon in it as a node in the graph structure, while extracting the geometric information of the polygon as node features;

[0022] The R-tree building module is used to calculate the minimum bounding rectangle of each node, organize all the minimum bounding rectangles into the R-tree structure, and build the R-tree spatial index.

[0023] The neighborhood search module performs a neighborhood search on each node using the R-tree spatial index to form a set of candidate neighboring nodes;

[0024] The interaction determination module determines whether there is an interaction between each candidate node pair in the candidate neighbor node set. If there is, an undirected edge is established between the two nodes, and the strength value of the interaction is used as the edge feature.

[0025] The hotspot detection module constructs a graph structure based on all nodes, edges, node features, and edge features, and inputs the graph structure into a pre-trained graph neural network model, which then outputs the hotspot prediction result for each node.

[0026] Thirdly, the present invention provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above-described method.

[0027] Fourthly, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the above-described method.

[0028] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0029] This invention constructs an R-tree spatial index, using the minimum bounding rectangle (MBR) of polygons as the index unit. It performs subsequent geometric determination only on spatially adjacent polygons, significantly reducing the number of candidate node pairs and achieving efficient graph structure construction. This lays the foundation for accurate subsequent connection relationship determination and solves the problem of high computational overhead in global traversal. The original coordinate sequences of polygons are used as node features within the graph structure to maximize geometric accuracy, and the area of ​​overlapping regions is used as edge features to quantify interaction strength, providing crucial physical information for the model. This invention eliminates the need for rectangular segmentation to construct the graph structure; instead, it directly treats each complete polygon in the layout as a node, reducing operational complexity and enabling the method to be applied to non-Manhattan layouts, thus expanding the applicability of hotspot detection models.

[0030] Furthermore, when determining whether to establish a connection edge between nodes, this invention not only considers geometric proximity but also reflects the error tolerance and bridging risk in the photolithography process through contour expansion and overlap area calculation, thereby realizing physically meaningful adjacency modeling, enabling the graph structure to more realistically represent potential optical coupling effects. Attached Figure Description

[0031] Figure 1 This is a flowchart of the present invention.

[0032] Figure 2 This is a schematic diagram illustrating the specific implementation of neighborhood search. Detailed Implementation

[0033] The present invention will be further described below with reference to the embodiments.

[0034] like Figure 1 As shown, this invention provides a method for detecting hotspots in integrated circuit layouts based on R-tree graph construction, comprising the following steps:

[0035] 1. Node definition and creation: Traverse the entire layout file (such as GDSII), and for each independent, continuous polygon geometry, whether it is a Manhattan rectangle or a non-Manhattan polygon (such as a hypotenuse or an arbitrary angle polygon), create it as a unique node in the graph.

[0036] 2. Initial screening of spatial adjacency relationships based on R-tree: Construct an R-tree index and calculate the minimum bounding rectangle (MBR) of each polygon node. Using all MBRs as input, construct an R-tree spatial index. This index organizes spatially adjacent MBRs into the same subtree. Perform range queries, such as... Figure 2 As shown, Figure 2 Medium polygon Treat as a node Using the MBR as the center, a predefined neighborhood search radius R is expanded outwards to form a query window. Then, an R-tree is used to quickly retrieve all MBRs that intersect with this query window (i.e., the black implementation box, including polygons). Polygon nodes included This forms a candidate neighbor set. .

[0037] 3. Precise determination of connected edges based on contour expansion: For each pair of candidate nodes obtained through initial screening using the R-tree... Perform the following operations:

[0038] Polygon contour expansion: for each node and The polygon being represented undergoes equidistant contour expansion. The expansion distance d is a key parameter, its physical meaning being the error tolerance in the photolithography process or the critical distance at which bridging may occur. It can be directly related to design rules (such as minimum spacing).

[0039] Calculate the overlapping area: Use the computational geometry library to perform a Boolean AND (intersection) operation on the two expanded polygons and accurately calculate the overlapping area Aoverlap, i.e., the gray area.

[0040] Establish connecting edges: If Aoverlap > 0, then at node and Establish an undirected edge between them If Aoverlap = 0, then no undirected edge is created.

[0041] Node and edge feature extraction: For each node Sequence of vertex coordinates of its polygon [(x1, y1),(x2, y2), ..., (xn, yn)] serves as the original feature of its nodes. This sequence fully encodes all the geometric information of the polygon in vector form. To facilitate subsequent GNN processing, this sequence is usually normalized. Specifically, hotspot detection divides the entire map into several clips of equal size, and then classifies each clip as either a hotspot or a non-hotspot. For example, if the bottom left corner of the entire map is (0, 0) and the top right corner is (500, 500), dividing the map into 10×10 clips results in each clip being 50×50 pixels. The diagonal coordinates of the top right clip are (450, 450) and (500, 500). The coordinates of the polygons within this clip are normalized, with the x-coordinate normalized to (x-450) / 50 and the y-coordinate normalized to (y-450) / 50. For each edge... The calculated area of ​​the overlapping region, Aoverlap, is used as its edge feature. This scalar value provides crucial information to the GNN: it not only indicates whether two nodes are connected, but also the strength of their interaction, directly related to the probability of hotspot formation.

[0042] Graph structure is constructed ,in Represents a set of nodes, each node Each polygon corresponds to a node feature vector. ; Represents the set of edges, each edge Connect two interacting nodes and And with an edge feature scalar. The scalar is the overlap area Aoverlap after the two polygon outlines are expanded. The constructed graph (nodes, edges, node features, edge features) is input into a graph neural network. Through learning, the network ultimately outputs a classification label (such as "hotspot" or "non-hotspot") or a regression value (representing the probability of becoming a hotspot) for each node (i.e., each polygon). Specifically, after the graph neural network output, either a wired layer and Softmax are used for classification, or a wired layer and Sigmoid are used for probability prediction, which can be selected according to actual needs.

[0043] In one embodiment of the present invention, the graph neural network may be GCN, GraphSAGE or GAT, and those skilled in the art can choose according to actual needs.

[0044] The above embodiments are not intended to limit the present invention, and the present invention is not limited to the above embodiments. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, all technical solutions obtained by equivalent substitution or equivalent transformation fall within the protection scope of the present invention.

Claims

1. A method for detecting hotspots in integrated circuit layouts based on R-tree graph construction, characterized in that, Includes the following steps: Each independent and continuous polygon in the integrated circuit layout file is created as a node in the graph structure, and the geometric information of the polygon is extracted as node features. Calculate the minimum bounding rectangle of each node, organize all minimum bounding rectangles into an R-tree structure to construct an R-tree spatial index, and perform a neighborhood search on each node using the R-tree spatial index to form a candidate neighbor node set; For each candidate node pair in the candidate neighbor set, determine whether there is an interaction between them. If there is, establish an undirected edge between the two nodes and use the strength value of the interaction as the edge feature. The determination of whether there is an interaction between them specifically involves: examining the nodes respectively. and nodes The corresponding polygonal outline is expanded equidistantly. A Boolean intersection operation is performed on the expanded two polygons to calculate the area of ​​the overlapping region. If the area of ​​the overlapping region is greater than 0, then at the node... and nodes Establish an undirected edge between them The area of ​​the overlapping region is used as the edge feature; when performing equidistant expansion, the expansion distance d is defined as the error tolerance or critical distance that may cause bridging in the photolithography process. Based on all nodes, edges, node features, and edge features, a complete graph structure is constructed. This structure is then input into a pre-trained graph neural network model, which outputs the hotspot prediction results for each node.

2. The integrated circuit layout hotspot detection method based on R-tree graph construction according to claim 1, characterized in that, The neighborhood search specifically involves: for any node Using its smallest bounding rectangle as the center, a preset neighborhood search radius is expanded outward to form a query window. The R-tree spatial index is then used to retrieve all nodes where the smallest bounding rectangle intersects with the query window. The candidate neighbor node set is formed. .

3. The integrated circuit layout hotspot detection method based on R-tree graph construction according to claim 1, characterized in that, The geometric information of the polygon includes a sequence of vertex coordinates, and the vertex coordinate sequence is normalized before being input into the graph neural network.

4. The integrated circuit layout hotspot detection method based on R-tree graph construction according to claim 1, characterized in that, The graph neural network model employs graph convolutional networks, graph sampling and aggregation networks, or graph attention networks. The hotspot prediction result is a classification label or a regression value representing the probability that a node becomes a hotspot.

5. An integrated circuit layout hotspot detection system implementing the method as described in any one of claims 1-4, characterized in that, include: The layout acquisition module acquires the integrated circuit layout file and creates each independent and continuous polygon in it as a node in the graph structure, while extracting the geometric information of the polygon as node features; The R-tree building module is used to calculate the minimum bounding rectangle of each node, organize all the minimum bounding rectangles into the R-tree structure, and build the R-tree spatial index. The neighborhood search module performs a neighborhood search on each node using the R-tree spatial index to form a set of candidate neighboring nodes; The interaction determination module determines whether there is an interaction between each candidate node pair in the candidate neighbor node set. If there is, an undirected edge is established between the two nodes, and the strength value of the interaction is used as the edge feature. The hotspot detection module constructs a graph structure based on all nodes, edges, node features, and edge features, and inputs the graph structure into a pre-trained graph neural network model to output the hotspot prediction result for each node.

6. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1-4.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1-4.

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