Data writing methods, storage controller chips, and flash memory devices

Abstract

This application relates to the field of storage device applications and discloses a data writing method, a storage control chip, and a flash memory device. The method includes: acquiring write requests and performing coarse programming and fine programming on the data contained in each write request to write the data to the flash memory medium. The flash memory device receives the first write request earlier than the second write request. When there is an overwrite conflict between the first and second write requests, based on the time when the fine programming is completed, the data contained in the second write request is re-coarsely and finely programmed to rewrite the data contained in the second write request to the flash memory medium. This application can perform coarse programming and fine programming on the data contained in two write requests with overwrite conflicts (i.e., the old write request and the new write request) without deadlock, and can ensure that the data finally written to the flash memory medium is the data contained in the new write request, thereby achieving data order preservation.

Description

Technical Field

[0001] This application relates to the field of storage device applications, and in particular to a data writing method, a storage control chip, and a flash memory device. Background Technology

[0002] Flash memory devices, such as solid-state drives (SSDs), are storage devices that use semiconductor flash memory (NAND flash) as their medium. Flash memory devices are prone to overwrite conflicts during write operations.

[0003] An overwrite conflict occurs when a write request (write request 1) is in the process of writing but has not yet completed, and another new write request (write request 2) arrives, requesting data that overlaps with the data in write request 1 in storage space. If write request 2 is allowed to execute immediately, the data in write request 2 will overwrite the data in write request 1, thus losing the data that write request 1 has not yet completed.

[0004] Currently, flash memory devices typically handle overwrite conflicts in the following way: After receiving write request 2 and determining that write request 2 has an overwrite conflict with write request 1, the front end (FE) pauses the processing of write request 2. After the processing of write request 1 is completed, the front end resumes the processing of write request 2.

[0005] In the process of developing this application, the inventors discovered at least the following problems in the prior art:

[0006] For flash memory devices that require two programming operations for write operations, such as Quad-Level Cell Solid State Drives (QLC SSDs), after the data in any write request has been programmed for the first time, the front-end module needs to continuously send new write requests to the flash memory algorithm module in order to drive the flash memory algorithm module and other subsequent modules to program the data a second time.

[0007] However, when the write address spaces of multiple write requests are relatively concentrated, it is easy for multiple write requests to have overwrite conflicts. When the above method is used to handle overwrite conflicts, for every two write requests with overwrite conflicts, the new write request must wait for the old write request to be processed before it can be sent by the front-end module to the flash algorithm module. The flash algorithm module cannot receive multiple new write requests and cannot perform a second programming on the data in the old write request, thus forming a deadlock. Furthermore, the write requests cannot be completed and continuously occupy the resources of the flash device, resulting in timeouts. Summary of the Invention

[0008] This application provides a data writing method, a storage control chip, and a flash memory device to solve the problem of deadlock and timeout caused by flash memory devices that require two programming operations for write operations when handling overwrite conflicts.

[0009] The embodiments of this application provide the following technical solutions:

[0010] In a first aspect, embodiments of this application provide a data writing method applied to a flash memory device, the data writing method comprising:

[0011] Obtain write requests and perform coarse and fine programming on the data contained in each write request to write the data to the flash memory medium. The write request includes a first write request or a second write request, and the flash memory device receives the first write request earlier than the second write request.

[0012] When there is an overwrite conflict between the first write request and the second write request, at the moment when fine programming is completed based on the data, the data contained in the second write request is re-coarsely programmed and finely programmed again so that the data contained in the second write request can be written to the flash memory medium again.

[0013] Secondly, embodiments of this application provide a storage control chip, comprising:

[0014] At least one processor; and,

[0015] A memory that is communicatively connected to at least one processor; wherein,

[0016] The memory stores instructions that can be executed by at least one processor, which enables the at least one processor to perform a data writing method as described in the first aspect.

[0017] Thirdly, embodiments of this application provide a flash memory device, including:

[0018] Such as the storage control chip in the second aspect;

[0019] At least one flash memory medium is communicatively connected to the storage controller chip.

[0020] Fourthly, embodiments of this application also provide a non-volatile computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, cause the processor to perform the data writing method as described in the first aspect.

[0021] The beneficial effects of the embodiments of this application are as follows: Unlike the prior art, the embodiments of this application provide a data writing method applied to a flash memory device. The data writing method includes: obtaining a write request, and performing coarse programming and fine programming on the data contained in each write request to write the data to the flash memory medium. The write request includes a first write request or a second write request, and the flash memory device receives the first write request earlier than the second write request. When there is an overwrite conflict between the first write request and the second write request, based on the time when the fine programming of the data is completed, the data contained in the second write request is re-coarsely programmed and finely programmed to rewrite the data contained in the second write request to the flash memory medium.

[0022] By performing coarse and fine programming on the data contained in each write request, and when a write conflict occurs between the first and second write requests, re-coarse and fine programming is performed on the data contained in the second write request based on the completion of fine programming, so as to rewrite the data contained in the second write request into the flash memory medium, this application can solve the problem of deadlock and timeout caused by flash memory devices that require two programming operations (e.g., coarse programming and fine programming) when handling write conflict. It can perform coarse and fine programming on the data contained in both write requests with write conflict, namely the old write request and the new write request, without deadlock, and can ensure that the data finally written into the flash memory medium is the data contained in the new write request, thereby achieving data order preservation, that is, keeping the final writing order of the data the same as the order of the corresponding write requests received by the flash memory device. Attached Figure Description

[0023] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0024] Figure 1 This is a schematic diagram of the structure of a flash memory device provided in an embodiment of this application;

[0025] Figure 2 This is a schematic diagram of the structure of a main control system for a flash memory device provided in an embodiment of this application;

[0026] Figure 3 This is a schematic diagram of a two-stage programming process provided in an embodiment of this application;

[0027] Figure 4 This is a flowchart illustrating a data writing method provided in an embodiment of this application;

[0028] Figure 5 yes Figure 4 A detailed flowchart of step S401 in the process;

[0029] Figure 6 yes Figure 5 A detailed flowchart of step S412 in the process;

[0030] Figure 7 This is a flowchart illustrating a process for determining whether to re-coarsely or finely reprogram the data contained in each write request, as provided in an embodiment of this application.

[0031] Figure 8 yes Figure 7 A detailed flowchart of step S704 in the process;

[0032] Figure 9 This is a schematic diagram of the structure of a storage control chip provided in an embodiment of this application;

[0033] Figure 10 This is a schematic diagram of another flash memory device provided in an embodiment of this application.

[0034] Explanation of icon numbers:

[0035] label name label name 100 Flash memory devices 101 connector 102 Storage controller chip 103 Other peripheral units 104 Cache unit 105 Flash memory media 210 Main control system 211 Front-end module 212 Flash algorithm module 213 Backend module 214 hardware module 121 processor 122 memory Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0037] It should be noted that, unless there is a conflict, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than the module division in the device or the order in the flowchart. Moreover, the terms "first," "second," and "third" used in this application do not limit the data or execution order, but only distinguish identical or similar items with essentially the same function and effect.

[0038] The technical solution of this application will be described in detail below with reference to the accompanying drawings:

[0039] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a flash memory device provided in an embodiment of this application;

[0040] like Figure 1 As shown, the flash memory device 100 includes a connector 101, a storage control chip 102, other peripheral units 103, a cache unit 104, and a flash memory medium 105.

[0041] The connector 101 connects the storage control chip 102 to the host for communication, such as a computer or server. The storage control chip 102 connects the connector 101, other peripheral units 103, cache unit 104, and flash memory medium 105, and serves as a control and processing unit to manage the internal system of the flash memory device. The storage control chip 102 includes, but is not limited to, a solid-state drive controller. The peripheral units 103 connect to the storage control chip 102 and include components such as serial ports, sensors, registers, and power chips. The cache unit 104 connects to the storage control chip 102 and serves as a cache and algorithm table storage unit. The cache unit 104 is generally a dynamic random access memory (DRAM).

[0042] The flash memory medium 105, serving as the storage medium of the flash memory device 100, is also known as flash memory, Flash, Flash storage, or Flash chip. It acts as a storage unit for storing user data, system data, etc. Multiple channels connect the storage control chip 102 and the flash memory medium 105, with each channel independently connected to one flash memory medium. For example, channel 0 connects to one flash memory medium, channel 1 connects to one flash memory medium, and so on, with channel x connecting to one flash memory medium.

[0043] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of a main control system for a flash memory device provided in an embodiment of this application;

[0044] It is understandable that the storage control chip of a flash memory device includes a main control system, which is used to connect the host and the flash memory array to realize data input and output (I / O) processing.

[0045] like Figure 2 As shown, the main control system 210 includes:

[0046] The front end module 211 (FE) is used to obtain host commands to generate I / O operations. The front end module 211 is also responsible for the communication protocol with the host 200, parsing host commands and flash device commands, etc.

[0047] The flash algorithm module 212, namely the flash translation layer (FTL), is used to map IO operations to determine the flash array to be sent.

[0048] The flash memory algorithm module 212 sends I / O operations to the back-end module 213 (BE) of the storage control chip, so that the back-end module 213 receives the I / O operations sent by the flash memory algorithm module 212.

[0049] Back End (BE) module 213 is connected to flash memory algorithm module 212 and is used to receive IO operations sent by flash memory algorithm module 212 to control hardware module 214 to perform read / write / erase operations on flash memory array.

[0050] Hardware module 214 (HW Op Nand Mode) refers to the module that operates the Flash memory. It is connected to the back-end module 213 and controlled by the back-end module 213. It is used to operate the Flash memory, such as performing operations on the corresponding flash array or flash media according to the IO operation, that is, to complete the operation processing of data to the Flash memory. The operations include read operations, write operations, or erase operations.

[0051] Flash memory devices are prone to overwrite conflicts during write operations. An overwrite conflict occurs when a write request (write request 1) is in progress but not yet completed, and another write request (write request 2) arrives, requesting data that overlaps with the data in write request 1 in storage space. If write request 2 is allowed to execute immediately, the data in write request 2 will overwrite the data in write request 1, resulting in the loss of the data that write request 1 has not yet completed.

[0052] Currently, flash memory devices typically handle overwrite conflicts in the following way: After receiving write request 2 and determining that write request 2 and write request 1 have an overwrite conflict, the front-end module 211 suspends the processing flow of write request 2, that is, it suspends write request 2 and does not allow the data of write request 2 to be written to disk. After the flash memory algorithm module 212, back-end module 213 and hardware module 214 have finished processing write request 1, the front-end module 211 resumes the processing flow of write request 2.

[0053] However, this method of handling overwrite conflicts is not suitable for flash memory devices that require two programming operations for write operations, such as Quad-Level Cell Solid State Drives (QLCSSDs). Each cell of a QLC SSD can store 4 bits of information, offering higher storage density compared to Single Level Cell (SLC), Multiple Level Cell (MLC), or Triple Level Cell (TLC) flash memory devices. This allows for greater storage capacity within the same physical space, but this high density is achieved by implementing more potential states within a single cell, requiring two programming operations to ensure accurate data writing to the flash memory medium.

[0054] Specifically, the writing process of a QLC SSD includes: 1. Data caching: caching data in the cache space of the flash memory device; 2. Data accumulation: as more data is written, the amount of data accumulated in the cache space gradually increases; 3. Triggered disk write: when the amount of data in the cache space reaches a certain threshold, some of the data in the cache space is written to the flash memory medium; 4. First programming: also known as coarse programming, used to initially store data in the flash memory medium, at which point the storage cells have not reached their final voltage state; 5. Second programming: also known as fine programming, adjusting the voltage level to ensure that the storage cells accurately reach their corresponding voltage state, so that the data is accurately stored in the flash memory medium and can be read correctly.

[0055] Please refer to the following: Figure 2 and Figure 3 , Figure 3 This is a schematic diagram of a two-stage programming process provided in an embodiment of this application;

[0056] In this embodiment, the front-end module 211 sends a set of write requests to the flash memory algorithm module 212 each time. Figure 3 Taking the example of the front-end module 211 sending 6 write requests to the flash memory algorithm module 212 each time.

[0057] like Figure 3As shown, write requests 0-5 are the first set of write requests sent by the front-end module 211 to the flash memory algorithm module 212, and data 0-data 5 are the data corresponding to write requests 0-5. Write requests 6, 8, 10, 12, and 14 are the second set of write requests sent by the front-end module 211 to the flash memory algorithm module 212, and data 6-data 10 are the data corresponding to write requests 6, 8, 10, 12, and 14, respectively.

[0058] After the front-end module 211 sends the first set of write requests to the flash memory algorithm module 212, the flash memory algorithm module 212, the back-end module 213, and the hardware module 214 perform the first programming (i.e., rough programming) on ​​the data 0-5 corresponding to the first set of write requests. After the front-end module 211 sends the second set of write requests to the flash memory algorithm module 212, the flash memory algorithm module 212, the back-end module 213, and the hardware module 214 perform the first programming (i.e., rough programming) on ​​the data 6-10 corresponding to the second set of write requests.

[0059] The issuance of the second set of write requests will drive the data corresponding to the first set of write requests to complete a second round of programming (i.e., fine-tuning). For example, when frontend module 211 issues write request 6, it will drive data 0 to complete the second round of programming. Figure 3 As shown, this is equivalent to issuing write request 7, which causes the flash memory algorithm module 212, backend module 213, and hardware module 214 to perform a second programming of data 0; when the frontend module 211 issues write request 8, it will push data 1 to complete the second programming, as shown. Figure 3 As shown, this is equivalent to issuing write request 9, causing the flash memory algorithm module 212, backend module 213, and hardware module 214 to perform a second programming of data 1; ...; and so on. When the frontend module 211 issues write request 16, it will push data 11 to complete the second programming, as shown. Figure 3 As shown, this is equivalent to issuing write request 17 to cause the flash memory algorithm module 212, backend module 213, and hardware module 214 to perform a second programming of data 5.

[0060] As can be seen, for flash memory devices that require two programming operations for write operations, after the flash algorithm module 212, backend module 213, and hardware module 214 have completed the first programming of the data in any write request, the frontend module 211 needs to continuously send new write requests to the flash algorithm module 212 in order to drive the flash algorithm module 212, backend module 213, and hardware module 214 to perform a second programming of the data after the first programming.

[0061] Combining the above methods for handling overwrite conflicts with the process of two programming steps for the flash memory device, it can be seen that in small-scale overwrite scenarios, where the write address spaces of multiple write requests are relatively concentrated, multiple write requests are prone to overwrite conflicts. For every two write requests with overwrite conflicts, the new write request is suspended, waiting for the old write request to be processed before it can be sent from the front-end module 211 to the flash memory algorithm module 212. Because multiple new write requests are suspended in this scenario, the flash memory algorithm module 212 cannot receive subsequent write requests and cannot perform a second programming on the data in the old write request, thus creating a deadlock. Write requests cannot be completed due to the deadlock, continuously occupying flash memory device resources and causing timeouts.

[0062] Based on this, embodiments of this application provide a data writing method to solve the problem of deadlock and timeout caused by overwrite conflicts in flash memory devices that require two programming operations for write operations.

[0063] Please see Figure 4 , Figure 4 This is a flowchart illustrating a data writing method provided in an embodiment of this application;

[0064] This data writing method is applied to flash memory devices, specifically to flash memory devices where the write operation requires two programming steps, such as QLC SSDs. The two programming steps include coarse programming and fine programming.

[0065] In this embodiment, the flash memory device includes a flash memory medium, and the flash memory device is communicatively connected to a host, which is used to send write requests to the flash memory device.

[0066] like Figure 4 As shown, the data writing method includes:

[0067] Step S401: Obtain write requests and perform coarse and fine programming on the data contained in each write request to write the data to the flash memory medium;

[0068] Specifically, the flash memory device receives write requests from the host and sequentially performs coarse programming and fine programming on the data contained in each write request to store the data in the flash memory medium. Each write request includes data and a write address, which is a logical block address (LBA). Each write address includes an address range, which consists of a series of consecutive addresses between a start address and an end address.

[0069] In this embodiment, a write request includes a first write request or a second write request. The flash memory device receives the first write request earlier than the second write request; that is, the flash memory device receives the first write request first, and then receives the second write request. A write conflict exists between the first and second write requests. Specifically, if the flash memory device is processing the first write request and has not yet completed writing the data contained in the first write request, and then receives the second write request, the address range of the write address in the second write request overlaps with the address range of the write address in the first write request. If the second write request is allowed to execute immediately, the data contained in the second write request will overwrite the data that the first write request has not yet completed writing, resulting in the loss or corruption of the data contained in the first write request.

[0070] In some embodiments of this application, the write request further includes a third write request, which is a write request that does not conflict with other write requests by overwriting. The flash memory device processes these write requests in the order they are received, and performs coarse programming and fine programming on the data contained in each write request.

[0071] In some embodiments of this application, there are multiple first write requests and multiple second write requests, with each second write request corresponding to one first write request. The flash memory device processes these write requests in the order they are received, and performs coarse programming and fine programming on the data contained in each write request.

[0072] Please see Figure 5 , Figure 5 yes Figure 4 A detailed flowchart of step S401 in the process;

[0073] In this embodiment, the flash memory device further includes a cache space for storing data contained in a write request. The cache space includes, but is not limited to, dynamic random access memory (DRAM).

[0074] In this embodiment, the flash memory device further includes a front-end module, a flash memory algorithm module, a back-end module, and a hardware module. For the functions and connection methods of these modules, please refer to [link / reference needed]. Figure 2 This will not be elaborated upon here.

[0075] like Figure 5 As shown, step S401: Obtaining write requests and performing coarse and fine programming on the data contained in each write request to write the data to the flash memory medium, including:

[0076] Step S411: Store the data contained in the received write request in the form of data blocks in the cache space, and add the write request to the flush queue;

[0077] Specifically, the flush queue manages write requests for data that is temporarily stored in the cache but has not yet been written to the flash memory. When the flash memory device receives any write request, the front-end module stores the data contained in the write request as data blocks in the cache and adds the write request to the flush queue. Each data block corresponds to a write address.

[0078] Step S412: Mark the data block based on the address range of the write address of the data block;

[0079] Specifically, after any data block is stored in the cache space, the front-end module marks the data block accordingly based on the relationship between the write address of the data block and the address range of the write addresses of the other data blocks in the cache space.

[0080] Please see Figure 6 , Figure 6 yes Figure 5 A detailed flowchart of step S412 in the process;

[0081] like Figure 6 As shown, step S412: Based on the address range of the write address of the data block, the data block is marked, including:

[0082] Step S4121: Determine which data block to store in the cache space;

[0083] Step S4122: Determine whether there is an address range conflict between the write address of the data block and the write addresses of other data blocks in the cache space;

[0084] Specifically, the front-end module compares the address range of the write address of the data block with the address ranges of the write addresses of the other data blocks in the cache space one by one. If the address range of the write address of the data block overlaps with the address range of any other data block, that is, at least one address is shared by two different data blocks simultaneously, then it is determined that the write address of the data block conflicts with the write addresses of the other data blocks in the cache space. If the write address of the data block is different from the address range of the write addresses of the other data blocks in the cache space, then it is determined that the write address of the data block does not conflict with the write addresses of the other data blocks in the cache space.

[0085] Further, if the write address of the data block conflicts with the write address of other data blocks in the cache space, proceed to step S4123; if the write address of the data block does not conflict with the write address of other data blocks in the cache space, proceed to step S4126.

[0086] Step S4123: Treat this data block as a new data block, and treat data blocks that have address range conflicts with this data block as old data blocks;

[0087] Specifically, if the write address of a data block conflicts with the write address of other data blocks in the cache space, the data block is treated as a new data block, and the data blocks that conflict with the write address of the data block are treated as old data blocks.

[0088] In this context, the new data block refers to the data block that has not yet been written to the flash memory medium, while the old data block refers to the data block that was stored in the cache space before the new data block and has an address range conflict with the new data block. The new data block corresponds to the second write request, and the old data block corresponds to the first write request.

[0089] Understandably, since the first write request and the second write request have an overwrite conflict, and the flash memory device receives the first write request earlier than the second write request, the first write request is treated as the old write request and the second write request is treated as the new write request, according to the time order in which the flash memory device receives the two write requests. The data block corresponding to the first write request is treated as the old data block and the data block corresponding to the second write request is treated as the new data block. The new data block needs to be written to the flash memory medium after the old data block in order to achieve data order preservation.

[0090] Step S4124: Set the data bits corresponding to the address conflict region in the valid bitmap of the old data block to the first value to update the valid bitmap of the old data block.

[0091] The address conflict area is the region where the address ranges of the write addresses of the new data block and the old data block overlap. Each data block corresponds to a valid bitmap, which includes several data bits. Each data bit corresponds to a logical block address, and each data bit is used to identify whether the data at its corresponding logical block address is valid.

[0092] When any data bit in the valid bitmap of a data block takes the value of the first value, the data at the logical block address corresponding to that data bit is invalid for that data block; when any data bit takes the value of the second value, the data at the logical block address corresponding to that data bit is valid for that data block. The number of data bits, the first value, and the second value can be set by those skilled in the art according to actual circumstances, and are not limited here. For example, the first value is 0, and the second value is 1.

[0093] When there is an address range conflict between the write address of the new data block and the old data block, the front-end module determines the address conflict area and updates the valid bitmap of the old data block, setting the data bit corresponding to the address conflict area in the valid bitmap of the old data block to the first value.

[0094] For example, the valid bitmap format of a data block is 0xffff, where f represents a data bit. The valid bitmap of the old data block is 0x1111, and each data bit of this valid bitmap is valid. When the address range of 8-11 of the new data block and the old data block conflict, the valid bitmap of the old data block is updated to 0x1011.

[0095] Step S4125: Set the write conflict flag of the new data block to the second value, and set the allow-to-flush flag for the new data block;

[0096] Specifically, the write-down flag is used to indicate whether a data block can be written from the cache space to the flash memory medium. Each data block corresponds to a write conflict flag, which is used to indicate whether a data block has an overwrite write conflict with other data blocks. When there is no overwrite write conflict between a data block and the other existing data blocks in the cache space, the write conflict flag of the data block takes the first value. When there is an overwrite write conflict between a data block and the other existing data blocks in the cache space, the write conflict flag of the data block takes the second value.

[0097] For example, the front-end module sets the write conflict flag of the new data block to 1 and sets the allow-to-flush flag for the new data block to allow for both coarse and fine programming of the data block.

[0098] Step S4126: Set the write conflict flag of the data block to the first value and set the allow-to-flush flag for the data block.

[0099] Specifically, after any data block is stored in the cache space, if the write address of the data block is different from the address range of the write addresses of other data blocks in the cache space, the write conflict flag of the data block is set to the first value, for example, 0, and the flush flag is set for the data block to allow coarse programming and fine programming of the data block.

[0100] Step S413: When the total number of data blocks stored in the cache space is the first quantity threshold, group several write requests according to the flushing order of the write requests in the flushing queue;

[0101] Specifically, when the total number of data blocks stored in the cache space is the first quantity threshold, the front-end module groups several write requests according to the flush order of the write requests in the flush queue, and sends the programming instructions corresponding to each group of write requests to the flash algorithm module in sequence, so that the flash algorithm module, the back-end module and the hardware module can perform corresponding operations to write the data blocks stored in the cache space into the flash medium.

[0102] A set of write requests comprises several write requests, with each set containing the same number of write requests. The first quantity threshold is the total number of data blocks stored in the cache space when the front-end module begins flushing data blocks. The flushing order is the order in which the write requests arrive in the flushing queue, such as the order in which they arrive at the flash memory device, or the order determined by other strategies (such as write size, priority, etc.). The number of write requests in each set, the first quantity threshold, and the flushing order can be set by those skilled in the art according to actual conditions, and are not limited here.

[0103] Step S414: Perform rough programming on several first data blocks corresponding to the first group of write requests;

[0104] Specifically, each write request corresponds to a data block, which includes a first data block or a second data block. The first data block is the data block corresponding to any write request in the first group of write requests, and the second data block is the data block corresponding to any write request in the second group of write requests.

[0105] The flash memory algorithm module, backend module, and hardware module perform coarse programming on several first data blocks corresponding to the first group of write requests, and initially store several first data blocks in the flash memory medium. At this time, the storage cells in the flash memory medium have not reached the final voltage state.

[0106] In this embodiment of the application, the step of coarsely programming several first data blocks corresponding to the first group of write requests includes steps S1-S2:

[0107] Step S1: Based on the front-end module, generate a first set of programming instructions according to the first set of write requests;

[0108] Specifically, the first programming instruction is the programming instruction corresponding to any one of the write requests in the first group of write requests, and each first programming instruction corresponds to a first data block. The front-end module generates a set of first programming instructions based on the first group of write requests. The first programming instructions are used to instruct the flash memory algorithm module and the back-end module to begin coarse programming of the corresponding first data block.

[0109] Step S2: Send each first programming instruction to the flash memory algorithm module in sequence, so that the flash memory algorithm module and the back-end module can perform coarse programming on the first data block corresponding to each first programming instruction.

[0110] Specifically, the front-end module sends each first programming instruction to the flash algorithm module in sequence. The flash algorithm module performs mapping processing from logical block address to physical block address (PBA) according to the first programming instruction to determine the issued flash array, and sends IO operations to the back-end module. The back-end module receives the IO operations sent by the flash algorithm module to control the hardware module to perform write operations on the flash array, thereby realizing the coarse programming of the first data block.

[0111] In some embodiments of this application, the method further includes: marking the first group of write requests as a flying state when the front-end module sends the first programming instruction to the flash memory algorithm module. The flying state indicates that the write request is in a state where it has been or is undergoing coarse programming but has not yet undergone fine programming.

[0112] Step S415: When the write request processed based on the brush order is the second group of write requests, coarse programming is performed on several second data blocks corresponding to the second group of write requests, and fine programming is performed on several first data blocks.

[0113] Specifically, after the front-end module sends the programming instructions corresponding to the first set of write requests to the flash memory algorithm module, the write requests being processed at this time are the second set of write requests. The front-end module sends the programming instructions corresponding to the second set of write requests to the flash memory algorithm module. The flash memory algorithm module, the back-end module, and the hardware module perform coarse programming on several second data blocks corresponding to the second set of write requests, and at the same time begin fine programming on several first data blocks corresponding to the first set of write requests.

[0114] Understandably, when the front-end module issues programming instructions corresponding to the second set of write requests, it will prompt subsequent modules to begin fine-tuning the first data blocks corresponding to the first set of write requests. For example, if the first set of write requests consists of write request 1, write request 2, and write request 3, and the second set of write requests consists of write request 4, write request 5, and write request 6, then the front-end module issuing programming instructions corresponding to write request 4 will prompt subsequent modules to fine-tune the data blocks corresponding to write request 1, the front-end module issuing programming instructions corresponding to write request 5 will prompt subsequent modules to fine-tune the data blocks corresponding to write request 2, and so on.

[0115] In this embodiment of the application, the steps of coarsely programming several second data blocks corresponding to the second group of write requests and finely programming several first data blocks include steps S3-S4:

[0116] Step S3: Based on the front-end module, generate a second set of programming instructions according to the second set of write requests;

[0117] Specifically, the second programming instruction is the programming instruction corresponding to any one of the write requests in the second group of write requests. Each second programming instruction corresponds to a second data block and a first data block. The write request corresponding to the second data block is flushed in the same order as the write request corresponding to the first data block in the same order as the write request corresponding to the first data block is flushed in the same group of write requests.

[0118] For example, if the first group of write requests are write request 1, write request 2 and write request 3, and the second group of write requests are write request 4, write request 5 and write request 6, then the order of write request 4 in the second group of write requests is the same as the order of write request 1 in the first group of write requests. The programming instructions issued by the front-end module for write request 4 will drive the subsequent modules to perform fine programming on the data block corresponding to write request 1.

[0119] The front-end module generates a second set of programming instructions based on the first set of write requests. The second programming instructions are used to instruct the flash memory algorithm module and the back-end module to start coarse programming of the corresponding second data block, and to instruct the flash memory algorithm module and the back-end module to start fine programming of the corresponding first data block.

[0120] Step S4: Send each second programming instruction to the flash memory algorithm module in sequence, so that the flash memory algorithm module and the back-end module can perform coarse programming on the second data block corresponding to each second programming instruction and fine programming on the first data block corresponding to each second programming instruction.

[0121] Specifically, the front-end module sends each second programming instruction to the flash memory algorithm module in sequence. While the flash memory algorithm module, the back-end module, and the hardware module perform coarse programming on the second data block corresponding to each second programming instruction, they also perform fine programming on the first data block corresponding to each second programming instruction by adjusting the voltage level, so that the storage cells in the flash memory medium accurately reach their corresponding voltage states, thereby completing the writing process of the first set of write requests.

[0122] Furthermore, upon receiving the programming instructions corresponding to the next set of write requests, the flash memory algorithm module performs coarse programming on the data blocks corresponding to the next set of write requests while simultaneously beginning fine programming on several second data blocks corresponding to the second set of write requests.

[0123] In this embodiment, by performing coarse and fine programming on the data contained in each write request to write the data to the flash memory medium, compared to the existing solution where, when two write requests have an overwrite conflict, the new write request needs to be suspended and the suspended write request can only be re-queued to wait for the next flush after the old write request is completed, this application removes the order-preserving suspension and resumption mechanism in the write process. When two write requests have an overwrite conflict, the front-end module still sends the programming instructions corresponding to these write requests to the flash memory algorithm module to drive the data to complete coarse and fine programming, and deadlock will not occur, resulting in timeout.

[0124] In this embodiment, each write request contains data that is coarsely programmed and finely programmed in the form of data blocks. The first write request corresponds to the third data block, and the second write request corresponds to the fourth data block. The third data block is the data block in the cache space corresponding to the data contained in the first write request, and the fourth data block is the data block in the cache space corresponding to the data contained in the second write request. In step S401, the flash memory device performs coarse programming and fine programming on the third data block or the fourth data block respectively to write the third data block or the fourth data block to the flash memory medium.

[0125] It is understandable that the flash memory algorithm module or backend module may not process write requests in a first-in-first-out (FIFO) order according to the flush queue. There may be cases where a received write request is processed before the first one is, resulting in the fourth data block being written to the flash memory medium before the third, causing the third data block to be lost. Based on this, this application, after sending each received write request to the flash memory medium, uses callbacks after coarse and fine programming of the data to determine whether data needs to be flushed again, thereby achieving data order preservation.

[0126] Specifically, in this embodiment of the application, after performing coarse programming and fine programming on the data contained in each write request, the method further includes: based on the front-end module, determining whether to re-perform coarse programming and fine programming on the data contained in each write request.

[0127] Please see Figure 7 , Figure 7 This is a flowchart illustrating a process for determining whether to re-coarsely or finely reprogram the data contained in each write request, as provided in an embodiment of this application.

[0128] like Figure 7 As shown, the process for determining whether to re-roughly or finely reprogram the data contained in each write request includes:

[0129] Step S701: Determine the data block corresponding to any write request and complete coarse programming and fine programming;

[0130] Step S702: Determine whether the write conflict flag of the data block is the second value;

[0131] Specifically, if the write conflict flag of the data block is the second value, then proceed to step S703; if the write conflict flag of the data block is not the second value, that is, the write conflict flag of the data block is the first value, then proceed to step S706.

[0132] Step S703: Determine that the write request is the second write request;

[0133] Specifically, after the data block corresponding to any write request has completed coarse programming and fine programming, if the write conflict flag of the data block is the second value, then the write request is determined to be the second write request, that is, the write request is a new write request. It is necessary to determine whether the data contained in the new write request was written to the flash memory medium before the data contained in the old write request (first write request).

[0134] It is understandable that if the write conflict flag of any data block is the second value, it means that there is an overwrite write conflict between the first write request and the second write request, and the write request corresponding to this data block is the second write request.

[0135] Step S704: Determine whether the time when the fourth data block completes fine programming is earlier than the time when the third data block completes fine programming;

[0136] Specifically, based on the callback function, it is determined whether the fourth data block completes fine-tuning earlier than the third data block. This is understandable because each data block undergoes coarse-tuning first, followed by fine-tuning. Therefore, determining the order in which two data blocks complete fine-tuning is essentially determining the order in which they complete a complete programming process (including coarse-tuning and fine-tuning).

[0137] A callback function is a function called via a function pointer. It allows a program to pass a function as an argument to another function, which then calls (i.e., invokes) that function at a certain point in time. The callback function is used to determine whether data from other write requests has been written to the flash memory medium after data from any write request has been written there, and to determine the order in which data is written to the flash memory medium. In this embodiment, the callback function includes, but is not limited to, the CacheFlash Translation Layer WriteDone (Cache_FtlWriteDone) callback function.

[0138] It is understandable that when there is an address range conflict between the write addresses of two data blocks, in order to ensure the correctness of the data in actual operation, the write times of these two data blocks are usually different, and the times when these two data blocks complete fine programming are also different, that is, the time when the fourth data block completes fine programming is earlier or later than the time when the third data block completes fine programming.

[0139] Please see Figure 8 , Figure 8 yes Figure 7 A detailed flowchart of step S704 in the process;

[0140] like Figure 8 As shown, step S704: Determining whether the time when the fourth data block completes fine programming is earlier than the time when the third data block completes fine programming includes:

[0141] Step S741: Traverse all data blocks stored in the cache space;

[0142] Step S742: Determine whether there is a data bit with the value of the second value in the valid bit map of the fourth data block;

[0143] For example, the front-end module determines whether there are any data bits with a value of 1 in the valid bitmap of the fourth data block, that is, whether the valid bitmap of the fourth data block is still valid.

[0144] Further, if there is a data bit in the valid bitmap of the fourth data block that has a value of the second value, then proceed to step S743; if there is no data bit in the valid bitmap of the fourth data block that has a value of the second value, that is, the value of each data bit in the valid bitmap of the fourth data block is the first value, then proceed to step S745.

[0145] It is understandable that when there are data bits with the second value in the valid bitmap of the fourth data block, the fourth data block itself still represents valid data, that is, it has not been completely covered by the newer data block.

[0146] Step S743: Determine whether there is an address range conflict between the write address of the fourth data block and the write addresses of the other data blocks in the cache space;

[0147] For example, the front-end module determines whether the write address of the fourth data block overlaps with the address range of the write addresses of the other data blocks in the cache space. If the write address of the fourth data block overlaps with the address range of the write addresses of the other data blocks in the cache space, then it is determined that the write address of the fourth data block has an address range conflict with the write addresses of the other data blocks in the cache space. The data block with the address range conflict with the write address of the fourth data block is the third data block.

[0148] If the write address of the fourth data block is different from the write address range of the other data blocks in the cache space, then there is no address range conflict between the write address of the fourth data block and the write address of the other data blocks in the cache space.

[0149] Furthermore, if the write address of the fourth data block conflicts with the write address of the other data blocks in the cache space, proceed to step S744; if the write address of the fourth data block does not conflict with the write address of the other data blocks in the cache space, proceed to step S745.

[0150] Step S744: Determine when the fourth data block completes fine programming earlier than when the third data block completes fine programming;

[0151] Specifically, if there is a data bit with the second value in the valid bitmap of the fourth data block, and there is a data block in the cache space that has an address range conflict with the write address of the fourth data block, then the time when the fourth data block completes fine programming is earlier than the time when the third data block completes fine programming.

[0152] In this embodiment, if the fourth data block completes its fine programming earlier than the third data block, the storage space occupied by the valid data in the fourth data block in the cache space is retained. Valid data satisfies the following condition: it has an address conflict region with the third data block, and the data bits corresponding to this address conflict region in the valid bitmap of the fourth data block are still valid; the data corresponding to this address conflict region is considered valid data.

[0153] Step S745: Determine when the fourth data block completes fine programming later than when the third data block completes fine programming.

[0154] Specifically, if the value of each data bit in the effective bitmap of the fourth data block is the first value, or if the write address of the fourth data block is different from the address range of the write addresses of the other data blocks in the cache space, then the time when the fourth data block completes fine programming is later than the time when the third data block completes fine programming.

[0155] Furthermore, if the fourth data block completes fine programming earlier than the third data block, proceed to step S705; if the fourth data block completes fine programming later than the third data block, proceed to step S706.

[0156] Step S705: Determine whether to coarsely or finely reprogram the data contained in the write request;

[0157] It is understandable that the fourth data block completes fine programming earlier than the third data block, meaning that the data contained in the new write request is stored in the flash memory medium before the data contained in the old write request. However, the data ordering requirement is that the data contained in the old write request is stored in the flash memory medium before the data contained in the new write request. Therefore, this application re-programs the data of the new write request with both coarse and fine programming to meet the data ordering requirement.

[0158] Step S706: Determine not to re-coarsely or finely program the data contained in the write request.

[0159] Specifically, if the write conflict flag of the data block corresponding to the write request is the first value, that is, the write request does not have an overwrite conflict with other write requests, or if the write request is the first write request, then the data contained in the write request will not be reprogrammed coarsely or finely. At this point, the flash memory device completes the write operation corresponding to the write request.

[0160] Alternatively, if the fourth data block completes fine programming later than the third data block, then the fourth data block is determined to be written to the flash memory medium after the third data block. That is, the data contained in the old write request is stored in the flash memory medium before the data contained in the new write request, thus ensuring data order. The data contained in the write request is not reprogrammed coarsely or finely. At this point, the flash memory device completes the write operation corresponding to the write request.

[0161] Step S402: When there is an overwrite conflict between the first write request and the second write request, at the moment when fine programming is completed based on the data, the data contained in the second write request is re-coarsely programmed and finely programmed to write the data contained in the second write request back into the flash memory medium.

[0162] Specifically, when the data contained in the second write request is stored in the flash memory medium before the data contained in the first write request, the data contained in the second write request is re-coarsely programmed and finely programmed to write the data contained in the second write request back into the flash memory medium, so that the data finally written into the flash memory medium is the data contained in the second write request, rather than the data contained in the first write request, thereby achieving data order preservation.

[0163] In this embodiment of the application, the step of re-coarsely and finely programming the data contained in the second write request based on the time when the data completes fine programming includes: if the time when the fourth data block completes fine programming is earlier than the time when the third data block completes fine programming, then the fourth data block is re-coarsely and finely programmed to write the fourth data block back into the flash memory medium.

[0164] Specifically, the second write request corresponding to the fourth data block is re-added to the flush queue, and steps S413-S415 are executed. For details on the coarse and fine programming steps, please refer to steps S413 and S415, which will not be repeated here.

[0165] In this embodiment, by performing coarse and fine programming on the data contained in each write request, and when there is an overwrite conflict between the first and second write requests, re-coarse and fine programming on the data contained in the second write request based on the moment when fine programming is completed, this application can adapt to the characteristic of flash memory devices to perform two programming operations (coarse and fine programming). When two write requests have an overwrite conflict, the front-end module still sends the programming instructions corresponding to these write requests to the flash memory algorithm module to drive the data to complete coarse and fine programming, and deadlock will not occur, resulting in timeout.

[0166] On the other hand, for two write requests that have an overwrite conflict (the old write request and the new write request), this application can ensure that the data written to the flash memory medium last is the data included in the new write request, thereby achieving data ordering in the overwrite scenario and improving the orderliness, integrity and consistency of data writing.

[0167] In this embodiment of the application, the method further includes: performing a forced refresh operation to write the data blocks stored in the cache space to the flash memory medium.

[0168] Specifically, in a forced refresh scenario, the flash memory device performs a forced refresh operation to coarsely and finely program the data blocks stored in the cache space and write them to the flash memory medium.

[0169] In this context, a forced refresh scenario refers to a scenario where data blocks in the cache space need to be forcibly written to the flash memory medium, and a forced refresh operation is an operation that forcibly writes data blocks in the cache space to the flash memory medium. Forced refresh scenarios include, but are not limited to: scenarios where power is about to run out and it is necessary to ensure that all data has been written to the flash memory medium, or scenarios where it is necessary to perform a formatting operation on the flash memory medium, etc. In this embodiment, the forced refresh scenario is not limited.

[0170] In this embodiment of the application, the steps for performing a forced refresh operation include steps S5-S7:

[0171] Step S5: Based on the front-end module, send a set of data blocks and an end flag sequentially to the flash memory algorithm module;

[0172] Specifically, the end flag indicates that the data block transmission is complete, meaning no further data blocks will be sent. The front-end module sequentially sends a set of data blocks from the cache space along with the end flag to the flash memory algorithm module. The number of data blocks in a set can be set by those skilled in the art according to actual needs, and is not limited here.

[0173] Step S6: Based on the flash memory algorithm module and the backend module, perform rough programming on a set of data blocks;

[0174] Specifically, this step is similar to the implementation of step S414, and will not be described in detail here.

[0175] Step S7: Based on the end marker, generate a set of virtual programming instructions to enable the flash algorithm module and the back-end module to fine-tune a set of data blocks.

[0176] Specifically, when the flash memory algorithm module receives an end flag, it indicates the end of the transmission of a set of data blocks and initiates a virtual write request supplementation mechanism. This mechanism simulates additional write requests (Dummy I / O) to generate a set of virtual programming instructions. These instructions instruct the flash memory algorithm module and the backend module to perform fine-grained programming on the set of data blocks. The number of virtual programming instructions can be set by those skilled in the art according to actual conditions and is not limited here.

[0177] The specific implementation methods for fine programming of a set of data blocks by the flash memory algorithm module and the back-end module are similar to those for fine programming in step S4, and will not be repeated here.

[0178] In this embodiment, a set of virtual programming instructions is generated based on an end marker, enabling the flash memory algorithm module and the backend module to perform fine programming on a set of data blocks. Compared to existing solutions where the frontend module cannot receive new write requests in a forced refresh scenario and cannot send new write requests to the flash memory algorithm module after step S6, thus failing to drive the data blocks to perform fine programming, this application enables the data blocks to continue to complete fine programming, reducing system instability and potential data corruption risks caused by interrupted write operations.

[0179] In this embodiment of the application, after coarse programming and fine programming of the data contained in each write request, the method further includes:

[0180] After fine programming is completed for a data block with the write conflict flag set to the first value, delete the valid bitmap of the data block, write the conflict flag, enable the flush flag, and release the storage space occupied by the data block in the cache space.

[0181] Alternatively, after determining that the fourth data block has completed fine programming later than the third data block, delete the valid bitmap, write conflict flag, and allow flushing flag of the fourth data block, and release the storage space occupied by the fourth data block in the cache space.

[0182] Specifically, if the write conflict flag of any data block is the first value, for example, the write conflict flag is 0, then the data block does not have an overwrite write conflict with other data blocks. Alternatively, if the data block is the data block corresponding to the first write request, and the data block has completed coarse programming and fine programming, then the valid bitmap, write conflict flag, and allow-to-flush flag of the data block are deleted, and the storage space occupied by the data block in the cache space is released.

[0183] Alternatively, if the fourth data block completes fine programming later than the third data block, the data ordering requirement is satisfied, meaning that the data contained in the old write request is stored in the flash memory medium before the data contained in the new write request. In this case, the valid bitmap, write conflict flag, and allow-to-flush flag of the fourth data block are deleted, and the storage space occupied by the fourth data block in the cache space is released.

[0184] In the embodiments of this application, by deleting all flags and releasing storage space for data blocks whose write conflict flag is the first value and have completed fine programming, or for fourth data blocks whose fine programming time is later than that of the third data block, this application can release cache space in a timely manner to provide storage space for data contained in new write requests.

[0185] In this embodiment of the application, a data writing method is provided, which is applied to a flash memory device. The data writing method includes: obtaining write requests, and performing coarse programming and fine programming on the data contained in each write request to write the data to the flash memory medium, wherein the write request includes a first write request or a second write request, and the flash memory device receives the first write request earlier than the second write request; when there is an overwrite conflict between the first write request and the second write request, based on the time when the fine programming of the data is completed, the data contained in the second write request is re-coarsely programmed and finely programmed to write the data contained in the second write request to the flash memory medium again.

[0186] By performing coarse and fine programming on the data contained in each write request, and when there is an overwrite conflict between the first and second write requests, re-coarse and fine programming on the data contained in the second write request based on the moment the fine programming is completed, so as to write the data contained in the second write request back to the flash memory medium, this application can solve the problem of deadlock and timeout caused by flash memory devices that require two programming operations (coarse and fine programming) when handling overwrite conflicts. It can perform coarse and fine programming on the data contained in the two write requests with overwrite conflicts, namely the old write request and the new write request, without deadlock, and can ensure that the data finally written to the flash memory medium is the data contained in the new write request, thereby achieving data order preservation, that is, keeping the final writing order of the data the same as the order of the corresponding write requests received by the flash memory device.

[0187] Please see Figure 9 , Figure 9 This is a schematic diagram of the structure of a storage control chip provided in an embodiment of this application;

[0188] like Figure 9 As shown, the storage control chip 102 includes one or more processors 121 and a memory 122. Wherein, Figure 9 Take a processor 121 as an example.

[0189] Processor 121 and memory 122 can be connected via a bus or other means. Figure 9 Taking the example of a connection between China and Israel via a bus.

[0190] Processor 121 is configured to provide computing and control capabilities to control flash memory device 100 to perform corresponding tasks, such as controlling flash memory device 100 to perform a data writing method in any of the above method embodiments, including: acquiring write requests and performing coarse programming and fine programming on the data contained in each write request to write the data to the flash memory medium, wherein the write request includes a first write request or a second write request, and the flash memory device receives the first write request earlier than the second write request; when there is an overwrite conflict between the first write request and the second write request, based on the time when the fine programming of the data is completed, coarse programming and fine programming are performed again on the data contained in the second write request to write the data contained in the second write request to the flash memory medium again.

[0191] By performing coarse and fine programming on the data contained in each write request, and when there is an overwrite conflict between the first and second write requests, re-coarse and fine programming on the data contained in the second write request based on the moment the fine programming is completed, so as to write the data contained in the second write request back to the flash memory medium, this application can solve the problem of deadlock and timeout caused by flash memory devices that require two programming operations (coarse and fine programming) when handling overwrite conflicts. It can perform coarse and fine programming on the data contained in the two write requests with overwrite conflicts, namely the old write request and the new write request, without deadlock, and can ensure that the data finally written to the flash memory medium is the data contained in the new write request, thereby achieving data order preservation, that is, keeping the final writing order of the data the same as the order of the corresponding write requests received by the flash memory device.

[0192] Processor 121 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a hardware chip, or any combination thereof; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The aforementioned PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0193] The memory 122, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the data writing method in the embodiments of this application. The processor 121 can implement the data writing method in any of the above method embodiments by running the non-transitory software programs, instructions, and modules stored in the memory 122. Specifically, the memory 122 may include volatile memory (VM), such as random access memory (RAM); the memory 122 may also include non-volatile memory (NVM), such as read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), or other non-transitory solid-state storage devices; the memory 122 may also include combinations of the above types of memory.

[0194] Memory 122 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 122 may optionally include memory remotely located relative to processor 121, and such remote memory may be connected to processor 121 via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0195] One or more modules are stored in memory 122. When executed by one or more processors 121, they perform the data writing method in any of the above method embodiments, for example, the method described above. Figure 4 The steps shown.

[0196] Please see Figure 10 , Figure 10 This is a schematic diagram of another flash memory device provided in an embodiment of this application;

[0197] like Figure 10 As shown, the flash memory device 100 includes a storage controller chip 102 and at least one flash memory medium 105. The flash memory medium 105 is communicatively connected to the storage controller chip 102. Figure 10 Take a flash memory medium 105 as an example.

[0198] The storage control chip 102 is used to execute the data writing method in any of the above embodiments, including: acquiring a write request, and performing coarse programming and fine programming on the data contained in each write request to write the data to the flash memory medium, wherein the write request includes a first write request or a second write request, and the flash memory device receives the first write request earlier than the second write request; when there is an overwrite conflict between the first write request and the second write request, based on the time when the fine programming of the data is completed, the data contained in the second write request is re-coarsely programmed and finely programmed to write the data contained in the second write request to the flash memory medium again.

[0199] Flash memory 105 is connected to storage control chip 102 for storing data.

[0200] By including a storage control chip in the flash memory device, which is used to execute the data writing method in any of the above embodiments, this application can perform coarse programming and fine programming on the data contained in two write requests that have an overwrite conflict, namely the old write request and the new write request, without deadlock, and can ensure that the data written to the flash memory medium last is the data contained in the new write request, thereby achieving data order preservation.

[0201] This application also provides a non-volatile computer storage medium storing computer-executable instructions that are executed by one or more processors. For example, the one or more processors can execute the data writing method in any of the above method embodiments, such as performing the steps described above.

[0202] The apparatus or device embodiments described above are merely illustrative. The unit modules described as separate components may or may not be physically separate, and the components shown as module units may or may not be physical units; that is, they may be located in one place or distributed across multiple network module units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0203] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions for a computer device (which may be a personal computer, server, or network device, etc.) to execute the various embodiments or some parts of the embodiments.

[0204] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above. For the sake of brevity, they are not provided in detail; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A data writing method, characterized in that, Applied to a flash memory device, the flash memory device including a flash memory medium, the method includes: A write request is acquired, and coarse programming and fine programming are performed on the data contained in each write request to write the data to the flash memory medium, wherein the write request includes a first write request or a second write request, and the flash memory device receives the first write request earlier than it receives the second write request. When there is an overwrite conflict between the first write request and the second write request, at the moment when fine programming is completed based on the data, the data contained in the second write request is re-coarsely programmed and finely programmed to write the data contained in the second write request back into the flash memory medium.

2. The method according to claim 1, characterized in that, The flash memory device further includes a cache space, and the coarse and fine programming of the data contained in each write request to write the data to the flash memory medium includes: The data contained in the received write request is stored in the cache space in the form of data blocks, and the write request is added to the flush queue; The data block is marked based on the address range of the write address of the data block; When the total number of data blocks stored in the cache space is a first quantity threshold, several write requests are grouped according to the flushing order of the write requests in the flushing queue, wherein each group of write requests has the same number of requests, and the data block includes a first data block or a second data block. Rough programming is performed on several first data blocks corresponding to the first group of write requests; When the write request processed based on the brush order is the second group of write requests, coarse programming is performed on several second data blocks corresponding to the second group of write requests, and fine programming is performed on several first data blocks.

3. The method according to claim 2, characterized in that, The step of marking the data block based on the address range of the write address of the data block includes: After any data block is stored in the cache space, if the write address of the data block is different from the address range of the write addresses of other data blocks in the cache space, the write conflict flag of the data block is set to the first value, and the flush flag is set for the data block. If the write address of the data block conflicts with the write address of other data blocks in the cache space, then the data block is treated as a new data block, and the data block that conflicts with the data block is treated as an old data block. The new data block corresponds to the second write request, and the old data block corresponds to the first write request. Set the data bit corresponding to the address conflict region in the valid bitmap of the old data block to the first value to update the valid bitmap of the old data block; Set the write conflict flag of the new data block to the second value, and set the allow-to-flush flag for the new data block.

4. The method according to claim 2, characterized in that, The flash memory device also includes a front-end module, a flash memory algorithm module, and a back-end module; The rough programming of the several first data blocks corresponding to the first group of write requests includes: Based on the front-end module, a set of first programming instructions is generated according to the first set of write requests, wherein each first programming instruction corresponds to a first data block; Each of the first programming instructions is sent sequentially to the flash memory algorithm module so that the flash memory algorithm module and the back-end module coarsely program the first data block corresponding to each first programming instruction. The coarse programming of several second data blocks corresponding to the second group of write requests, and the fine programming of several first data blocks, include: Based on the front-end module, a set of second programming instructions is generated according to the second set of write requests, wherein each second programming instruction corresponds to a second data block and a first data block; Each of the second programming instructions is sent sequentially to the flash memory algorithm module, so that the flash memory algorithm module and the back-end module perform coarse programming on the second data block corresponding to each second programming instruction, and fine programming on the first data block corresponding to each second programming instruction.

5. The method according to claim 1, characterized in that, Each write request contains data that is coarsely and finely programmed in the form of data blocks. The first write request corresponds to the third data block, and the second write request corresponds to the fourth data block. Before re-coarsely and finely reprogramming the data contained in the second write request, the method further includes: After coarse programming and fine programming are completed for the data block corresponding to any write request, if the write conflict flag of the data block is the second value, then the write request is determined to be the second write request. Based on the callback function, determine whether the time when the fourth data block completes fine programming is earlier than the time when the third data block completes fine programming; If the fourth data block completes fine programming later than the third data block, then the fourth data block is determined to be written to the flash memory medium after the third data block. When the fine programming is completed based on the data, the data contained in the second write request is re-coarsely and finely programmed, including: If the fourth data block completes fine programming earlier than the third data block, then the fourth data block is reprogrammed (both coarse and fine) to rewrite the fourth data block into the flash memory medium.

6. The method according to claim 5, characterized in that, The flash memory device includes a cache space, and determining whether the time when the fourth data block completes fine programming is earlier than the time when the third data block completes fine programming includes: Traverse all data blocks stored in the cache space. If there is a data bit with the value of the second value in the effective bit map of the fourth data block, and there is a data block in the cache space that has an address range conflict with the write address of the fourth data block, then it is determined that the time when the fourth data block completes fine programming is earlier than the time when the third data block completes fine programming. If the value of each data bit in the effective bitmap of the fourth data block is the first value, or if the write address of the fourth data block is different from the address range of the write addresses of the other data blocks in the cache space, then it is determined that the time when the fourth data block completes fine programming is later than the time when the third data block completes fine programming.

7. The method according to claim 4, characterized in that, The method further includes: Perform a forced refresh operation to write the data blocks stored in the cache space to the flash memory medium, specifically including: Based on the aforementioned front-end module, a set of data blocks and an end marker are sequentially sent to the flash memory algorithm module; Based on the flash memory algorithm module and the backend module, a set of data blocks are roughly programmed; Based on the end marker, a set of virtual programming instructions is generated to enable the flash memory algorithm module and the backend module to finely program a set of data blocks.

8. The method according to claim 5 or 6, characterized in that, The flash memory device includes a cache space, and the method further includes: After fine programming is completed for a data block with the write conflict flag set to the first value, delete the valid bitmap of the data block, write the conflict flag, enable the flush flag, and release the storage space occupied by the data block in the cache space. Alternatively, after determining that the fourth data block has completed fine programming later than the third data block, delete the valid bitmap, write conflict flag, and allow flushing flag of the fourth data block, and release the storage space occupied by the fourth data block in the cache space.

9. A storage control chip, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the data writing method as described in any one of claims 1-8.

10. A flash memory device, characterized in that, include: The storage control chip as described in claim 9; At least one flash memory medium is communicatively connected to the storage control chip.

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