Standard cell metal line patterning method and related apparatus

Abstract

The application belongs to the technical field of semiconductor design automation, and proposes a metal line pattern layout method of a standard cell and related equipment. The method comprises the following steps: in response to a user selecting a target region in a design interface of an integrated circuit layout, determining a standard cell falling into the target region as a to-be-processed standard cell; determining a MOS tube position of the to-be-processed standard cell based on a geometric configuration parameter of the to-be-processed standard cell; taking the MOS tube position as an index, obtaining pattern feature information of each MOS tube in the to-be-processed standard cell; and based on the pattern feature information, laying a metal line pattern meeting a set requirement on at least one metal line layer above the to-be-processed standard cell. The technical scheme provided by the application can improve the metal line pattern layout efficiency of a standard cell.

Description

Methods and related equipment for laying out metal wire patterns in standard units Technical Field

[0001] This application belongs to the field of semiconductor design automation technology, and in particular relates to a method and related equipment for laying out metal wire patterns of standard cells. Background Technology

[0002] In the field of integrated circuit design, standard cells (such as AND gates, OR gates, and flip-flops) serve as the basic units for implementing chip logic functions. The quality of their metal line patterns directly affects the chip's electrical performance, signal integrity, and manufacturing yield. Especially in analog circuit design, because analog signals are more sensitive to noise and parasitic parameters, parameters such as the width, spacing, and interlayer connection reliability of metal line patterns must strictly adhere to design rules. Furthermore, the number of standard cells in analog circuits is often extremely large. For example, a high-precision analog chip may contain thousands or even tens of thousands of standard cells. Each standard cell requires metal line patterns to be laid out on at least 1-2 metal line layers (such as the first metal line layer and the second metal line layer) to achieve the interconnection of the source and drain terminals of MOS transistors and signal transmission.

[0003] Currently, the layout of metal lines for standard cells in the industry generally relies on manual editing. Designers must manually complete the layout of metal lines for standard cells using layout design tools, such as Electronic Design Automation (EDA) tools. However, due to the large number of metal lines in analog circuits, manually connecting and drawing each one consumes a lot of time, resulting in extremely low design efficiency and severely slowing down the overall chip design cycle.

[0004] As chip process nodes continue to evolve (e.g., from 16nm to 5nm and 3nm), the size of standard cells continues to shrink, and the design rules for metal line patterns are becoming increasingly stringent. Manual editing methods are no longer sufficient to meet the demands for high-precision and high-efficiency metal line pattern placement. Therefore, how to address this is a pressing technical problem. Summary of the Invention

[0005] The embodiments of this application provide a method, apparatus, computer program product, computer-readable storage medium, and electronic device for laying out metal wire patterns of standard cells, which can improve the efficiency of laying out metal wire patterns of standard cells to a certain extent.

[0006] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0007] According to a first aspect of the present application, a method for laying out metal line patterns of standard cells is provided. The method includes: in response to a user selecting a target area in an integrated circuit layout design interface, determining standard cells falling into the target area as standard cells to be processed; determining the MOS transistor positions of the standard cells to be processed based on the geometric configuration parameters of the standard cells to be processed, wherein the geometric configuration parameters are used to characterize the position of the standard cells to be processed in the integrated circuit layout and the morphological characteristics of the standard cells to be processed; using the MOS transistor positions as indexers, obtaining graphic feature information of each MOS transistor in the standard cells to be processed, wherein the graphic feature information includes the graphic type and spatial position of each graphic in the MOS transistor; and laying out metal line patterns that meet set requirements on at least one metal line layer above the standard cells to be processed based on the graphic feature information.

[0008] In some embodiments of this application, based on the foregoing scheme, determining the MOS transistor position of the standard cell to be processed based on the geometric configuration parameters of the standard cell to be processed includes: for each standard cell in the standard cell to be processed, if the cell type of each standard cell is a single MOS transistor cell, then the coordinates of each standard cell in the integrated circuit layout are read from the geometric configuration parameters as the MOS transistor position of each standard cell; if the cell type of each standard cell is a MOS transistor cell array, then the coordinates of each MOS transistor in each standard cell are calculated based on the coordinates of each standard cell in the integrated circuit layout in the geometric configuration parameters and the tiling parameters of the MOS transistor cell array in each standard cell, as the MOS transistor position of each standard cell.

[0009] In some embodiments of this application, based on the foregoing scheme, the step of obtaining the graphic feature information of each MOS transistor in the standard unit to be processed by using the MOS transistor position as an index includes: defining a preset range of screening area centered on the MOS transistor position of each MOS transistor; obtaining the graphic type and spatial position of each graphic within the screening area as the graphic feature information of each MOS transistor.

[0010] In some embodiments of this application, based on the aforementioned scheme, the spatial location includes the graphic's layer level and the graphic's corner coordinates. The step of laying out metal line graphics that meet the set requirements on at least one metal line layer above the standard unit to be processed based on the graphic feature information includes: selecting target graphics in the target area whose graphic type is a solid graphic and whose graphic's layer level is the first metal line layer; and laying out metal line graphics that meet the set requirements on at least one metal line layer above the standard unit to be processed based on the graphic corner coordinates of the target graphic.

[0011] In some embodiments of this application, based on the aforementioned scheme, the step of filtering target graphics within the target area that are solid graphics and belong to the first layer of metal wire layers includes: traversing each graphic within the target area; if each graphic is solid graphics and belongs to the first layer of metal wire layers, then verifying whether the corner coordinates of each graphic are missing and whether there are breakpoints on the edges of the graphic; if the verification passes, then each graphic is determined as a target graphic; if the verification fails, then each graphic is marked as an abnormal graphic, and the location and abnormality type of the abnormal graphic are recorded in the design log.

[0012] In some embodiments of this application, based on the foregoing scheme, the step of laying out a metal line graphic that meets the set requirements on at least one metal line layer above the standard unit to be processed based on the graphic corner coordinates of the target graphic includes: copying the reference outline and graphic position of the target graphic based on the graphic corner coordinates of the target graphic; calling a shape conversion function to convert the reference outline from a polygon to a path shape at the graphic position on the first metal line layer; setting the width of the path shape to a first width set by the user, so as to lay out a first metal line graphic that meets the set requirements on the first metal line layer above the standard unit to be processed.

[0013] In some embodiments of this application, based on the aforementioned scheme, after all the first metal wire patterns are laid out in the first metal wire layer, the method further includes: performing a spacing check on each of the first metal wire patterns in the first metal wire layer to determine whether the spacing between adjacent first metal wire patterns meets a preset spacing; if the spacing between any adjacent first metal wire pattern meets the preset spacing, then the any adjacent first metal wire pattern is used as the final metal wire pattern laid out on the first metal wire layer above the standard unit to be processed; if the spacing between any adjacent first metal wire pattern does not meet the preset spacing, then the spacing between any adjacent first metal wire pattern is adjusted until the preset spacing is met, and then the laying out of the first metal wire patterns is completed.

[0014] In some embodiments of this application, based on the foregoing scheme, after the first metal line pattern that meets the set requirements is laid out on the first metal line layer above the standard unit to be processed, the method further includes: copying the spatial position parameters of the first metal line pattern, and changing the layer to which the pattern belongs in the spatial position parameters from the first metal line layer to the second metal line layer; setting the width of the path shape of the second metal line layer to a second width set by the user, so as to lay out the second metal line pattern that meets the set requirements on the second metal line layer above the standard unit to be processed.

[0015] In some embodiments of this application, based on the foregoing scheme, after all the second metal wire patterns are laid out in the second metal wire layer, the method further includes: performing alignment verification on the second metal wire patterns and the first metal wire patterns, calculating the deviation values ​​of the center lines of the second metal wire patterns and the first metal wire patterns in the x-axis and y-axis directions; if the deviation value is less than or equal to a preset deviation value, the alignment is deemed qualified, and the second metal wire patterns that meet the set requirements are laid out in the second metal wire layer above the standard unit to be processed; if the deviation value is greater than the preset deviation value, the position of the second metal wire patterns is corrected based on the center line coordinates of the first metal wire patterns until the deviation value is less than or equal to the preset deviation value, and then the laying out of the second metal wire patterns is completed.

[0016] In some embodiments of this application, based on the aforementioned scheme, after all the second metal wire patterns are laid out in the second metal wire layer, the method further includes: determining the center coordinates of the metal via based on the overlapping area of ​​the first metal wire pattern and the second metal wire pattern; generating the outline of the metal via pattern according to the center coordinates of the metal via and the metal via size standard provided by the manufacturer; determining whether the metal via pattern completely falls within the overlapping area; if the metal via pattern completely falls within the overlapping area, then the laying out of the metal via pattern is completed; if the metal via pattern does not completely fall within the overlapping area, then the center coordinates of the metal via are adjusted until the metal via pattern completely falls within the overlapping area, and then the laying out is completed.

[0017] In some embodiments of this application, based on the foregoing scheme, after all metal wire patterns meeting the set requirements are laid out on at least one metal wire layer above the standard unit to be processed, the method further includes: calling a design rule check engine to perform a global check on the laid-out metal wire patterns; wherein, the global check includes at least whether the width of the metal wire pattern meets the width threshold set by the user, whether the spacing between the metal wire pattern and adjacent patterns meets the set spacing threshold, and whether the overlap between the metal through-hole pattern and the metal wire pattern is greater than or equal to the set overlap; if there are no violations in the global check, the metal wire pattern is determined to be qualified; if there are violations, a design rule check violation report is generated, and based on the design rule check violation report, the parameters of the violating metal wire pattern are automatically adjusted, and the global check is re-executed after adjustment until there are no violations in the global check.

[0018] According to a second aspect of the present application, a metal line pattern layout apparatus for standard cells is provided. The apparatus includes: a first determining unit, configured to determine standard cells falling into the target area as standard cells to be processed in response to a user selecting a target area in an integrated circuit layout design interface; a second determining unit, configured to determine the MOS transistor position of the standard cell to be processed based on the geometric configuration parameters of the standard cell to be processed, wherein the geometric configuration parameters are used to characterize the position of the standard cell to be processed in the integrated circuit layout and the morphological characteristics of the standard cell to be processed; an acquiring unit, configured to acquire graphic feature information of each MOS transistor in the standard cell to be processed using the MOS transistor position as an index, wherein the graphic feature information includes the graphic type and spatial position of each graphic in the MOS transistor; and a layout unit, configured to lay out metal line patterns that meet set requirements on at least one metal line layer above the standard cell to be processed based on the graphic feature information.

[0019] According to a third aspect of the embodiments of this application, a computer program product is provided, the computer program product including computer instructions stored in a computer-readable storage medium and adapted to be read and executed by a processor to cause a computer device having the processor to perform the operations performed by the method described in the first aspect above.

[0020] According to a fourth aspect of the embodiments of this application, a computer-readable storage medium is provided, the computer-readable storage medium storing at least one computer program instruction, the at least one computer program instruction being loaded and executed by a processor to perform the operation as described in the first aspect above.

[0021] According to a fifth aspect of the present application, an electronic device is provided, the electronic device including one or more processors and one or more memories, the one or more memories storing at least one computer program instruction, the at least one computer program instruction being loaded and executed by the one or more processors to perform the operation as described in the first aspect above.

[0022] Based on the technical solution proposed in this application, the efficiency of laying out metal line patterns for standard cells can be significantly improved. Specifically, this application eliminates the need for manual selection of standard cells one by one; the user only needs to select the target area to automatically lock the standard cells to be processed. This avoids the tedious operation and risk of omissions associated with manual selection, greatly reducing the time cost of standard cell screening. Simultaneously, determining the MOSFET position based on the geometric configuration parameters of the standard cells can replace the traditional method of manually calibrating MOSFETs, ensuring the accuracy of MOSFET position calibration and saving the time spent on MOSFET verification. Automatically extracting graphic feature information using MOSFET positions as indexes enables batch collection and integration of graphic feature data, avoiding the errors and time-consuming process of manually entering graphic feature information line by line. This ensures the timeliness and completeness of data retrieval, laying an efficient data foundation for subsequent metal line pattern laying. Finally, based on standardized graphic feature information, the layout of metal wire graphics is automatically completed in at least one metal wire layer without the need for repeated manual adjustment of parameters such as the layer and position of the metal wires. This reduces the repetitive operation of laying out metal wire graphics in multiple layers and ensures the consistency of the layout. It can greatly shorten the layout cycle of metal wire graphics in standard units, while reducing the error rate caused by manual intervention, thus balancing the efficiency and quality of metal wire graphic layout.

[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:

[0025] Figure 1 shows a flowchart of the method for laying out the metal wire pattern of the standard unit in an embodiment of this application;

[0026] Figure 2 shows a schematic diagram of standard units in the target area in an embodiment of this application;

[0027] Figure 3 shows a schematic diagram of standard units in the target area in an embodiment of this application;

[0028] Figure 4 shows a block diagram of the metal wire pattern layout device for the standard unit in an embodiment of this application;

[0029] Figure 5 shows a schematic diagram of the structure of the electronic device in an embodiment of this application. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0031] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0032] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices. It should also be noted that, for the sake of simplicity, certain components in the drawings that do not affect the interpretation of the technical solution of this application have been appropriately omitted.

[0033] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined. Therefore, the actual execution order may change depending on the actual situation.

[0034] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "multiple" means two or more.

[0035] To enable those skilled in the art to better understand this application, a brief explanation of the technical concepts and application background involved in this application will be given first.

[0036] Integrated Circuit (IC): An integrated circuit, also known as a microchip or chip, is a miniature electronic device that uses semiconductor manufacturing processes (such as photolithography, etching, doping, deposition, etc.) to fabricate a large number of electronic components such as transistors, diodes, resistors, capacitors, and inductors, as well as the interconnection lines between these components, onto one or more semiconductor wafers (usually silicon wafers), insulating substrates, or other carriers, and then encapsulates them in a housing to form a miniature electronic device with specific circuit functions.

[0037] Chip Analog Circuit (CAC): Chip analog circuits are the core functional circuit modules in integrated circuits that process analog signals. Analog signals are signals that change continuously in both time and amplitude (such as continuously changing voltage and current signals), in contrast to digital signals (which are represented by only two discrete states, 0 and 1).

[0038] Metal line patterns: In the field of integrated circuit design, metal line patterns (also known as metal lines or metal wiring) are the core physical carriers for realizing the electrical interconnection of components such as transistors, resistors, and capacitors in chip analog circuits. They are the basic units that constitute the chip interconnection network, and the rationality of their design directly affects the chip's performance, stability, and manufacturing yield.

[0039] In the field of integrated circuit design, standard cells are the basic units for implementing chip logic functions (such as AND gates, OR gates, flip-flops, etc.).

[0040] However, in standard cells, the metal patterns on the source and drain terminals of the MOSFETs provided by the fabrication plant only meet the minimum metal width but not the minimum wiring width standard set by the designer. This necessitates re-laying the metal lines on the standard cells. The quality of the metal line layout directly affects the chip's electrical performance, signal integrity, and manufacturing yield. Especially in analog circuit design, because analog signals are more sensitive to noise and parasitic parameters, parameters such as the width, spacing, and interlayer connection reliability of the metal lines must strictly adhere to design rules. Furthermore, the number of standard cells in analog circuits is often extremely large; for example, a high-precision analog chip may contain thousands or even tens of thousands of standard cells. Each standard cell requires metal lines to be laid out on at least 1-2 metal line layers (such as the first metal line layer and the second metal line layer) to achieve the interconnection of the MOSFET source and drain terminals and signal transmission.

[0041] Currently, the layout of metal lines for standard cells in the industry generally relies on manual editing. This means that designers need to manually complete the layout of metal lines for standard cells using layout design tools, such as electronic design automation (EDA) tools. However, due to the large number of metal lines in analog circuits, manually connecting and drawing each one consumes a significant amount of time, resulting in extremely low design efficiency and severely slowing down the overall chip design cycle.

[0042] As chip process nodes continue to evolve (such as from 16nm to 5nm and 3nm), the size of standard cells continues to shrink, and the design rules for metal line patterns are becoming increasingly stringent. Manual editing methods can no longer meet the requirements for high-precision and high-efficiency metal line pattern layout.

[0043] In this context, this application proposes a metal wire pattern layout scheme for standard cells to improve the efficiency of metal wire pattern layout for standard cells.

[0044] The implementation details of the technical solutions in the embodiments of this application are described below:

[0045] Referring to Figure 1, a flowchart of a method for laying out the metal wire pattern of a standard cell in an embodiment of this application is shown. This method for laying out the metal wire pattern of a standard cell can be executed by a device with computing processing capabilities. As shown in Figure 1, the method for laying out the metal wire pattern of a standard cell includes at least steps 110 to 140, which are described in detail below:

[0046] In step 110, in response to the user selecting a target area in the integrated circuit layout design interface, the standard cells falling into the target area are determined as standard cells to be processed.

[0047] In this application, the scope of metal line pattern layout can be accurately defined based on user interaction commands, and the standard units to be processed that need to be laid out with metal line patterns can be selected, providing clear processing objects for subsequent MOS transistor positioning, pattern feature extraction and metal line pattern layout.

[0048] Specifically, users can trigger region selection operations (such as rectangular selection or polygon selection) in the integrated circuit layout design interface (such as the interface of mainstream tools like EDA) according to actual design needs. This region selection operation is then converted into a standard cell filtering instruction, identifying standard cells falling within the target region as the standard cells to be processed. This approach ensures user control over the layout range while using programmed coordinate judgment rules to ensure the accuracy of the cell filtering, preventing irrelevant standard cells from entering subsequent processes and thus improving the overall layout efficiency of standard cell metal line graphics.

[0049] Referring again to Figure 1, in step 120, the position of the MOS transistor of the standard cell to be processed is determined based on the geometric configuration parameters of the standard cell to be processed. The geometric configuration parameters are used to characterize the position of the standard cell to be processed in the integrated circuit layout and the morphological characteristics of the standard cell to be processed.

[0050] In this application, geometric configuration parameters are core feature data of standard cells pre-stored in integrated circuit layout design tools. Specifically, they can include two categories: positional parameters and shape parameters. Positional parameters can include data such as the overall center coordinates, boundary coordinates, and graphic level of the standard cell in the integrated circuit layout. These parameters can be used to determine the macroscopic position of the standard cell and serve as the basic reference for MOSFET positioning. Shape parameters can include data such as the cell type identifier (single MOSFET cell / MOSFET cell array), the internal device arrangement rules, and MOSFET array tiling parameters (horizontal step size, vertical step size, number of rows, number of columns). These parameters are used to distinguish the standard cell type and guide the coordinate calculation of MOSFETs within the cell array.

[0051] By using the geometric configuration parameters of the standard cell to be processed, the specific coordinates of the MOS transistors within the standard cell can be accurately located, providing a key positional reference for subsequent pattern feature acquisition and metal line pattern layout.

[0052] In step 120 above, determining the MOS transistor position of the standard cell to be processed based on its geometric configuration parameters can be performed according to steps 121 to 122 as follows:

[0053] Step 121: For each standard cell in the standard cells to be processed, if the cell type of each standard cell is a single MOS transistor cell, then read the coordinates of each standard cell in the integrated circuit layout from the geometric configuration parameters, as the MOS transistor position of each standard cell.

[0054] Step 122: If the cell type of each standard cell is a MOS transistor cell array, then based on the coordinates of each standard cell in the integrated circuit layout in the geometric configuration parameters and the tiling parameters of the MOS transistor cell array in each standard cell, calculate the coordinates of each MOS transistor in each standard cell as the MOS transistor position of each standard cell.

[0055] In this application, the type identifier of the standard cell to be processed can be read, and then the MOS transistor positioning logic in step 121 or step 122 above can be triggered respectively to ensure that the positioning process is compatible with the cell form of the standard cell.

[0056] In this application, for a single MOS transistor unit (i.e., a standard unit that integrates only one MOS transistor, such as a basic inverter, a single-transistor amplifier unit, etc.), since the core function of a single MOS transistor unit is a single MOS transistor, in the layout design specification of the standard unit, the geometric center of the single MOS transistor unit coincides with the overall geometric center of the standard unit. Therefore, the coordinates of the standard unit can be directly reused as the position of the MOS transistor without additional calculation.

[0057] In this application, for a MOS transistor cell array (i.e., a standard cell that integrates multiple MOS transistors arranged in a regular array, such as a current steering array, a memory cell array, an analog multiplier array, etc.), the coordinates can be calculated based on its reference coordinates and array tiling parameters. That is, taking the overall coordinates of the standard cell as the reference origin, and combining the tiling rules of the array, the coordinates of each MOS transistor are calculated by traversing the formula, so as to achieve full coverage positioning of all MOS transistors in the array.

[0058] In this application, the origin coordinates of the standard cell, which is a MOS transistor cell array (for example, the geometric center coordinates of the MOS transistor at the bottom left corner of the array), can be used as the reference for calculating the coordinates of all MOS transistors. The tiling parameters of the MOS transistor cell array in the standard cell specifically include the horizontal step size (x-axis spacing between adjacent MOS transistors), the vertical step size (y-axis spacing between adjacent MOS transistors), the number of rows (number of MOS transistors in the y-axis direction), and the number of columns (number of MOS transistors in the x-axis direction).

[0059] To enable those skilled in the art to better understand this application, a specific embodiment will be described below with reference to FIG2.

[0060] Referring to Figure 2, a schematic diagram of a standard unit in the target area of ​​an embodiment of this application is shown.

[0061] As shown in Figure 2, when determining the position of MOS transistors in the MOS transistor cell array, the target standard cell 200 with the type identifier of MOS transistor cell array can be selected from the target area. The target standard cell 200 is a 2×2 MOS transistor cell array, which consists of 4 MOS transistors 201. Among them, MOS transistor A11 and MOS transistor A21 share a source terminal, and MOS transistor A12 and MOS transistor A22 share a source terminal.

[0062] As shown in Figure 2, the reference coordinates (X1, Y1) of the target standard cell 200 and the array tiling parameters, including the horizontal step size dx, the vertical step size dy, the number of rows M=2, and the number of columns N=2, are then calculated row by row and column by column according to a preset formula. The x-coordinate of the MOS transistor in the i-th row and j-th column is:

[0063] Xij = X1 + (j-1) × dx (j is the column index, with a value range of 1 to N);

[0064] The y-coordinate is:

[0065] Yij = Y1 + (i-1) × dy (i is the row number, and its value ranges from 1 to M).

[0066] Finally, all the calculated MOS transistor coordinates are summarized to form a set of MOS transistor positions for the MOS transistor cell array, thereby completing the MOS transistor positioning of the target standard cell.

[0067] Based on the technical solutions in steps 121 and 122 above, this approach can adapt to determining the positions of MOSFETs in different types of standard cells. Positioning logic is designed separately for individual MOSFET cells and MOSFET cell arrays, solving the problem of difficult MOSFET positioning within cell arrays in traditional manual positioning. This achieves accurate positioning of MOSFETs within all types of standard cells. Simultaneously, this method improves cell array positioning efficiency. For MOSFET cell arrays, the coordinates of MOSFETs are automatically calculated using formulas, replacing the manual measurement and positioning operation. Furthermore, it reduces positioning errors. The formulaic calculation method avoids subjective biases from manual measurement, ensuring the positioning accuracy of each MOSFET coordinate and laying the foundation for accurate layout of subsequent metal wire patterns.

[0068] Referring again to Figure 1, in step 130, the graphic feature information of each MOS transistor in the standard cell to be processed is obtained using the position of the MOS transistor as an index. The graphic feature information includes the graphic type and spatial position of each graphic in the MOS transistor.

[0069] In this application, the step of obtaining the graphic feature information of each MOS transistor in the standard cell to be processed by using the position of the MOS transistor as an index can be performed according to the following steps 131 to 132:

[0070] Step 131: Delineate a preset screening area centered on the MOS transistor position of each MOS transistor.

[0071] Step 132: Obtain the graphic type and spatial position of each graphic within the filtering area as graphic feature information of each MOS transistor.

[0072] In this application, the MOSFET serves as the core device for realizing the electrical functions of the standard cell, and the associated pattern is a key reference for metal line interconnection. Therefore, a preset screening area can be automatically delineated based on the process node and cell size corresponding to the standard cell to be processed, with each MOSFET location as the center. The shape and size of the screening area can be adapted to different design requirements.

[0073] Specifically, the screening area can be rectangular or circular. Rectangular areas facilitate coordinate calculations and boundary determination, while circular areas can more evenly cover the effective range associated with the MOSFET. The size of the screening area can also be determined by the process node. Advanced process nodes (such as 5nm and 3nm) have smaller cell sizes, and the side length or diameter of the screening area can be 5μm-8μm. Mature process nodes (such as 16nm and 28nm) have larger cell sizes, and the screening area can be expanded to 10μm-15μm to ensure coverage of all patterns associated with the MOSFET that can be used for metal interconnects.

[0074] In this application, the graphic feature information may include two dimensions: graphic type and spatial location.

[0075] Specifically, graphic types can be used to distinguish the physical properties of graphics, and can be mainly divided into two categories. One category is physical graphics that have actual electrical connection significance, such as metal graphics in metal wire layers, metal graphics in metal via layers, and polysilicon graphics in POLY layers. The other category is identification graphics without physical connection function, such as text labels and component number labels in the layout. Only physical graphics can serve as the basis for the layout of metal wire graphics.

[0076] In this application, spatial location can be used to determine the hierarchical affiliation and coordinates of a graphic in the integrated circuit layout. Specifically, it can include the hierarchical level to which the graphic belongs and the coordinates of the graphic vertices or corners, which is the core basis for subsequently determining the location and range of the metal line graphic layout.

[0077] Based on the technical solutions in steps 131 to 132 above, the screening area is delineated using the MOSFET location as an index. This allows for focusing on graphics directly related to the MOSFET interconnection, avoiding indiscriminate searching across the entire layout, reducing the amount of invalid data processed, and thus improving the targeting and efficiency of feature extraction. Simultaneously extracting both graphic type and spatial location information eliminates interference from invalid graphics and clarifies the hierarchy and coordinates of valid graphics, providing complete data support for subsequent metal line hierarchy selection and precise positioning. This effectively avoids layout deviations caused by missing baseline data. Furthermore, the size and shape of the screening area can be flexibly adjusted according to process nodes, meeting the different unit size requirements from mature to advanced processes, exhibiting strong process compatibility and scenario adaptability.

[0078] Referring again to Figure 1, in step 140, based on the graphic feature information, at least one metal line layer above the standard unit to be processed is laid out with metal line graphics that meet the set requirements.

[0079] In this application, based on the acquired graphic feature information, metal line patterns conforming to design requirements can be laid out in a specified metal line layer for subsequent electrical interconnection between MOSFETs. Furthermore, single-layer or multi-layer metal line layers can be selected according to actual design needs to meet different circuit interconnection requirements.

[0080] In this application, the step of laying out a metal line pattern that meets the set requirements on at least one metal line layer above the standard unit to be processed based on the graphic feature information can be performed according to the following steps 141 to 142:

[0081] Step 141: Filter the target graphics within the target area. The graphic type is a solid graphic and the graphic belongs to the first layer of metal wire layer.

[0082] Step 142: Based on the corner coordinates of the target graphic, lay out a metal line graphic that meets the set requirements on at least one metal line layer above the standard unit to be processed.

[0083] In this application, by using a dual filtering condition of graphic type and graphic level, entity graphics (such as drawing graphics) that have actual physical connection value and belong to the first metal wire layer (i.e., METAL1 layer) can be selected as target graphics from all graphics in the target area. The first metal wire layer is the basic layer for metal wire interconnection, while entity graphics have actual conductive physical form. The combination of the two can ensure that the selected target graphics can be directly used as the basis for metal wire graphic layout, eliminating the interference of meaningless graphics.

[0084] Specifically, during target pattern selection, the pattern feature information corresponding to all MOSFETs within the target area can be retrieved, allowing for a full traversal of all patterns. First, pattern type determination is performed, reading the type attribute of each pattern and filtering out candidate patterns of the entity type. Identifiers such as text labels and device numbers, which lack physical conductivity, are directly filtered out to prevent them from entering subsequent baseline processes. Next, metal line layer level determination is performed. The layer information of the selected entity patterns is further read, retaining only those at the first metal line layer and excluding entity patterns at other functional layers such as the POLY layer and active area, ensuring that the layer attributes of the candidate patterns meet the baseline requirements for metal line pattern layout. Finally, patterns that simultaneously meet both the conditions of being entity patterns and being at the first metal line layer are determined as the final target patterns.

[0085] In step 141 above, the step of selecting target graphics within the target area that are solid graphics and belong to the first metal wire layer can be performed according to the following steps 1411 to 1412:

[0086] Step 1411: Traverse each graphic within the target area. If the graphic type of each graphic is a solid graphic and the graphic belongs to the first metal line layer, then check whether the corner coordinates of each graphic are missing and whether there are breakpoints on the graphic edge.

[0087] Step 1412: If the verification passes, each of the graphics is identified as the target graphic. If the verification fails, each of the graphics is marked as an abnormal graphic, and the location and type of the abnormal graphic are recorded in the design log.

[0088] In this application, by verifying both the integrity of the corner coordinates and the continuity of the edges, it is possible to further determine whether the initially selected graphics meet the morphological requirements for serving as a basis for laying out metal wire patterns. Corner coordinates are the core data for determining the outline of the graphics, while edge continuity determines the physical integrity of the graphics; both are crucial prerequisites for ensuring the accuracy of metal wire replication.

[0089] Specifically, when conducting graphic integrity verification, the first step is to verify the integrity of corner coordinates. This involves reading the corner coordinate data of each graphic to be verified, counting the number of coordinate data, and determining whether the number of corner coordinates of regular geometric shapes such as rectangles and squares reaches a preset threshold. For example, a rectangle requires two corner coordinates.

[0090] To enable those skilled in the art to better understand this application, a specific embodiment will be described below with reference to FIG3.

[0091] Referring to Figure 3, a schematic diagram of a standard unit in the target area of ​​an embodiment of this application is shown.

[0092] As shown in subgraph (a) of Figure 3, the graphic to be verified, 203, is a rectangle, which includes diagonal points B1 and B2. It can be understood that if the corner point coordinate data is complete, the quantity is sufficient, and a closed graphic outline can be formed, then the verification of this dimension is deemed to have passed. If there are missing corner point coordinate data, insufficient quantity, or failure to form a closed outline, then the verification of this dimension is deemed to have failed.

[0093] Next, edge continuity verification can be performed. Specifically, the edge detection interface of the layout design tool can be called to scan the edge contour of the graphic segment by segment, detecting whether there are any morphological defects such as breaks or gaps. At the same time, a threshold for judging edge breaks can be set. For example, under 5nm process, a break length exceeding 0.01μm is judged as a defect. If there are no breaks or the break length is less than the threshold after scanning, the verification of this dimension is considered to be passed. If there are breaks exceeding the threshold, the verification of this dimension is considered to be failed. Finally, a comprehensive verification result is judged. Only when both the corner coordinate integrity and the edge continuity of the graphic are verified as passed is the overall verification considered to be qualified. If either dimension fails, the graphic is judged to have morphological abnormalities.

[0094] After verifying the integrity of the graphics, classification and processing can begin. Qualified graphics can be identified as target graphics for metal line layout. Core data such as corner coordinates and outline range of these target graphics can be classified and archived according to MOS transistor numbers. For abnormal graphics, their abnormality type can be clearly identified, such as missing corner coordinates or edge breaks. The specific location coordinates of the abnormal graphics in the layout can be recorded to form basic information about the abnormal graphics. The location and type of the abnormal graphics should then be entered into the design log. This facilitates designers' subsequent retrospective investigation of the causes of the abnormal graphics and provides data reference for subsequent layout design optimization.

[0095] Based on the technical solutions in steps 1411 to 1412 above, pre-screening of the target pattern can be achieved. The integrity of the baseline pattern is verified before the metal line pattern is laid out, eliminating patterns with morphological defects in advance and avoiding problems such as incomplete outlines and connection breaks that may occur when laying out metal line patterns based on defective patterns. Simultaneously, this process is adaptable to advanced process precision, allowing for the setting of precise verification thresholds according to different process nodes. This meets the stringent requirements of advanced processes such as 5nm and 3nm for pattern morphology, ensuring the accuracy and process compatibility of the baseline pattern.

[0096] In this application, after the target graphic is obtained through screening, a metal line graphic that meets the process and design requirements can be laid out on at least one metal line layer above the standard unit to be processed, based on the corner coordinates of the target graphic and through operations such as contour replication, shape transformation, and parameter adjustment.

[0097] Specifically, in step 142 above, the step of laying out a metal line graphic that meets the set requirements on at least one metal line layer above the standard unit to be processed based on the corner coordinates of the target graphic can be performed according to the following steps 1421 to 1423:

[0098] Step 1421: Based on the corner coordinates of the target graphic, copy the baseline outline and position of the target graphic.

[0099] Step 1422: Call the shape conversion function to convert the reference contour from a polygon to a path shape at the graphic position on the first metal line layer.

[0100] Step 1423: Set the width of the path shape to a first width set by the user, so as to lay out a first metal line pattern that meets the set requirements on the first metal line layer above the standard unit to be processed.

[0101] In this application, based on the corner coordinates of the target graphic, the baseline outline and spatial position of the target graphic can be replicated, ensuring that the subsequently laid-out metal wire graphics accurately match the baseline graphic in spatial orientation, providing a basic shape and position reference for the precise layout of the metal wire graphics. The corner coordinates of the target graphic are core data representing its outline and position; replicating based on these coordinates ensures the accuracy of the initial shape of the metal wire graphics. Specifically, the geometric outline of the target graphic can be restored in the layout design space based on its corner coordinates. For regular graphics such as rectangles and squares, a closed outline is formed by directly connecting the coordinates; for irregular polygonal graphics, the corners are connected sequentially to ensure that the replicated outline is completely consistent with the target graphic. Furthermore, while replicating the outline, it can be precisely placed in the layout space corresponding to the target graphic, ensuring that the corner coordinates of the replicated outline completely coincide with the corner coordinates of the target graphic, achieving precise alignment and avoiding initial positional deviations. After copying the baseline outline and graphic position, the corner coordinates and outline range of the replicated outline and the original target graphic can be compared. After confirming that there is no deviation, the next step of the shape conversion process can be carried out.

[0102] In this application, a shape conversion function can be called to convert the replicated reference contour into a path shape. This is because the path shape is better suited to the electrical signal transmission requirements of the metal wire pattern compared to the reference contour, and it allows for flexible adjustment of the width, effectively improving the conductivity continuity and process adaptability of the metal wire pattern. Specifically, the shape conversion function built into the layout design tool can be called. This function can convert the reference contour from a polygon to a path shape while preserving the spatial position attributes of the shape. Subsequently, the copied reference contour can be input into the conversion function at the corresponding graphic position in the first metal wire layer. The function can automatically convert the reference contour from a polygon to a path shape with conductive properties, and during the conversion process, it can keep the center line of the path shape coincident with the center line of the reference contour, ensuring that the position does not shift. After the conversion is completed, it can be checked whether the coverage area of ​​the path shape is consistent with the original reference contour, and the path's layer attribute is confirmed to be the first metal wire layer, avoiding shape deformation or layer errors.

[0103] In this application, the width of the converted path shape can be adjusted according to the user-defined first width that meets process requirements, ultimately generating a first metal line pattern that satisfies design and process requirements. The first width, set by the user in conjunction with the minimum wiring width standard and circuit current transmission requirements of a specific process node, is a key parameter ensuring the electrical performance and process compliance of the metal line. Specifically, the user-defined first width parameter can be read first; for example, it can be set to 0.15μm for a 5nm process and 0.2μm for a 16nm process. Then, the read first width parameter can be assigned to the path shape to be adjusted, automatically expanding or contracting the path width along the path centerline until the set first width is reached. During the adjustment process, the centerline position of the path remains unchanged, ensuring that the overall position of the metal line pattern does not shift. After the width adjustment is completed, it can be verified whether the adjusted path width conforms to the process design rules, i.e., whether it is greater than or equal to the minimum wiring width of the process, and simultaneously confirm that the width is uniform and without deviation, avoiding local width discrepancies.

[0104] To enable those skilled in the art to better understand this application, the following description will continue with reference to FIG3 and a specific embodiment.

[0105] As shown in sub-figure (a) of Figure 3, based on the coordinates of the corner points B1 and B2 of the target graphic 202, according to the technical solutions of steps 1421 to 1423 above, a first metal line graphic satisfying the first width Δd can be laid out in the first metal line layer, as shown in sub-figure (b) of Figure 3.

[0106] Based on the technical solutions in steps 1421 to 1423 above, the outline and position of the target graphic are directly copied based on the corner coordinates, eliminating the need for designers to manually draw the baseline outline of the target graphic. This significantly shortens the preparation time for metal wire pattern layout and improves the efficiency of metal wire pattern layout. Furthermore, converting the baseline outline from a polygon to a path shape results in a more continuous conductive path for the metal wire pattern, reducing parasitic resistance and capacitance during signal transmission. This is particularly suitable for high-precision signal transmission in analog circuits. The path shape also supports flexible width parameter modification, quickly adapting to the varying width requirements of different process nodes, facilitating subsequent width settings. In addition, by setting width parameters that meet process requirements, it is ensured that the metal wire pattern width complies with process design rules, avoiding design rule violations due to insufficient width. Users can also flexibly set the first width according to the circuit's current carrying capacity requirements, such as setting a wider first width for high-current transmission paths, thereby improving the current carrying capacity of the metal wire pattern and ensuring stable circuit operation.

[0107] In this application, after all the first metal wire patterns have been laid out in the first metal wire layer, the following steps 151 to 153 can also be performed:

[0108] Step 151: Perform a spacing check on each first metal line graphic in the first metal line layer to determine whether the spacing between adjacent first metal line graphics meets the preset spacing.

[0109] Step 152: If the spacing between any adjacent first metal line patterns meets the preset spacing, then the any adjacent first metal line pattern is taken as the final metal line pattern laid out on the first metal line layer above the standard unit to be processed.

[0110] Step 153: If the spacing between any adjacent first metal wire patterns does not meet the preset spacing, adjust the spacing between any adjacent first metal wire patterns until the preset spacing is met, and then complete the layout of the first metal wire patterns.

[0111] In this application, by calculating the edge spacing of adjacent first metal line patterns and comparing it with a preset spacing threshold, it can be determined whether the spacing meets the process design rules. The spacing of metal line patterns is a key parameter to ensure that there is no signal crosstalk and short circuit between metal lines in the same layer. The preset spacing threshold varies for different process nodes. For example, the preset spacing is usually not less than 0.12μm for 5nm process and not less than 0.2μm for 16nm process. For adjacent first metal line patterns that pass the spacing verification, their final shape and position in the first metal line layer can be directly confirmed without additional adjustments, thereby locking in metal line patterns that meet the process requirements and providing a stable underlying metal interconnect reference for subsequent multi-layer metal line pattern layout or overall layout verification. For adjacent first metal line patterns with insufficient spacing, their edge spacing can be increased by shifting the position of the metal line pattern or fine-tuning the outline of the metal line pattern until the preset spacing requirement is met, thereby correcting the process compliance without changing the electrical connection function of the metal lines. It is evident that completing the spacing verification before the finalization of the metal line pattern can detect potential problems of insufficient spacing in advance, avoid short circuits or signal crosstalk issues on the same layer of metal lines after tape-out, and reduce the risk of chip scrap.

[0112] In this application, after the first metal wire pattern that meets the set requirements is laid out on the first metal wire layer above the standard unit to be processed, the following steps 154 to 155 can also be performed:

[0113] Step 154: Copy the spatial position parameters of the first metal line graphic, and change the layer to which the graphic belongs in the spatial position parameters from the first metal line layer to the second metal line layer.

[0114] Step 155: Set the width of the path shape of the second metal wire layer to the second width set by the user, so as to lay out the second metal wire pattern that meets the set requirements on the second metal wire layer above the standard unit to be processed.

[0115] In this application, the spatial position parameters of the first metal wire pattern, including core data such as centerline coordinates and endpoint coordinates, can be read first. Then, the above parameters are fully copied to generate a parameter copy that is completely consistent with the position of the first metal wire pattern, providing a precise basis for anchoring the position of the second metal wire pattern.

[0116] For the generated parameter copy, the layer attribute of its corresponding metal wire graphic can be further modified, replacing the original first-layer metal wire layer attribute with the second-layer metal wire layer attribute (i.e., METAL2 layer), thus completing the layer migration of the metal wire graphic. After the modification, the layer attribute of the parameter copy can be verified to ensure its effectiveness. The modified parameter copy is pre-mapped in the layout space, and the pre-mapped position of the second metal wire graphic is compared with the actual position of the first metal wire graphic to ensure that the coordinates of their center lines and endpoints are consistent.

[0117] Furthermore, a user-preset second width parameter can be read. This second width parameter must simultaneously meet the minimum wiring width standard of the second metal line layer and the circuit functional requirements. Then, the read second width parameter is assigned to the path shape obtained after modifying the first metal line graphic layer, expanding or contracting the width along the path centerline until the set second width is reached. It is important to note that the position of the path centerline in the second metal line layer remains unchanged during the width adjustment process.

[0118] Finally, after the path of the second metal line layer passes both width compliance and alignment checks, the path becomes the second metal line graphic of the second metal line layer above the standard unit to be processed. At this point, its parameters can be archived to the layout database to complete the layout of the second metal line graphic.

[0119] Based on the technical solutions in steps 154 to 155 above, the alignment of the first and second metal wire patterns in different metal wire layers can be ensured. Precise matching of the positions of multi-layer metal wire patterns is achieved through parameter reuse, providing a positional reference for the accurate placement of metal vias between subsequent metal wire layers. Simultaneously, this solution simplifies the placement process of metal wire patterns in multi-metal wire layers, eliminating the need to redraw the positional outline of the second metal wire pattern. By directly reusing the parameters of the first metal wire pattern and modifying its corresponding metal wire layer, the preparation time for multi-layer metal wire placement can be significantly shortened. Furthermore, this solution can adapt to the process and functional requirements of multi-metal wire layers, supporting differentiated settings for the width of the second metal wire pattern. It can meet the minimum wiring width standard of the process and adjust the width according to circuit requirements to improve current carrying capacity. During width adjustment, the alignment of the metal wire patterns in different metal wire layers is maintained, avoiding offset of the metal wire patterns between different metal wire layers due to width modification. This eliminates the potential for positional deviations in the placement of metal vias between subsequent metal wire layers, improving the reliability of interconnecting multiple metal wire patterns in different metal wire layers.

[0120] In this application, after all the second metal wire patterns have been laid out on the second metal wire layer, the following steps 156 to 158 can also be performed:

[0121] Step 156: Alignment verification is performed between the second metal line pattern and the first metal line pattern, and the deviation values ​​of the center lines of the second metal line pattern and the first metal line pattern in the x-axis and y-axis directions are calculated.

[0122] Step 157: If the deviation value is less than or equal to the preset deviation value, the alignment is deemed qualified, and the second metal line pattern that meets the set requirements is completed in the second metal line layer above the standard unit to be processed.

[0123] Step 158: If the deviation value is greater than the preset deviation value, the position of the second metal wire pattern is corrected based on the centerline coordinates of the first metal wire pattern until the deviation value is less than or equal to the preset deviation value, and then the layout of the second metal wire pattern is completed.

[0124] In this application, the deviation of the centerline coordinates of the first and second metal wire patterns directly reflects the positional offset of the metal wire patterns between different metal wire layers. This is a key indicator for measuring the accuracy of multi-layer interconnection of metal wire patterns. By extracting the centerline coordinates of the first and second metal wire patterns and calculating their coordinate deviations along the x and y axes, the alignment degree of the two metal wire patterns is determined. For the second metal wire pattern with a coordinate deviation value less than or equal to a preset deviation value, its final position and shape in the second metal wire layer can be directly confirmed without additional adjustments. This solidifies the metal wire structure that meets the inter-layer alignment requirements, providing a stable positional reference for subsequent interconnection of metal wire patterns in different metal wire layers. For the second metal wire pattern with a coordinate deviation value greater than the preset deviation value, the coordinate deviation value can be eliminated by translating the overall position of the second metal wire pattern, using the centerline coordinates of the first metal wire pattern as a reference, until the preset deviation requirement is met. This allows for compliance correction of the alignment accuracy of the two metal wire patterns without changing the width and conductive path of the second metal wire pattern.

[0125] Based on the technical solution proposed in this application, the efficiency of laying out metal line patterns for standard cells can be significantly improved. Specifically, this application eliminates the need for manual selection of standard cells one by one; the user only needs to select the target area to automatically lock the standard cells to be processed. This avoids the tedious operation and risk of omissions associated with manual selection, greatly reducing the time cost of standard cell screening. Simultaneously, determining the MOSFET position based on the geometric configuration parameters of the standard cells can replace the traditional method of manually calibrating MOSFETs, ensuring the accuracy of MOSFET position calibration and saving the time spent on MOSFET verification. Automatically extracting graphic feature information using MOSFET positions as indexes enables batch collection and integration of graphic feature data, avoiding the errors and time-consuming process of manually entering graphic feature information line by line. This ensures the timeliness and completeness of data retrieval, laying an efficient data foundation for subsequent metal line pattern laying. Finally, based on standardized graphic feature information, the layout of metal wire graphics is automatically completed in at least one metal wire layer without the need for repeated manual adjustment of parameters such as the layer and position of the metal wires. This reduces the repetitive operation of laying out metal wire graphics in multiple layers and ensures the consistency of the layout. It can greatly shorten the layout cycle of metal wire graphics in standard units, while reducing the error rate caused by manual intervention, thus balancing the efficiency and quality of metal wire graphic layout.

[0126] In this application, after all the second metal wire patterns have been laid out on the second metal wire layer, the following steps 161 to 164 can also be performed:

[0127] Step 161: Determine the center coordinates of the metal via based on the overlapping area of ​​the first metal wire pattern and the second metal wire pattern.

[0128] Step 162: Generate the outline of the metal through hole pattern based on the center coordinates of the metal through hole and the metal through hole size standard provided by the process manufacturer.

[0129] Step 163: Determine whether the metal through-hole pattern falls completely within the overlapping area.

[0130] Step 164: If the metal through-hole pattern falls completely within the overlapping area, the layout of the metal through-hole pattern is complete. If the metal through-hole pattern does not fall completely within the overlapping area, the center coordinates of the metal through-hole are adjusted until the metal through-hole pattern falls completely within the overlapping area, thus completing the layout.

[0131] In this application, by identifying the spatial overlap area between the first metal wire pattern and the second metal wire pattern, and using the geometric center of this area as the center coordinate of the metal via, it can be ensured that the metal via can simultaneously cover the effective conductive area of ​​the two metal wire patterns, thereby achieving stable conduction of interlayer current.

[0132] In this application, a through-hole graphic outline that meets process requirements can be generated based on the center coordinates of the metal through-hole and the through-hole size standard provided by the process manufacturer, ensuring that the physical size of the through-hole is adapted to the processing accuracy and conductivity requirements of the current process node. The dimensional parameters such as the length L and width W of the metal through-hole are determined by the process manufacturer according to the process capability and electrical performance requirements. The size difference between different process nodes is significant. For example, the through-hole size is usually 0.12μm×0.12μm in the 5nm process and 0.2μm×0.2μm in the 16nm process.

[0133] In this application, by comparing the overall outline of the via pattern with the boundary range of the overlapping area, it can be determined whether the via completely falls within the overlapping area. This ensures that the via can simultaneously form effective contact with both layers of metal wires, avoiding poor interlayer contact caused by the via exceeding the overlapping area. If the via partially exceeds the overlapping area, it may only contact a single layer of metal wire, leading to a sudden increase in contact resistance or even an interconnection break. If the metal via pattern does not completely fall within the overlapping area, the geometric center can be reselected within the overlapping area as the new center coordinates of the via, the via outline can be regenerated, and the verification can be repeated until the via completely falls within the overlapping area. This achieves spatial adaptation between the via and the overlapping area without changing the via size. Finally, the final qualified via center coordinates and outline parameters are synchronized to the layout database, completing the final layout of the metal via.

[0134] Based on the technical solutions in steps 161 to 164 above, the geometric center of the overlapping area of ​​the two metal wires is used as the via reference, ensuring a symmetrical distribution of the contact area between the via and the two metal wires. This effectively reduces the non-uniformity of contact resistance and improves the stability of interlayer current transmission. Simultaneously, spatial intersection calculations accurately pinpoint the overlapping area, preventing interconnect failures caused by vias being placed in non-overlapping areas. Regarding process adaptation, vias are generated according to the dimensional standards provided by the process manufacturer, ensuring they meet processing requirements and avoiding fabrication errors due to dimensional discrepancies. Furthermore, standardized generation of via contours is achieved through coordinate derivation, replacing tedious manual drawing and significantly improving the design efficiency of the interconnect process. For compliance verification, spatial compatibility verification is completed before the final via design, preemptively eliminating potential contact problems. Automated verification is achieved through coordinate extreme value comparison, eliminating the need for manual visual confirmation, avoiding subjective misjudgments, and ensuring the accuracy of verification results. To address the boundary out-of-bounds issue, spatial adaptation can be achieved by adjusting only the center coordinates while retaining the standard through-hole dimensions. This satisfies both processing requirements and ensures effective contact. Furthermore, the through-hole position can be precisely corrected by reselecting the center of the sub-region, avoiding other graphic interferences caused by the adjustment and further improving the overall quality of interlayer interconnection.

[0135] In this application, after all the metal wire patterns that meet the set requirements are laid out on at least one metal wire layer above the standard unit to be processed, the following steps 171 to 172 can also be performed:

[0136] Step 171: Invoke the design rule check engine to perform a global check on the completed metal wire pattern. This global check includes at least checking whether the width of the metal wire pattern meets the user-defined width threshold, whether the spacing between the metal wire pattern and adjacent patterns meets the set spacing threshold, and whether the overlap between the metal via pattern and the metal wire pattern is greater than or equal to the set overlap.

[0137] Step 172: If no violations are found in the global check, the metal wire pattern layout is deemed acceptable. If violations exist, a design rule check violation report is generated, and based on the design rule check violation report, the parameters of the violating metal wire pattern are automatically adjusted. After adjustment, the global check is re-executed until no violations are found in the global check.

[0138] In this application, a Design Rule Check (DRC) engine can be invoked to perform batch comparisons of the parameters of the deployed metal line patterns and metal via patterns with preset process rule thresholds, thereby achieving multi-dimensional global compliance determination. The Design Rule Check engine is a professional verification tool in integrated circuit layout design, which can accurately identify various process violations, and its verification dimensions cover the core performance and process constraint indicators of metal interconnects.

[0139] Furthermore, metal wire patterns with no violations in the global verification can be directly confirmed as qualified. For metal wire patterns with violations, a violation report is generated and automated parameter correction is carried out. Violations are cleared through repeated verification, ensuring that all interconnected metal wire patterns comply with the process design rules, taking into account both layout compliance and electrical reliability.

[0140] Based on the technical solution proposed in this application, the efficiency and quality of integrated circuit design can be significantly improved. By automating the generation of metal line patterns for standard cells, the need for manual operation can be greatly reduced. According to preliminary tests, the metal line pattern adjustment time can be reduced by approximately 80%. In typical ASIC design projects, the placement and adjustment time of metal line patterns in standard cells can be shortened by approximately 40%, saving design personnel time and accelerating the overall design process. Simultaneously, automated processing can reduce errors that may be caused by human operation. In a test case containing 1000 standard cells, the number of errors can be reduced from 5 to 10 manually adjusted to less than 1. Furthermore, the automated process ensures the consistency of all processed objects, directly and positively impacting the reliability and yield of large-scale integrated circuits. The technical solution proposed in this application supports user-defined widths of the first and second metal line patterns, adapting to various process nodes from 65nm to 5nm, offering high flexibility. The automatically generated metal line patterns meet design requirements, improving signal integrity and enhancing overall chip performance. Its framework design also possesses good scalability, easily extending to more metal layers and reserving space for future technological development.

[0141] The following describes an embodiment of the apparatus of this application, which can be used to execute the method for laying out metal wire patterns of standard units in the above embodiments of this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method for laying out metal wire patterns of standard units described above.

[0142] Referring to Figure 4, a block diagram of the metal wire pattern layout device for the standard unit in an embodiment of this application is shown.

[0143] As shown in FIG4, the metal wire pattern layout device 400 of the standard unit according to the embodiment of the present application includes: a first determining unit 401, a second determining unit 402, an acquiring unit 403 and a layout unit 404.

[0144] The system includes: a first determining unit 401, configured to determine standard cells falling within a target area as standard cells to be processed in response to a user selecting such a target area in the integrated circuit layout design interface; a second determining unit 402, configured to determine the position of the MOS transistor in the standard cell to be processed based on the geometric configuration parameters of the standard cell to be processed, wherein the geometric configuration parameters characterize the position and morphological features of the standard cell to be processed in the integrated circuit layout; an acquiring unit 403, configured to acquire graphic feature information of each MOS transistor in the standard cell to be processed using the MOS transistor position as an index, wherein the graphic feature information includes the graphic type and spatial position of each graphic in the MOS transistor; and a placement unit 404, configured to place metal line graphics that meet set requirements on at least one metal line layer above the standard cell to be processed based on the graphic feature information.

[0145] In some embodiments of this application, based on the foregoing scheme, the second determining unit 402 is configured as follows: for each standard unit in the standard units to be processed, if the unit type of each standard unit is a single MOS transistor unit, then the coordinates of each standard unit in the integrated circuit layout are read from the geometric configuration parameters as the MOS transistor position of each standard unit; if the unit type of each standard unit is a MOS transistor array, then the coordinates of each MOS transistor in each standard unit are calculated based on the coordinates of each standard unit in the integrated circuit layout in the geometric configuration parameters and the tiling parameters of the MOS transistor array in each standard unit as the MOS transistor position of each standard unit.

[0146] In some embodiments of this application, based on the foregoing scheme, the acquisition unit 403 is configured to: delineate a preset range of screening area centered on the MOS transistor position of each MOS transistor; acquire the graphic type and spatial position of each graphic within the screening area as graphic feature information of each MOS transistor.

[0147] In some embodiments of this application, based on the foregoing scheme, the spatial location includes the layer to which the graphic belongs and the coordinates of the graphic corner points. The layout unit 404 is configured to: filter target graphics in the target area whose graphic type is a solid graphic and whose graphic layer is the first metal line layer; and based on the graphic corner point coordinates of the target graphic, lay out metal line graphics that meet the set requirements in at least one metal line layer above the standard unit to be processed.

[0148] In some embodiments of this application, based on the aforementioned scheme, the deployment unit 404 is configured to: traverse each graphic within the target area; if the graphic type of each graphic is a solid graphic and the graphic belongs to the first layer of metal wire layer, then check whether the corner coordinates of each graphic are missing and whether there are breakpoints on the graphic edge; if the check passes, then each graphic is determined as a target graphic; if the check fails, then each graphic is marked as an abnormal graphic, and the location and abnormality type of the abnormal graphic are recorded in the design log.

[0149] In some embodiments of this application, based on the foregoing scheme, the layout unit 404 is configured to: copy the reference outline and graphic position of the target graphic based on the graphic corner coordinates of the target graphic; call a shape conversion function to convert the reference outline from a polygon to a path shape at the graphic position on the first metal line layer; set the width of the path shape to a first width set by the user, so as to lay out a first metal line graphic that meets the set requirements on the first metal line layer above the standard unit to be processed.

[0150] In some embodiments of this application, based on the foregoing scheme, the method further includes: a first verification unit, configured to verify the spacing of each first metal line pattern in the first metal line layer after all the first metal line patterns have been laid out in the first metal line layer, and determine whether the spacing of each adjacent first metal line pattern meets the preset spacing; if the spacing of any adjacent first metal line pattern meets the preset spacing, then the any adjacent first metal line pattern is used as the final metal line pattern laid out on the first metal line layer above the standard unit to be processed; if the spacing of any adjacent first metal line pattern does not meet the preset spacing, then the spacing of any adjacent first metal line pattern is adjusted until the preset spacing is met and the laying out of the first metal line pattern is completed.

[0151] In some embodiments of this application, based on the foregoing scheme, the layout unit 404 is configured as follows: after laying out a first metal line graphic that meets the set requirements on the first metal line layer above the standard unit to be processed, the spatial position parameters of the first metal line graphic are copied, and the layer to which the graphic belongs in the spatial position parameters is changed from the first metal line layer to the second metal line layer; the width of the path shape of the second metal line layer is set to a second width set by the user, so as to lay out a second metal line graphic that meets the set requirements on the second metal line layer above the standard unit to be processed.

[0152] In some embodiments of this application, based on the foregoing scheme, the method further includes: a second verification unit, configured to perform alignment verification between the second metal wire pattern and the first metal wire pattern after all the second metal wire patterns have been laid out in the second metal wire layer, and calculate the deviation values ​​of the center lines of the second metal wire pattern and the first metal wire pattern in the x-axis and y-axis directions; if the deviation value is less than or equal to a preset deviation value, the alignment is deemed qualified, and the second metal wire pattern that meets the set requirements is laid out in the second metal wire layer above the standard unit to be processed; if the deviation value is greater than the preset deviation value, the position of the second metal wire pattern is corrected based on the center line coordinates of the first metal wire pattern until the deviation value is less than or equal to the preset deviation value, and then the laying out of the second metal wire pattern is completed.

[0153] In some embodiments of this application, based on the foregoing scheme, the layout unit 404 is configured as follows: after all the second metal wire patterns are laid out in the second metal wire layer, the center coordinates of the metal through-hole are determined based on the overlapping area of ​​the first metal wire pattern and the second metal wire pattern; the outline of the metal through-hole pattern is generated according to the center coordinates of the metal through-hole and the metal through-hole size standard provided by the manufacturer; it is determined whether the metal through-hole pattern falls completely within the overlapping area; if the metal through-hole pattern falls completely within the overlapping area, the layout of the metal through-hole pattern is completed; if the metal through-hole pattern does not fall completely within the overlapping area, the center coordinates of the metal through-hole are adjusted until the metal through-hole pattern falls completely within the overlapping area, and then the layout is completed.

[0154] In some embodiments of this application, based on the foregoing scheme, the method further includes: a third verification unit, configured to, after all metal wire patterns meeting the set requirements have been laid out on at least one metal wire layer above the standard unit to be processed, call a design rule inspection engine to perform a global verification on the laid-out metal wire patterns; wherein, the global verification includes at least whether the width of the metal wire pattern meets the width threshold set by the user, whether the spacing between the metal wire pattern and adjacent patterns meets the set spacing threshold, and whether the overlap between the metal through-hole pattern and the metal wire pattern is greater than or equal to the set overlap; if there are no violations in the global verification, the metal wire pattern is determined to be qualified; if there are violations, a design rule inspection violation report is generated, and based on the design rule inspection violation report, the parameters of the violating metal wire pattern are automatically adjusted, and the global verification is re-executed after adjustment until there are no violations in the global verification.

[0155] Based on the same inventive concept, embodiments of this application provide a computer program product, the computer program product including computer instructions stored in a computer-readable storage medium and adapted to be read and executed by a processor, so as to cause a computer device having the processor to perform operations to implement the metal wire pattern layout method of the standard unit as described above.

[0156] Based on the same inventive concept, embodiments of this application provide a computer-readable storage medium storing at least one computer program instruction, which is loaded and executed by a processor to implement the operations performed by the metal wire pattern layout method of the standard unit as described above.

[0157] Based on the same inventive concept, this application also provides an electronic device. Referring to FIG5, a schematic diagram of the structure of the electronic device in this application is shown. The electronic device includes one or more memories 504, one or more processors 502, and at least one computer program (computer program instruction) stored in the memory 504 and executable on the processor 502. When the processor 502 executes the computer program, it implements the metal wire pattern layout method of the standard unit as described above.

[0158] In Figure 5, a bus architecture (represented by bus 500) is shown. Bus 500 may include any number of interconnected buses and bridges, linking various circuits including one or more processors represented by processor 502 and memory represented by memory 504. Bus 500 may also link various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. Bus interface 505 provides an interface between bus 500 and receiver 501 and transmitter 503. Receiver 501 and transmitter 503 may be the same element, i.e., a transceiver, providing a unit for communicating with various other devices over a transmission medium. Processor 502 is responsible for managing bus 500 and general processing, while memory 504 can be used to store data used by processor 502 during operation.

[0159] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope and spirit of this application and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Furthermore, the functional units may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit.

[0160] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0161] The units described as separate components may or may not be physically separate. Similarly, the components of the control device may or may not be physical units; they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0162] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all and / or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all and / or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing computer program instructions, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0163] The above description is merely an embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A method for arranging metal wire patterns in a standard unit, characterized in that, The method includes: responding to a user selecting a target area in an integrated circuit layout design interface, identifying standard cells falling within the target area as standard cells to be processed; determining the MOS transistor positions of the standard cells to be processed based on their geometric configuration parameters, wherein the geometric configuration parameters characterize the position and morphological features of the standard cells to be processed in the integrated circuit layout; and obtaining graphic feature information of each MOS transistor in the standard cells to be processed using the MOS transistor positions as indexes, wherein the graphic feature information includes the graphic type and spatial position of each graphic in the MOS transistor, and the spatial position includes... The layer to which the graphic belongs and the coordinates of its corner points are determined. Each graphic within the target area is traversed. If the graphic type of each graphic is a solid graphic and its layer is the first metal line layer, the corner coordinates of each graphic are checked for missing points, and the edges of the graphic are checked for breakpoints. If the check passes, each graphic is identified as the target graphic. If the check fails, each graphic is marked as an abnormal graphic, and the location and type of the abnormal graphic are recorded in the design log. Based on the corner coordinates of the target graphic, metal line graphics that meet the set requirements are laid out on at least one metal line layer above the standard unit to be processed.

2. The method according to claim 1, characterized in that, The step of determining the MOS transistor position of the standard cell to be processed based on the geometric configuration parameters of the standard cell to be processed includes: for each standard cell in the standard cell to be processed, if the cell type of each standard cell is a single MOS transistor cell, then the coordinates of each standard cell in the integrated circuit layout are read from the geometric configuration parameters as the MOS transistor position of each standard cell; if the cell type of each standard cell is a MOS transistor cell array, then based on the coordinates of each standard cell in the integrated circuit layout in the geometric configuration parameters and the tiling parameters of the MOS transistor cell array in each standard cell, the coordinates of each MOS transistor in each standard cell are calculated as the MOS transistor position of each standard cell.

3. The method according to claim 1, characterized in that, The step of using the position of the MOS transistor as an index to obtain the graphic feature information of each MOS transistor in the standard unit to be processed includes: defining a preset range of screening area centered on the position of each MOS transistor; and obtaining the graphic type and spatial position of each graphic within the screening area as the graphic feature information of each MOS transistor.

4. The method according to claim 1, characterized in that, The step of laying out a metal line graphic that meets the set requirements on at least one metal line layer above the standard unit to be processed, based on the corner coordinates of the target graphic, includes: copying the reference outline and graphic position of the target graphic based on the corner coordinates of the target graphic; calling a shape conversion function to convert the reference outline from a polygon to a path shape at the graphic position on the first metal line layer; and setting the width of the path shape to a first width set by the user, so as to lay out a first metal line graphic that meets the set requirements on the first metal line layer above the standard unit to be processed.

5. The method according to claim 4, characterized in that, After all the first metal wire patterns are laid out in the first metal wire layer, the method further includes: performing a spacing check on each of the first metal wire patterns in the first metal wire layer to determine whether the spacing between adjacent first metal wire patterns meets a preset spacing; if the spacing between any adjacent first metal wire pattern meets the preset spacing, then the any adjacent first metal wire pattern is used as the final metal wire pattern laid out on the first metal wire layer above the standard unit to be processed; if the spacing between any adjacent first metal wire pattern does not meet the preset spacing, then the spacing between any adjacent first metal wire pattern is adjusted until the preset spacing is met, and then the laying out of the first metal wire patterns is completed.

6. The method according to claim 4, characterized in that, After the first metal line graphic that meets the set requirements is laid out on the first metal line layer above the standard unit to be processed, the method further includes: copying the spatial position parameters of the first metal line graphic, and changing the layer to which the graphic belongs in the spatial position parameters from the first metal line layer to the second metal line layer; setting the width of the path shape of the second metal line layer to a second width set by the user, so as to lay out the second metal line graphic that meets the set requirements on the second metal line layer above the standard unit to be processed.

7. The method according to claim 6, characterized in that, After all the second metal wire patterns are laid out in the second metal wire layer, the method further includes: performing alignment verification between the second metal wire patterns and the first metal wire patterns, and calculating the deviation values ​​of the center lines of the second metal wire patterns and the first metal wire patterns in the x-axis and y-axis directions; if the deviation value is less than or equal to a preset deviation value, the alignment is deemed qualified, and the second metal wire patterns that meet the set requirements are laid out in the second metal wire layer above the standard unit to be processed; if the deviation value is greater than the preset deviation value, the position of the second metal wire patterns is corrected based on the center line coordinates of the first metal wire patterns until the deviation value is less than or equal to the preset deviation value, and the laying out of the second metal wire patterns is completed.

8. The method according to claim 6, characterized in that, After all the second metal wire patterns are laid out in the second metal wire layer, the method further includes: determining the center coordinates of the metal through-hole based on the overlapping area of ​​the first metal wire pattern and the second metal wire pattern; generating the outline of the metal through-hole pattern according to the center coordinates of the metal through-hole and the metal through-hole size standard provided by the manufacturer; determining whether the metal through-hole pattern falls completely within the overlapping area; if the metal through-hole pattern falls completely within the overlapping area, the laying out of the metal through-hole pattern is completed; if the metal through-hole pattern does not fall completely within the overlapping area, the center coordinates of the metal through-hole are adjusted until the metal through-hole pattern falls completely within the overlapping area, and then the laying out is completed.

9. The method according to claim 8, characterized in that, After all metal wire patterns meeting the set requirements are laid out on at least one metal wire layer above the standard unit to be processed, the method further includes: calling the design rule inspection engine to perform a global verification on the laid-out metal wire patterns; wherein, the global verification includes at least whether the width of the metal wire pattern meets the width threshold set by the user, whether the spacing between the metal wire pattern and adjacent patterns meets the set spacing threshold, and whether the overlap between the metal via pattern and the metal wire pattern is greater than or equal to the set overlap; if there are no violations in the global verification, the metal wire pattern is determined to be qualified; if there are violations, a design rule inspection violation report is generated, and based on the design rule inspection violation report, the parameters of the violating metal wire pattern are automatically adjusted, and the global verification is re-executed after adjustment until there are no violations in the global verification.

10. A device for laying out metal wire patterns in a standard unit, characterized in that, The device includes: a first determining unit, configured to, in response to a user selecting a target area in an integrated circuit layout design interface, determine standard cells falling within the target area as standard cells to be processed; a second determining unit, configured to, based on the geometric configuration parameters of the standard cells to be processed, determine the MOS transistor positions of the standard cells to be processed, wherein the geometric configuration parameters characterize the position and morphological features of the standard cells to be processed in the integrated circuit layout; and an acquiring unit, configured to, using the MOS transistor positions as indexers, acquire graphic feature information of each MOS transistor in the standard cells to be processed, wherein the graphic feature information includes the graphic type and spatial position of each graphic in the MOS transistor. The spatial location includes the graphic's layer level and corner coordinates; a layout unit is used to traverse each graphic within the target area. If each graphic's graphic type is a solid graphic and its layer level is the first metal line layer, then the corner coordinates of each graphic are checked for missing values, and the edges of the graphic are checked for breakpoints. If the check passes, each graphic is identified as a target graphic; if the check fails, each graphic is marked as an abnormal graphic, and the location and type of the abnormal graphic are recorded in the design log. Based on the corner coordinates of the target graphic, metal line graphics that meet the set requirements are laid out on at least one metal line layer above the standard unit to be processed.

11. A computer program product, characterized in that, The computer program product includes computer instructions stored in a computer-readable storage medium and adapted to be read and executed by a processor to cause a computer device having the processor to perform the method as described in any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores at least one piece of program code, which is loaded and executed by a processor to perform the operations performed by the method as described in any one of claims 1 to 9.

13. An electronic device, characterized in that, The electronic device includes one or more processors and one or more memories, wherein at least one piece of program code is stored in the one or more memories, and the at least one piece of program code is loaded and executed by the one or more processors to implement the method as described in any one of claims 1 to 9.

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