A wide frequency three-phase phase-locked loop method

Abstract

The application discloses a wide-frequency three-phase phase-locked loop method, relates to the technical field of three-phase phase-locked loops, and comprises an alternating-current signal acquisition and coordinate transformation unit, a double-reduction-order generalized integrator, a frequency-locked loop frequency estimation unit, a double-second-order generalized integrator, a parallel delay signal cancellation filter module and a phase-locked loop phase estimation unit. Three-phase power grid voltage signals are input into the alternating-current signal acquisition and coordinate transformation unit to obtain two-phase voltages in a stationary coordinate system. The double-reduction-order generalized integrator and the frequency-locked loop frequency estimation unit output a three-phase power grid frequency estimation value and perform feedforward. The double-second-order generalized integrator outputs three-phase power grid positive sequence components and inputs the three-phase power grid positive sequence components into the parallel delay signal cancellation filter module to filter high-order harmonic components, and then inputs the three-phase power grid positive sequence components into the phase-locked loop phase estimation unit to output a three-phase power grid phase estimation value. The application can effectively solve the problem that a traditional phase-locked loop is difficult to quickly and accurately phase-lock when facing a wide-range fluctuation of a ship micro-grid frequency, and improves phase-locking precision and dynamic performance.

Description

Technical Field

[0001] This invention relates to the field of three-phase phase-locked loop technology, and more specifically to a wide-frequency three-phase phase-locked loop method. Background Technology

[0002] With increasingly stringent requirements for energy conservation, emission reduction, and energy efficiency improvement, new energy power generation systems and power electronic devices are widely used in the marine sector. The increasing number and capacity of these devices have led to more severe harmonic pollution in marine power grids. Active power filters can effectively control harmonic pollution, eliminate harmonic components, and improve the power supply quality and stability of marine power grids, thus gaining widespread use in ships. However, the power quality requirements of marine microgrids differ significantly from those of large land-based power grids, and their operating characteristics also differ considerably. Due to the smaller capacity of marine power systems, when the load is general AC equipment, the steady-state frequency variation of the marine power grid should not exceed ±5% of the rated frequency, and the instantaneous frequency variation should not exceed ±10% of the rated frequency. Therefore, when the rated frequency of the power grid is 50Hz, the frequency deviation of the marine power grid reaches ±2.5Hz when AC equipment is operating in steady state, while the transient frequency fluctuation can reach ±5Hz. For traditional active power filter designs, the fundamental frequency of the power grid needs to be stabilized at 50±1Hz when the phase-locked loop (PLL) is operating. Therefore, when directly applied to marine power grids, the harmonic control effect is greatly affected.

[0003] Conventional three-phase phase-locked loops (PLLs) include Synchronous Reference Frame PLLs (SRF-PLLs) and Double Second Order Generalized Integrator PLLs (DSOGI-PLLs). Both algorithms can quickly and accurately lock phases under unbalanced three-phase power grid conditions. However, due to the presence of phase feedback coupling stages—that is, the angular frequencies and phases required for the preceding coordinate transformation and orthogonal filtering stages need to be fed back from the subsequent stages—the dynamic performance of the PLLs is reduced, making them unable to cope with large-scale fluctuations in the power grid's fundamental frequency. Therefore, it is necessary to design a wide-frequency three-phase PLL capable of handling large-scale frequency fluctuations in the shipboard power grid to solve the aforementioned technical problems.

[0004] The differences from existing technologies are as follows:

[0005] Technical comparison with Chinese patent CN110165706B "An adaptive three-phase grid-connected converter phase-locked loop and its phase-locked control method";

[0006] 1. The technical positioning of patent CN110165706B is to solve the problem of dynamic detection of grid voltage phase under complex operating conditions, especially when the grid is experiencing asymmetrical faults and harmonic components. Its core is to filter the dq-axis voltage components using a series delay signal cancellation module, a second-order generalized integrator, and a series PI regulator. The difference between the output components of the second-order generalized integrator is then used to obtain the q-axis difference, which is then used to achieve closed-loop phase angle output and feedback via the PI regulator. In contrast, the application scenario of this invention focuses on solving the problem of traditional phase-locked loops struggling to quickly and accurately lock phase under wide-range frequency fluctuations in marine microgrids, improving phase-locking accuracy and dynamic performance over a wide frequency range. The application scenarios of the two are significantly different.

[0007] 2. The core of patent CN110165706B is a "series delay signal cancellation module and a second-order generalized integrator." Its implementation involves using the series delay signal cancellation module to eliminate higher harmonics in the dq-axis voltage component, while simultaneously utilizing the orthogonal signal output characteristics of the second-order generalized integrator to eliminate the influence of negative-sequence components. The core of this invention is a "frequency-locked loop frequency feedforward." Its implementation involves using a frequency-locked loop feedforward based on a double-decreasing-order generalized integrator to estimate the grid frequency, while simultaneously achieving phase and angular frequency cross-feedback coupling between the pre-parallel delay signal cancellation module and the subsequent phase-locked loop, significantly improving the dynamic performance and accuracy of phase-locked loops under wide-frequency operating conditions of the power grid. The core working principles of the two inventions are fundamentally different.

[0008] 3. The system architecture of patent CN110165706B adds a second-order generalized integrator to a traditional single-synchronous coordinate system phase-locked loop (PLL), utilizing its orthogonal signal output characteristics to eliminate the influence of negative-sequence components. Simultaneously, a series delay signal cancellation module is added to eliminate the influence of harmonics on phase and frequency detection. The system architecture of this invention, on the other hand, adds a frequency-locked loop feedforward to a conventional three-phase synchronous coordinate system PLL based on dual generalized second-order integrators. Compared to a single PLL, this achieves faster grid frequency estimation. Furthermore, a parallel delay signal cancellation module is added to eliminate the 5th, 7th, 11th, and 13th odd harmonics present in the three-phase AC grid and reduce filtering delay. The two system architectures have significant differences.

[0009] Technical comparison with Chinese patent CN120127662A "A three-phase grid-connected phase-locked loop two-stage filter and its filtering method";

[0010] 1. Patent CN120127662A addresses the problem that traditional phase-locked loop (PLL) filters, under non-ideal power grid conditions, cannot completely filter out harmonics and DC offset voltages due to insufficient filtering capability. Its core principle is to use a dual-hybrid-order generalized integrator as the first-stage filtering unit, while simultaneously introducing a Parker transform unit and a comb filter as the second-stage filtering unit, forming a dual-stage filter. In contrast, this invention focuses on solving the problem of traditional PLLs struggling to quickly and accurately lock onto phases when facing large-scale frequency fluctuations in marine microgrids. Its core principle is the introduction of an independent frequency-locked loop based on a dual-decreased-order generalized integrator, along with a pre-connected parallel delay signal cancellation module. The application scenarios of the two inventions differ significantly.

[0011] 2. The core of patent CN120127662A is a "dual hybrid-order generalized integrator," which is implemented by cascading a second-order generalized integrator and a first-order generalized integrator to form a hybrid-order generalized integrator filter (MGIF), enabling it to have DC offset voltage capability. A comb filter (CF) is used to filter out the fundamental positive-sequence voltage, which contains the main odd-order harmonic voltages and some even-order harmonic voltages. The core of this invention is a "reduced-order generalized integrator and frequency-locked loop feedforward," implemented by using a frequency-locked loop feedforward (DROGI-FLL) based on a dual reduced-order generalized integrator to estimate the grid frequency, improving the phase-locked dynamic performance under wide frequency conditions. Simultaneously, a pre-parallel delayed signal cancellation module (MDSC) is used to eliminate the main odd-order harmonics in the three-phase AC grid. The core working principles of the two are fundamentally different.

[0012] 3. The system architecture of patent CN120127662A is based on a conventional SRF-PLL three-phase phase-locked loop, introducing a pre-amplified mixed-order generalized integral filter and an in-loop comb filter to form a two-stage filter. Simultaneously, the three-phase grid phase angle output from the phase-locked loop is fed back to the aforementioned two-stage filter, resulting in front-to-back phase coupling that affects the dynamic performance of wide-frequency grid phase-locking. The system architecture of this invention, on the other hand, adds a frequency-locked loop feedforward to a conventional three-phase synchronous coordinate system phase-locked loop based on dual generalized second-order integrals. This removes the cross-feedback coupling link between the three-phase grid phase and angular frequency, and adds a pre-amplified parallel delay signal cancellation module in the αβ stationary coordinate system. This enhances the ability to suppress harmonic interference in phase-locked loops while focusing on improving wide-frequency phase-locking accuracy and dynamic performance. The two system architectures are significantly different.

[0013] Technical comparison with Chinese patent CN116155270A, "A method for a three-phase voltage phase-locked loop including an improved MSTOGI structure and a nonlinear PI regulation";

[0014] 1. Patent CN116155270A addresses the issue of DC components and high-order harmonics in grid voltage affecting the accuracy of phase-locked loops (PLLs). Its core technology involves introducing a second / third-order hybrid generalized integrator (MSTOGI) and a frequency compensation stage Gc(s), aiming to accurately extract the fundamental positive-sequence component of the three-phase voltage even when it is unbalanced and contains DC components, low-order harmonics, and high-order harmonics. In contrast, this invention focuses on solving the problem of traditional PLLs struggling to handle large-range frequency fluctuations in marine microgrids. Its core technology involves introducing an independent frequency-locked loop (DROGI-FLL) based on a double-decreasing-order generalized integrator, and a pre-connected parallel delay signal cancellation module (αβMDSC), enabling accurate extraction of the fundamental positive-sequence component and maintaining PLL accuracy even with large-range frequency shifts in the three-phase grid. The application scenarios of the two inventions differ significantly.

[0015] 2. The core of patent CN116155270A is a "hybrid generalized integrator and nonlinear PI controller." Its implementation utilizes the bandpass filter characteristics of the hybrid generalized integrator to suppress the positive-sequence DC offset, avoiding its impact on the phase-locked loop (PLL) tracking voltage. Simultaneously, a nonlinear PI controller is introduced to reduce PLL frequency and phase output overshoot during voltage dips. The core of this invention is "frequency-locked loop feedforward," implemented by using a frequency-locked loop feedforward based on a dual-decreasing-order generalized integrator for grid frequency estimation, accelerating phase locking and frequency tracking during three-phase grid frequency jumps. The core working principles of the two inventions are fundamentally different.

[0016] 3. The system architecture of patent CN116155270A is based on a conventional decoupled dual-synchronous reference coordinate system phase-locked loop (DDSRF-PLL), incorporating an improved second / third-order hybrid generalized integrator and a frequency compensation stage. It utilizes the bandpass filtering characteristics to suppress low-frequency DC components and high-frequency harmonic components such as the 5th and 7th harmonics. Simultaneously, a nonlinear PI regulator based on a hyperbolic threshold function is added to reduce PLL frequency overshoot and improve PLL stability and reliability. The system architecture of this invention, on the other hand, is based on a conventional dual-generalized second-order integrator three-phase synchronous coordinate system phase-locked loop with added frequency-locked loop feedforward and a parallel delay signal cancellation module. Compared to the second / third-order hybrid generalized integrator and nonlinear PI, this architecture is simpler and computationally less complex, thus ensuring excellent wideband dynamic performance of the overall PLL. The two system architectures are significantly different.

[0017] Compared to conventional three-phase phase-locked loops such as SRF-PLL and DSOGI-PLL, this invention utilizes a feedforward-based Double Reduced Order Generalized Integrator Frequency Locked Loop (DROGI-FLL) to extract the fundamental frequency of the power grid and provide it as a reference to the DSOGI operator of the phase-locked loop. This eliminates the cross-feedback coupling link between the phase and angular frequency of the three-phase power grid, accelerating the frequency adaptation speed of the phase-locked loop. At the same time, the Multiple Delay Signal Cancelation (MDSC) operator in the αβ coordinate system is used as a pre-filter of the phase-locked loop to further eliminate phase-locked interference caused by power grid harmonic components and shorten the delay time to improve the dynamic response performance of the phase-locked loop. Thus, it can better adapt to the frequency shift and transient fluctuations of the ship's power grid. Summary of the Invention

[0018] To address the shortcomings of the aforementioned technologies, the present invention aims to provide a wide-frequency three-phase phase-locked loop method to solve the problem that existing three-phase phase-locked loops are unable to cope with the wide-range frequency fluctuations of ship power grids.

[0019] To achieve the above objectives, the technical solution of the present invention is as follows:

[0020] A wide-frequency three-phase phase-locked loop method includes the following steps:

[0021] S1. Three-phase power grid voltage signal input AC signal acquisition and coordinate transformation unit to obtain two-phase voltage in stationary coordinate system;

[0022] S2. The dual-order reduced generalized integrator and frequency-locked loop frequency estimation unit output the estimated three-phase power grid frequency and perform feedforward;

[0023] S3. The dual second-order generalized integrator outputs the positive sequence component of the three-phase power grid and inputs it to the parallel delay signal cancellation filter module to filter out high-order harmonic components. Then, it is input to the phase-locked loop phase estimation unit to output the phase estimate value of the three-phase power grid.

[0024] Furthermore, in step S1, the AC signal acquisition and coordinate transformation unit obtains the three-phase AC grid voltage signal through an AC sampling circuit. Then, the two-phase voltages in the αβ stationary coordinate system are obtained through the coordinate transformation. ;

[0025] The formula for calculating the coordinate transformation is as follows:

[0026] .

[0027] Furthermore, in step S2, the double-decreasing generalized integrator converts the two-phase voltages in the αβ stationary coordinate system... The positive and negative order components are separated by a double-order generalized integrator and its positive and negative order component network. ;

[0028] The transfer function of the positive-sequence component of the double-reduced generalized integrator is:

[0029] ;

[0030] In the formula: D(s) is the transfer function of the double-reduced-order generalized integrator bandpass filter; Q(s) is the transfer function of the double-reduced-order generalized integrator lowpass filter; ω' is the frequency value of the frequency-locked loop feedforward grid; k is the gain coefficient; s is the Laplace complex frequency domain operator; j is the imaginary unit; u α and u β These are the axis components of the three-phase AC grid voltage in the αβ stationary coordinate system; u + α and u + β These are the positive sequence components of the three-phase AC grid voltage in the αβ stationary coordinate system after filtering, u - α and u - β These are the negative sequence axis components of the three-phase AC grid voltage in the αβ stationary coordinate system after filtering.

[0031] Furthermore, in step S2, the frequency estimation unit of the frequency-locked loop will... The synchronization error signal is obtained by subtracting the sum of the positive and negative sequence components separated by the corresponding double-decreasing generalized integrator and its positive and negative sequence component network. Then and , and The product of these two signals is used as the frequency error signal. The frequency error signal is obtained by subtracting the two. After passing through a negative gain coefficient The integrator, along with the gain normalization coefficient, forms a closed-loop circuit to obtain the estimated three-phase AC grid angular frequency. The signal is fed back to the dual-decreasing generalized integrator and then fed into the dual second-order generalized integrator and the parallel delay signal cancellation filter module.

[0032] Furthermore, in step S3, the dual second-order generalized integrator will... Orthogonal separation of positive-sequence components and filtering of higher harmonics are performed, and the results are fed into a parallel delayed signal cancellation filter module and a phase-locked loop phase estimation unit. The three-phase AC grid phase is obtained through closed-loop calculation. .

[0033] Furthermore, in step S3, the parallel delay signal cancellation filtering module filters out the positive sequence components of the three-phase power grid containing mid-to-high order harmonics. A specific order of delayed signal is generated by a delay stage and added to the original positive sequence component to obtain the filtered signal. After the delay error is compensated by a rotation factor, the two signals are added together and fed into an averaging stage to obtain the three-phase power grid positive sequence component after high-order harmonics are filtered out. .

[0034] Furthermore, the transfer function of the parallel delay signal cancellation filter module in step S3 is:

[0035] ,

[0036] In the formula: n is the delay cancellation factor specifying the integer harmonic order; T is the period of the fundamental component of the input AC signal; l is an integer; s is the Laplace complex frequency domain operator; j is the imaginary unit; l For summation, the value of l in each term of the expression starts from 0 and goes up to n-1. l It is an integer; Input the positive-order component complex vector to the filtering module; The filter module outputs a positive-order component complex vector.

[0037] In this invention, the T value of the parallel delay signal cancellation filter module is determined by the estimated three-phase AC power grid angular frequency. The decision is as follows: Since the three-phase AC power grid is mainly dominated by odd harmonics of the 5th, 7th, 11th and 13th orders, and higher-order harmonics have been filtered out by the double-reduced-order generalized integrator and its positive and negative sequence component network, n is 15 in this invention.

[0038] The technical solution of this invention has the following advantages:

[0039] (1) The wide-frequency three-phase phase-locked loop method and system provided by the present invention, compared with the conventional three-phase phase-locked loop, innovatively adds a three-phase phase-locked loop feedforward and parallel delay signal cancellation filtering module based on a dual-decreasing generalized integrator, removes the three-phase power grid phase and angular frequency cross-feedback coupling link, and further enhances the ability of harmonics to suppress phase-locked interference, thereby improving phase-locked accuracy and dynamic performance.

[0040] (2) The wide-frequency three-phase phase-locked loop method and system provided by the present invention can effectively solve the problem that conventional three-phase phase-locked loops are difficult to lock phase quickly and accurately when the frequency of ship microgrids fluctuates over a wide range, while avoiding the problems of large phase-locking error and slow phase-locking speed. Attached Figure Description

[0041] Figure 1 This is a control block diagram of a wide-frequency three-phase phase-locked loop provided in an embodiment of the present invention;

[0042] Figure 2 A control block diagram of a three-phase frequency-locked loop based on a dual generalized reduced-order integrator and its positive and negative sequence decoupling network is provided for an embodiment of the present invention.

[0043] Figure 3 A structural block diagram of a parallel delay signal cancellation filtering module provided in an embodiment of the present invention;

[0044] Figure 4 The phase-locked loop test results of the wide-frequency three-phase phase-locked loop and the conventional three-phase phase-locked loop provided in the embodiments of the present invention are shown. Detailed Implementation

[0045] The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0046] A wide-frequency three-phase phase-locked loop (PLL) method includes an AC signal acquisition and coordinate transformation unit, a dual-order reduced-order generalized integrator, a frequency estimation unit for the PLL, dual second-order generalized integrators, a parallel delay signal cancellation filtering module, and a PLL phase estimation unit. The control block diagram of the wide-frequency three-phase PLL is shown below. Figure 1 As shown, the control block diagram of the three-phase frequency-locked loop based on the dual generalized reduced-order integrator and its positive and negative sequence decoupling network is as follows: Figure 2 As shown, the block diagram of the parallel delay signal cancellation filter module is as follows: Figure 3 As shown.

[0047] Furthermore, the AC signal acquisition and coordinate transformation unit obtains the three-phase AC grid voltage signal through an AC sampling circuit. Then, the two-phase voltages in the αβ stationary coordinate system are obtained through the coordinate transformation. ;

[0048] The formula for calculating the coordinate transformation is as follows:

[0049] .

[0050] Furthermore, the dual-order reduced generalized integrator converts the two-phase voltages in the αβ stationary coordinate system... The positive and negative order components are separated by a double-order generalized integrator and its positive and negative order component network. ;

[0051] The transfer function of the positive-sequence component of the double-reduced generalized integrator is:

[0052] ,

[0053] In the formula: D(s) is the transfer function of the double-reduced-order generalized integrator bandpass filter; Q(s) is the transfer function of the double-reduced-order generalized integrator lowpass filter; ω' is the frequency value of the frequency-locked loop feedforward grid; k is the gain coefficient; s is the Laplace complex frequency domain operator; j is the imaginary unit; u α and u β These are the axis components of the three-phase AC grid voltage in the αβ stationary coordinate system; u + α and u + β These are the positive sequence axis components of the three-phase AC grid voltage in the αβ stationary coordinate system after filtering.

[0054] Furthermore, the frequency estimation unit of the frequency-locked loop will The synchronization error signal is obtained by subtracting the sum of the positive and negative sequence components separated by the corresponding double-decreasing generalized integrator and its positive and negative sequence component network. Then and , and The product of these two signals is used as the frequency error signal. The frequency error signal is obtained by subtracting the two. After passing through a negative gain coefficient The integrator, along with the gain normalization coefficient, forms a closed-loop circuit to obtain the estimated three-phase AC grid angular frequency. The signal is fed back to the dual-decreasing generalized integrator and then fed into the dual second-order generalized integrator and the parallel delay signal cancellation filter module.

[0055] Furthermore, the dual second-order generalized integrator will Orthogonal separation of positive-sequence components and filtering of higher harmonics are performed, and the results are fed into a parallel delayed signal cancellation filter module and a phase-locked loop phase estimation unit. The three-phase AC grid phase is obtained through closed-loop calculation. .

[0056] Furthermore, the parallel delay signal cancellation filtering module filters out the positive sequence components of the three-phase power grid containing mid-to-high order harmonics. A specific order of delayed signal is generated by a delay stage and added to the original positive sequence component to obtain the filtered signal. After the delay error is compensated by a rotation factor, the two signals are added together and fed into an averaging stage to obtain the three-phase power grid positive sequence component after high-order harmonics are filtered out. .

[0057] Furthermore, the transfer function of the parallel delay signal cancellation filter module is:

[0058] ,

[0059] In the formula: n is the delay cancellation factor specifying the integer harmonic order; T is the period of the fundamental component of the input AC signal; l is an integer; s is the Laplace complex frequency domain operator; j is the imaginary unit; Input the positive-order component complex vector to the filtering module; The filter module outputs a positive-order component complex vector.

[0060] In this invention, the T value of the parallel delay signal cancellation filter module is determined by the estimated three-phase AC power grid angular frequency. The decision is as follows: Since the three-phase AC power grid is mainly dominated by odd harmonics of the 5th, 7th, 11th and 13th orders, and higher-order harmonics have been filtered out by the double-reduced-order generalized integrator and its positive and negative sequence component network, n is 15 in this invention.

[0061] As a specific embodiment of the present invention:

[0062] In an embodiment of the present invention, in order to compare the performance of the wide-frequency three-phase phase-locked loop (PLL) proposed in this invention with that of a conventional three-phase PLL under wide-range fluctuations and harmonic voltage interference in a three-phase marine microgrid, models of the wide-frequency three-phase PLL and a three-phase PLL based on dual generalized second-order integrals were built in MATLAB / Simulink. The two three-phase PLLs were tested under a three-phase simulated power grid containing 5th, 7th, 11th, and 13th harmonic interferences and three fundamental frequencies of 45Hz, 50Hz, and 55Hz.

[0063] Figure 4 The test results for two types of three-phase phase-locked loops (PLLs) are shown. The solid black line represents the wide-frequency three-phase PLL proposed in this invention, while the dashed black line represents the conventional three-phase PLL compared to this invention. The PLL test results show that when the frequency changes instantaneously from 50Hz to 45Hz and from 45Hz to 55Hz, the wide-frequency three-phase PLL proposed in this invention exhibits less settling time and overshoot, demonstrating better dynamic performance. Furthermore, once the PLL output frequency stabilizes, the wide-frequency three-phase PLL proposed in this invention exhibits less steady-state error, demonstrating better PLL accuracy.

[0064] It should be noted that in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0065] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A wide-frequency three-phase phase-locked loop method, characterized in that, Includes the following steps: S1. Three-phase power grid voltage signal input AC signal acquisition and coordinate transformation unit to obtain two-phase voltage in stationary coordinate system; S2. The dual-order reduced generalized integrator and frequency-locked loop frequency estimation unit output the estimated three-phase power grid frequency and perform feedforward; S3. The dual second-order generalized integrator outputs the positive sequence component of the three-phase power grid and inputs it to the parallel delay signal cancellation filter module to filter out high-order harmonic components. Then, it is input to the phase-locked loop phase estimation unit to output the phase estimation value of the three-phase power grid. The T value of the parallel delay signal cancellation filter module is determined by the frequency estimation value of the three-phase power grid. The transfer function of the parallel delay signal cancellation filter module in step S3 is: ； In the formula: n is the delay cancellation factor specifying the integer harmonic order; T is the period of the fundamental component of the input AC signal; l is an integer; s is the Laplace complex frequency domain operator; j is the imaginary unit; l For summation, the value of l in each term of the expression starts from 0 and goes up to n-1. l It is an integer; Input the positive-order component complex vector to the filtering module; The filter module outputs a positive-order component complex vector.

2. The wide-frequency three-phase phase-locked loop method according to claim 1, characterized in that, In step S1, the AC signal acquisition and coordinate transformation unit obtains the three-phase AC grid voltage signal through an AC sampling circuit. Then, the two-phase voltages in the αβ stationary coordinate system are obtained through the coordinate transformation. ; The formula for calculating the coordinate transformation is as follows: 。 3. The wide-frequency three-phase phase-locked loop method according to claim 2, characterized in that, In step S2, the double-order reduced generalized integrator converts the two-phase voltages in the αβ stationary coordinate system. The positive and negative order components are separated by a double-order generalized integrator and its positive and negative order component network. ; The transfer function of the positive-sequence component of the double-reduced generalized integrator is: ； In the formula: D(s) is the transfer function of the double-reduced-order generalized integrator bandpass filter; Q(s) is the transfer function of the double-reduced-order generalized integrator lowpass filter; ω' is the frequency value of the frequency-locked loop feedforward grid; k is the gain coefficient; s is the Laplace complex frequency domain operator; j is the imaginary unit; u α and u β These are the axis components of the three-phase AC grid voltage in the αβ stationary coordinate system; u + α and u + β These are the positive sequence components of the three-phase AC grid voltage in the αβ stationary coordinate system after filtering, u - α and u - β These are the negative sequence axis components of the three-phase AC grid voltage in the αβ stationary coordinate system after filtering.

4. The wide-frequency three-phase phase-locked loop method according to claim 3, characterized in that, In step S2, the frequency estimation unit of the frequency-locked loop will The synchronization error signal is obtained by subtracting the sum of the positive and negative sequence components separated by the corresponding double-decreasing generalized integrator and its positive and negative sequence component network. Then and , and The product of these two signals is used as the frequency error signal. The frequency error signal is obtained by subtracting the two. After passing through a negative gain coefficient The integrator, along with the gain normalization coefficient, forms a closed-loop circuit to obtain the estimated three-phase AC grid angular frequency. The signal is fed back to the dual-decreasing generalized integrator and then fed into the dual second-order generalized integrator and the parallel delay signal cancellation filter module.

5. A wide-frequency three-phase phase-locked loop method according to claim 3 or 4, characterized in that, In step S3, the double second-order generalized integrator will... Orthogonal separation of positive-sequence components and filtering of higher harmonics are performed, and the results are fed into a parallel delayed signal cancellation filter module and a phase-locked loop phase estimation unit. The three-phase AC grid phase is obtained through closed-loop calculation. .

6. The wide-frequency three-phase phase-locked loop method according to claim 5, characterized in that, In step S3, the parallel delay signal cancellation filtering module will filter the positive sequence components of the three-phase power grid containing mid-to-high order harmonics. A specific order of delayed signal is generated by a delay stage and added to the original positive sequence component to obtain the filtered signal. After the delay error is compensated by a rotation factor, the two signals are added together and fed into an averaging stage to obtain the three-phase power grid positive sequence component after high-order harmonics are filtered out. .

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