Semiconductor structure, manufacturing method thereof and semiconductor device
By forming connected first and second trenches in the transition region of the DRAM, the word line end distortion problem is solved, improving the performance and reliability of the DRAM.
Patent Information
- Application Number
- CN202411022419.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-26
- Publication Date
- 2026-01-27
AI Technical Summary
As DRAM process nodes shrink, the manufacturing process of word lines becomes increasingly complex, and word line tip distortion has an adverse effect on DRAM performance.
A first trench is formed in the first isolation structure in the transition region. The first trench extends along a first direction and has a depth less than the depth of the isolation structure, and communicates with a second trench. The second trench extends from the storage region to the transition region. This design reduces the obstruction effect of etching gas and releases the stress at the end of the second trench.
The bending at the end of the second trench was improved, which enhanced the performance of the semiconductor structure, ensured the neatness and reliability of the word line trenches, and prevented short circuits.
Smart Images
Figure CN121419221A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure, a method for manufacturing the same, and a semiconductor device. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory widely used in multi-computer systems.
[0003] As semiconductor manufacturing processes continue to advance, the size of semiconductor memories is becoming smaller and smaller. In particular, as DRAM process nodes become smaller and smaller, the feature size of word lines continues to shrink, making the manufacturing process of word lines increasingly complex. This leads to word line tip distortion, which in turn negatively impacts DRAM performance. Summary of the Invention
[0004] According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising:
[0005] The substrate includes a storage region, a peripheral region, and a transition region located between the storage region and the peripheral region, wherein a first isolation structure is present in the transition region;
[0006] A first trench is located in the isolation structure and extends along a first direction; the depth of the first trench is less than the depth of the isolation structure.
[0007] In some embodiments, the first trench includes:
[0008] The first sidewall is located near the storage area;
[0009] The second sidewall is located near the outer perimeter area;
[0010] The width of the first sidewall is greater than the width of the second sidewall.
[0011] In some embodiments, the semiconductor structure further includes:
[0012] The second trench extends along the second direction from the storage area to the transition area;
[0013] The first trench is connected to the second trench.
[0014] In some embodiments, the depth of the first trench is greater than the depth of the second trench.
[0015] In some embodiments, the semiconductor structure further includes:
[0016] A second isolation structure, wherein the second trench passes through the second isolation structure;
[0017] In the second direction, the width of the first trench is greater than the width of the second isolation structure.
[0018] In some embodiments, the depth of the first trench is less than the depth of the second isolation structure.
[0019] In some embodiments, the top surface of the first sidewall is lower than the top surface of the second sidewall, the top surface of the first sidewall is higher than the bottom surface of the second trench, and the top surface of the first sidewall is flush with the top surface of the storage area.
[0020] According to a second aspect of the present disclosure, a semiconductor device is provided, comprising:
[0021] The substrate includes a storage region, a peripheral region, and a transition region located between the storage region and the peripheral region, wherein a first isolation structure is present in the transition region;
[0022] A first trench is located in the first isolation structure and extends along a first direction; the depth of the first trench is less than the depth of the isolation structure.
[0023] The second trench extends along the second direction from the storage area to the transition area;
[0024] The word line conductive layer is located in the second trench;
[0025] The first trench is connected to the second trench.
[0026] In some embodiments, the semiconductor device further includes:
[0027] An insulating layer is essentially filled in the first trench;
[0028] The top surface of the insulating layer is higher than the top surface of the word line conductive layer.
[0029] In some embodiments, the semiconductor device further includes:
[0030] The word line contact layer is located in the first trench;
[0031] The word line contact layer is connected to the word line conductive layer.
[0032] In some embodiments, the width of the word line contact layer is greater than the width of the word line conductive layer in the direction parallel to the first direction.
[0033] In some embodiments, in a direction parallel to the first direction, the gap between adjacent word line contact layers is smaller than the width of adjacent word line conductive layers.
[0034] In some embodiments, the bottom surface of the word line contact layer is lower than the bottom surface of the word line conductive layer.
[0035] In some embodiments, the top surface of the word line contact layer is higher than the top surface of the word line conductive layer.
[0036] In some embodiments, the first trench includes:
[0037] The first sidewall is located near the storage area;
[0038] The second sidewall is located away from the storage area;
[0039] Wherein, in the direction parallel to the second direction, the width of the first sidewall is greater than the width of the second sidewall.
[0040] In some embodiments, the word line contact layer is located between the first sidewall and the second sidewall, with the top surface of the word line contact layer extending beyond the first sidewall and below the second sidewall.
[0041] According to a third aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising:
[0042] A substrate is provided, the substrate including a storage region, a peripheral region, and a transition region located between the storage region and the peripheral region, the transition region having a first isolation structure;
[0043] A first trench is formed in the first isolation structure, the depth of the first trench being less than the depth of the first isolation structure.
[0044] In some embodiments, it also includes:
[0045] The storage area and a portion of the first isolation structure are etched to form the second trench, which extends along a second direction from the storage area to the transition area;
[0046] The first trench is connected to the second trench, the first trench is substantially perpendicular to the second trench, and the depth of the second trench is less than the depth of the first trench.
[0047] In some embodiments, it also includes:
[0048] A word line conductive layer is formed in the second trench;
[0049] An insulating layer is formed in the first trench;
[0050] The top surface of the insulating layer is higher than the top surface of the word line conductive layer.
[0051] In some embodiments, it also includes:
[0052] A word line conductive layer is formed in the second trench;
[0053] A word line contact layer is formed in the first trench;
[0054] The word line conductive layer is connected to the word line contact layer;
[0055] In the first direction, the width of the word line contact layer is greater than the width of the word line conductive layer.
[0056] In summary, this disclosure provides a semiconductor structure, a method for manufacturing the same, and a semiconductor device. Because a first isolation structure exists in the transition region, a first trench is formed within this first isolation structure. The first trench extends along a first direction, and its depth is less than the depth of the first isolation structure. Therefore, when a second trench is formed on the substrate, the second trench extends from the storage region into the transition region. Consequently, the end of the second trench communicates with the first trench, thereby releasing the end stress of the second trench, improving end bending, and ultimately ensuring the performance of the semiconductor structure. Attached Figure Description
[0057] Figure 1 This is an electron microscope image of a trench in the related art, as illustrated in an exemplary embodiment;
[0058] Figure 2 This is a flowchart illustrating a method for manufacturing a semiconductor structure according to an exemplary embodiment;
[0059] Figure 3 This is a top view of a substrate according to an exemplary embodiment;
[0060] Figure 4 This is illustrated according to an exemplary embodiment. Figure 3 Cross-sectional view along the AA direction;
[0061] Figure 5 This is a schematic diagram of a patterned photoresist layer according to an exemplary embodiment;
[0062] Figure 6 This is another schematic diagram of a substrate according to an exemplary embodiment;
[0063] Figure 7A This is illustrated according to an exemplary embodiment. Figure 6 Cross-sectional view along the AA direction;
[0064] Figure 7B This is a schematic diagram of a first trench according to an exemplary embodiment;
[0065] Figure 8 This is another schematic diagram of a substrate according to an exemplary embodiment;
[0066] Figure 9 This is illustrated according to an exemplary embodiment. Figure 9 Cross-sectional view along the AA direction;
[0067] Figure 10 This is illustrated according to an exemplary embodiment. Figure 9 Cross-sectional view in the BB direction;
[0068] Figure 11 This is another schematic diagram of the first trench according to an exemplary embodiment;
[0069] Figure 12 This is another schematic diagram of a substrate according to an exemplary embodiment;
[0070] Figure 13 This is illustrated according to an exemplary embodiment. Figure 12 Cross-sectional view along the AA direction;
[0071] Figure 14 This is another schematic diagram of a substrate according to an exemplary embodiment;
[0072] Figure 15 This is illustrated according to an exemplary embodiment. Figure 14 Cross-sectional view along the AA direction;
[0073] Figure 16 This is another schematic diagram of a substrate according to an exemplary embodiment;
[0074] Figure 17 This is illustrated according to an exemplary embodiment. Figure 16 Cross-sectional view along the AA direction;
[0075] Figure 18 This is illustrated according to an exemplary embodiment. Figure 16 Another cross-sectional view along the AA direction;
[0076] Figure 19 This is a schematic diagram illustrating the formation of a protective layer according to an exemplary embodiment;
[0077] Figure 20 This is illustrated according to an exemplary embodiment. Figure 8 Electron micrograph. Detailed Implementation
[0078] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.
[0079] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.
[0080] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.
[0081] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0082] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.
[0083] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.
[0084] like Figure 1 As shown, Figure 1 The image shown is an electron microscope (EM) image of a trench in the related art. The image shows an EEM image of a trench formed in a substrate 100. The substrate 100 may include a storage region 101, a transition region 102, and a peripheral region 103. The trench on the substrate 100 extends from the storage region 101 into the transition region 102, i.e., the ends of the trench are located in the transition region 102. Figure 1 As can be seen, the trenches in storage region 101 are neat and straight. However, the trenches in transition region 102 are distorted, meaning that the ends of the trenches are deformed, which affects the performance of the device.
[0085] This study reveals that during trench formation, the etching gas gradually consumes the substrate, thus forming the trench. Near the trench ends, the unconsumed substrate acts as a barrier, causing the etching gas above the trench ends to become disturbed and concentrated. This results in different etching rates at the trench ends, leading to deformation at the trench ends. Furthermore, because the trench ends are closed, there is significant stress concentration at these ends, further exacerbating the deformation.
[0086] Therefore, as Figure 2 As shown in the embodiments of this disclosure, a method for manufacturing a semiconductor structure is proposed, which can improve the end deformation of the trench and enhance the performance of the semiconductor structure.
[0087] S1: A substrate is provided, the substrate including a memory region, a peripheral region and a transition region located between the memory region and the peripheral region, the transition region having a first isolation structure;
[0088] S2: A first trench is formed in the first isolation structure, the depth of the first trench being less than the depth of the first isolation structure.
[0089] like Figures 3-4 As shown, Figure 3 Shown as a top view of substrate 100, Figure 4 Displayed as Figure 3 A cross-sectional view along the AA direction. The substrate 100 may sequentially include a storage region 101, a transition region 102, and a peripheral region 103. The substrate 100 may be a single-layer structure or a multi-layer structure. For example, the substrate 100 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, the substrate 100 may be a layered substrate including materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. An active region 104 is present in the storage region 101. The storage region 101 may be used to form word line structures, bit line structures, and capacitor structures, etc. A peripheral circuit structure is formed in the peripheral region 103.
[0090] like Figure 4As shown, the transition region 102 can be used to separate the storage region 101 and the peripheral region 103, thereby forming a first isolation structure 105 in the transition region 102. Meanwhile, in order to form an active region 104 in the storage region 101, the storage region 101 has a second isolation structure 106 and a third isolation structure 107. In the AA direction, the width of the first isolation structure 105 is greater than the width of the second isolation structure 106, and the width of the second isolation structure 106 is greater than the width of the third isolation structure 107. In the vertical direction, the depth of the first isolation structure 105 is greater than the depth of the second isolation structure 106, and the depth of the second isolation structure 106 is greater than the depth of the third isolation structure 107. Because the first isolation structure 105 is wider and deeper, it effectively isolates the storage region 101 and the peripheral region 103. At the same time, because the first isolation structure 105 is wider, the end of the subsequently formed trench can be located in the first isolation structure 105, effectively preventing the end of the trench from extending into the peripheral region 103. In some embodiments, the first isolation structure 105, the second isolation structure 106, and the third isolation structure 107 can all be shallow trench isolation structures. The first isolation structure 105 can be filled with silicon oxide, the second isolation structure 106 can be filled with silicon nitride, and the third isolation structure 107 can be filled with silicon oxide.
[0091] like Figures 5-7A As shown, in step S2, a patterned photoresist layer 108 is first formed on the substrate 100. The patterned photoresist layer 108 covers the storage region 101 and the peripheral region 103. An opening 109 is present in the patterned photoresist layer 108, exposing the first isolation structure 105. Then, using the patterned photoresist layer 108 as a mask, etching gas etches the first isolation structure 105 through the opening 109, thereby forming a first trench 110 in the first isolation structure 105. Since the first isolation structure 105 extends along a first direction, the first trench 110 extends along the first direction as well. Simultaneously, because the first isolation structure 105 is not completely etched, the width of the first trench 110 is smaller than the width of the first isolation structure 105 in the second direction (AA direction), and the depth of the first trench 110 is smaller than the depth of the first isolation structure 105 in the vertical direction.
[0092] like Figures 6-7BAs shown, the first trench 110 may include a first sidewall 1101 and a second sidewall 1102. The first sidewall 1101 is close to the storage area 101, and the second sidewall 1102 is close to the peripheral area 103. In the second direction, the width of the first sidewall 1101 is greater than the width of the second sidewall 1102. That is, the first trench 110 is not located at the center of the first isolation structure 105, that is, in the second direction, the first trench 110 is closer to the peripheral area 103. At the same time, in the second direction, the opening width W1 of the first trench 110 is greater than the width W2 of the second isolation structure 106. If the opening width W1 of the first trench 110 is small, when word line trenches are formed in the storage area 101 and the transition area 102, the second sidewall 1102 may also block the etching gas, thereby causing the end of the word line trench to bend. This embodiment of the invention increases the opening width W1 of the first groove 110, thereby effectively reducing the influence of the second sidewall 1102 on the etching gas, and thus ensuring the neatness of the ends of the word line groove.
[0093] like Figure 8 As shown, Figure 8 The diagram shows a top view of the formation of the second trench 111. The second trench 111 can be formed on the substrate 100 after the first trench 110 is formed. The second trench 111 extends from the storage region 101 to the transition region 102, meaning the end of the second trench 111 is located in the transition region 102. Simultaneously, the end of the second trench 111 communicates with the first trench 110 as it extends into the first isolation structure 105. Figure 8 The image shows multiple second trenches 111, which are insulated from each other and all connected to the first trench 110. In a first direction, the length of the first trench 110 is greater than the length of each individual second trench 110 and also greater than the sum of the lengths of all the second trenches 110, thus ensuring that all the second trenches 111 are connected to the first trench 110. In a second direction, the second trenches 111 are substantially perpendicular to the first trench 110.
[0094] like Figure 9 As shown, Figure 9 Displayed as Figure 8 A cross-sectional view along the AA direction. To show the relationship between the first groove 110 and the second groove 111, in... Figure 9 The second groove 111 is shown in the image. Figure 9The location is shown in the dashed box. Etching gas etches the substrate of storage region 101, specifically the first sidewall 1101 of the first trench 110, thereby forming the second trench 111. Simultaneously, because the first sidewall 111 is etched, the first trench 110 and the second trench 111 become connected. In this embodiment, when the second trench 111 is formed, the first trench 110 has already been formed in the first isolation structure 105, and the second sidewall 1102 is far from the first sidewall 1101. Therefore, the first trench 110 can reduce its obstruction effect on the etching gas, thereby improving the neatness of the end of the second trench 111. Furthermore, since the first trench 110 and the second trench 111 are connected, i.e., the end of the second trench 111 is open, it facilitates stress release at the end of the second trench 111, further improving the neatness of the end of the second trench 111.
[0095] like Figure 9 As shown, in this embodiment, the bottom surface of the first groove 110 is lower than the bottom surface of the second groove 111, that is, in the vertical direction, the depth of the first groove 110 is greater than the depth of the second groove 110. This can prevent the bottom surface of the first groove 110 from blocking the etching gas, thereby ensuring the neatness of the second groove 110.
[0096] like Figure 10 As shown, Figure 10 Displayed as Figure 8 A cross-sectional view in the BB direction. In the first direction, the second trenches 111 are spaced apart from each other. These second trenches 111 are separated by a third isolation structure 107. The second trenches 111 pass through the second isolation structure 106 and the third isolation structure 107. In the vertical direction, the depth of the second trenches 111 is less than the depth of the second isolation structure 106, and the depth of the second trenches 111 is less than the depth of the third isolation structure 106, thereby preventing the second trenches 111 from extending into the active area and preventing short circuits. In some embodiments, the second trenches 111 may be word line trenches.
[0097] like Figure 11 As shown, when the second trench 111 is formed, part of the first sidewall 1101 is etched, thereby reducing the height of the first sidewall 1101. That is, in the vertical direction, the top surface of the first sidewall 1101 is lower than the top surface of the second sidewall 1102, the top surface of the first sidewall 1101 is higher than the bottom surface of the second trench 111, the top surface of the first sidewall 1101 is flush with the top surface of the storage area 101, and the top surface of the second sidewall 1102 is also flush with the top surface of the peripheral area 103.
[0098] like Figure 12 As shown, Figure 12This is a top view showing the formation of the word line conductive layer 114. After forming the second trench 111, a word line conductive layer 112 can be formed in the second trench 111, followed by the formation of a second conductive layer 113 on the word line conductive layer 112, and a protective layer 114 on the second conductive layer 113. The word line conductive layer 112 substantially fills the second trench 111 and the first trench 110. After forming the protective layer 114, the top surface of the protective layer 114 is flush with the top surface of the peripheral region 103.
[0099] like Figure 13 As shown, Figure 13 Displayed as Figure 12 Cross-sectional view along the AA direction. From Figure 13 As can be seen, the word line conductive layer 112 extends from the storage region 101 into the transition region 102. The word line conductive layer 112 covers the first sidewall 1101, and the top surface of the word line conductive layer 112 is lower than the top surface of the second sidewall 1102. The second conductive layer 113 substantially covers the word line conductive layer 112, and the protective layer 114 substantially covers the second conductive layer 113. In the vertical direction, the thickness of the second conductive layer 113 is less than the thickness of the word line conductive layer 112. The second conductive layer 113 and the word line conductive layer 112 are made of different materials and have different work functions. The material of the word line conductive layer 112 may include, but is not limited to, As (arsenic) or B (boron) doped silicon, P (phosphorus) or As doped germanium, W (tungsten), Ti (titanium), TiN (titanium nitride), or Au (gold). The material of the second conductive layer 113 may include, but is not limited to, polycrystalline silicon. In this embodiment, the thickness of the protective layer 114 is greater than the thickness of the second conductive layer 113, and the top surface of the protective layer 114 is flush with the top surface of the peripheral region 103. The protective layer 114 can be used to protect the second conductive layer 113. The material of the protective layer 114 may include, but is not limited to, silicon oxide, silicon nitride, or silicon oxynitride.
[0100] like Figures 14-15 As shown, Figure 14 The diagram shows a top view of the formation of insulating layer 115. Figure 15 Displayed as Figure 14 In the cross-sectional view along the AA direction, to show the structure of the insulating layer 115, in Figure 15The insulating layer 115 is indicated by a dashed box. In some embodiments, after forming the protective layer 114, the protective layer 114, the second conductive layer 113, and the word line conductive layer 112 located in the first trench 110 can be etched, i.e., the protective layer 114, the second conductive layer 113, and the word line conductive layer 112 located in the second trench 111 can be retained. After removing the protective layer 114, the second conductive layer 113, and the word line conductive layer 112 from the first trench 110, the insulating layer 115 can be filled into the first trench 110. The top surface of the insulating layer 115 can be flush with the top surface of the peripheral region 103. Since the first trench 110 and the second trench 111 are connected, the word line conductive layers 112 in the first trench 110 and the second trench 111 are also connected. By removing the word line conductive layer 112 in the first trench 110 and retaining the word line conductive layer 112 in the second trench 111, it is ensured that the word line conductive layer 112 is located only in the second trench 111. Since the second trench 112 is isolated, it can be ensured that the word line conductive layer 112 located in the second trench 111 is also isolated. Since there is an insulating layer 115 in the first trench 110, and the top surface of the insulating layer 115 is higher than the top surface of the word line conductive layers 112, it is possible to prevent these word line conductive layers 112 from connecting. In this embodiment, the word line conductive layer 112, the second protective layer 113, and the protective layer 114 can be defined as a word line structure.
[0101] like Figure 16 As shown, Figure 16 The diagram shows a top view of the formation of the word line contact layer 1122. In some embodiments, after forming the word line conductive layer 112, the word line conductive layer 112 located in the first trench 110 is etched to form the word line contact layer 116. Simultaneously, the word line conductive layer 112 in the second trench 111 is retained. Figure 16 As can be seen, this embodiment does not completely etch away the word line conductive layer 112 in the first trench 110. In the first direction, the second trenches 112 are separated by a third isolation structure 107. In this embodiment, a portion of the word line conductive layer 112 located in the first trench 110 corresponding to the third isolation structure 107 is etched, thereby dividing the word line conductive layer 112 into multiple word line contact layers 116. Then, insulating material is filled in the gaps between the word line contact layers 116 to isolate the word line contact layers 116. The word line contact layers 116 and the word line conductive layer 112 are connected. In this embodiment, the word line contact layers 116 and the word line conductive layer 112 can be defined as word line body layers 117. Since these word line contact layers 116 are separated from each other and are insulated, and the word line conductive layers 112 are separated from each other and are insulated, these word line body layers 117 are mutually insulated and independent.
[0102] like Figure 16As shown, in the first direction, the width of the word line conductive layer 112 etched in the first trench 110 is smaller than the width of the third isolation structure 107, thereby the width of the word line contact layer 116 is greater than the width of the word line conductive layer 112. In the first direction, the gap between the word line contact layers 116 is smaller than the gap between the word line conductive layers 112. In this embodiment, the gap between the word line conductive layers 112 can be 5-7 nm larger than the gap between the word line contact layers 116. If the gap between the word line contact layers 116 is too small, it is not conducive to filling the word line contact layers 116 with insulating material.
[0103] like Figure 17 As shown, Figure 17 Displayed as Figure 16 The cross-sectional view in the AA direction is Figure 17 In the middle, the word line conductive layer 112 is connected to the word line contact layer 116, and the top surface of the word line conductive layer 112 is flush with the top surface of the word line contact layer 116. Of course, a second conductive layer 113 and a protective layer 114 can also be formed on the word line body layer 117 to form a word line structure.
[0104] like Figure 15 and Figure 17 As shown, in Figure 15 In the middle, the first trench 110 is filled with the insulating layer 115. Figure 17 In the first trench 110, a word line contact layer 116 is present, which is connected to the word line conductive layer 112. After forming the word line structure, interconnect pillars also need to be formed, which are connected to the word line structure to provide signals for the word line structure. This disclosure embodiment finds that when forming the interconnect pillars in the transition region 102, the following method is used... Figure 15 In the structure described, if the position of the interconnect pillar shifts, it will shift into the memory area 101. Simultaneously, because the etching gas will etch away part of the word line conductive layer 112, the interconnect pillar may connect to the active area in the memory area 101, thus forming a short circuit. However, using... Figure 17 When the interconnect pillars are formed in the structure, they can be formed on the word line contact layer 116. The word line contact layer 116 is far from the memory region 101, so the interconnect pillars are less likely to shift towards the memory region 101. Simultaneously, the depth of the word line contact layer 116 is greater than the depth of the word line conductive layer 112, and the bottom of the word line contact layer 116 is an insulating material. Therefore, even if the word line contact layer 116 is etched, it will not contact the active region, thereby preventing short circuits between the interconnect pillars and the active region. Furthermore, in the first direction, the width of the word line contact layer 116 is greater than the width of the word line conductive layer 112, thus increasing the offset range of the interconnect pillars and the contact area with the interconnect pillars, reducing contact resistance.
[0105] like Figures 18-19 As shown, Figure 18 Displayed as Figure 16Another cross-sectional view along the AA direction. Figure 18 In this embodiment, the word line conductive layer 112 is connected to the word line contact layer 116, and the top surface of the word line conductive layer 112 is lower than the top surface of the word line contact layer 116. A second conductive layer 113 is also present on the word line conductive layer 112, and the top surface of the second conductive layer 113 is flush with the top surface of the word line contact layer 116. A protective layer 114 is also present on the second conductive layer 113, and the protective layer 114 also covers the word line contact layer 116, so that the top surface of the protective layer 114 is flush with the top surface of the word line contact layer 116. In this embodiment, the word line conductive layer 112 and the word line contact layer 116 can be defined as the word line body layer 117. The word line body layer 117, the second conductive layer 113, and the protective layer 114 can be defined as the word line structure.
[0106] like Figures 17-18 As shown, in Figure 17 In this configuration, the top surface of the word line conductive layer 112 is flush with the top surface of the word line contact layer 116. When interconnect pillars are formed on the word line contact layer 116, the interconnect pillars are relatively deep, requiring a longer etching time. Figure 18 In this case, the top surface of the word line conductive layer 112 is lower than the top surface of the word line contact layer 116, which can reduce the depth of the interconnect pillars, reduce the etching time, reduce the impact on the sidewalls of the interconnect holes, and improve the short circuit between interconnect pillars.
[0107] like Figure 20 As shown, Figure 20 Displayed as Figure 8 Electron micrographs. The rectangular dashed box shows the first groove 110, and the circular dashed box shows the end of the second groove 111. Relative to... Figure 1 Let's take a look. Figure 20 The end of the second trench 111 is connected to the first trench 110, and the end of the second trench 111 is neat and straight. Therefore, the manufacturing method of this embodiment can effectively improve the end bending of the second trench 111 and improve the performance of the semiconductor structure.
[0108] like Figures 8-9As shown, this disclosure provides a semiconductor structure that may include a substrate 100. The substrate 100 may include a memory region 101, a transition region 102, and a peripheral region 103. A first isolation structure 105 is provided in the peripheral region 103, and a first trench 110 is provided in the first isolation structure 105. The first trench 110 extends along a first direction, and the depth of the first trench 110 is less than the depth of the first isolation structure 105. The first trench 110 may include a first sidewall 1101 and a second sidewall 1102. The first sidewall 1101 is adjacent to the memory region 101, and the second sidewall 1102 is adjacent to the peripheral region 103. The top surface of the first sidewall 1101 is lower than the top surface of the second sidewall 1102. The top surface of the first sidewall 1101 is higher than the bottom surface of the second trench, and the top surface of the second sidewall 1102 is flush with the top surface of the memory region. In the second direction, the width of the first sidewall 1101 is greater than the width of the second sidewall 1102, thereby increasing the distance between the second sidewall 1102 and the storage region 101 and reducing the obstruction effect of the second sidewall 1102 on the etching gas. Before forming the second trench 111, the first trench 110 is first formed in the first isolation structure 105. Therefore, when forming the second trench 111, the obstruction effect of the second sidewall 1102 on the etching gas can be reduced, and the concentration of etching gas at the end of the second trench 111 can be reduced, thereby ensuring the neatness of the end of the second trench 111. At the same time, since the end of the second trench 111 is connected to the first trench 110, the end stress of the second trench 111 can be released, reducing the distortion of the second trench 111. The substrate 100 has a second trench 111 that extends along the second direction from the storage region 101 to the transition region 102, thereby communicating with the first trench 110. The first groove 110 is basically perpendicular to the second groove 111.
[0109] like Figures 8-11 As shown, in the vertical direction, the depth of the first trench 110 is greater than the depth of the second trench 111, thereby preventing the end of the second trench 111 from being blocked by the bottom surface of the first trench 110, thus further improving the neatness of the end of the second trench 111. There is also a second isolation structure 106 in the storage area 101, through which the second trench 111 passes. The width W2 of the second isolation structure 106 is smaller than the opening width W1 of the first trench 110, thereby reducing the obstruction effect of the second sidewall 1102 on the etching gas and improving the straightness of the end of the second trench 111. In the vertical direction, the depth of the first trench 110 is less than the depth of the second isolation structure 106, and the first trench 110 is at a certain distance from the active area below, preventing short circuits.
[0110] like Figure 15As shown, this disclosure provides a semiconductor device including a substrate 100, which may include a storage region 101, a transition region 102, and a peripheral region 103. A first isolation structure 105 is located in the transition region 102. A first trench 110 is located in the first isolation structure 105, and a second trench 111 extends along a second direction from the storage region 101 into the transition region 102 to communicate with the first trench 110. A word line conductive layer 112 is located in the second trench 111. An insulating layer 115 is filled in the first trench 110, with the top surface of the insulating layer 115 higher than the top surface of the word line conductive layer 112. The ends of the second trench 111 are neat.
[0111] like Figures 16-18 As shown, this disclosure provides another semiconductor device, which is related to... Figure 15 The difference is that, Figures 16-18 In the first trench 110, there is a word line contact layer 116, which is connected to the word line conductive layer 112. In the direction parallel to the first direction, the width of the word line contact layer 116 is greater than the width of the word line conductive layer 112. In the direction parallel to the first direction, the width of adjacent word line contact layers 116 is less than the width of adjacent word line conductive layers 112. Figure 17 In this configuration, the top surface of the word line conductive layer 112 is flush with the top surface of the word line contact layer 116, while the bottom surface of the word line conductive layer 112 is higher than the bottom surface of the word line contact layer 116. Figure 18 In this configuration, the top surface of the word line contact layer 116 is higher than the top surface of the word line conductive layer 112. The word line contact layer 116 is located between the first sidewall 1101 and the second sidewall 1102, with its top surface extending beyond the first sidewall 1101 and lower than the second sidewall 1102. The function of the word line contact layer 116 can be referred to the above description.
[0112] The aforementioned semiconductor devices can be used in electronic devices. These electronic devices may include one or more of the following: for example, smartphones, tablet PCs, mobile phones, video phones, e-book readers, desktop PCs, laptop PCs, netbooks, workstations, servers, personal digital assistants (PDAs), portable multimedia players (PMPs), MPEG-1 audio layer 3 (MP3) players, mobile medical devices, cameras, home appliances, medical devices, Internet of Things (IoT) devices, and wearable devices. Wearable devices can be accessory-type, fabric or clothing-type, body-attached type, or implantable circuit type. Accessory-type wearable devices can be, for example, watches, rings, bracelets, anklets, necklaces, glasses, contact lenses, or head-mounted devices (HMDs).
[0113] In summary, this disclosure provides a semiconductor structure, a method for manufacturing the same, and a semiconductor device. This disclosure first forms a first trench in a first isolation structure within a transition region, and then forms a second trench. This reduces the obstruction of the etching gas by the first isolation structure, resulting in relatively uniform etching gas near the end of the second trench. This improves the uniformity of the end of the second trench and mitigates end distortion problems.
[0114] Secondly, since the second trench is connected to the first trench, the end stress of the second trench can be released, the end bending problem of the second trench can be improved, and the performance of the semiconductor structure can be enhanced.
[0115] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A semiconductor structure, characterized in that, include: The substrate includes a storage region, a peripheral region, and a transition region located between the storage region and the peripheral region, wherein a first isolation structure is present in the transition region; A first trench is located in the isolation structure and extends along a first direction; The depth of the first trench is less than the depth of the isolation structure.
2. The semiconductor structure according to claim 1, characterized in that, The first trench includes: The first sidewall is located near the storage area; The second sidewall is located near the outer perimeter area; The width of the first sidewall is greater than the width of the second sidewall.
3. The semiconductor structure according to claim 1 or 2, characterized in that, Also includes: The second trench extends along the second direction from the storage area to the transition area; The first trench is connected to the second trench.
4. The semiconductor structure according to claim 3, characterized in that, The depth of the first trench is greater than the depth of the second trench.
5. The semiconductor structure according to claim 3, characterized in that, Also includes: A second isolation structure, wherein the second trench passes through the second isolation structure; In the second direction, the width of the first trench is greater than the width of the second isolation structure.
6. The semiconductor structure according to claim 5, characterized in that, The depth of the first trench is less than the depth of the second isolation structure.
7. The semiconductor structure according to claim 2, characterized in that, The top surface of the first sidewall is lower than the top surface of the second sidewall, the top surface of the first sidewall is higher than the bottom surface of the second trench, and the top surface of the first sidewall is flush with the top surface of the storage area.
8. A semiconductor device, characterized in that, include: The substrate includes a storage region, a peripheral region, and a transition region located between the storage region and the peripheral region, wherein a first isolation structure is present in the transition region; A first trench is located in the first isolation structure and extends along a first direction; The depth of the first trench is less than the depth of the isolation structure; The second trench extends along the second direction from the storage area to the transition area; The word line conductive layer is located in the second trench; The first trench is connected to the second trench.
9. The semiconductor device according to claim 8, characterized in that, Also includes: An insulating layer is essentially filled in the first trench; The top surface of the insulating layer is higher than the top surface of the word line conductive layer.
10. The semiconductor device according to claim 8, characterized in that, Also includes: The word line contact layer is located in the first trench; The word line contact layer is connected to the word line conductive layer.
11. The semiconductor device according to claim 10, characterized in that, In the direction parallel to the first direction, the width of the word line contact layer is greater than the width of the word line conductive layer.
12. The semiconductor device according to claim 10, characterized in that, In the direction parallel to the first direction, the gap between adjacent word line contact layers is smaller than the width of adjacent word line conductive layers.
13. The semiconductor device according to claim 10, characterized in that, The bottom surface of the word line contact layer is lower than the bottom surface of the word line conductive layer.
14. The semiconductor device according to claim 10, characterized in that, The top surface of the word line contact layer is higher than the top surface of the word line conductive layer.
15. The semiconductor device according to claim 10, characterized in that, The first trench includes: The first sidewall is located near the storage area; The second sidewall is located away from the storage area; Wherein, in the direction parallel to the second direction, the width of the first sidewall is greater than the width of the second sidewall.
16. The semiconductor device according to claim 15, characterized in that, The word line contact layer is located between the first sidewall and the second sidewall, with the top surface of the word line contact layer extending beyond the first sidewall and below the second sidewall.
17. A method for manufacturing a semiconductor structure, characterized in that... ； A substrate is provided, the substrate including a storage region, a peripheral region, and a transition region located between the storage region and the peripheral region, the transition region having a first isolation structure; A first trench is formed in the first isolation structure, the depth of the first trench being less than the depth of the first isolation structure.
18. The manufacturing method according to claim 17, characterized in that, Also includes: The storage area and a portion of the first isolation structure are etched to form the second trench, which extends along a second direction from the storage area to the transition area; The first trench is connected to the second trench, the first trench is substantially perpendicular to the second trench, and the depth of the second trench is less than the depth of the first trench.
19. The manufacturing method according to claim 18, characterized in that, Also includes: A word line conductive layer is formed in the second trench; An insulating layer is formed in the first trench; The top surface of the insulating layer is higher than the top surface of the word line conductive layer.
20. The manufacturing method according to claim 18, characterized in that, Also includes: A word line conductive layer is formed in the second trench, and a word line contact layer is formed in the first trench; The word line conductive layer is connected to the word line contact layer; In the first direction, the width of the word line contact layer is greater than the width of the word line conductive layer.