Solar cell and photovoltaic module

Abstract

The invention discloses a solar cell and a photovoltaic module, which are used for realizing light trapping, electric leakage prevention, minority carrier lifetime prolonging and cell efficiency improving. Comprising a silicon substrate, a first doped semiconductor layer, a second doped semiconductor layer and a passivation layer, the silicon substrate has a first surface, a second surface and a side surface. The first surface has a pyramid structure, and the side surface comprises a first region and a second region which are sequentially distributed; the first region is adjacent to the first surface and the second region is adjacent to the first region. The second region is recessed into the silicon substrate by a first distance relative to the first region; the first doped semiconductor layer and the second doped semiconductor layer with opposite conduction types are respectively arranged on the first surface and the second surface; the passivation layer is arranged on the first surface, the second surface and the side surface; the second surface comprises groove regions and doped regions which are alternately arranged, and the groove regions are recessed towards the silicon substrate by a second distance relative to the doped regions; the second doped semiconductor layer is located in the doped region, and the passivation layer is located in the trench region and the doped region; wherein the first distance is greater than or equal to the second distance.

Description

[0001] This application is a divisional application of application number 202510955714.6, entitled "A Solar Cell and Photovoltaic Module". The application date of patent application number 202510955714.6 is July 14, 2025. Technical Field

[0002] This invention relates to the field of photovoltaic technology, and more particularly to a solar cell and a photovoltaic module. Background Technology

[0003] Solar cells are increasingly being used as a new energy alternative. A solar cell is a device that converts solar energy into electrical energy. Specifically, solar cells use the photovoltaic principle to generate charge carriers, and then use electrodes to extract these carriers, thus facilitating the efficient use of electrical energy.

[0004] Due to different structural designs on the surface of silicon substrates, depending on their morphology and location, they can play functions such as increasing light trapping and preventing leakage. However, they can also increase the undulation of the relatively flat silicon substrate surface, increase surface defects, and thus affect the lifetime of minority carriers and reduce battery efficiency. Summary of the Invention

[0005] The purpose of this invention is to provide a solar cell and a photovoltaic module that can simultaneously achieve the effects of light trapping, preventing leakage, improving minority carrier lifetime, and improving battery efficiency.

[0006] In a first aspect, the present invention provides a solar cell comprising a silicon substrate, a first doped semiconductor layer, a second doped semiconductor layer, and a passivation layer; The silicon substrate has a first surface, a second surface, and a side surface connecting the first surface and the second surface; A first doped semiconductor layer is disposed on the first surface; The second doped semiconductor layer is disposed on the second surface, and the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types. A passivation layer is disposed on the first surface, the second surface, and the side surface, with the passivation layer located on the side of the first doped semiconductor layer and the second doped semiconductor layer away from the silicon substrate; The first face has multiple pyramid structures, and the side includes a first section and a second section distributed sequentially along the direction from the first face to the second face; the first section is adjacent to the first face, and the second section is adjacent to the first section. The second region is recessed into the silicon substrate by a first distance relative to the first region; The second surface includes alternating trench regions and doped regions, with the trench regions recessed into the silicon substrate by a second distance relative to the doped regions; a second doped semiconductor layer is located in the doped regions, and the passivation layer is located in the trench regions and the doped regions; Wherein, the first distance is greater than or equal to the second distance.

[0007] In the above technical solution, for bifacial solar cells, since the doped semiconductor layers with opposite doping types are located on the front and back sides of the solar cell, leakage will occur if the doped semiconductor layers on the front and back sides overlap on the side. Due to area and position limitations, it is difficult to pattern and form isolation trenches on the side of the solar cell using lasers during mass production. Therefore, by etching the side to remove the doped semiconductor layer deposited around the side, the second region on the side is recessed into the silicon substrate relative to the first region of the first side. This serves two purposes: first, it ensures the removal of the doped semiconductor layer deposited on the side during the etching process, as well as the inner expansion layer formed by the doped semiconductor layer in the side silicon substrate; second, the recessed second region increases the junction area near the first side while preventing leakage risk due to the small spacing between the first and second doped semiconductor layers along the thickness direction of the silicon substrate. The trench region does not have a second doped semiconductor layer, reducing parasitic absorption caused by the second doped semiconductor layer. The depth of the downward recess ensures that the inner expansion layer below the trench region is removed, reducing recombination problems caused by high doping concentration in non-power generation areas. Furthermore, the trench region on the back side and the recess formed by the second region on the side relative to the first region can both enhance the light-trapping effect and improve the light absorption efficiency of the battery. In comparison, the trench region on the back side does not require a deeper recess to avoid leakage problems because the adjacent doped semiconductor layers have the same doping type. Moreover, since the trench region is located on the second side and has a large distribution area, a shallower trench region can better balance the mechanical strength of the battery and reduce damage to the silicon substrate. Therefore, the second distance is set smaller than the first distance. Due to the smaller depth of the second distance, the etching and removal time of the trench region can be reduced, improving the fabrication efficiency.

[0008] In some possible implementations, the second distance is 0.5 μm to 9 μm, and / or the first distance is 2 μm to 10 μm. A second distance of 0.5 μm or greater in the trench recess is to ensure the removal of the film layer and inner extension layer, reducing parasitic absorption caused by the second doped semiconductor layer and reducing recombination problems in non-power-generating regions due to higher doping concentrations. However, it cannot be too large; a second distance of 9 μm or less ensures continuous coverage of the passivation layer on the second surface, maintaining passivation performance, ensuring the mechanical strength of the battery, and reducing damage to the silicon substrate.

[0009] In some possible implementations, the first distance is 3μm to 6μm, and / or the second region has multiple second pyramid structures.

[0010] In some possible implementations, the second surface includes alternating trench regions and doped regions, with the trench regions recessed into the silicon substrate relative to the doped regions. The trench regions include a fourth pyramid structure or a second texture structure. A second doped semiconductor layer is located in the doped regions, and a passivation layer is located in the trench regions and the doped regions.

[0011] With the above technical solution, no second doped semiconductor layer is set in the trench region, reducing parasitic absorption caused by the second doped semiconductor layer. The downward recessed depth ensures that the inner extension layer below the trench region is removed, reducing recombination problems caused by high doping concentration in non-power generation areas. The fourth pyramid textured structure in the trench region further enhances the light trapping effect on the second side of the bifacial cell, increasing the overall bifaciality of the cell and comprehensively improving cell performance. The second textured structure in the trench region better meets the passivation layer coverage requirements, satisfies the passivation performance requirements of the trench region, and improves the fill factor of the solar cell.

[0012] In some possible implementations, when the trench region includes a second texture structure, the second distance is 0.5 μm to 3.5 μm; or, when the trench region includes a fourth pyramid structure, the second distance is 3.5 μm to 9 μm.

[0013] When the trench region includes the second texture structure, the second distance D2 ranges from 0.5 μm to 3.5 μm. Since the second texture structure is a polygonal structure recessed into the silicon substrate, a smaller trench depth can accommodate the second texture structure. A shallower trench region can better balance the mechanical strength of the battery and reduce damage to the silicon substrate. When the trench region includes the fourth pyramid structure, the second distance D2 ranges from 3.5 μm to 9 μm. The greater depth of the trench region allows the apex height of the fourth pyramid structure to be lower than the surface of the doped region at the boundary with the trench region, avoiding the negative impact on gate line printing or passivation layer coating caused by the height difference of the fourth pyramid structure protruding from the second surface.

[0014] In some possible implementations, the average one-dimensional dimension of the base of the fourth pyramid structure ranges from 0.5 μm to 6 μm; and / or, the height of the fourth pyramid structure ranges from 0.5 μm to 5 μm.

[0015] In some possible implementations, the side also includes a third zone adjacent to the second side, the second zone being located between the first and third zones, and the third zone having multiple third pyramid structures and / or multiple first texture structures.

[0016] With the above technical solution, the third pyramid structure in the third region can cause light to be reflected multiple times within the third pyramid structure, increasing the optical path and reducing the reflectivity of the third region to sunlight, making the reflectivity of the third region 2% to 20%, allowing more light to be absorbed by the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell.

[0017] In some possible implementations, the side also includes a third region adjacent to the second surface. The second region is located between the first and third regions and is recessed into the silicon substrate relative to the third region. The third distance of the recess is 0.1 μm to 5 μm.

[0018] With the above technical solution, the second region has a smaller indentation depth into the silicon substrate compared to the third region. Combined with the fact that the indentation depths on the front and back sides of the solar cell can be set to be relatively small, the structure of electrical isolation is satisfied while taking into account the mechanical strength of the cell.

[0019] In some possible implementations, the passivation layer thickness in the trench region is less than that in the doped region. Due to the difference in surface roughness and surface height between the two regions, it is more difficult to deposit a thick passivation layer in the trench region compared to the doped region. This thickness setting simplifies the process while still meeting performance requirements.

[0020] In some possible implementations, the passivation layer includes a second passivation layer and a third passivation layer, with the second passivation layer disposed on the first surface and / or the second surface, and the third passivation layer disposed on the side surface; wherein the thickness of the third passivation layer is greater than the thickness of the second passivation layer.

[0021] With the above technical solution, the third passivation layer covers the side of the battery. Due to the low conductivity of the third passivation layer, it can provide partial electrical isolation. In addition, due to the complexity of the side surface morphology, a better passivation effect is required. Therefore, setting a thicker third passivation layer on the side can further enhance the electrical isolation effect, while also enhancing the passivation effect on the side and reducing recombination.

[0022] In some possible implementations, the thickness difference between the third passivation layer and the second passivation layer is greater than or equal to 20 nm. Because the side surface has a first, second, and third region with varying elevations, the morphology of the silicon substrate surface is complex, requiring a thicker passivation layer to passivate the side surface of the solar cell. Therefore, considering the enhanced side passivation effect and overall cell performance, the thickness difference between the third and second passivation layers is greater than or equal to 20 nm.

[0023] In some possible implementations, the thickness of the second passivation layer on the first surface is 65 nm to 95 nm, and / or the thickness of the second passivation layer on the second surface is 70 nm to 100 nm.

[0024] In some possible implementations, the passivation layer includes a second passivation layer disposed on the first surface and / or the second surface; the second passivation layer located on the second surface is disposed on the surface of the doped region and the trench region, and the second passivation layer located in the doped region is disposed on the side of the second doped semiconductor layer away from the silicon substrate; the thickness of the second passivation layer located in the trench region is different from the thickness of the second passivation layer located in the doped region.

[0025] With the above technical solution, the thickness of the second passivation layer varies in different regions of the second surface. This allows for flexible adjustment of the battery film structure to meet the improvement requirements of different battery parameters, such as open-circuit voltage, fill factor, or short-circuit current. Setting the thickness of the second passivation layer in the trench region to be greater than that in the doped region better satisfies the passivation requirements of the silicon substrate surface in the trench region, thereby improving the open-circuit voltage of the solar cell. Alternatively, when the solar cell needs to improve contact performance by increasing the burn-through performance of the electrodes on the doped semiconductor layer, a thicker passivation layer needs to be set on the surface of the doped region to protect the non-electrode regions on the doped region, balancing the requirements of contact performance and passivation performance. However, simply increasing the thickness of all passivation layers on the second surface will reduce the uniformity of the second passivation layer, leading to varying degrees of carrier recombination and easily affecting the current density of the solar cell. In this case, setting the thickness of the second passivation layer in the doped region to be greater than that in the trench region balances the contact performance, passivation performance, and current density of the solar cell, ultimately improving battery efficiency.

[0026] In some possible implementations, the length of the second region accounts for 50% to 95% of the thickness of the solar cell in the thickness direction.

[0027] With the above technical solution, if the length of the second region is less than 50%, the length is too small to meet the light-trapping effect on the side, and the spacing between the first and second doped semiconductor layers on the side is too small, posing a risk of leakage. If the length of the second region is greater than 95%, the length is too large, resulting in a small proportion of the first region, which is not conducive to increasing the junction area on the side adjacent to the first surface and will increase damage to the surface of the first surface during the wet process, reducing the yield of battery production. Therefore, considering reducing the risk of leakage and increasing the junction area on the side, the length of the second region is selected to be 50%~95%.

[0028] In some possible implementations, the doped region has a third texture structure, which exhibits a non-pyramid-shaped microstructure morphology, including at least two or more first substructures that are partially stacked, the bottom surface of the first substructure being a polygonal plane; wherein, the one-dimensional dimension of the bottom surface of the first substructure is larger than the one-dimensional dimension of the bottom surface of the second texture structure of the trench region.

[0029] By adopting the above technical solution, forming a fourth pyramid structure or a second texture structure in the trench region and a non-pyramid texture structure in the doped region can enable the formed cell to have different levels of light-trapping structure, increasing the effective light contact area. Moreover, for the third texture structure formed in the doped region, the one-dimensional dimension of the bottom surface of the first substructure is larger than the one-dimensional dimension of the bottom surface of the second texture structure in the trench region, which is beneficial to improve the uniformity of the second doped semiconductor layer, further suppress the local high doping concentration of the second doped semiconductor layer, reduce the contact resistivity, increase the open circuit voltage of the solar cell, and improve the fill factor and photoelectric conversion efficiency.

[0030] In some possible implementations, when the trench region includes a fourth pyramid structure, the dimensional consistency of the pyramid structure on the first face is better than that of the fourth pyramid structure located in the trench region.

[0031] By employing the above technical solution, controlling the size consistency of the pyramid structures on the light-receiving and back-light-receiving sides of the silicon substrate within a certain range, and ensuring good consistency of the pyramid structures on the first side (the light-receiving side) of the same solar cell, the light-trapping effect of the pyramid structures on the light-receiving side can be improved. This also helps to improve the uniformity of the passivation layer formed on the pyramid structures, resulting in better passivation layer performance and increasing the open-circuit voltage of the solar cell. The size consistency requirement for the fourth pyramid structure on the back-light-receiving side is lower, which can improve the overall light-trapping effect of the solar cell while reducing the etching degree of other areas of the solar cell during the fabrication of the fourth pyramid structure, thus reducing the difficulty of the fabrication process. In other words, setting pyramid structures with the aforementioned size consistency differences at different locations can achieve both improved solar cell performance and reduced fabrication difficulty.

[0032] In some possible implementations, the first zone has multiple first pyramid structures, and the second zone has multiple second pyramid structures.

[0033] With the above technical solution, a second pyramid structure is set in the recessed second region. On the one hand, it can further etch towards the silicon substrate, increase the etching depth of the side surface, and ensure the removal of the inner expansion layer on the side of the cell. On the other hand, the undulating structure of the second pyramid textured surface can effectively increase the randomness of the surface height, break the continuity of the side surface, and further reduce the risk of leakage caused by the overlap of different doped film layers or inner expansion layers on the side.

[0034] In some possible implementations, when the trench region includes a fourth pyramid structure, the dimensional consistency of the second pyramid structure located in the second region is comparable to that of the fourth pyramid structure located in the trench region. Since the dimensional consistency of the second pyramid structure and the pyramid structure in the trench region is similar, the texturing steps for both regions can be performed in a unified process step, simplifying the solar cell manufacturing process and saving production costs.

[0035] In some possible implementations, the dimensional consistency of the pyramid structure on the first face is better than that of the second pyramid structure on the second face.

[0036] By employing the above technical solution, and controlling the size consistency of the pyramidal structures on the light-receiving surface and sides of the silicon substrate within a certain range, better consistency of the pyramidal structures on the first surface (the light-receiving surface) of the same solar cell can improve the light-trapping effect of the pyramidal structures on the light-receiving surface. It also helps to improve the uniformity of the passivation layer formed on the pyramidal structures, resulting in better performance of the passivation layer and increasing the open-circuit voltage of the solar cell. The size consistency requirement for the second pyramidal structure in the second region of the side is lower. This can improve the overall light-trapping effect of the solar cell while reducing the etching degree of other areas of the solar cell during the fabrication of the second pyramidal structure, thus reducing the difficulty of the fabrication process. In other words, setting pyramidal structures with the aforementioned size consistency differences at different locations can achieve both improved solar cell performance and reduced fabrication difficulty.

[0037] In some possible implementations, the average one-dimensional dimension of the base of the first pyramid structure ranges from 0.5 μm to 6 μm; and / or, the height of the first pyramid structure ranges from 0.5 μm to 5 μm; The average one-dimensional dimension of the base of the second pyramid structure ranges from 0.5μm to 6μm; and / or, the height of the second pyramid structure ranges from 0.5μm to 5μm.

[0038] In some possible implementations, the trench region includes a fourth pyramid structure, the ratio of the height of the fourth pyramid structure to the depth of the trench region being in the range of 1:1.5 to 1:4.

[0039] In some possible implementations, the inclination angle of the sidewall of the trench relative to the second face is α, and the inclination angle of the sidewall connecting the base and top of the fourth pyramid structure relative to the base is β; the ratio of β to α ranges from 1:0.5 to 1:2; and / or, the range of α is 35° to 65°.

[0040] Secondly, the present invention also provides a photovoltaic module, comprising: A battery string, comprising a plurality of solar cells and interconnects as described in any of the above, wherein the interconnects are electrically connected to the solar cells to form a battery string; And the encapsulation layer, covering the surface of the battery string.

[0041] Since photovoltaic modules include solar cells as described in the first aspect, they have the same beneficial effects as those described in the first aspect, which will not be elaborated further. Attached Figure Description

[0042] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 A cross-sectional schematic diagram of a solar cell provided in an embodiment of the present invention; Figure 2 This is a schematic diagram showing the first distance by which the second region of the solar cell in the present invention is recessed into the silicon substrate relative to the first region; Figure 3 This is a schematic diagram of the second distance by which the trench region of the solar cell in an embodiment of the present invention is recessed into the silicon substrate relative to the doped region; Figure 4 A cross-sectional schematic diagram of another solar cell provided in an embodiment of the present invention; Figure 5 A schematic diagram of the side structure of a solar cell provided in an embodiment of the present invention; Figure 6 A three-dimensional diagram of a side tower base structure of a solar cell provided in an embodiment of the present invention; Figure 7 A schematic diagram of a pyramid structure within the trench region of a solar cell provided in an embodiment of the present invention; Figure 8 A schematic diagram of the one-dimensional dimensions of a first textured structure or a second textured structure of a solar cell provided in an embodiment of the present invention; Figure 9 Another schematic diagram of the one-dimensional dimensions of a first textured structure or a second textured structure of a solar cell provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of the one-dimensional dimensions of the first substructure of the third texture structure of a solar cell provided in an embodiment of the present invention.

[0043] Reference numerals: 10 is silicon substrate, 11 is tunneling oxide layer, 12 is second doped semiconductor layer, 13 is passivation layer, 131 is aluminum oxide layer, 132 is silicon nitride layer, 14 is first doped semiconductor layer, 15 is second electrode, 16 is first electrode, 101 is first region, 102 is second region, 103 is third region, 104 is doped region, 105 is trench region, 106 is first pyramid structure, 107 is second pyramid structure, 108 is fourth pyramid structure, 109 is first texture structure, 110 is pyramid structure. Detailed Implementation

[0044] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0045] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0046] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0047] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0048] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0049] In solar cells, different structural designs on the surface of the silicon substrate can increase light trapping and prevent leakage, depending on the morphology and position. However, they can also increase the undulation of the relatively flat silicon substrate surface and increase surface defects, thereby affecting the lifetime of minority carriers and reducing cell efficiency.

[0050] In view of this, such as Figures 1-6 As shown, an embodiment of the present invention provides a solar cell, including a silicon substrate 10, a first doped semiconductor layer 14, a second doped semiconductor layer 12, and a passivation layer 13; wherein, the silicon substrate 10 has a first side, a second side, and a side connecting the first side and the second side; the first side can be the light-receiving side of the solar cell, i.e., the front side, and the second side can be the back side of the solar cell, i.e., the back side; or, the first side can be the back side of the solar cell, and the second side can be the front side of the solar cell.

[0051] The first surface of the silicon substrate 10 has multiple pyramidal structures 110. The side surface of the silicon substrate 10 includes a first region 101 and a second region 102 sequentially distributed along the direction from the first surface to the second surface. The first region 101 is adjacent to the first surface, and the second region 102 is adjacent to the first region 101. The second region 102 is recessed into the silicon substrate 10 relative to the first region 101, with a first recess distance D1 that can be 2μm to 10μm, specifically 2μm, 4μm, 6μm, 8μm, 10μm, etc. The second surface includes alternating trench regions 105 and doped regions 104. The distance by which the trench region 105 is recessed into the silicon substrate 10 relative to the doped region 104 is a second distance D2. The first distance D1 is greater than or equal to the second distance D2. That is, the depth of the second region 102 recessed into the silicon substrate 10 relative to the first region 101 is greater than or equal to the depth of the trench region 105 recessed into the silicon substrate 10 relative to the doped region 104. A first doped semiconductor layer 14 is disposed on a first surface; a second doped semiconductor layer 12 is disposed on a second surface, wherein the conductivity types of the first doped semiconductor layer 14 and the second doped semiconductor layer 12 are opposite; a passivation layer 13 is disposed on the first surface, the second surface and the side surface, wherein the passivation layer 13 is located on the side of the first doped semiconductor layer 14 and the second doped semiconductor layer 12 that is away from the silicon substrate 10.

[0052] In some embodiments, the first region 101 has a plurality of first pyramid structures 106, and the second region 102 has a plurality of second pyramid structures 107.

[0053] It should be noted that the first distance D1 indented in the silicon substrate 10 by the second region 102 relative to the first region 101 can be the distance difference between the top of the first pyramid structure 106 in the first region 101 and the top of the second pyramid structure 107 in the second region 102; it can also be the distance difference between the bottom of the first pyramid structure 106 in the first region 101 and the bottom of the second pyramid structure 107 in the second region 102; or it can be the distance difference between the top of the first pyramid structure 106 in the first region 101 and the bottom of the second pyramid structure 107 in the second region 102, such as... Figure 2 As shown; or the distance difference between the side planes of the silicon substrate 10 where the first region 101 and the second region 102 are located. Further, the first distance D1 can be 3μm~6μm, specifically 3μm, 4μm, 5μm, 6μm, etc.

[0054] The second distance D2 can be the distance difference between the top of the texture structure in the trench region 105 and the bottom of the third texture structure in the doped region 104, or the distance difference between the bottom of the texture structure in the trench region 105 and the bottom of the third texture structure in the doped region 104, or the distance difference between the planes of the silicon substrate 10 where the trench region 105 and the doped region 104 are located.

[0055] The pyramid structure 110 on the first face and the first pyramid structure 106 in the first region 101 on the side can be formed in the same step. The first pyramid structure 106 in the first region 101 on the side may also be affected by other process steps in subsequent preparation processes, causing the first pyramid structure 106 to change and become different from the pyramid structure 110 on the first face.

[0056] The pyramid structure 110, the first pyramid structure 106, and the second pyramid structure 107 have a base, a apex, and multiple sides connecting the base and the apex. The base can be at least one of other polygons such as rectangle, square, rhombus, trapezoid, approximate rectangle, approximate square, approximate rhombus, and approximate trapezoid.

[0057] When using the above technical solution, for bifacial solar cells, since the doped semiconductor layers with opposite doping types are located on the front and back sides of the solar cell, for example, the first doped semiconductor layer 14 on the first side and the second doped semiconductor layer 12 on the second side have opposite doping types, leakage will occur if the doped semiconductor layers on the front and back sides overlap on the side. That is, when the first doped semiconductor layer 14 and the second doped semiconductor layer 12 are prepared, due to the characteristics of certain preparation processes (such as film deposition), the first doped semiconductor layer 14 and the second doped semiconductor layer 12 may form a wrap-around plating of the first doped semiconductor layer and the second doped semiconductor layer on the side, so that the first doped semiconductor layer and the second doped semiconductor layer overlap on the side and leakage occurs. Due to the limitations of area and position on the side of the solar cell, it is difficult to use laser to pattern and form isolation trenches during mass production to isolate the first doped semiconductor layer and the second doped semiconductor layer on the side.

[0058] Therefore, by etching the side surface, the doped semiconductor layer deposited around the side surface is removed, so that the second region 102 on the side surface is recessed into the silicon substrate 10 relative to the first region 101 adjacent to the first surface. This has two advantages: First, it ensures that the doped semiconductor layer deposited on the side surface during the etching process, as well as the inner expansion layer formed by the doped semiconductor layer in the silicon substrate on the side surface, are removed. The recessed second region 102 does not contain the first doped semiconductor layer, the second doped semiconductor layer, or the corresponding inner expansion layer, thus preventing leakage risk due to the small spacing between the first doped semiconductor layer and the second doped semiconductor layer along the thickness direction of the silicon substrate. Second, only the second region 102 needs to be etched and recessed, and the entire side surface does not need to be etched to the same depth. In this way, the first doped semiconductor layer 14 at the first region 101 on the side adjacent to the first surface can be retained to increase the junction area on the side adjacent to the first surface and improve the carrier collection efficiency.

[0059] In addition, the first distance D1 of the second region 102 recessed into the silicon substrate 10 relative to the first region 101 is greater than or equal to 2μm in order to ensure that the film layer and the inner expansion layer are removed to reduce the risk of leakage current; however, it cannot be too large, and the first distance D1 of the recess is less than or equal to 10μm to ensure that the passivation layer 13 is uniformly and continuously covered on the side and to ensure the side passivation performance.

[0060] Furthermore, since the trench region 105 does not have a second doped semiconductor layer 12, the parasitic absorption caused by the second doped semiconductor layer 12 is reduced. The depth of the downward recess ensures that the inner extension layer below the trench region 105 is removed, reducing recombination problems caused by the high doping concentration in the non-power generation area. On the one hand, since the doping type of the second doped semiconductor layer 12 in the adjacent doped regions 104 on the second surface is the same, the trench region 105 does not need a deep recess to avoid leakage problems. Moreover, since the trench region 105 is located on the second surface and has a large distribution area, the relatively shallow trench region 105 can better take into account the mechanical strength of the battery. Therefore, the second distance D2 is set to be less than or equal to the first distance D1. On the other hand, since the depth of the second distance D2 is small, the etching time of the trench region 105 can be reduced, improving the fabrication efficiency.

[0061] In addition, a second pyramid structure 107 is provided in the recessed second region 102. During the anisotropic etching process of forming the second pyramid structure 107, on the one hand, it can further etch towards the silicon substrate 10, increase the etching depth of the side surface, ensure the removal of the inner expansion layer on the side of the silicon substrate, and at the same time reduce the mechanical strength damage caused by the full-surface recess of the second region 102; on the other hand, by utilizing the undulating characteristics of the second pyramid structure 107 on the surface of the silicon substrate 10, it can effectively increase the randomness of the surface height, break the continuity of the side surface, and further reduce the leakage risk caused by the overlap of different doped film layers or inner expansion layers on the side.

[0062] For example, the second distance D2 can be 0.5μm to 9μm, specifically 0.5μm, 1μm, 1.5μm, 2μm, 2.5μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm, 7μm, 7.5μm, 8μm, 8.5μm, 9μm, etc. The second distance D2 of the trench region 105 is greater than or equal to 0.5μm to ensure that the film layer and inner extension layer are removed, reducing parasitic absorption caused by the second doped semiconductor layer 12, and reducing recombination problems in non-power generation areas due to high doping concentration; however, it cannot be too large, and the second distance D2 of the recess is less than or equal to 9μm to ensure continuous coverage of the passivation layer 13 on the second surface, ensuring the passivation performance of the second surface, as well as ensuring the mechanical strength of the battery and reducing damage to the silicon substrate 10.

[0063] like Figure 1 , Figure 4 and Figure 7As shown, in some embodiments, the second surface includes alternating trench regions 105 and doped regions 104. The trench regions 105 are recessed into the silicon substrate 10 relative to the doped regions 104. The trench regions 105 include a fourth pyramid structure 108 or a second texture structure. A second doped semiconductor layer 12 is located in the doped region 104, and a passivation layer 13 is located in the trench regions 105 and the doped regions 104. The second texture structure exhibits a non-pyramid-shaped microstructure morphology. The bottom surface of the second texture structure is a polygonal plane, and the shape of the polygonal plane includes at least one of rectangle, rhombus, square, trapezoid, approximately rectangular, approximately rhombus, approximately square, and approximately trapezoidal. The second texture structure includes a pyramid base structure and / or a polished structure, whose average roughness is less than that of the pyramid structure and whose reflectivity is greater than that of the pyramid structure. Multiple second texture structures can exist independently or can be stacked. It is understood that in the actual manufacturing process, the bottom surface morphology of the second texture structure presents an irregular polygonal plane, but overall exhibits morphological characteristics similar to rhombus, square, or trapezoid.

[0064] In the actual fabrication process, by etching a local area on the second surface, the second doped semiconductor layer originally formed on that area is etched away down to the surface of the silicon substrate 10 to form a trench region 105, while the remaining areas on the second surface are not etched, and the second doped semiconductor layer 12 originally formed on the remaining areas is retained to form a doped region 104. The trench region 105 is recessed into the silicon substrate 10 relative to the doped region 104, and the surface of the trench region 105 is etched to form a textured structure.

[0065] In some embodiments, the trench region 105 includes a fourth pyramid structure 108 or a second textured structure. Exemplarily, providing a fourth pyramid structure 108 in the trench region 105 can further enhance the light-trapping effect on the second side of the bifacial cell, increase the overall bifaciality of the cell, and comprehensively improve cell performance. Providing a second textured structure in the trench region 105 can better meet the coverage requirements of the passivation layer in the trench region 105, satisfy the passivation performance requirements of the trench region 105, and improve the fill factor of the solar cell.

[0066] In some embodiments, when the trench region 105 includes a second texture structure, the second distance D2 ranges from 0.5 μm to 3.5 μm. Since the second texture structure is a polygonal structure recessed into the silicon substrate 10, a smaller trench region 105 depth can accommodate the second texture structure. A shallower trench region 105 can better balance the mechanical strength of the battery and reduce damage to the silicon substrate 10.

[0067] In some embodiments, when the trench region 105 includes the fourth pyramid structure 108, the second distance D2 ranges from 3.5 μm to 9 μm. The greater depth of the trench region 105 allows the apex height of the fourth pyramid structure 108 to be lower than the surface of the doped region 104 that intersects with the trench region 105, thus avoiding the negative impact on gate line printing or passivation layer coating caused by the height difference generated by the fourth pyramid structure 108 protruding from the second surface.

[0068] To further improve the light-trapping effect of the trench region 105, the depth of the trench region 105 can be increased to accommodate more types of fourth pyramid structures 108, reduce the reflectivity of the trench region 105, and avoid the height difference between the larger fourth pyramid structure 108 in the trench region 105 and the doped region 104. At the same time, considering the mechanical strength of the solar cell, the second distance D2 of the trench region 105 should not be set too large. For example, the height of the fourth pyramid structure 108 in the trench region 105 can be 0.5μm, 2μm, 3.5μm, 5μm, etc., which increases the number of reflections of light between multiple fourth pyramid structures 108 and reduces the reflectivity of the fourth pyramid structure 108. If the height of the fourth pyramid structure 108 is less than 0.5μm, the undulation amplitude of the fourth pyramid structure 108 is smaller, which will reduce the number of reflections of light between multiple fourth pyramid structures 108, resulting in an increase in the reflectivity of the texture structure of the trench region 105 and a decrease in the photoelectric conversion efficiency of the solar cell. If the height of the fourth pyramid structure 108 is greater than 5μm, some light will not be reflected twice, which will increase the reflectivity of the texture structure of the trench region 105 and also increase the internal stress of the solar cell, thereby affecting the service life and stability of the solar cell.

[0069] In some embodiments, the second distance D2 can be set to be greater than the first distance D1. That is, the depth of the trench region 105 recessed into the silicon substrate 10 relative to the doped region 104 is greater than the depth of the second region 102 recessed into the silicon substrate 10 relative to the first region 101. The trench region 105 can be formed by removing the surface protective layer with a laser and then etching it using wet etching or other methods. Therefore, the depth of the trench region 105 can be adjusted by controlling the laser energy. In the actual fabrication process, the wet etching steps of the trench region 105 and the partial formation of the second region 102 can be placed in the same process step. In this case, setting the second distance D2 of the trench region 105 to be greater than the height of the fourth pyramid structure 108 and greater than the first distance D1 can satisfy the requirement of improving the light trapping effect on the back side while simplifying the process steps, saving production time, and increasing production capacity. On this basis, the fourth pyramid structure 108 in the trench region 105 and the second pyramid structure 107 in the second region 102 on the side of the cell can jointly improve the light trapping effect of the solar cell.

[0070] In some embodiments, the side surface further includes a third region 103 adjacent to the second surface. The second region 102 is located between the first region 101 and the third region 103. The third region 103 has multiple third pyramid structures and / or multiple first texture structures 109. The third pyramid structures are recessed into the silicon substrate 10. The first texture structures 109 include a base structure and / or a polished structure, with an average roughness lower than the average roughness of the pyramid structure and a reflectivity higher than the reflectivity of the pyramid structure. The first texture structures 109 exhibit a non-pyramid-shaped microstructure morphology. The bottom surface of the first texture structure 109 is a polygonal plane, and the shape of the polygonal plane includes at least one of rectangle, rhombus, square, trapezoid, approximately rectangular, approximately rhombus, approximately square, and approximately trapezoidal. The first texture structures 109 include a base structure and / or a polished structure, with an average roughness lower than the average roughness of the pyramid structure and a reflectivity higher than the reflectivity of the pyramid structure. Multiple first texture structures 109 can exist individually or in a stacked state. Understandably, in the actual manufacturing process, the bottom surface of the first texture structure 109 presents an irregular polygonal plane, but overall it exhibits morphological features that are approximately rhomboid, square, or trapezoidal.

[0071] With the above technical solution, the third pyramid structure on the third region 103 can cause light to be reflected multiple times within the third pyramid structure, increasing the optical path and reducing the reflectivity of the third region 103 to sunlight, so that the reflectivity of the third region 103 is 2% to 20%, allowing more light to be absorbed by the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell.

[0072] In some embodiments, the second region 102 is recessed into the silicon substrate 10 relative to the third region 103, and the third distance D3 of the recess is 0.1 μm to 5 μm. The recess depth of the second region 102 into the silicon substrate 10 relative to the third region 103 is relatively small. Combined with the fact that the front and back recess depths of the solar cell can be set to be relatively small, the structure of electrical isolation is satisfied, while also taking into account the mechanical strength of the cell.

[0073] In some embodiments, the third pyramid structure of the third region 103 is recessed into the silicon substrate 10. The apex of the third pyramid structure is similar to an inverted square pyramid structure, recessed into the silicon substrate 10 to a depth of 0.1 μm to 4 μm. The inverted square pyramid structure allows light to be reflected multiple times within the third pyramid structure, increasing the optical path and reducing the reflectivity of the third region 103 to sunlight. This results in a reflectivity of the third region 103 of 2% to 20%, allowing more light to be absorbed by the solar cell and thus improving the photoelectric conversion efficiency of the solar cell.

[0074] In some embodiments, the first pyramid structure 106 of the first region 101 is recessed into the silicon substrate 10. The apex of the first pyramid structure 106 is similar to an inverted square pyramid structure, recessed into the silicon substrate 10 with a depth of 0.1 μm to 4 μm. The inverted square pyramid structure 106 allows light to be reflected multiple times within the first pyramid structure 106, increasing the optical path and reducing the reflectivity of the first region 101 to sunlight, resulting in a reflectivity of 2% to 20%. This allows more light to be absorbed by the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell.

[0075] In some embodiments, the passivation layer 13 includes a first passivation layer, the thickness of which is greater than ...

[0076] With the above technical solution, the first region 101 is closer to the edge of the solar cell than the second region 102. The edge of the solar cell has relatively more defects, affecting the overall passivation effect. Therefore, the thickness of the first passivation layer on the first region 101 is greater than the thickness of the first passivation layer on the second region 102, which can increase the passivation effect on the edge of the solar cell. Furthermore, due to the height difference between the surfaces of the first region 101 and the second region 102, it is more difficult to deposit a thicker first passivation layer in the second region 102 compared to the first region 101. This thickness setting, while meeting performance requirements, eliminates the need for control measures to maintain consistent first passivation layer thickness in both regions, further simplifying the process.

[0077] For example, the thickness of the first passivation layer can be 2nm to 20nm, specifically 2nm, 5nm, 8nm, 10nm, 12nm, 15nm, 18nm, 20nm, etc. The difference between the thickness of the first passivation layer located on the first region 101 and the thickness of the first passivation layer located on the second region 102 is less than or equal to 2nm, specifically, the thickness difference can be 0.1nm, 0.3nm, 0.5nm, 0.8nm, 1nm, 1.2nm, 1.5nm, 1.7nm, 2nm, etc. When the difference is greater than 2nm, the thickness difference is too large, the thickness uniformity of the first passivation layer on the side is poor, the degree of carrier recombination is different, the current density of the solar cell is easily affected, and the turn-on voltage of the solar cell decreases. Therefore, considering the improvement of edge passivation effect and the overall performance of the solar cell, the thickness difference is less than or equal to 2nm.

[0078] In some embodiments, the thickness of the passivation layer 13 located on the trench region 105 is less than the thickness of the passivation layer 13 located on the doped region 104. Due to the difference in surface roughness and surface height between the two regions, it is more difficult to deposit a thicker passivation layer 13 in the trench region 105 than in the doped region 104. This thickness setting, while meeting performance requirements, eliminates the need to maintain a consistent passivation layer 13 thickness in both regions through control measures, thus simplifying the process.

[0079] like Figure 1 and Figure 4 As shown, in some embodiments, the passivation layer 13 includes a second passivation layer and a third passivation layer. The second passivation layer is disposed on a first surface and / or a second surface, and the third passivation layer is disposed on a side surface; wherein the thickness of the third passivation layer is greater than the thickness of the second passivation layer. The materials of the second and third passivation layers can be silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, and silicon carbide, etc. For example, the second and third passivation layers can be a silicon nitride layer 132, or a stack of an aluminum oxide layer 131 and a silicon nitride layer 132. It is understood that the second and third passivation layers can be made of the same material or different materials, and the same or different materials are selected according to the passivation requirements; the second and third passivation layers can be formed in different process steps or in the same process step. When formed in the same process step, the process can be simplified.

[0080] In some embodiments, a second passivation layer is disposed on the side of the first passivation layer on the first and second surfaces that is opposite to the silicon substrate 10. The second passivation layer can reduce light reflection on the first and second surfaces, enhance light absorption, and improve the conversion efficiency of the solar cell. For example, the thickness of the second passivation layer on the first surface is 65nm to 95nm, specifically 65nm, 68nm, 70nm, 72nm, 74nm, 76nm, 78nm, 80nm, 82nm, 85nm, 87nm, 89nm, 92nm, 95nm, etc., and / or the thickness of the second passivation layer on the second surface is 70nm to 100nm, specifically 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, etc.

[0081] With the above technical solution, the third passivation layer covers the side of the battery. Due to the low conductivity of the third passivation layer, it can provide partial electrical isolation. In addition, due to the complexity of the side surface morphology, a better passivation effect is required. Therefore, the third passivation layer on the side is thicker than the second passivation layer on the first and / or second sides, which can further enhance the electrical isolation effect, while also enhancing the passivation effect on the side and reducing recombination.

[0082] For example, the thickness difference between the third passivation layer and the second passivation layer is greater than or equal to 20 nm, and the specific thickness difference can be 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, etc. Since the side surface has a first region 101, a second region 102, and a third region 103, and has a height difference, the surface morphology is relatively complex, requiring a thicker passivation layer to passivate the side surface of the battery cell. Therefore, considering the enhanced side passivation effect and the overall battery performance, the thickness difference between the third passivation layer and the second passivation layer is greater than or equal to 20 nm.

[0083] In some embodiments, the passivation layer 13 includes a second passivation layer disposed on a first surface and / or a second surface; the second passivation layer located on the second surface is disposed on the surface of the doped region 104 and the trench region 105, and the second passivation layer located on the doped region 104 is disposed on the side of the second doped semiconductor layer 12 away from the silicon substrate 10; the thickness of the second passivation layer located in the trench region 105 is different from the thickness of the second passivation layer located in the doped region 104.

[0084] The second passivation layer has different thicknesses in different regions of the second surface, allowing for flexible adjustment of the cell film structure to meet the improvement requirements of different cell parameters, such as open-circuit voltage, fill factor, or short-circuit current. For example, when a doped region 104 and a trench region 105 are provided on the second surface of the solar cell, while reducing the parasitic absorption problem caused by the second doped semiconductor layer 12, the passivation performance requirements will be correspondingly increased. In this case, the thickness of the second passivation layer in the trench region 105 is greater than that in the doped region 104, which can better meet the passivation requirements of the silicon substrate 10 surface in the trench region 105 and improve the open-circuit voltage of the solar cell. Alternatively, when the solar cell needs to improve contact performance by increasing the burn-through performance of the electrodes to the second doped semiconductor layer 12, a thicker second passivation layer needs to be provided on the surface of the doped region 104 to protect the non-electrode regions on the doped region 104, balancing the requirements of contact performance and passivation performance. However, simply increasing the thickness of all the second passivation layers on the second surface will reduce the uniformity of the second passivation layers, resulting in different degrees of carrier recombination and affecting the current density of the solar cell. In this case, setting the thickness of the second passivation layer in the doped region 104 to be greater than the thickness of the second passivation layer in the trench region 105 takes into account the balance between factors such as the contact performance, passivation performance and current density of the solar cell, and ultimately improves the cell efficiency.

[0085] like Figure 1 and Figure 5 As shown, in some embodiments, the length of the second region 102 in the thickness direction of the solar cell accounts for 50% to 95% of the solar cell thickness, specifically 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%, etc. If the length of the second region 102 is less than 50%, the length of the second region 102 is too small, the isolation distance between the first doped semiconductor layer 14 and the second doped semiconductor layer 12 on the side is too small, posing a risk of leakage current and failing to meet the light trapping effect on the side. If the length of the second region 102 is greater than 95%, the length is too large, resulting in a small proportion of the first region 101, which is not conducive to increasing the junction area on the side adjacent to the first surface and will increase damage to the surface of the first surface during the wet process, reducing the yield of cell production. Therefore, considering factors such as reducing the risk of leakage current and improving the yield of cell production, the length of the second region 102 is selected to be 50% to 95%.

[0086] like Figure 5As shown, in some embodiments, the boundary portions of the first region 101 and / or the third region 103 near the second region 102 are distributed in an island-like pattern, i.e., they exhibit a structure that is discontinuously arranged with the main regions of the first region 101 or the third region 103, with the discontinuous portions extending into the second region 102. In this case, the length of the second region 102 refers to the length along the thickness direction of the silicon substrate 10, from the position where the second region 102 intersects with the main region of the first region 101 to the position where the second region 102 intersects with the main region of the third region 103. In practical applications, the boundary line between the first region 101 and the second region 102 is a wavy line, and the boundary line between the third region 103 and the second region 102 is also a wavy line. That is, the boundary line is not a regular straight line, but an irregular zigzag line. This can increase the specific surface area of ​​the side, enhance the light-trapping effect, and improve the utilization rate of light by the side.

[0087] It should be noted that due to uncontrollable factors in the wet process, some edges on the side of the solar cell may lack the first or third region.

[0088] In some embodiments, the doped region 104 has a third texture structure, which exhibits a non-pyramid microstructure morphology, including at least two or more first substructures that are partially stacked, and the bottom surface of the first substructure is a polygonal plane; wherein, the one-dimensional dimension of the bottom surface of the first substructure is greater than the one-dimensional dimension of the bottom surface of the fourth pyramid structure 108 or the second texture structure of the trench region 105.

[0089] In some embodiments, by providing textured structures with different morphologies in the doped region 104 and the trench region 105, the textured structure formed in the trench region 105 and the non-pyramid textured structure formed in the doped region 104 can enable the formed battery to have different levels of light-trapping structures, increasing the effective contact area of ​​light. Moreover, for the third textured structure formed in the doped region 104, the one-dimensional dimension of the bottom surface of the first substructure is larger than the one-dimensional dimension of the bottom surface of the textured structure in the trench region 105, which is beneficial to improve the uniformity of the second doped semiconductor layer 12 and further suppress the local high doping concentration of the second doped semiconductor layer 12, reduce the contact resistivity, increase the open-circuit voltage of the solar cell, and improve the fill factor and photoelectric conversion efficiency.

[0090] It should be noted that the second and third texture structures exhibit non-pyramid-shaped microstructures, similar to the first texture structure 109. The base of the second, third, or first substructure is a polygonal plane, and the shape of the polygonal plane includes at least one of the following: rectangle, rhombus, square, trapezoid, approximately rectangular, approximately rhombus, approximately square, and approximately trapezoidal. The second and third texture structures include a base structure and / or a polished structure, whose average roughness is less than that of the pyramid structure, and whose reflectivity is greater than that of the pyramid structure. Understandably, in the actual manufacturing process, the base structure exhibits an irregular polygonal plane shape, but overall presents approximate rhomboid, square, or trapezoidal morphological characteristics. Figures 8-10 As shown, the one-dimensional dimension of the bottom surface or pyramid bottom surface of the outermost first substructure of the first texture structure, the second texture structure, and the third texture structure can be the length, width, diagonal length, diameter of the circle, or distance between the two farthest endpoints of the surface or bottom surface, etc., which is not limited here.

[0091] In some embodiments, the one-dimensional dimension of the bottom surface of the first substructure can refer to the average value of the one-dimensional dimensions of the bottom surfaces of multiple outermost first substructures within a predetermined range area of ​​the second surface. The average one-dimensional dimension of the bottom surface of the outermost first substructure can specifically be 4μm to 14μm, etc., specifically 4μm, 6μm, 8μm, 10μm, 12μm, 14μm, etc. The average one-dimensional dimension of the base of the pyramid structure 110, the first pyramid structure 106, the second pyramid structure 107, the third pyramid structure, and the fourth pyramid structure 108 can be 0.5μm to 6μm, specifically 0.5μm, 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm, 6μm, etc.; the height of the pyramid structure is 0.5μm to 5μm, specifically 0.5μm, 0.8μm, 1μm, 1.2μm, 1.5μm, 1.8μm, 2μm, 2.3μm, 2.5μm, 2.8μm, 3μm, 3.2μm, 3.4μm, 3.7μm, 4μm, 4.3μm, 4.6μm, 4.8μm, 5μm, etc. When the height of the pyramid structure is within 5μm, the pyramid structure has the characteristics of low reflection, low recombination, and easy filling, which improves the photoelectric conversion efficiency of the battery.

[0092] In some instances, when measuring the texture dimensions characteristic of solar cells, such as the one-dimensional dimension of the base of the first pyramid structure 106, the surface calibration of the film layer can be directly measured using testing instruments (optical microscope, atomic force microscope, scanning electron microscope, transmission electron microscope, etc.). In one case, since the film thickness is at the nanometer level, it can be directly obtained using the film measurement data corresponding to the first pyramid structure 106; the film measurement data is the sum of the film thickness and texture dimensions. In another case, it can also be obtained by subtracting the film thickness data from the aforementioned film measurement data. The above measurement methods are merely examples and are not intended to limit the scope of this application.

[0093] In some embodiments, the size of the pyramid structure 110 on the first face is larger than the size of the second pyramid structure 107 in the second region 102, or the size of the pyramid structure 110 on the first face is larger than the size of the fourth pyramid structure 108 in the trench region 105. The dimensions of the pyramid structure 110, the second pyramid structure 107, and the fourth pyramid structure 108 on the first face include the one-dimensional dimension of the base and the height, and may refer to the average one-dimensional dimension of the base of multiple pyramid structures 110, 107, or 108 within a predetermined range of the region where each pyramid structure is located. Using the above technical solution, when the first face is the light-receiving surface, the textured surface structure of the solar cell's light-receiving surface can better meet the characteristics of low reflection, low recombination, and easy filling.

[0094] In some embodiments, the dimensional consistency of the pyramid structure 110 located on the first face is better than that of the second pyramid structure 107 located in the second region 102. The dimensions of the pyramid structure include the one-dimensional dimension of its base and its height. Dimensional consistency refers to the consistency of the one-dimensional dimension of the base and / or the height of the pyramid structure. Dimensional consistency is the difference between the dimensions of the pyramid structures within a certain region and the average dimensions of the pyramid structures within that region. For example, by statistically analyzing the one-dimensional dimensions of the base of the pyramid structures 110 and the second pyramid structures 107 within a unit area on the first face, the variance or range of the dimensions of these pyramid structures 110 and the second pyramid structures 107 can be calculated respectively. Using the variance or range of the pyramid structures 110 and 107 as a reference for consistency, different pyramid structures can be compared to determine their level of consistency.

[0095] By adopting the above technical solution, and controlling the size consistency of the pyramid structures on the light-receiving surface and side of the silicon substrate 10 within a certain range, the consistency of the pyramid structure 110 on the first surface (the light-receiving surface) can be better controlled on the same solar cell. This improves the light-trapping effect of the pyramid structure 110 on the light-receiving surface and also helps to improve the uniformity of the passivation layer formed on the pyramid structure 110, resulting in better performance of the passivation layer and increasing the open-circuit voltage of the solar cell. The size consistency requirement for the second pyramid structure 107 in the second side region 102 is lower. This allows for improved overall light-trapping effect of the solar cell while reducing the etching degree in other areas of the solar cell during the fabrication of the second pyramid structure 107, thus reducing the difficulty of the fabrication process. In other words, setting pyramid structures with the aforementioned size consistency differences at different locations can achieve both improved solar cell performance and reduced fabrication difficulty.

[0096] In some embodiments, when the trench region 105 includes a fourth pyramid structure 108, the dimensional consistency of the pyramid structure 110 on the first face is better than the dimensional consistency of the fourth pyramid structure 108 in the trench region 105.

[0097] By controlling the size consistency of the pyramid structures on the light-receiving and back-light-receiving sides of the silicon substrate 10 within a certain range, better consistency control of the pyramid structure 110 on the first side (the light-receiving side) of the same solar cell can improve the light-trapping effect of the pyramid structure 110 on the light-receiving side and is beneficial to improving the uniformity of the passivation layer 13 formed on the pyramid structure 110. This results in better performance of the passivation layer 13 and increases the open-circuit voltage of the solar cell. The second side (the back-light-receiving side) has lower size consistency requirements for the fourth pyramid structure 108. This can improve the overall light-trapping effect of the solar cell while reducing the etching degree of other areas of the solar cell during the fabrication of the fourth pyramid structure 108, thus reducing the difficulty of the fabrication process. In other words, setting pyramid structures with the aforementioned size consistency differences at different locations can achieve both improved solar cell performance and reduced fabrication difficulty.

[0098] In some possible implementations, the difference between the one-dimensional dimension of the base of different pyramid structures 110 within a certain region of the first face and the average one-dimensional dimension of the base of the pyramid structures 110 within that region is less than or equal to 1 μm. This results in better dimensional consistency of the pyramid structures 110, improving the light-trapping effect and the uniformity of the passivation layer.

[0099] In some embodiments, when the trench region 105 includes a fourth pyramid structure 108, the size consistency of the second pyramid structure 107 located in the second region 102 is comparable to the size consistency of the fourth pyramid structure 108 in the trench region 105.

[0100] Thus, the dimensions of the second pyramid structure 107 and the fourth pyramid structure 108 in the trench area 105 are similar, and the texturing steps of the two areas can be carried out in a unified process step, simplifying the solar cell process and saving production costs.

[0101] like Figure 7 As shown, in some embodiments, the ratio of the height of the fourth pyramid structure 108 to the depth of the trench region 105 is 1:1.5 to 1:4, specifically 1:1.5, 1:2, 1:25, 1:3, 1:35, 1:4, etc. The depth of the trench region 105 is the height difference between the bottom of the trench region 105 and the surface of the doped region 104. The top of the fourth pyramid structure 108 within the trench region 105 is located within the recessed trench region 105 and does not extend beyond the top surface of the recess, i.e., it does not extend beyond the surface where the doped region 104 is located. In other words, the downward etching depth of the trench region 105 on the second surface of the silicon substrate 10 is greater than the height of the fourth pyramid structure 108. The depth of the trench region 105 can be 1μm to 10μm, specifically 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, etc. In this way, the textured surface can be guaranteed to have good light trapping and passivation effects, while also taking into account the requirements of etching depth on process difficulty, preparation efficiency, and mechanical strength of silicon substrate.

[0102] like Figure 7 As shown, in some embodiments, the ratio of the inclination angle β of the fourth pyramid structure 108 to the inclination angle α of the sidewall of the trench region 105 is 1:0.5 to 1:2. The inclination angle β of the fourth pyramid structure 108 refers to the inclination angle of the sidewall connecting the base and the top of the fourth pyramid structure 108 relative to the base. The inclination angle α of the sidewall of the trench region 105 refers to the inclination angle of the sidewall of the trench region 105 relative to the bottom plane (i.e., the second surface) of the trench region 105. The inclination angle α of the sidewall of the trench region 105 relative to the second surface is 35° to 65°, specifically 35°, 40°, 45°, 50°, 55°, 60°, 65°, etc. The inclination angle of the fourth pyramid structure 108 is slightly smaller than that of the sidewall of the trench region 105, which is conducive to the formation of a uniform passivation layer 13 on the fourth pyramid structure 108 of the trench region 105, avoiding the sidewall of the trench region 105 from blocking the formation of the passivation layer 13, and increasing the specific surface area of ​​the trench region 105, which is beneficial to enhancing the light trapping effect.

[0103] like Figure 1 and Figure 4As shown, in some possible implementations, a tunneling oxide layer 11 is further disposed on one side of the second surface. The tunneling oxide layer 11 is located between the silicon substrate 10 and the side of the second doped semiconductor layer 12 closest to the silicon substrate 10. In this case, the second doped semiconductor layer 12 can be a doped polycrystalline silicon layer. The doped polycrystalline silicon layer and the tunneling oxide layer 11 form a tunneling passivation structure contact. The tunneling passivation contact structure partially covers the second surface of the silicon substrate 10, forming a certain pattern, such as an alternating stripe pattern or a grid pattern. In a solar cell with a tunneling passivation contact structure, the tunneling oxide layer 11 located between the silicon substrate 10 and the second doped semiconductor layer 12 can allow electrons to pass through while blocking hole transport, thereby achieving efficient charge separation, reducing interface recombination loss, improving interface passivation effect, and enhancing photoelectric conversion efficiency. Furthermore, the tunneling oxide layer 11 can prevent the metal crystals of the electrode from penetrating the second doped semiconductor layer 12 and entering the silicon substrate 10, avoiding damage to the passivation of the solar cell surface and thus reducing cell efficiency.

[0104] For example, the silicon substrate 10 can be N-type or P-type monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, etc. The materials of the first doped semiconductor layer 14 and the second doped semiconductor layer 12 can include doped monocrystalline silicon, doped polycrystalline silicon, doped microcrystalline silicon, doped nanocrystalline silicon, doped amorphous silicon, etc. The materials and doping types of the silicon substrate and doped semiconductor layers are selected appropriately according to the type of cell. For example, when the doped semiconductor layer is doped polycrystalline silicon, it can form a tunneling passivation contact structure with the tunneling oxide layer; when the doped semiconductor layer is doped amorphous silicon, it can form a heterojunction contact structure with intrinsic amorphous silicon. The resulting solar cell can be a bifacial solar cell with a tunneling passivation contact structure and / or a heterojunction contact structure, without specific limitations.

[0105] like Figure 1 and Figure 4 As shown, based on the solar cells described in any of the above embodiments, this invention also provides a method for preparing a solar cell, comprising the following steps: Step S100: A silicon substrate 10 is provided, the silicon substrate 10 having opposing first surfaces, second surfaces, and side surfaces connecting the first surfaces and the second surfaces.

[0106] For example, the silicon substrate 10 can be N-type or P-type monocrystalline silicon, polycrystalline silicon or microcrystalline silicon. For instance, the silicon substrate 10 can be an N-type monocrystalline silicon wafer.

[0107] In step S200, an integral and continuous pyramid structure 110 is formed on the first surface and the side surface. The pyramid structure 110 may be formed during the double-sided texturing process of the silicon substrate 10, that is, during texturing, the pyramid structure 110 is formed on the first surface, the second surface and the side surface.

[0108] For example, the silicon wafer is first pre-cleaned to remove impurities from its surface. The pre-cleaning solution can be an alkaline solution and hydrogen peroxide, with a volume ratio of 1:1 to 1:6. The pre-cleaning temperature is 60℃ to 80℃, and the pre-cleaning time is 1 min to 4 min. Next, the silicon wafer is texturized. The volume ratio of the alkaline solution to the texturizing additive is 2:1 to 8:1, the texturizing temperature is 60℃ to 85℃, and the texturizing time is 4 min to 8 min. The resulting pyramid structure 110 has a base dimension of 1 μm to 6 μm, a height of 1 μm to 5 μm, and a specific surface area of ​​1 to 3.

[0109] In step S300, a first doped semiconductor layer 14 and a first glass semiconductor layer located on the side of the first doped semiconductor layer 14 facing away from the silicon substrate 10 are formed on the first surface, and the first doped semiconductor layer 14 and the first glass semiconductor layer are formed in a portion of the side and second surfaces.

[0110] For example, a boron-doped silicon layer (the first doped semiconductor layer) is formed by boron diffusion deposition on the first surface. Simultaneously, a borosilicate glass layer (the first glass semiconductor layer) is grown on the surface of the boron-doped silicon layer. Due to the presence of wrap-around plating, the sides of the silicon substrate and portions of the second surface are wrapped with boron-doped silicon wrap-around plating and borosilicate glass wrap-around plating to form a boron-doped silicon wrap-around plating layer and a borosilicate glass wrap-around plating layer. Specifically, when depositing boron on the first surface, the doping depth can be 300 nm to 1000 nm, the doping surface concentration can be 2E18 to 5E19, the thickness of the borosilicate glass layer (BSG) is 40 nm to 120 nm, and the doping source can be BCl3. Of course, the first doped semiconductor layer can also be a doped silicon phosphide layer, and the first glass semiconductor layer can be a silicon phosphide glass layer.

[0111] Step S400: Remove the first glass semiconductor layer and the first doped semiconductor layer on the second surface and the portion of the side surface adjacent to the second surface, and remove the pyramid structure in a portion of the side surface, so that the area on the side surface where the pyramid structure has not been removed and is close to the first surface becomes the first region 101, and the pyramid structure located in the first region 101 becomes the first pyramid structure 106.

[0112] For example, firstly, the borosilicate glass layer and doped borosilicate layer deposited on the second surface and the side surface adjacent to the second surface in step S300 are removed. This step can be performed using a chain-type single-sided pickling device to remove the borosilicate glass layer on the second surface, using an HF aqueous solution at room temperature, with an HF to water ratio of 1:0.3 to 1:3. Specifically, the second surface is placed on the chain-type single-sided pickling device with the first surface facing upwards. Only the portion of the second surface and the side surface adjacent to the second surface is removed, ensuring that the borosilicate glass layer on the second surface is completely removed, while the doped borosilicate layer and borosilicate glass layer on the first surface remain unaffected. Then, a pre-cleaning with an alkaline solution and / or hydrogen peroxide is performed, where the volume ratio of the alkaline solution to hydrogen peroxide is 1:1 to 1:10, the pre-cleaning temperature is 60℃ to 80℃, and the pre-cleaning time is 1 min to 5 min. Finally, alkaline polishing is performed on the second surface and the portions of the side adjacent to the second surface. In the alkaline polishing solution, the volume ratio of alkaline solution to polishing additive can be 3:1 to 10:1, the alkaline polishing temperature can be 60℃ to 85℃, and the alkaline polishing time is 3 min to 8 min. After alkaline polishing, the pyramid structure on the second surface is polished to obtain the third texture structure on the second surface. The pyramid structure portion on the upper part of the side is polished to form a polished surface, leaving only the first pyramid structure 106 adjacent to the first surface, forming the first region 101. The remaining regions except for the first region 101 are recessed into the silicon substrate 10 relative to the first region 101.

[0113] In step S500, a second doped semiconductor layer 12 and a second glass semiconductor layer are formed on the second surface and on the side of the second doped semiconductor layer 12 facing away from the silicon substrate 10. The second doped semiconductor layer and the second glass semiconductor layer are also formed in at least a portion of the side surface and the first surface.

[0114] For example, a tunneling oxide layer 11 and a doped silicon phosphate layer (as the second doped semiconductor layer) are grown on the second side of the alkaline-polished silicon wafer. Simultaneously, a silicon phosphate glass layer (as the second glass semiconductor layer) is grown on the surface of the doped silicon phosphate layer. This effectively separates minority and majority carriers, improves passivation, reduces corrosion of the silicon substrate during printing, and improves contact performance. The thickness of the doped silicon phosphate layer can be 80 nm to 250 nm. In this case, the first and side surfaces are coated with the doped silicon phosphate layer and the silicon phosphate glass layer.

[0115] Step S600: Remove the second doped semiconductor layer and the second glass semiconductor layer from the first region 101 on the side and the remaining area on the side, and form a second pyramid structure 107 in the area outside the first region 101 on the side to obtain the second region 102. Then, form a third pyramid structure and / or a first texture structure 109 in the area adjacent to the second side outside the first region 101 and the second region 102 on the side to obtain the third region 103. Figure 6The first texture structure 109 shown; wherein, the second region 102 is recessed into the silicon substrate 10 relative to the first region 101, and the first distance D1 of the recess is 2μm~10μm.

[0116] For example, firstly, the phosphorosilicon glass layer and doped phosphorosilicon layer deposited on the first and side surfaces in step S500 are removed. This step can be performed using a chain-type single-sided cleaning device to remove the phosphorosilicon glass layer on the first and side surfaces. The chain-type acid washing is carried out at room temperature using an HF aqueous solution, with an HF to water ratio of 1:3 to 1:15. Then, a portion of the side surface is etched and texturized. The original tower base structure on the side surface is further etched, increasing the one-dimensional size of the tower base structure, resulting in the first texture structure 109, as shown below. Figure 6 As shown, texturing of the side portion creates a third pyramid structure, resulting in a third region 103 that combines the first texture structure 109 and the third pyramid structure. The remaining regions, excluding the first region 101 and the third region 103, are texturized to form a second pyramid structure 107, creating a second region 102 that is recessed into the silicon substrate 10 relative to the first region 101, with a first recess distance D1 of 2 μm to 10 μm. The third recess distance D3 of the second region 102 relative to the third region 103 into the silicon substrate 10 is 0.1 μm to 5 μm. The volume ratio of the alkaline solution to the texturing additive used in texturing is 2:1 to 8:1, the alkaline texturing temperature is 60℃ to 85℃, and the texturing time is 3 min to 8 min.

[0117] In step S700, a passivation layer 13 is formed on the first surface, the second surface, and the side surface.

[0118] For example, an aluminum oxide layer 131 is simultaneously formed on the first, second, and side surfaces of a silicon wafer using atomic layer deposition (ALD) technology. The thickness of the aluminum oxide layer 131 can be 2 nm-20 nm. Too thick a layer may cause film bursting, while too thin a layer cannot effectively passivate the silicon substrate surface or the surface of the film layer in the solar cell. Then, a silicon nitride layer 132 is deposited on both the front and back surfaces of the silicon wafer using plasma-enhanced chemical vapor deposition (PECVD) to passivate the silicon wafer surface, reduce surface recombination, and improve the open-circuit voltage and fill factor. Simultaneously, the silicon nitride layer 132 protects the silicon wafer, reducing contamination and mechanical damage. Specifically, the thickness of the front silicon nitride layer 132 can be 65 nm-85 nm, with a refractive index of 1.7-2.2, while the thickness of the back silicon nitride layer 132 can be 70 nm-100 nm, with a refractive index of 2-2.4.

[0119] In step S800, a metallization structure is formed on the passivated silicon wafer using methods such as screen printing or electroplating, namely, the first electrode 16 and the second electrode 15. The metal paste can be a silver alloy, silver-copper alloy, copper alloy, nickel alloy, etc. The paste is solidified by a low-temperature sintering process, and then the hydrogen passivation effect is improved by light injection. Finally, a good ohmic contact is formed using laser-assisted sintering contact technology (LECO) to complete the fabrication of the solar cell.

[0120] When the above technical solution is adopted, the solar cell described in the first aspect can be obtained by the method of preparing the solar cell. Therefore, it has the same beneficial effects as the solar cell described in any of the above embodiments, and will not be repeated here.

[0121] In some embodiments, after forming the second doped semiconductor layer 12 and the second glass semiconductor layer on the side of the second doped semiconductor layer 12 facing away from the silicon substrate 10 in step S500, and before removing the second doped semiconductor layer and the second glass semiconductor layer on the first region 101 of the side surface and the remaining portion of the side surface in step S600, the fabrication method further includes the following steps: Step S501: The laser irradiates a portion of the second glass semiconductor layer on the second surface.

[0122] For example, when a phosphosilicate glass layer is formed on the second surface, the phosphosilicate glass layer on the second surface is laser-patterned. The laser-irradiated area is a non-metallized region, which is used to form the trench region 105 later. Through high-energy laser irradiation, the laser acts on the phosphosilicate glass layer for a short time, causing the phosphosilicate glass to be modified, porous, or vaporized, reducing the protective ability of the phosphosilicate glass layer in the laser-irradiated area. This ensures that a reaction rate gradient is formed between the laser-irradiated area and the non-laser-irradiated area during subsequent alkaline corrosion. The laser-irradiated area can be corroded as required, while the non-laser-irradiated area remains unaffected by the protection of the phosphosilicate glass layer. The laser wavelength can be 300nm~600nm, and the laser-opening width can be 250μm~800μm.

[0123] Subsequently, step S600 further includes removing the second glass semiconductor layer and the second doped semiconductor layer from the area on the second surface that was irradiated by the laser, to obtain the trench region 105, and forming a texture structure in the trench region 105, the texture structure including the fourth pyramid structure 108 or the second texture structure.

[0124] For example, while removing the doped silicon phosphate layer and silicon phosphate glass layer on the first region 101 and the remaining areas of the side, and forming a second pyramid structure 107 in the area outside the first region 101 on the side, the second surface is etched. The doped silicon phosphate layer in the non-laser irradiated area of ​​the second surface is not etched due to the protection of the silicon phosphate glass layer, forming a doped region 104. The laser irradiated area on the second surface is etched by alkaline corrosion due to the destruction of the silicon phosphate glass layer, and further etched downwards to tunnel through the oxide layer 11 and the silicon substrate 10, forming a trench region 105. After texturing etching, a fourth pyramid structure 108 or a second textured structure of the trench region 105 is obtained.

[0125] With the above technical solution, the trench region 105 does not have a second doped semiconductor layer, which reduces the parasitic absorption caused by the second doped semiconductor layer. The depth of the downward indentation can ensure that the inner expansion layer below the trench region 105 is removed, reducing the recombination problem caused by the high doping concentration in the non-power generation area. The trench region 105 is further provided with a fourth pyramid structure 108, which can further increase the light trapping effect of the second side of the bifacial cell, increase the bifaciality of the overall cell, and comprehensively improve the cell performance.

[0126] Based on the solar cells described in any of the above embodiments, this invention also provides a photovoltaic module, including a cell string, interconnecting components, and an encapsulation layer. The cell string is formed by electrically connecting a plurality of solar cells as described in any of the above embodiments; the interconnecting components are electrically connected to the solar cells; and the encapsulation layer covers the surface of the cell string. The encapsulation layer may include cover plates and back plates located on both sides of the cell string, as well as encapsulating films and other structures for encapsulation. Because this photovoltaic module uses the solar cells described in any of the above embodiments, it has the same beneficial effects as any of the above embodiments.

[0127] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0128] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A solar cell, characterized in that, It includes a silicon substrate, a first doped semiconductor layer, a second doped semiconductor layer, and a passivation layer; The silicon substrate has opposing first surfaces, second surfaces, and a side surface connecting the first surface and the second surface; The first doped semiconductor layer is disposed on the first surface; The second doped semiconductor layer is disposed on the second surface, and the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types. The passivation layer is disposed on the first surface, the second surface, and the side surface, and the passivation layer is located on the side of the first doped semiconductor layer and the second doped semiconductor layer away from the silicon substrate; The first face has multiple pyramid structures, and the side includes a first area and a second area distributed sequentially along the direction from the first face to the second face; the first area is adjacent to the first face, and the second area is adjacent to the first area; The second region is recessed into the silicon substrate by a first distance relative to the first region; The second surface includes alternating trench regions and doped regions, the trench regions being recessed into the silicon substrate by a second distance relative to the doped regions; the second doped semiconductor layer is located in the doped regions, and the passivation layer is located in the trench regions and the doped regions; Wherein, the first distance is greater than or equal to the second distance.

2. The solar cell according to claim 1, characterized in that, The second distance is 0.5μm to 9μm, and / or the first distance is 2μm to 10μm.

3. The solar cell according to claim 1 or 2, characterized in that, The first distance is 3μm to 6μm, and / or the second region has multiple second pyramid structures.

4. The solar cell according to claim 1, characterized in that, The second surface includes alternating trench regions and doped regions, wherein the trench regions are recessed into the silicon substrate relative to the doped regions, and the trench regions include a fourth pyramid structure or a second texture structure; The second doped semiconductor layer is located in the doped region, and the passivation layer is located in the trench region and the doped region.

5. The solar cell according to claim 4, characterized in that, When the groove region includes the second texture structure, the second distance is 0.5μm~3.5μm; Alternatively, when the trench region includes the fourth pyramid structure, the second distance is 3.5μm~9μm.

6. The solar cell according to claim 4 or 5, characterized in that, The average one-dimensional dimension of the base of the fourth pyramid structure ranges from 0.5μm to 6μm; and / or, the height of the fourth pyramid structure ranges from 0.5μm to 5μm.

7. The solar cell according to claim 1, characterized in that, The side also includes a third region adjacent to the second side, the second region being located between the first region and the third region, the third region having multiple third pyramid structures and / or multiple first texture structures.

8. The solar cell according to claim 1 or 7, characterized in that, The side surface also includes a third region, which is adjacent to the second surface. The second region is located between the first region and the third region. The second region is recessed into the silicon substrate relative to the third region, and the recessed distance is a third distance, which is 0.1 μm to 5 μm.

9. The solar cell according to claim 1, characterized in that, The thickness of the passivation layer located on the trench region is less than the thickness of the passivation layer located on the doped region.

10. The solar cell according to claim 1, characterized in that, The passivation layer includes a second passivation layer and a third passivation layer, wherein the second passivation layer is disposed on the first surface and / or the second surface, and the third passivation layer is disposed on the side surface; The thickness of the third passivation layer is greater than the thickness of the second passivation layer.

11. The solar cell according to claim 10, characterized in that, The difference between the thickness of the third passivation layer and the thickness of the second passivation layer is greater than or equal to 20 nm.

12. The solar cell according to claim 10, characterized in that, The thickness of the second passivation layer on the first surface is 65nm~95nm, and / or the thickness of the second passivation layer on the second surface is 70nm~100nm.

13. The solar cell according to claim 1, characterized in that, The passivation layer includes a second passivation layer, which is disposed on the first surface and / or the second surface; The second passivation layer located on the second surface is disposed on the surface of the doped region and the trench region, and the second passivation layer located in the doped region is disposed on the side of the second doped semiconductor layer away from the silicon substrate; The thickness of the second passivation layer located in the trench region is different from the thickness of the second passivation layer located in the doped region.

14. The solar cell according to claim 1, characterized in that, In the thickness direction of the solar cell, the length of the second region accounts for 50% to 95% of the thickness of the solar cell.

15. The solar cell according to claim 4, characterized in that, The doped region has a third texture structure, which exhibits a non-pyramid-shaped microstructure morphology and includes at least two or more first substructures that are partially stacked, wherein the bottom surface of the first substructure is a polygonal plane. Wherein, the one-dimensional dimension of the bottom surface of the first substructure is larger than the one-dimensional dimension of the bottom surface of the second texture structure in the groove region.

16. The solar cell according to claim 4, characterized in that, When the trench region includes a fourth pyramid structure, the dimensional consistency of the pyramid structure located on the first face is better than the dimensional consistency of the fourth pyramid structure located in the trench region.

17. The solar cell according to claim 1, characterized in that, The first area has multiple first pyramid structures, and the second area has multiple second pyramid structures.

18. The solar cell according to claim 17, characterized in that, When the trench region includes a fourth pyramid structure, the size consistency of the second pyramid structure located in the second region is comparable to the size consistency of the fourth pyramid structure located in the trench region.

19. The solar cell according to claim 17, characterized in that, The dimensional consistency of the pyramid structure located on the first face is better than that of the second pyramid structure located in the second area.

20. The solar cell according to claim 17, characterized in that, The average one-dimensional dimension of the base of the first pyramid structure ranges from 0.5 μm to 6 μm; and / or, the height of the first pyramid structure ranges from 0.5 μm to 5 μm; The average one-dimensional dimension of the base of the second pyramid structure ranges from 0.5μm to 6μm; and / or, the height of the second pyramid structure ranges from 0.5μm to 5μm.

21. The solar cell according to claim 4, characterized in that, The trench area includes the fourth pyramid structure, and the ratio of the height of the fourth pyramid structure to the depth of the trench area is in the range of 1:1.5 to 1:

4.

22. The solar cell according to claim 4, characterized in that, The inclination angle of the sidewall of the trench area relative to the second face is α, and the inclination angle of the sidewall connecting the base and top of the fourth pyramid structure relative to the base is β. The ratio of β to α ranges from 1:0.5 to 1:2; And / or, α ranges from 35° to 65°.

23. A photovoltaic module, characterized in that, include: A battery string, the battery string comprising a plurality of solar cells and interconnects as described in any one of claims 1 to 22, the interconnects being electrically connected to the solar cells; And an encapsulation layer that covers the surface of the battery string.

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