Display panel, electronic device including the same, and method for manufacturing the display panel

Abstract

A display panel, an electronic device including the display panel, and a method for manufacturing the display panel are provided. The display panel having a display area and a non-display area adjacent to the display area includes: a base layer including a first resin layer and a second resin layer defining an upper resin opening; a pad electrode between the first resin layer and the second resin layer; a driving element layer including a barrier layer defining a barrier opening, a data line over the barrier layer, a conductive pattern including a pad conductive portion, an insulating layer defining a connection opening and a main opening, and a bridge conductive pattern; and a display element layer on the second resin layer.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0099240, filed on July 26, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display panel with improved reliability, an electronic device including the display panel, and a method for manufacturing the display panel. Background Technology

[0003] Electronic devices such as smartphones, tablets, laptops, car navigation systems, and smart TVs are under development. These electronic devices include display devices used to provide information.

[0004] Various types of display devices are being developed to meet user experience (UX) and user interface (UI) requirements. Research is underway to provide display devices with a wide display area and a narrow non-display area. Summary of the Invention

[0005] This disclosure provides a display panel with improved reliability due to the reduction in the size of the non-display area.

[0006] This disclosure provides an electronic device including a display panel with a reduced non-display area and improved reliability.

[0007] This disclosure provides a method for manufacturing a display panel with a reduced non-display area and improved reliability.

[0008] Embodiments of this disclosure provide a display panel having a display area and a non-display area adjacent to the display area. The display panel includes: a substrate layer comprising a first resin layer and a second resin layer, the first resin layer being stacked with the display area and the non-display area, the second resin layer being on top of the first resin layer and defining an upper resin opening stacked with the non-display area; a pad electrode being between the first and second resin layers, stacked with the non-display area, and a portion of the upper surface of the pad electrode being exposed through the upper resin opening; a driving element layer including: a barrier layer being on top of the second resin layer and defining a barrier opening stacked with the upper resin opening; a data line being on top of the barrier layer; a conductive pattern including a pad conductive portion in the upper resin opening and contacting the pad electrode and a data conductive portion contacting the data line; and an insulating layer being on the conductive pattern, defining a layer that exposes a portion of the data conductive portion. The structure includes an exposed connection opening and a main opening superimposed on the upper resin opening; a bridge conductive pattern on the conductive pattern and the insulating layer, which contacts the conductive portion of the pad through the upper resin opening and contacts the conductive portion of the data through the connection opening; and a display element layer including a light-emitting element superimposed on the second resin layer and the display area, wherein transistors of the driving element layer are electrically connected to the light-emitting element and electrically connected to the data line, wherein the blocking opening is defined by a protruding blocking side surface adjacent to the connection opening and by a main blocking side surface surrounding a portion of the upper resin opening in the plan view, wherein the main opening is defined by a protruding insulating side surface adjacent to the connection opening and by a main insulating side surface surrounding a portion of the upper resin opening in the plan view and superimposed on the main blocking side surface in the plan view, and wherein the protruding blocking side surface is between the protruding insulating side surface and the connection opening.

[0009] The display panel may also include a first substrate insulating layer, which is located between a first resin layer and a second resin layer and beneath a portion of the pad electrode.

[0010] The display panel may also include a second substrate insulating layer between the first substrate insulating layer and the second resin layer, and has a portion on the pad electrode.

[0011] The first and second substrate insulating layers may include silicon oxide.

[0012] In a plan view, the upper resin opening can have a larger size than the connecting opening.

[0013] In a plan view, the upper resin opening can have a smaller size than the main opening.

[0014] The insulating layer can be overlapped with the boundary between the pad conductive portion and the data conductive portion.

[0015] The distance from the protruding barrier side surface to the center of the upper resin opening can be greater than the distance from the main barrier side surface to the center of the upper resin opening.

[0016] The barrier layer may include at least one of silicon oxide and silicon nitride.

[0017] The blocking opening may be defined by a protruding blocking side surface, a main blocking side surface, and a sub-blocking side surface connecting the protruding blocking side surface and the main blocking side surface, wherein the protruding blocking side surface is substantially parallel to a first direction, and wherein the sub-blocking side surface is substantially parallel to a second direction intersecting the first direction.

[0018] The pad electrode can be configured as multiple pad electrodes, which are spaced apart in the first direction.

[0019] The upper resin opening can be configured as multiple upper resin openings, and portions of the upper surfaces of multiple pad electrodes are exposed through multiple upper resin openings.

[0020] The connection opening can be located between the upper resin opening and the display area.

[0021] The upper resin opening can be located between the connection opening and the display area.

[0022] The upper resin opening may include a first upper resin opening and a second upper resin opening, the second upper resin opening being spaced apart from the first upper resin opening in a fourth direction, the fourth direction intersecting the first direction and a second direction intersecting the first direction, and wherein the connecting opening includes a first connecting opening and a second connecting opening, the first connecting opening being spaced apart from the first upper resin opening in a second direction, and the second connecting opening being spaced apart from the second upper resin opening in a direction opposite to the second direction.

[0023] The connection opening may include: a first-first connection opening adjacent to the display area; and a first-second connection opening spaced apart from the first-first connection opening in the plan view, with the upper resin opening between the first-first connection opening and the first-second connection opening.

[0024] Embodiments of this disclosure provide an electronic device comprising: a flexible circuit board; and a display panel having a display area and a non-display area adjacent to the display area on the flexible circuit board, and comprising: a substrate layer including a first resin layer and a second resin layer, the first resin layer being stacked with the display area and the non-display area and defining a lower resin opening, the second resin layer being on the first resin layer and defining an upper resin opening stacked with the non-display area; a pad electrode being stacked with the non-display area between the first resin layer and the second resin layer, a portion of the lower surface of the pad electrode contacting the flexible circuit board through the lower resin opening, and a portion of the upper surface of the pad electrode being exposed through the upper resin opening; a driving element layer including: a barrier layer being on the second resin layer and defining a barrier opening stacked with the upper resin opening; a data line being on the barrier layer; and a conductive pattern including a pad conductive portion in the upper resin opening and contacting the pad electrode and a contact... The data cable has a data conductive portion; an insulating layer on the conductive pattern defining a connection opening that exposes a portion of the data conductive portion and a main opening superimposed on an upper resin opening; a bridge conductive pattern on the conductive pattern and the insulating layer, contacting a pad conductive portion through the upper resin opening and contacting the data conductive portion through the connection opening; and a display element layer including a light-emitting element on a second resin layer, superimposed on a display area and electrically connected to the data cable, wherein a blocking opening is defined by a protruding blocking side surface adjacent to the connection opening and by a main blocking side surface surrounding a portion of the upper resin opening in a plan view, wherein the main opening is defined by a protruding insulating side surface adjacent to the connection opening and by a main insulating side surface surrounding a portion of the upper resin opening in a plan view and superimposed on the main blocking side surface in a plan view, and wherein the protruding insulating side surface is between the protruding blocking side surface and the upper resin opening.

[0025] The driving element layer may also include transistors, which are electrically connected to the light-emitting element and electrically connected to the data line.

[0026] The data cable can be stacked with the display area and the non-display area.

[0027] Embodiments of this disclosure provide a method for manufacturing a display panel, the method comprising the following steps: forming a pad electrode on a first resin layer; forming a preliminary second resin layer over the first resin layer, the preliminary second resin layer covering the pad electrode; forming a preliminary barrier layer over the preliminary second resin layer; etching a portion of the preliminary second resin layer to form a second resin layer, the second resin layer defining an upper resin opening to expose a portion of the upper surface of the pad electrode; etching a portion of the preliminary barrier layer to form a barrier layer, the barrier layer defining a barrier opening overlapping the upper resin opening; forming a data line on the barrier layer; forming a conductive pattern, the conductive pattern including a pad conductive portion in the upper resin opening and contacting the pad electrode and a data conductive portion contacting the data line; forming a preliminary insulating layer on the conductive pattern; etching the preliminary second resin layer; and etching a preliminary barrier layer on the first resin layer. A portion of an insulating layer is provided on the conductive pattern to define a connection opening that exposes a portion of the data conductive portion, and to define a main opening that overlaps with the upper resin opening; and a bridge conductive pattern is provided on the conductive pattern and the insulating layer to contact the pad conductive portion through the upper resin opening and to contact the data conductive portion through the connection opening, wherein the blocking opening is defined by a protruding blocking side surface adjacent to the connection opening, and by a main blocking side surface surrounding a portion of the upper resin opening in the plan view, wherein the main opening is defined by a protruding insulating side surface adjacent to the connection opening and a main insulating side surface surrounding a portion of the upper resin opening in the plan view and overlapping with the main blocking side surface, and wherein the protruding blocking side surface is between the protruding insulating side surface and the connection opening.

[0028] According to the display panel and the electronic device including the display panel, the insulating layer that defines the main opening and the connection opening and the bridge conductive pattern that is electrically connected to the conductive pattern through the main opening and the connection opening are located on the conductive pattern that transmits signals from the circuit board to the data line. Therefore, the size of the non-display area is reduced, while the reliability of the display panel is improved. Attached Figure Description

[0029] The above and other aspects of this disclosure will readily become apparent when considered in conjunction with the accompanying drawings, and by referring to the following detailed description, in which: Figure 1 This is a perspective view of an electronic device according to one or more embodiments of the present disclosure; Figure 2 This is an exploded perspective view of an electronic device according to one or more embodiments of the present disclosure; Figure 3 It is along Figure 2 A cross-sectional view of the display device taken by line I-I'; Figure 4 This is a cross-sectional view of a display module according to one or more embodiments of the present disclosure; Figure 5This is a plan view of a display panel according to one or more embodiments of the present disclosure; Figure 6 This is a cross-sectional view of a display module according to one or more embodiments of the present disclosure; Figure 7A This is a plan view of an input sensor according to one or more embodiments of the present disclosure; Figure 7B It is along Figure 7A A cross-sectional view of the input sensor taken by line II-II'; Figure 8 This is an enlarged plan view of the non-display area of ​​a display module according to one or more embodiments of the present disclosure; Figure 9 It is along Figure 8 A cross-sectional view of the display module taken by line III-III'; Figure 10 This is an enlarged plan view of the non-display area of ​​a display module according to one or more embodiments of the present disclosure; Figure 11 yes Figure 10 Enlarged plan view of region AA'; Figure 12 It is along Figure 11 A cross-sectional view of the display panel taken by line IV-IV'; Figure 13 yes Figure 12 Enlarged plan view of area BB'; Figure 14 This is an enlarged plan view of the non-display area of ​​a display module according to one or more embodiments of the present disclosure; Figure 15 yes Figure 14 A magnified plan view of region CC'; Figure 16 It is along Figure 15 A cross-sectional view of the display panel taken by line V-V'; Figure 17 This is a flowchart illustrating a method of manufacturing a display panel according to one or more embodiments of the present disclosure; and Figures 18 to 25 This is a view illustrating the process of manufacturing a display panel according to one or more embodiments of the present disclosure. Detailed Implementation

[0030] Aspects of some embodiments of this disclosure and methods of implementing them can be more readily understood by referring to the detailed description and accompanying drawings of the embodiments. The described embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey aspects of this disclosure to those skilled in the art. Therefore, redundant processes, elements, and techniques that are irrelevant or unrelated to the description of the embodiments, or that are not essential for a person of ordinary skill in the art to fully understand aspects of this disclosure, may be omitted. Unless otherwise stated, the same reference numerals, characters, or combinations thereof denote the same elements throughout the drawings and written description; therefore, repeated descriptions may be omitted.

[0031] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. In describing embodiments, the use of “may,” “can,” or “may not” corresponds to one or more embodiments of this disclosure.

[0032] Those skilled in the art will understand that, in view of the whole of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined in part or in whole, or combined with each other, and may be technically interlocked and operated in a variety of suitable ways, and each embodiment may be implemented independently of each other or in combination with each other in any suitable way, unless otherwise stated or implied.

[0033] In the accompanying drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In other words, the disclosure is not limited thereto because the dimensions and thicknesses of elements in the drawings are arbitrarily shown for ease of description. Furthermore, crosshairs and / or shading are typically provided in the drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, scale, commonalities and / or any other characteristics, properties, etc., of the elements shown.

[0034] Various embodiments are described herein with reference to cross-sectional views that serve as schematic diagrams of examples and / or intermediate structures. Thus, variations in the illustrated shapes are contemplated due to factors such as manufacturing techniques and / or tolerances. Furthermore, the specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concepts of this disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the shapes shown for elements, layers, or regions, but rather include deviations in shape caused, for example, by manufacturing processes.

[0035] For example, an injection region shown as rectangular will typically have circular or curved features at its edges and / or a gradient of injection concentration, rather than a binary variation from the injection region to the non-injection region. Similarly, the buried region formed by injection may result in some injection in the region between the buried region and the surface through which the injection occurs.

[0036] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “lower side,” “below,” “above,” “above,” “higher,” “upper side,” “side” (e.g., as in “sidewall”) may be used herein to describe the relationship of one element or feature to another, as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below,” “under,” or “below” other elements or features will subsequently be oriented “above” said other elements or features. Thus, the example terms “below” and “below” can cover both above and below orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly. Similarly, when the first part is described as being arranged "on" the second part, this means that the first part is arranged on the upper or lower side of the second part, and is not limited to the upper side of the second part based on the direction of gravity.

[0037] Furthermore, the phrase "in a plan view" means when viewing a portion of the object from above, and the phrase "in a schematic sectional view" means when viewing a schematic section taken by vertically cutting a portion of the object from the side. The term "overlay" or variations thereof means that the first object may be above, below, or to the side of the second object, or vice versa. Furthermore, the term "overlay" can include stacking, facing or oriented, extending over, covering or partially covering, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art. The expression "not overlay" can include meanings such as "spaced apart from," "offset from," or "offset from," and any other suitable equivalent as will be understood and appreciated by one of ordinary skill in the art. The terms "facing" and "oriented" can mean that the first object may be directly or indirectly opposite the second object. In the case where a third object is placed between the first and second objects, the first and second objects, although still facing each other, can be understood as being indirectly opposite each other.

[0038] It will be understood that when an element, layer, region, or component (e.g., device, apparatus, circuit, wiring, electrode, terminal, conductive film, etc.) is referred to as being "formed on," "on," "connected to," or "(operably, functionally, or communicatively) incorporated into" another element, layer, region, or component, the element, layer, region, or component may be directly formed on, directly on, directly connected to, or directly incorporated into the other element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly incorporated into the other element, layer, region, or component, such that one or more intermediary elements, layers, regions, or components may exist. Additionally, this can collectively mean direct (or indirect) incorporation (or connection) and integral (or non-integral) incorporation (or connection). For example, when a layer, region, or component is referred to as "electrically connected" or "electrically bonded" to another layer, region, or component, the layer, region, or component may be directly electrically connected or directly bonded to the other layer, region, and / or component, or one or more intermediary layers, regions, or components may be present. One or more intermediary components may include switches, transistors, resistors, inductors, capacitors, diodes, etc. Therefore, connections are not limited to those shown in the accompanying drawings or detailed descriptions, and may also include other types of connections. In describing embodiments, unless explicitly described as a direct connection, the expression for a connection indicates an electrical connection, and "directly connected / directly bonded" or "directly on" means that one component is directly connected to or directly bonded to another component, or directly on another component without any intermediate components.

[0039] Furthermore, in this specification, when a portion of a layer, film, region, plate, etc., is formed on another portion, the forming direction is not limited to the upward direction, but includes forming the portion on a side surface or in the downward direction. Conversely, when a portion of a layer, film, region, plate, etc., is formed "below" another portion, this includes not only the case where the portion is "directly" "below" the other portion, but also the case where there is another portion between the portion and the other portion. Similarly, other expressions describing relationships between components, such as "between," "immediately between," "adjacent to," and "directly adjacent to," can be interpreted similarly. It will be understood that when an element or layer is referred to as "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or there may be one or more intervening elements or layers.

[0040] For the purposes of this disclosure, expressions such as “at least one of…”, “any one of…”, or “one or more of…” modify the entire list of elements without modifying any individual element within that list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z (e.g., XYZ, XY, YZ, and XZ) or any variation thereof. Similarly, the expression “at least one of A and B” can include A, B, or A and B. As used herein, “or” generally means “and / or”, and the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” can include A, B, or A and B. Similarly, expressions such as “at least one of…”, “multiple…”, “one of…”, and other prepositional phrases modify the entire list of elements before (or after) it, without modifying any individual elements within that list. When stating “C to D”, unless otherwise specified, it means C or greater and D or less.

[0041] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms do not correspond to a particular order, position, or priority, and are used only to distinguish one element, component, assembly, region, area, layer, segment, or part from another. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or segment described below may be referred to as a second element, component, region, layer, or segment. Describing an element as a “first” element does not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish different categories or sets of elements. For the sake of brevity, the terms “first,” “second,” etc., may respectively represent “first category (or first set),” “second category (or second set),” etc.

[0042] In this example, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0043] The terminology used herein is for the purpose of describing embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are intended to include the plural forms as well, and the plural forms are intended to include the singular forms as well. It will also be understood that when the terms “comprising,” “having,” and “including,” and “featuring,” are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0044] When one or more embodiments can be implemented differently, a particular process sequence can be performed differently than the described sequence. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of their description.

[0045] As used herein, the terms “basic,” “about,” “approximate,” and similar terms are used as approximate terms rather than as terms of degree and are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. For example, “basic” can include a range of + / - 5% of the corresponding value. As used herein, “about” or “approximate” includes the stated value and means: within an acceptable deviation range of the specific value as determined by one of ordinary skill in the art, taking into account the measurement under discussion and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.” Additionally, the expression “identical” can mean “substantially identical.” In other words, the expression “identical” can include a range that is tolerable by one of ordinary skill in the art. Other expressions may also be those from which “basic” has been omitted.

[0046] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the context of the relevant field and / or in this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0047] Figure 1 This is a perspective view of an electronic device ED according to one or more embodiments of the present disclosure. Figure 2 This is an exploded perspective view of an electronic device ED according to one or more embodiments of the present disclosure. Figure 3 It is along Figure 2 The sectional view of the display device DD taken by line I-I'.

[0048] Reference Figure 1 The electronic device ED may include a display surface DS defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. The electronic device ED can provide an image IM to a user through the display surface DS.

[0049] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA may display an image IM, while the non-display area NDA may not be displayed or may not be used to display an image. The non-display area NDA may (e.g., in a plan view) surround the display area DA. However, this disclosure should not be limited to or construed therein, and the shapes of the display area DA and the non-display area NDA may be varied.

[0050] In the following text, the direction substantially perpendicular to the plane defined by the first direction DR1 and the second direction DR2 may be referred to as the third direction DR3. The front and rear surfaces of each component of the electronic device ED may be distinguished from each other relative to the third direction DR3. In this disclosure, the expression "when viewed in a plane" or "in a plan view" may refer to the state viewed on the third direction DR3.

[0051] The electronic device ED can be a foldable electronic device configured to fold relative to a folding axis. The folding axis can be substantially parallel to a first direction DR1 or a second direction DR2, and the folding area can be defined within a portion of the display area DA. The electronic device ED can fold inward (inward folding) to allow a portion of the display area DA to face another portion of the display area DA, or it can fold outward (outward folding) to allow a portion of the display area DA not to face another portion of the display area DA.

[0052] Reference Figure 2 The electronic device ED may include a display device DD, an electronic module EM, a power module PSM, and a housing HM. The electronic device ED is schematically shown in... Figure 2 Furthermore, the electronic device ED may also include a mechanical structure (e.g., a hinge) to control the operation of the display device DD (e.g., folding or rolling operation).

[0053] The display device DD can generate an image IM and sense external input. The display device DD may include a window WM, an upper component UM, a display module DM, a lower component LM, a flexible circuit board FCB, and a driver chip DIC. The upper component UM may include components located above the display module DM, and the lower component LM may include components located below the display module DM.

[0054] The window WM can provide the front surface of the electronic device ED. The window WM may include a transmissive area TA and a frame area BZA. Figure 1 The display area DA and non-display area NDA of the display surface DS shown can be defined by a transmission area TA and a border area BZA. The transmission area TA can be the area through which the image passes, and the border area BZA can be the area covering the structure / component located below the window WM.

[0055] The display module (DM) may include at least the display panel (DP). Figure 2 Only the display panel DP is shown among the components of the display module DM. However, in addition to the display panel DP, the display module DM may also include additional components located on top of the display panel DP. The stacking structure of the display module DM will be described in detail later.

[0056] While not particularly limiting, the display panel DP can be an organic light-emitting display panel or an inorganic light-emitting display panel. The display panel DP may include those corresponding to... Figure 1 The display area DA and the non-display area NDA shown are the display area DP-DA and the non-display area DP-NDA. In this disclosure, the expression "area / part corresponds to another area / part" can mean "area / part is superimposed on another area / part". However, they should not be limited to having the same size as each other.

[0057] The pad (also known as a solder pad or solder pad) area PA can be defined on one side of the non-display area DP-NDA. The pad area PA can be electrically bonded or connected to the flexible circuit board FCB, which will be described later. The pad area PA can be defined in the rear surface of the display panel DP.

[0058] Display panels (DPs) can have a generally quadrilateral shape. The term "generally quadrilateral shape" as used herein can refer not only to the mathematical concept of a rectangle, but also to a shape that resembles a rectangle and is perceived as such by the user. For example, a generally quadrilateral shape can include a quadrilateral shape with rounded corners. Furthermore, the edges of a display panel (DP) with a generally rectangular shape should not be limited to straight lines, and the edges may have curved areas.

[0059] The upper component UM may include a protective film or an optical film. The optical film may include a polarizer or a retarder to reduce the reflection of external light. The lower component LM may include a protective film for the display panel DP, a support component for supporting the display panel DP, and a digitizer. The upper component UM and the lower component LM will be described in detail later.

[0060] Figure 2The flexible circuit board (FCB) shown can be located below the display panel (DP). The FCB can be bonded to the rear surface of the display panel (DP) and can electrically connect the display panel (DP) to the main circuit board. The FCB may include at least one insulating layer and at least one conductive layer. The conductive layer may include multiple signal lines.

[0061] The driver chip DIC can be mounted on the flexible circuit board FCB. The driver chip DIC may include driving circuitry (e.g., data driving circuitry) for driving the pixels of the display panel DP. Figure 2 The diagram illustrates a structure in which the driver chip DIC is mounted on a flexible circuit board FCB; however, this disclosure should not be limited thereto or thereby restricted. As an example, the driver chip DIC may be mounted on a display panel DP or a main circuit board.

[0062] The electronic module (EM) may include a control module, a wireless communication module, an image input module, an audio input module, an audio output module, a memory, and an external interface module. The EM may include a main circuit board, and the module may be mounted on the main circuit board or electrically connected to the main circuit board via a flexible circuit board. The EM may be electrically connected to the power supply module (PSM).

[0063] In one or more embodiments, the electronic device ED may further include a photoelectric module. The photoelectric module may be an electronic component that outputs or receives light signals. The photoelectric module may include a camera module and / or a proximity sensor. The camera module may capture images of external objects via an area of ​​the display panel DP.

[0064] Figure 2 The housing HM shown can be integrated into the display device DD (e.g., integrated into the window WM) to accommodate the aforementioned module. Although it should not be limited to or restricted by this, the housing HM is shown as having a monolithic shape. The housing HM may include multiple parts that are joined together, such as side surface edges and a bottom.

[0065] Figure 3 Further shown Figure 2 The adhesive layers AL1, AL2, AL3, and AL4 are not shown. The window WM may include a substrate BS and a border pattern BM located on the lower surface of the substrate BS. The substrate BS may include a synthetic resin film or a glass substrate. The substrate BS may have a multilayer structure. The substrate BS may include a thin glass substrate, a protective film located on the thin glass substrate, and an adhesive layer to which the thin glass substrate and the protective film are attached.

[0066] The border pattern BM can be a colored light-blocking layer and can be formed through a coating process. The border pattern BM can include a base material and pigments or dyes mixed with the base material. The border pattern BM can be combined with... Figure 1 The non-display area NDA and shown Figure 2 The border region BZA shown is stacked. The border pattern BM can be located on the lower surface of the substrate BS. When the substrate BS has a multilayer structure, the border pattern BM can be located at the interface defined between the multiple layers. For example, the border pattern BM can be located between a thin glass substrate and a protective film. In one or more embodiments, the window WM can include at least one of a hard coating, an anti-fingerprint layer, and an anti-reflective layer located on the upper surface of the substrate BS.

[0067] The upper component UM may include the upper membrane UF. The upper membrane UF may include a synthetic resin membrane. The synthetic resin membrane may include polyimide, polycarbonate, polyamide, cellulose triacetate, polymethyl methacrylate, or polyethylene terephthalate.

[0068] The upper UF film can absorb external impacts applied to the front surface of the display device DD. According to one or more embodiments, the display module DM may include a color filter as an anti-reflective component instead of a polarizing film, and in this case, the impact resistance of the display device DD relative to external impacts applied to its front surface may be reduced. The upper UF film can compensate for the reduction in impact resistance relative to external impacts caused by applying a color filter to the display module DM.

[0069] The top film UF can be superimposed on the border region BZA and the transmission region TA. The top film UF can also be superimposed on only a portion of the border region BZA. A portion of the border pattern BM can be exposed and not covered by the top film UF. According to one or more embodiments, the top film UF can be omitted. According to one or more embodiments, the top film UF can be replaced by an optical film including a polarizer and a retarder.

[0070] The upper component UM may further include a first adhesive layer AL1 for attaching the upper film UF to the window WM and a second adhesive layer AL2 for attaching the upper film UF to the display module DM. The first adhesive layer AL1 and the second adhesive layer AL2 may be a pressure-sensitive adhesive (PSA) film or an optically clear adhesive (OCA). The adhesive layers described below may also include the same adhesive as the first adhesive layer AL1.

[0071] The display module DM can be located below the upper film UF. The display module DM can be overlaid with the border area BZA and the transmission area TA. The display module DM can be completely overlaid with the upper film UF within the border area BZA. When viewed in a plane, the side surface of the display module DM can be aligned with the side surface of the upper film UF, and the corners of the display module DM can be aligned with the corners of the upper film UF.

[0072] In the bezel area BZA, the pad area PA of the display module DM can be stacked with the upper film UF. The portion of the display module DM corresponding to the pad area PA can be bonded to the lower surface of the upper film UF through the second adhesive layer AL2. Because the pad area PA is stacked with the upper film UF and the portion of the display module DM that is stacked with the pad area PA is bonded to the upper film UF, the upper film UF can adequately support the pad area PA when the flexible circuit board FCB is bonded to the pad area PA.

[0073] The lower component LM may include the lower membrane PF, the cover plate CP, the third adhesive layer AL3, and the fourth adhesive layer AL4. The lower component LM may also include a support plate and a digitizer.

[0074] The lower film PF can be located below the display module DM and can be bonded to the lower surface of the display module DM via a third adhesive layer AL3. The lower film PF can protect the lower part of the display module DM. The lower film PF can include a flexible synthetic resin film. As an example, the lower film PF can include polyethylene terephthalate or polyimide. However, this disclosure should not be limited thereto or thereby restricted.

[0075] The lower film PF can expose at least the pad area PA of the display module DM. The lower film PF can have an area smaller than that of the display module DM. For example, the lower film PF can be superimposed only on the display area DA.

[0076] The lower film PF can have essentially the same dimensions as the display module DM. The lower film PF can be configured to correspond to the pad area PA (see reference). Figure 2 The opening area PF-OP. Even if the lower film PF completely protects the lower surface of the display module DM, the opening area PF-OP can be defined to allow the flexible circuit board FCB to approach the pad area PA.

[0077] like Figure 3 As shown, the lower film PF can be bonded to the cover panel CP via a fourth adhesive layer AL4. The cover panel CP can increase resistance to compressive forces caused by external pressure. Therefore, the cover panel CP can reduce or prevent deformation of the display module DM. The cover panel CP can include flexible plastic materials, such as polyimide or polyethylene terephthalate. Alternatively, the cover panel CP can be a colored film with low light transmittance. The cover panel CP can absorb light incident upon it from the outside. As an example, the cover panel CP can be a black synthetic resin film. When the display device DD is viewed from above the window WM, the components located under the cover panel CP are not visible to the user.

[0078] In one or more embodiments, the support plate may also be located below the cover panel CP. The support plate may include a high-strength metallic material. The support plate may include a fiber-reinforced composite material. The support plate may include reinforcing fibers located in the matrix portion. The reinforcing fibers may be carbon fiber or glass fiber. The matrix portion may include a polymer resin. The matrix portion may include a thermoplastic resin. As an example, the matrix portion may include a polyamide resin or a polypropylene resin. For example, the fiber-reinforced composite material may be carbon fiber reinforced plastic (CFRP) or glass fiber reinforced plastic (GFRP).

[0079] Figure 4 This is a cross-sectional view of a display module DM according to one or more embodiments of the present disclosure.

[0080] Reference Figure 4 The display module DM may include a display panel DP and an input sensor ISL. The display panel DP may include a substrate layer 110, a driving element layer 120, and a light-emitting element layer 130. The display panel DP may also include an encapsulation layer 140.

[0081] The substrate layer 110 may be a flexible substrate that is bendable, foldable, or rollable. The substrate layer 110 may be a glass substrate, a metal substrate, or a polymer substrate. However, this disclosure should not be limited thereto or thereby restricted. According to one or more embodiments, the substrate layer 110 may be an inorganic layer, an organic layer, or a composite material layer. The substrate layer 110 may have substantially the same shape as the display panel DP.

[0082] The substrate layer 110 may include a first resin layer (see reference). Figure 12 110-B1), second resin layer (refer to ... Figure 12 (110-B2). Each of the first and second resin layers may comprise a polyimide resin. However, embodiments of this disclosure are not limited thereto. Reference will be made to... Figure 12 Describe the structure of the matrix layer 110 in detail.

[0083] The driving element layer 120 may be located on the substrate layer 110 (as used herein, "located on" can mean "above"). The driving element layer 120 may include multiple insulating layers, multiple semiconductor patterns, multiple conductive patterns, and multiple signal lines. The driving element layer 120 may include pixel driving circuitry. In the following text, unless otherwise stated, the statement "components A and B are located on the same layer" may mean that components A and B are formed by the same process and contain the same materials or have the same stacked structure. Conductive patterns or semiconductor patterns located on the same layer may be interpreted as described above.

[0084] The light-emitting element layer 130 may be located on the driving element layer 120. The light-emitting element layer 130 may include light-emitting elements and transistors. For example, the light-emitting element may include organic light-emitting materials, inorganic light-emitting materials, organic-inorganic light-emitting materials, quantum dots, quantum rods, micro-LEDs, or nano-LEDs. (See reference...) Figure 6 Describe the transistor in detail.

[0085] Encapsulation layer 140 may be located on light-emitting element layer 130. Encapsulation layer 140 may protect light-emitting element layer 130 (e.g., light-emitting element) from moisture, oxygen, and foreign matter such as dust particles. Encapsulation layer 140 may include at least one encapsulating inorganic layer. Encapsulation layer 140 may include a stacked structure in which a first encapsulating inorganic layer, an encapsulating organic layer, and a second encapsulating inorganic layer are sequentially stacked.

[0086] The input sensor ISL can be directly located on the display panel DP. The input sensor ISL can sense user input using either electromagnetic induction or capacitive methods. The display panel DP and the input sensor ISL can be formed through a continuous process. As used herein, the phrase "directly located on" can mean that there are no intermediate components between the input sensor ISL and the display panel DP. That is, a separate adhesive layer may not be required between the input sensor ISL and the display panel DP.

[0087] Figure 5 This is a plan view of a display panel DP according to one or more embodiments of the present disclosure. Figure 6 This is a cross-sectional view of a display module DM according to one or more embodiments of the present disclosure.

[0088] Reference Figure 5 The display panel DP may include a scan drive circuit SDC, multiple signal lines SGL, and multiple pixels PX. The pixels PX may be arranged in the display area DP-DA. Each pixel PX may include a light-emitting element and a pixel drive circuit connected to the light-emitting element. The scan drive circuit SDC, signal lines SGL, and pixel drive circuit may be included in... Figure 4 In the driving element layer 120 shown.

[0089] The scan drive circuit SDC may include a gate drive circuit. The gate drive circuit can generate multiple scan signals and sequentially output these scan signals to multiple scan lines GL, described later. The scan drive circuit SDC may also include a light-emitting drive circuit, separate from the gate drive circuit. The light-emitting drive circuit can output scan signals to another set of scan lines.

[0090] The scan drive circuit SDC may include multiple thin-film transistors formed using the same process as the pixel drive circuit (e.g., low-temperature polycrystalline silicon (LTPS) process or low-temperature polycrystalline oxide (LTPO) process).

[0091] The signal line SGL can include scan lines GL, data lines DL, power lines PL, and control signal lines CSL. Each scan line GL can be connected to a corresponding pixel PX, and each data line DL can be connected to a corresponding pixel PX. The power line PL can be connected to a pixel PX. The data line DL can provide data signals to the pixel PX. The control signal line CSL can provide control signals to the scan drive circuit SDC.

[0092] like Figure 8 As shown, the power line PL may include a first power line PL1 for receiving a first power supply voltage and a second power line PL2 for receiving a second power supply voltage having a level higher than the first power supply voltage. The first power supply voltage may be provided to the pixel PX via the first power line PL1, and the second power supply voltage may be provided to the pixel PX via the second power line PL2. Although multiple control signal lines CSL may be configured, in Figure 5 The diagram shows a control signal line CSL as a representative example.

[0093] Scan lines GL, data lines DL, and power lines PL can be stacked with the display area DP-DA and the non-display area DP-NDA, and control signal lines CSL can be stacked with the non-display area DP-NDA. Each of the signal lines GL can have a monolithic shape, but can include multiple portions located on different layers. The different portions, distinguished from each other by an insulating layer, can be connected to each other via contact holes defined through the insulating layer. For example, data line DL can include a first portion located in the display area DP-DA and a second portion located in the non-display area DP-NDA on a different layer from the first portion. The first and second portions can include different materials and can have different stacking structures.

[0094] The display panel DP may include insulating patterns DMP1 and DMP2. Figure 5 A first insulating pattern DMP1 and a second insulating pattern DMP2 are shown as representative examples. The first insulating pattern DMP1 and the second insulating pattern DMP2 can be arranged in the non-display area DP-NDA and can surround the display area DP-DA. Each of the first insulating pattern DMP1 and the second insulating pattern DMP2 can have a closed line shape. The first insulating pattern DMP1 and the second insulating pattern DMP2 can act as dams to reduce or prevent the possibility of liquid organic material spillage during the inkjet process used for the display panel DP.

[0095] Figure 6 Is with Figure 5 A cross-sectional view of the display module DM corresponding to pixel PX.

[0096] The pixel driving circuit PC that drives the light-emitting element LD can include multiple pixel driving elements. The pixel driving circuit PC can include multiple transistors S-TFT and O-TFT and capacitor Cst. Figure 6 The diagram shows silicon transistor S-TFT and oxide transistor O-TFT as representative examples of transistors. Figure 6 The pixel driving circuit PC is merely an example, and the components of the pixel driving circuit PC should not be limited to or restricted by it. The pixel driving circuit PC may consist of only one type of transistor, between silicon transistors (S-TFTs) and oxide transistors (O-TFTs).

[0097] Reference Figure 6 Even though the substrate layer 110 is shown as having a single-layer structure, the substrate layer 110 may include a first resin layer (see reference). Figure 12 110-B1) and the second resin layer (refer to) Figure 12 (110-B2). The substrate layer 110 may include a synthetic resin such as polyimide. The substrate layer 110 can be formed by coating a layer of synthetic resin onto a working substrate (or carrier substrate). The working substrate can be removed when the display module DM is completed by subsequent processes.

[0098] Reference Figure 6 The barrier layer 10br may be located on (e.g., on top of) the substrate layer 110. The barrier layer 10br may reduce or prevent the possibility of foreign matter entering from the outside. The barrier layer 10br may include at least one inorganic layer. The barrier layer 10br may include at least one of a silicon oxide layer and a silicon nitride layer. Each of the silicon oxide layer and the silicon nitride layer may be provided in multiples, and the silicon oxide layer may be stacked alternately with the silicon nitride layer.

[0099] The barrier layer 10br may include a lower barrier layer 10br1 and an upper barrier layer 10br2. A first shielding electrode BMLa may be located between the lower barrier layer 10br1 and the upper barrier layer 10br2. The first shielding electrode BMLa may correspond to a silicon transistor S-TFT. The first shielding electrode BMLa may include a metallic material (e.g., molybdenum).

[0100] The first shielding electrode BMLa can receive a bias voltage. The first shielding electrode BMLa can receive a first power supply voltage. The first shielding electrode BMLa can reduce or prevent the potential of the silicon transistor S-TFT caused by polarization from affecting it. The first shielding electrode BMLa can reduce or prevent external light from reaching the silicon transistor S-TFT. According to one or more embodiments, the first shielding electrode BMLa can be a floating electrode isolated from other electrodes or lines.

[0101] A buffer layer 10bf may be located on the barrier layer 10br. The buffer layer 10bf can reduce or prevent the diffusion of metal atoms or impurities from the substrate layer 110 to the first semiconductor pattern SC1 located thereon. The buffer layer 10bf may include at least one inorganic layer. The buffer layer 10bf may include a silicon oxide layer and a silicon nitride layer.

[0102] The first semiconductor pattern SC1 may be located on the buffer layer 10bf. The first semiconductor pattern SC1 may include a silicon semiconductor. As an example, the silicon semiconductor may include amorphous silicon or polycrystalline silicon. For example, the first semiconductor pattern SC1 may include low-temperature polycrystalline silicon.

[0103] The first semiconductor pattern SC1 can have different electrical properties depending on whether it is doped. The first semiconductor pattern SC1 may include a first region with relatively high conductivity and a second region with relatively low conductivity. The first region may be doped with N-type or P-type dopant. A P-type transistor may include a doped region doped with P-type dopant, and an N-type transistor may include a doped region doped with N-type dopant. The second region may be an undoped region or a region doped at a lower concentration than the first region. The first semiconductor pattern SC1 may be doped with N-type dopant.

[0104] The first region can have a higher conductivity than the second region and can be essentially used as an electrode or signal line. The second region can essentially correspond to the channel region (or active region) of a transistor. In other words, a portion of the first semiconductor pattern SC1 can be the channel of a silicon transistor S-TFT, another portion of the first semiconductor pattern SC1 can be the source or drain of a silicon transistor S-TFT, and other portions of the first semiconductor pattern SC1 can be connecting electrodes or connecting signal lines.

[0105] The source region SE1, channel region (or active region) AC1, and drain region DE1 of a silicon S-TFT can be formed by a first semiconductor pattern SC1. The source region SE1 and drain region DE1 can extend from the channel region AC1 in opposite directions to each other.

[0106] The first insulating layer 10 may be located on the buffer layer 10bf. The first insulating layer 10 may cover the first semiconductor pattern SC1. The first insulating layer 10 may be an inorganic layer. The first insulating layer 10 may have a single-layer structure of silicon oxide. However, this disclosure should not be limited thereto or thereby. The inorganic layer of the driving element layer 120, described later, may have a single-layer or multi-layer structure and may include at least one of the materials described above. However, this disclosure should not be limited thereto or thereby.

[0107] The gate GT1 of the silicon S-TFT can be located on the first insulating layer 10. The gate GT1 can be part of a metal pattern. The gate GT1 can be stacked with the channel region AC1. The gate GT1 can be used as a mask in the process of doping the first semiconductor pattern SC1. The first electrode CE10 of the capacitor Cst can be located on the first insulating layer 10. Figure 6 Unlike those shown, the gate GT1 and the first electrode CE10 can be integrally arranged together.

[0108] The second insulating layer 20 may be located on the first insulating layer 10 and may cover the gate GT1. The upper electrode may also be located on the second insulating layer 20 to be stacked with the gate GT1. The second electrode CE20 may be located on the second insulating layer 20 to be stacked with the first electrode CE10. When viewed in a plane, the upper electrode may be integrally disposed with the second electrode CE20.

[0109] The second shielding electrode BMLb may be located on the second insulating layer 20. The second shielding electrode BMLb may correspond to the oxide transistor O-TFT. According to one or more embodiments, the second shielding electrode BMLb may be omitted. According to one or more embodiments, the first shielding electrode BMLa may extend to the lower part of the oxide transistor O-TFT and may replace the second shielding electrode BMLb.

[0110] The third insulating layer 30 may be located on the second insulating layer 20. The second semiconductor pattern SC2 may be located on the third insulating layer 30. The second semiconductor pattern SC2 may include the channel region AC2 of an oxide transistor O-TFT. The second semiconductor pattern SC2 may include a metal oxide semiconductor. The second semiconductor pattern SC2 may include a transparent conductive oxide (TCO), such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or zinc oxide (ZnO). x ) or indium oxide (In2O3).

[0111] The metal-oxide-semiconductor (MOS) can include multiple regions SE2, AC2, and DE2, distinguished from each other based on whether the transparent conductive oxide is reduced. The regions where the transparent conductive oxide is reduced (hereinafter referred to as reduced regions) have a higher conductivity than the regions where the transparent conductive oxide is not reduced (hereinafter referred to as non-reduced regions). The reduced regions can essentially function as the source / drain of a transistor or as signal lines. The non-reduced regions can essentially correspond to the semiconductor regions (or channels) of a transistor. In other words, a portion of the second semiconductor pattern SC2 can be the semiconductor region of an oxide transistor O-TFT, another portion of the second semiconductor pattern SC2 can be the source region SE2 / drain region DE2 of an oxide transistor O-TFT, and other portions of the second semiconductor pattern SC2 can be signal transmission regions.

[0112] The fourth insulating layer 40 may be located on top of the third insulating layer 30. For example... Figure 6 As shown, the fourth insulating layer 40 may cover the second semiconductor pattern SC2. According to one or more embodiments, the fourth insulating layer 40 may be an insulating pattern stacked with the gate GT2 of the oxide transistor O-TFT and exposing the source region SE2 and the drain region DE2.

[0113] The gate GT2 of the oxide transistor O-TFT can be located on the fourth insulating layer 40. The gate GT2 of the oxide transistor O-TFT can be part of a metal pattern. The gate GT2 of the oxide transistor O-TFT can be stacked with the channel region AC2.

[0114] The fifth insulating layer 50 may be located on the fourth insulating layer 40 and may cover the gate GT2. Each of the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40 and the fifth insulating layer 50 may be an inorganic layer.

[0115] The first connection pattern CNP1 and the second connection pattern CNP2 may be located on the fifth insulating layer 50. The first connection pattern CNP1 and the second connection pattern CNP2 may be formed using the same process; therefore, the first connection pattern CNP1 and the second connection pattern CNP2 may include the same material and the same stacked structure. The first connection pattern CNP1 may be connected to the drain region DE1 of the silicon transistor S-TFT via a first pixel contact hole PCH1 defined through the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50. The second connection pattern CNP2 may be connected to the source region SE2 of the oxide transistor O-TFT via a second pixel contact hole PCH2 defined through the fourth insulating layer 40 and the fifth insulating layer 50. The connection relationship of the first connection pattern CNP1 and the second connection pattern CNP2 with respect to the silicon transistor S-TFT and the oxide transistor O-TFT should not be limited thereto or restricted by this.

[0116] A sixth insulating layer 60 may be located on the fifth insulating layer 50. A third connection pattern CNP3 may be located on the sixth insulating layer 60. The third connection pattern CNP3 may be connected to the first connection pattern CNP1 via a third pixel contact hole PCH3 defined through the sixth insulating layer 60. A data line DL may be located on the sixth insulating layer 60. An upper insulating layer 70 may be located on the sixth insulating layer 60 and may cover the third connection pattern CNP3 and the data line DL. The third connection pattern CNP3 and the data line DL may be formed using the same process; therefore, the third connection pattern CNP3 and the data line DL may include the same material and the same stacking structure. Each of the sixth insulating layer 60 and the upper insulating layer 70 may be an organic layer.

[0117] The first shielding electrode BMLa, the gate GT1 of the silicon transistor S-TFT, the second electrode CE20, and the gate GT2 of the oxide transistor O-TFT may comprise molybdenum (Mo), a molybdenum (Mo)-containing alloy, titanium (Ti), or a titanium (Ti)-containing alloy, all of which have good heat resistance. The first connection pattern CNP1 and the second connection pattern CNP2 may comprise aluminum, which has high electrical conductivity. The first connection pattern CNP1 and the second connection pattern CNP2 may have a titanium / aluminum / titanium three-layer structure.

[0118] A light-emitting element (LD) may include an anode (or first electrode) AE, a light-emitting layer EL, and a cathode (or second electrode) CE. The anode AE ​​of the LD may be located on the upper insulating layer 70. The anode AE ​​may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The anode AE ​​may have a stacked structure of sequentially stacked ITO / Ag / ITO. The positions of the anode AE ​​and the cathode CE may be interchanged.

[0119] The pixel-defining layer (PDL) may be located on the upper insulating layer 70. The PDL may be an organic layer. The PDL may have light-absorbing properties and may be black. As an example, the PDL may include a black colorant. The black colorant may include a black dye or a black pigment. The black colorant may include carbon black, a metallic material such as chromium, or an oxide thereof. The PDL may correspond to a light-blocking pattern with light-blocking properties.

[0120] The pixel-defining layer (PDL) may cover a portion of the anode (AE). As an example, an opening (PDL-OP) may be defined through the PDL to expose a portion of the anode (AE). The light-emitting region (LA) may be defined corresponding to the opening (PDL-OP). In this disclosure, a hole control layer may be located between the anode (AE) and the light-emitting layer (EL). The hole control layer may include a hole transport layer and may also include a hole injection layer. An electron control layer may be located between the light-emitting layer (EL) and the cathode (CE). The electron control layer may include an electron transport layer and may also include an electron injection layer.

[0121] Encapsulation layer 140 may cover the light-emitting element (LD). Encapsulation layer 140 may include sequentially stacked encapsulation inorganic layer 141, encapsulation organic layer 142, and encapsulation inorganic layer 143; however, the layers forming encapsulation layer 140 should not be limited to or restricted by this. Encapsulation inorganic layers 141 and 143 may include silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, or aluminum oxide layers. Each of encapsulation inorganic layers 141 and 143 may have a multilayer structure. Encapsulation organic layer 142 may include acrylic organic layers, but should not be limited to or restricted by this.

[0122] The input sensor ISL may include at least one conductive layer (or at least one sensor conductive layer) and at least one insulating layer (or at least one sensor insulating layer). The input sensor ISL may include a first insulating layer (or first sensor insulating layer) 210, a first conductive layer 220, a second insulating layer (or second sensor insulating layer) 230, a second conductive layer 240, and a third insulating layer (or third sensor insulating layer) 250. Figure 6 The conductive lines of the first conductive layer 220 and the conductive lines of the second conductive layer 240 are schematically shown.

[0123] The first insulating layer 210 may be directly located on the display panel DP. The first insulating layer 210 may be an inorganic layer including at least one of silicon nitride, silicon oxynitride, and silicon oxide. Each of the first conductive layer 220 and the second conductive layer 240 may have a single-layer structure or a multilayer structure of layers stacked on a third-direction DR3. The first conductive layer 220 and the second conductive layer 240 may include conductive lines of electrodes defining a grid shape. The conductive lines of the first conductive layer 220 and the second conductive layer 240 may be connected to each other via contact holes defined through the second insulating layer 230, or they may not be connected to each other. The connection relationship between the conductive lines of the first conductive layer 220 and the conductive lines of the second conductive layer 240 may be determined according to the type of sensor forming the input sensor ISL.

[0124] The first conductive layer 220 and the second conductive layer 240, having a single-layer structure, may comprise a metal layer or a transparent conductive layer. The metal layer may comprise molybdenum, silver, titanium, copper, aluminum, or alloys thereof. The transparent conductive layer may comprise a transparent conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO). x Examples of conductive materials include indium zinc tin oxide (ITZO), etc. Additionally, transparent conductive layers can include conductive polymers such as PEDOT, metal nanowires, graphene, etc.

[0125] The first conductive layer 220 and the second conductive layer 240, having a multilayer structure, may include a metal layer. The metal layer may have a titanium / aluminum / titanium three-layer structure. The first conductive layer 220 and the second conductive layer 240, having a multilayer structure, may include at least one metal layer and at least one transparent conductive layer. A second insulating layer 230 may be located between the first conductive layer 220 and the second conductive layer 240. A third insulating layer 250 may cover the second conductive layer 240. According to one or more embodiments, the third insulating layer 250 may be omitted. The second insulating layer 230 and the third insulating layer 250 may include inorganic or organic layers.

[0126] Figure 7A This is a plan view of an input sensor ISL according to one or more embodiments of the present disclosure. Figure 7B It is along Figure 7AThe cross-sectional view of the input sensor ISL taken from line II-II'.

[0127] Reference Figure 7A The input sensor ISL may include a sensing area IS-DA and a non-sensing area IS-NDA adjacent to the sensing area IS-DA. The sensing area IS-DA and the non-sensing area IS-NDA may respectively correspond to Figure 5 The diagram shows the display area DP-DA and the non-display area DP-NDA. The input sensor ISL may include first electrodes (or first sensing electrodes) E1-1 to E1-5, second electrodes (or second sensing electrodes) E2-1 to E2-4, a first signal line (or first sensor signal line) SL1, and a second signal line (or second sensor signal line) SL2. Figure 7A The first insulating pattern DMP1 and the second insulating pattern DMP2 are also shown to illustrate their relative positions with respect to the input sensor ISL.

[0128] First electrodes E1-1 to E1-5 and second electrodes E2-1 to E2-4, which are insulated from and intersect with the first electrodes E1-1 to E1-5, can be arranged in the sensing area IS-DA. A first signal line SL1 electrically connected to the first electrodes E1-1 to E1-5 and a second signal line SL2 electrically connected to the second electrodes E2-1 to E2-4 can be arranged in the non-sensing area IS-NDA. One of the first signal line SL1 and the second signal line SL2 can transmit a drive signal to the corresponding electrode to sense external input from external circuitry, and the other of the first signal line SL1 and the second signal line SL2 can output a sensing signal. The change in capacitance between the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 can be measured based on the sensing signal. A mutual capacitance type input sensor is shown as a representative example, but should not be limited to or construed as such. A self-capacitance type input sensor can be used as an input sensor. A self-capacitance type input sensor may include one type of sensing electrode.

[0129] Each of the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may have a grid shape, the grid shape being provided with a plurality of openings defined therethrough. The openings may be defined as light-emitting areas LA corresponding to the display panel DP (see reference). Figure 6 ). Figure 6An opening E-OP corresponding to the light-emitting area is shown. The second electrodes E2-1 to E2-4 may be insulated from, and intersect with, the first electrodes E1-1 to E1-5. One of the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may have an integral shape. The first electrodes E1-1 to E1-5 may have an integral shape. The first electrodes E1-1 to E1-5 may include a sensing portion SP1 and an intermediate portion BP1.

[0130] Each of the second electrodes E2-1 to E2-4 may include a sensing pattern SP2 and a bridge pattern (or connection pattern) BP2. Two adjacent sensing patterns SP2 may be connected to two bridge patterns BP2; however, the number of bridge patterns should not be particularly limited.

[0131] Reference Figures 6 to 7B The bridge pattern BP2 can be formed by the first conductive layer 220, and the first electrodes E1-1 to E1-5 and the sensing pattern SP2 can be formed by the second conductive layer 240. The bridge pattern BP2 can be connected to the sensing pattern SP2 via the contact hole TH-I formed through the second insulating layer 230.

[0132] Figure 7A Each of the first signal line SL1 and the second signal line SL2 can be made by Figure 6 The first conductive layer 220 is formed. Therefore, Figure 7A Each of the first signal line SL1 and the second signal line SL2 can be connected to Figure 7B The bridge pattern BP2 is located on the same layer. However, according to one or more embodiments, each of the first signal line SL1 and the second signal line SL2 may be formed by the second conductive layer 240. Each of the first signal line SL1 and the second signal line SL2 may include a line formed by the first conductive layer 220 and a line formed by the second conductive layer 240.

[0133] Figure 8 This is an enlarged plan view of the non-display area DP-NDA of a display module DM according to one or more embodiments of the present disclosure. Figure 9 It is along Figure 8 The sectional view of the display module DM is taken from line III-III'.

[0134] Reference Figure 8 and Figure 9 The display area DP-DA and non-display area DP-NDA of the display module DM are assigned to... Figure 5 The reference numerals for the display area DP-DA and the non-display area DP-NDA of the display panel DP are the same. Alternatively, the display area DP-DA and the non-display area DP-NDA can be respectively associated with... Figure 7AThe sensing area IS-DA and the non-sensing area IS-NDA. In Figure 8 middle, Figure 7A The first electrode E1-5 among the first electrodes E1-1 to E1-5 shown in the figure and Figure 7A Some of the second electrodes E2-1 to E2-4 shown are shown in the display area DP-DA, and the components in the display area DP-DA of the display panel DP are not shown.

[0135] Figure 8 It shows when based on Figure 5 and Figure 7A When viewed in a plane, it is an enlarged planar view of a corner region (or vertex region) CNA and the non-display region DP-NDA located on the lower side of the display region DP-DA. Figure 8 The components shown are stacked on different layers.

[0136] The first power line PL1 and the second power line PL2 can be arranged in the non-display area DP-NDA. The first power line PL1 can be extended through the corner area CNA to... Figure 5 The non-display area DP-NDA is defined to the left of the display area DP-DA. In the corner region CNA, when viewed in a plane, the boundary between the display area DP-DA and the non-display area DP-NDA can be a curve. The boundary between the display area DP-DA and the non-display area DP-NDA is... Figure 8 The middle is indicated by a dashed line.

[0137] The first power line PL1 can pass through Figure 5 The non-display area DP-NDA, defined to the left of the display area DP-DA, extends to the non-display area DP-NDA defined above the display area DP-DA and then to the non-display area DP-NDA defined to the right of the display area DP-DA. When viewed in a plane, the second electric field line PL2 may be located within the non-display area DP-NDA defined below the display area DP-DA and may extend in the first direction DR1. The first electric field line PL1 and the second electric field line PL2 may be connected to... Figure 6 The third connection pattern CNP3 shown is located on the same layer.

[0138] The first voltage line VL1 and the second voltage line VL2 can be arranged in the non-display area DP-NDA. Although each of the first voltage line VL1 and the second voltage line VL2 can be configured as multiple lines, in Figure 8The diagram shows a first voltage line VL1 and a second voltage line VL2. The first voltage line VL1 can receive a first voltage, and the second voltage line VL2 can receive a second voltage higher than the first voltage. The first voltage can be a first power supply voltage, and the second voltage can be a second power supply voltage.

[0139] The first voltage line VL1 and the second voltage line VL2 may not overlap with the second electric field line PL2, and when viewed in a plane, they may be positioned below the second electric field line PL2. The first voltage line VL1 and the second voltage line VL2 may be positioned closer to the edge EG of the display module DM than the second electric field line PL2. The edge EG of the display module DM may be... Figure 9 The edge 110-EG of the substrate layer 110 is shown. When viewed in a plane, the edge 110-EG of the substrate layer 110 indicates the side surface of the substrate layer 110. The first voltage line VL1 and the second voltage line VL2 can be... Figure 6 The third connection pattern CNP3 or the first connection pattern CNP1 shown are located on the same layer.

[0140] At least one control signal line (CSL) can be located in the non-display area DP-NDA. The control signal line (CSL) can be connected via the corner area CNA. Figure 5 The scan drive circuit SDC is shown in the diagram. The control signal line CSL can be superimposed with the first power line PL1 and the second power line PL2. The control signal line CSL can be... Figure 6 The first shielding electrode BMLa, the gate GT1 of the silicon transistor S-TFT, the second electrode CE20, and the gate GT2 of the oxide transistor O-TFT shown are located in the same layer.

[0141] The data cable DL can be arranged within the display area DP-DA and the non-display area DP-NDA. Within the data cable DL, the portion overlapping the display area DP-DA can be... Figure 6 The first connection pattern CNP1 and the third connection pattern CNP3 shown are located on the same layer. Within the data line DL, the portion overlapping the non-display area DP-NDA can be... Figure 6The first shielding electrode BML1, the gate GT1 of the silicon transistor S-TFT, the second electrode CE20, and the gate GT2 of the oxide transistor O-TFT shown are located in the same layer. The portions of the data line DL stacked with the display area DP-DA and the portions of the data line DL stacked with the non-display area DP-NDA can be connected to each other via contact holes defined by at least one of the barrier layer 10br, the buffer layer 10bf, and the insulating layers 10, 20, 30, 40, 50, 60, and 70. The connection portions connecting the portions of the data line DL stacked with the display area DP-DA and the portions of the data line DL stacked with the non-display area DP-NDA can be located in the non-display area DP-NDA adjacent to the boundary between the display area DP-DA and the non-display area DP-NDA.

[0142] The data line DL can cross the first voltage line VL1, the second voltage line VL2, and the second power line PL2. The electrostatic discharge (ESD) protection circuit connected to the data line DL, the first voltage line VL1, and the second voltage line VL2 can be located in the non-display area DP-NDA. The ESD protection circuit can be located between the first voltage line VL1 and the second voltage line VL2. Figure 8 An electrostatic discharge (ESD) protection circuit is shown as a representative example. However, this disclosure should not be limited thereto or thereby restricted. According to one or more embodiments, the ESD protection circuit may be connected to each of the data lines DL, or multiple ESD protection circuits may be connected to each of the data lines DL.

[0143] The second signal line SL2 can be located in the non-display area DP-NDA. The second signal line SL2 can be superimposed on the control signal line CSL, and can also be superimposed on the first power line PL1 or the second power line PL2. Each of the second signal lines SL2 can be connected to a corresponding electrode among the second electrodes E2-1 to E2-3 located in the display area DP-DA.

[0144] Figure 8 The alignment mark AM is shown located in the corner region CNA. The alignment mark AM can be used as a reference point for aligning the display module DM and the mask during the deposition process. The alignment mark AM can be compared with later references. Figure 12 The first pad electrode PD1 described is located in the same layer and can be formed with the first pad electrode PD1 by the same process.

[0145] Figure 9 It is along Figure 8 The sectional view of the display module DM is taken from line III-III'.

[0146] Structure and reference of substrate layer 110, driving element layer 120, light-emitting element layer 130, encapsulation layer 140 and input sensor ISL located in the display area DP-DA Figure 6 The structures described are basically the same, therefore, their details will be omitted. Figure 9 schematically shown Figure 6 The pixel driving circuit of the PC uses silicon transistors S-TFTs. (Refer to...) Figure 6 Each of the described barrier layer 10br, buffer layer 10bf, insulating layers 10, 20, 30, 40, 50, 60, and 70, and pixel defining layer PDL, can extend from the display area DP-DA to the non-display area DP-NDA. The extension form of the barrier layer 10br, buffer layer 10bf, insulating layers 10, 20, 30, 40, and 50, and pixel defining layer PDL can vary depending on the layer. (See reference...) Figure 6 Each of the described sixth insulating layer 60, upper insulating layer 70, encapsulation layer 140, first insulating layer 210, second insulating layer 230, and third insulating layer 250 can extend from the display area DP-DA to the non-display area DP-NDA. The extension form of the sixth insulating layer 60, upper insulating layer 70, encapsulation layer 140, first insulating layer 210, second insulating layer 230, and third insulating layer 250 can vary depending on the layers. Each of the sixth insulating layer 60, upper insulating layer 70, encapsulation layer 140, first insulating layer 210, second insulating layer 230, and third insulating layer 250 can be located within a portion of the non-display area DP-NDA.

[0147] In one or more embodiments, the pad electrode and data line DL may be located in the non-display area DP-NDA, and will be referenced Figure 12 Describe its details.

[0148] Figure 10 This is an enlarged plan view of the non-display area DP-NDA of a display module DM according to one or more embodiments of the present disclosure. Figure 10 The image is further enlarged to show Figure 8 The non-display area DP-NDA. Figure 10 The data line DL is shown.

[0149] Reference Figure 10 The first voltage line VL1 and the second voltage line VL2 can be positioned. The electrostatic discharge (ESD) protection circuit can be arranged between the first voltage line VL1 and the second voltage line VL2, and can be spaced apart from each other in the first direction DR1. The ESD protection circuit may include a first transistor connected from a diode on the first voltage line VL1 to the data line DL, and a second transistor connected from a diode on the data line DL to the second voltage line VL2.

[0150] Each of the data lines DL can be electrically connected to the conductive patterns CP1 and CP2 via contact hole CA. Contact hole CA can be positioned adjacent to the first voltage line VL1. However, this disclosure should not be limited thereto or thereby restricted.

[0151] Each of the first conductive pattern CP1 and the second conductive pattern CP2 can be configured as multiple. The first conductive pattern CP1 and the second conductive pattern CP2 can be positioned in a direction opposite to the second direction DR2, spaced apart from the first voltage line VL1. The first conductive pattern CP1 and the second conductive pattern CP2 can be arranged alternately to correspond to the data line DL in a one-to-one correspondence. The first conductive pattern CP1 can be arranged alternately with the second conductive pattern CP2, and can be arranged spaced apart from each other in the first direction DR1. Figure 10 The positions of the first conductive pattern CP1 and the second conductive pattern CP2 shown are merely examples and can be changed.

[0152] Figure 11 yes Figure 10 An enlarged plan view of region AA' Figure 12 It is along Figure 11 A cross-sectional view of the display panel DP taken along line IV-IV'. (Refer to...) Figure 6 The described buffer layer 10bf, the second insulating layer 20 to the fourth insulating layer 40 and the upper insulating layer 70 are in Figure 12 The text is omitted and refers to... Figure 6 The same description provided can be applied to Figure 12 The omitted components.

[0153] Reference Figure 11 and Figure 12 The substrate layer 110 may include a first resin layer 110-B1 and a second resin layer 110-B2 located on the first resin layer 110-B1. The substrate layer 110 may further include a first substrate insulating layer 110-I1 located between the first resin layer 110-B1 and the second resin layer 110-B2, a second substrate insulating layer 110-I2 located between the first substrate insulating layer 110-I1 and the second resin layer 110-B2, a third substrate insulating layer 110-I3 located between the second substrate insulating layer 110-I2 and the second resin layer 110-B2, and a fourth substrate insulating layer 110-I4 located between the third substrate insulating layer 110-I3 and the second resin layer 110-B2. Each of the first substrate insulating layer 110-I1, the second substrate insulating layer 110-I2, and the fourth substrate insulating layer 110-I4 may include silicon oxide (SiO2). x The third substrate insulating layer 110-I3 may include amorphous silicon.

[0154] The first resin layer 110-B1 may be provided with a lower resin opening LROP that extends through it. The lower surface of the first pad electrode PD1 may be exposed through the lower resin opening LROP. Flexible circuit board FCB (reference) Figure 2 It can be bonded to the first pad electrode PD1 through the lower resin opening LROP.

[0155] The upper resin openings UROP1 and UROP2 can be defined to penetrate the second resin layer 110-B2 to overlap with the non-display area DP-NDA. Multiple upper resin openings UROP1 and UROP2 can be provided. Upper resin openings UROP1 and UROP2 can include a first upper resin opening UROP1 and a second upper resin opening UROP2. Each of the first upper resin opening UROP1 and the second upper resin opening UROP2 can penetrate the first substrate insulating layer 110-I1 to the fourth substrate insulating layer 110-I4. The second upper resin opening UROP2 can be spaced apart from the first upper resin opening UROP1 in a fourth direction DR4 that intersects each of the first direction DR1 and the second direction DR2. The first upper resin openings UROP1 and the second upper resin opening UROP2 can be arranged alternately to each other and can be staggered to each other in the first direction DR1. Therefore, the first conductive pattern CP1 and the second conductive pattern CP2 can be effectively placed in space.

[0156] A first pad electrode PD1 may be located between a first resin layer 110-B1 and a second resin layer 110-B2, and may be stacked with a non-display area DP-NDA. A portion of the upper surface of the first pad electrode PD1 may be exposed through a first upper resin opening UROP1. A portion of the first pad electrode PD1 may be located on a first substrate insulating layer 110-I1. A portion of a second substrate insulating layer 110-I2 may be located on the first pad electrode PD1. Multiple first pad electrodes PD1 may be provided, and the first pad electrodes PD1 may be arranged spaced apart from each other in a first direction DR1. In one or more embodiments, a second pad electrode may be located between a first resin layer 110-B1 and a second resin layer 110-B2, and may be stacked with a non-display area DP-NDA. In one or more embodiments, a portion of the upper surface of the second pad electrode may be exposed through a second upper resin opening UROP2. In one or more embodiments, the first pad electrode PD1 and the second pad electrode may be arranged alternately with each other in the first direction DR1. Hereinafter, and in one or more embodiments, the term "pad electrode" (e.g., Figure 19 The reference numeral PD in the figure can be used as a combined term for the first pad electrode PD1 and the second pad electrode, and the description of the first pad electrode PD1 can be applied to the second pad electrode in the same way.

[0157] The driving element layer 120 may include a barrier layer 10br, a data line DL, conductive patterns CP1 and CP2, a sixth insulating layer 60, and bridge conductive patterns BCP1 and BCP2.

[0158] The barrier layer 10br may be located on the second resin layer 110-B2. The barrier layer 10br may be located directly on the second resin layer 110-B2. The barrier layer 10br may be provided with (e.g., may define) barrier openings BOP1 and BOP2 extending through it to correspond to the upper resin openings UROP1 and UROP2. The barrier openings BOP1 and BOP2 may include a first barrier opening BOP1 superimposed with the first upper resin opening UROP1 and a second barrier opening BOP2 superimposed with the second upper resin opening UROP2.

[0159] When viewed in a plane, the first upper resin opening UROP1 may have a smaller size than the first blocking opening BOP1. The first blocking opening BOP1 may be defined by a first protruding blocking side surface PBS1 and a first main blocking side surface MBS1. The first protruding blocking side surface PBS1 may be substantially parallel to the first direction DR1. The first blocking opening BOP1 may be defined by the first protruding blocking side surface PBS1, the first main blocking side surface MBS1, and a first sub-blocking side surface SBS1 connecting the first protruding blocking side surface PBS1 and the first main blocking side surface MBS1.

[0160] The first sub-blocking side surface SBS1 may be substantially parallel to the second direction DR2. The first protruding blocking side surface PBS1 may be adjacent to the contact hole CA. The first protruding blocking side surface PBS1 may be located between the first main blocking side surface MBS1 and the contact hole CA. The first main blocking side surface MBS1 may surround a portion of the first upper resin opening UROP1. The first upper resin opening UROP1, except for the portion surrounded by the first protruding blocking side surface PBS1 and the first sub-blocking side surface SBS1, may be surrounded by the first main blocking side surface MBS1 (e.g., the first main blocking side surface MBS1 may generally have the same shape as the first upper resin opening UROP1, or may follow the outline of the first upper resin opening UROP1). The distance from the first protruding blocking side surface PBS1 to the center of the first upper resin opening UROP1 may be greater than the distance from the first main blocking side surface MBS1 to the center of the first upper resin opening UROP1. When viewed in a plane, the first upper resin opening UROP1 may have a smaller dimension than the first blocking opening BOP1.

[0161] The second blocking opening BOP2 may be defined by the second protruding blocking side surface PBS2 and the second main blocking side surface MBS2. The second protruding blocking side surface PBS2 may be substantially parallel to the first direction DR1. The second blocking opening BOP2 may be defined by the second protruding blocking side surface PBS2, the second main blocking side surface MBS2, and a second sub-blocking side surface SBS2 connecting the second protruding blocking side surface PBS2 and the second main blocking side surface MBS2. The second sub-blocking side surface SBS2 may be substantially parallel to the second direction DR2. The second main blocking side surface MBS2 may be adjacent to the contact hole CA. The second protruding blocking side surface PBS2 may be located between the second main blocking side surface MBS2 and the second connecting opening COP2 (described below).

[0162] The second primary barrier side surface MBS2 may surround a portion of the second upper resin opening UROP2. The second upper resin opening UROP2, except for the portion surrounded by the second protruding barrier side surface PBS2 and the second sub-barrier side surface SBS2, may be surrounded by the second primary barrier side surface MBS2. The distance from the second protruding barrier side surface PBS2 to the center of the second upper resin opening UROP2 may be greater than the distance from the second primary barrier side surface MBS2 to the center of the second upper resin opening UROP2.

[0163] The data line DL can be located on the blocking layer 10br. The data line DL can also be located on the first insulating layer 10 in the non-display area DP-NDA. The data line DL can be connected to the display area DP-DA (see reference). Figure 5 Each of the overlays in the non-display area DP-NDA. The data line DL (in the plan view) may not be overlaid with the upper resin openings UROP1 and UROP2 or the blocking openings BOP1 and BOP2, or may be separated from the upper resin openings UROP1 and UROP2 or the blocking openings BOP1 and BOP2.

[0164] The fifth insulating layer 50 may be located on the data line DL in the non-display area DP-NDA. The fifth insulating layer 50 may be directly located on the data line DL in the non-display area DP-NDA. The contact hole CA may be defined as a portion passing through the fifth insulating layer 50 to expose the data line DL. When viewed in a plane, the contact hole CA may have a smaller size than the dimensions of the upper resin openings UROP1 and UROP2. The contact hole CA may be located between the upper resin openings UROP1 and UROP2 and the display area DP-DA.

[0165] Conductive patterns CP1 and CP2 may include a first conductive pattern CP1 and a second conductive pattern CP2. The following description of the first conductive pattern CP1 can be applied equivalently to the second conductive pattern CP2. The first conductive pattern CP1 may include a first pad conductive portion PCP1 and a first data conductive portion DCP1. The first pad conductive portion PCP1 may be located in a first upper resin opening UROP1 and may be in contact with a first pad electrode PD1. The first data conductive portion DCP1 may be in contact with a data line DL. The first conductive pattern CP1 may also include a first additional conductive portion LCP1. The first pad conductive portion PCP1 may be located between the first data conductive portion DCP1 and the first additional conductive portion LCP1.

[0166] A sixth insulating layer 60 may be located on conductive patterns CP1 and CP2. The sixth insulating layer 60 may overlap with the boundary between the first pad conductive portion PCP1 and the first data conductive portion DCP1. The sixth insulating layer 60 may be provided with / may define connection openings COP1 and COP2 extending through it, and main openings MOP1 and MOP2 extending through it. The first connection opening COP1 may be formed between the first upper resin opening UROP1 and the display area DP-DA (see reference). Figure 5 The second upper resin opening UROP2 can be formed between the second connecting opening COP2 and the display area DP-DA (see reference). Figure 5 Between. Connecting openings COP1 and COP2 may include a first connecting opening COP1 and a second connecting opening COP2. Main openings MOP1 and MOP2 may include a first main opening MOP1 and a second main opening MOP2. The following description of the first connecting opening COP1 can be applied equivalently to the second connecting opening COP2, and the following description of the first main opening MOP1 can be applied equivalently to the second main opening MOP2.

[0167] A portion of the first data conductive portion DCP1 can be exposed through the first connection opening COP1. The first main opening MOP1 can be stacked with the first upper resin opening UROP1. A portion of the first pad conductive portion PCP1 can be exposed through the first main opening MOP1. Main openings MOP1 and MOP2 can be defined by protruding insulating side surfaces PIS1 and PIS2 and main insulating side surfaces MIS1 and MIS2. Main openings MOP1 and MOP2 can be defined by protruding insulating side surfaces PIS1 and PIS2, main insulating side surfaces MIS1 and MIS2, and sub-insulating side surfaces SIS1 and SIS2 connecting the protruding insulating side surfaces PIS1 and PIS2 to the main insulating side surfaces MIS1 and MIS2.

[0168] The first main opening MOP1 may be defined by the first protruding insulating side surface PIS1 and the first main insulating side surface MIS1. The first main opening MOP1 may be defined by the first protruding insulating side surface PIS1, the first main insulating side surface MIS1, and the first sub-insulating side surface SIS1. The second main opening MOP2 may be defined by the second protruding insulating side surface PIS2 and the second main insulating side surface MIS2. The second main opening MOP2 may be defined by the second protruding insulating side surface PIS2, the second main insulating side surface MIS2, and the second sub-insulating side surface SIS2. When viewed in a plane, the first upper resin opening UROP1 may have a larger dimension than the first connecting opening COP1. The first connecting opening COP1 may be spaced apart from the first upper resin opening UROP1 in the second direction DR2. The second connecting opening COP2 may be spaced apart from the second upper resin opening UROP2 in a direction opposite to the second direction DR2.

[0169] The first protruding insulating side surface PIS1 may be adjacent to the contact hole CA. The first protruding insulating side surface PIS1 may be located between the first main insulating side surface MIS1 and the contact hole CA. The first main insulating side surface MIS1 may (e.g., in a plan view) surround a portion of the first upper resin opening UROP1. The distance between the center of the first main insulating side surface MIS1 and the center of the first upper resin opening UROP1 may be less than the distance between the center of the first protruding insulating side surface PIS1 and the center of the first upper resin opening UROP1.

[0170] The second primary insulating side surface MIS2 may be adjacent to the contact hole CA. The second primary insulating side surface MIS2 may be located between the second raised insulating side surface PIS2 and the contact hole CA. The second primary insulating side surface MIS2 may (e.g., in a plan view) surround a portion of the second upper resin opening UROP2. The spacing between the centers of the second primary insulating side surface MIS2 and the second upper resin opening UROP2 may be less than the spacing between the centers of the second raised insulating side surface PIS2 and the second upper resin opening UROP2.

[0171] Bridge conductive patterns BCP1 and BCP2 may include a first bridge conductive pattern BCP1 and a second bridge conductive pattern BCP2. The following description of the first bridge conductive pattern BCP1 can be applied equivalently to the second bridge conductive pattern BCP2. The first bridge conductive pattern BCP1 may be located on the first conductive pattern CP1 and the sixth insulating layer 60. The first bridge conductive pattern BCP1 may contact the first pad conductive portion PCP1 through the first upper resin opening UROP1, and may contact the first data conductive portion DCP1 through the first connection opening COP1. The first bridge conductive pattern BCP1 can electrically connect the first pad conductive portion PCP1 and the first data conductive portion DCP1.

[0172] The first protruding blocking side surface PBS1 can be located between the first protruding insulating side surface PIS1 and the first connection opening COP1. When viewed in a plane, the first main insulating side surface MIS1 can be superimposed on the first main blocking side surface MBS1.

[0173] The second protruding blocking side surface PBS2 can be located between the second protruding insulating side surface PIS2 and the second connection opening COP2. When viewed in a plane, the second primary insulating side surface MIS2 can be superimposed on the second primary blocking side surface MBS2.

[0174] According to the display panel DP disclosed herein, unlike conventional display panels, the barrier layer 10br includes a first protruding barrier side surface PBS1, and the distance from the first protruding barrier side surface PBS1 to the center of the first upper resin opening UROP1 is greater than the distance from the first main barrier side surface MBS1 to the center of the first upper resin opening UROP1. Therefore, it can be ensured that the sixth insulating layer 60 covers the space at the boundary between the first pad conductive portion PCP1 and the first data conductive portion DCP1. When the sixth insulating layer 60 does not cover the boundary between the first pad conductive portion PCP1 and the first data conductive portion DCP1, the first bridge conductive pattern BCP1 may break due to the step difference between the first pad conductive portion PCP1 and the first data conductive portion DCP1, and the reliability of the display panel may deteriorate.

[0175] When the sixth insulating layer 60 covers the boundary between the first pad conductive portion PCP1 and the first data conductive portion DCP1, and when the first bridge conductive pattern BCP1 is located on the sixth insulating layer 60 covering the first pad conductive portion PCP1 and the first data conductive portion DCP1, the first bridge conductive pattern BCP1 can electrically connect the first pad conductive portion PCP1 and the first data conductive portion DCP1 without disconnection, thereby improving the reliability of the display panel. In the following text, reference will be made to... Figure 13 The boundary between the first pad conductive portion PCP1 and the first data conductive portion DCP1 is described in detail.

[0176] Figure 13 yes Figure 12 A magnified plan view of region BB'. Figure 13 This is an enlarged view of the region BB' adjacent to the first pad conductive portion PCP1 and the first data conductive portion DCP1.

[0177] Reference Figure 12 and Figure 13The first pad conductive portion PCP1 and the first data conductive portion DCP1 can be spaced apart from each other and can be non-contacting. A portion of the second resin layer 110-B2 can be etched during the process of forming the first barrier opening BOP1, resulting in an over-etched area OEA that partially exposes the lower surface of the barrier layer 10br. When conductive material is applied to the second resin layer 110-B2 and the barrier layer 10br to form the first conductive pattern CP1, a separation portion CK can be formed between the first pad conductive portion PCP1 and the first data conductive portion DCP1 located on the second resin layer 110-B2 due to the over-etched area OEA. The separation portion CK can be a space that allows the first pad conductive portion PCP1 and the first data conductive portion DCP1 to be separated from each other. Due to the separation portion CK, the first pad conductive portion PCP1 and the first data conductive portion DCP1 can be non-electrically connected to each other or can be electrically insulated / separated. The separation portion CK can also be formed between the first additional conductive portion LCP1 and the first pad conductive portion PCP1.

[0178] Figure 14 This is an enlarged plan view of the non-display area DP-NDA of the display module DM' according to one or more embodiments of the present disclosure. Figure 15 yes Figure 14 A magnified plan view of region CC'. Figure 16 It is along Figure 15 The cross-sectional view of the display panel DP taken by line V-V'.

[0179] exist Figures 14 to 16 In the figures, the same reference numerals indicate Figures 10 to 12 Since these are the same elements, detailed descriptions of the same elements will be omitted.

[0180] Reference Figure 14 and Figure 15 First connecting opening (refer to) Figure 11 COP1 may include a first-first connecting opening COP1-1 and a first-second connecting opening COP1-2. The first-first connecting opening COP1-1 may be connected to the display area (see reference). Figure 5The first-second connecting opening COP1-2 may be spaced apart from the first-first connecting opening COP1-1, and the first upper resin opening UROP1 is disposed therebetween. The first-first connecting opening COP1-1 may be spaced apart from the first upper resin opening UROP1 in the second direction DR2. The first-second connecting opening COP1-2 may be spaced apart from the first upper resin opening UROP1 in a direction opposite to the second direction DR2. The first blocking opening BOP1', the first main opening MOP1', and the first upper resin opening UROP1 may be defined between the first-first connecting opening COP1-1 and the first-second connecting opening COP1-2.

[0181] The first blocking opening BOP1' may be defined by a first-first protruding blocking side surface PBS1-1, a first-first main blocking side surface MBS1-1, and a first-second protruding blocking side surface PBS1-2. The first-first protruding blocking side surface PBS1-1 may be adjacent to the first-first connecting opening COP1-1. The first-second protruding blocking side surface PBS1-2 may be adjacent to the first-second connecting opening COP1-2. The first-first protruding blocking side surface PBS1-1 may be connected to the first-first main blocking side surface MBS1-1 via a first-first sub-blocking side surface SBS1-1. The first-second protruding blocking side surface PBS1-2 may be connected to the first-first main blocking side surface MBS1-1 via a first-second sub-blocking side surface SBS1-2.

[0182] The first main opening MOP1' may be defined by a first-first protruding insulating side surface PIS1-1, a first-first main insulating side surface MIS1-1, and a first-second protruding insulating side surface PIS1-2. The first-first protruding insulating side surface PIS1-1 may be adjacent to the first-first connecting opening COP1-1. The first-second protruding insulating side surface PIS1-2 may be adjacent to the first-second connecting opening COP1-2. The first-first protruding insulating side surface PIS1-1 may be connected to the first-first main insulating side surface MIS1-1 via a first-first sub-insulating side surface SIS1-1. The first-second protruding insulating side surface PIS1-2 may be connected to the first-first main insulating side surface MIS1-1 via a first-second sub-insulating side surface SIS1-2.

[0183] Second connection opening (refer to) Figure 11 COP2 may include a second-first connection opening COP2-1 and a second-second connection opening COP2-2. The second-first connection opening COP2-1 may be connected to the display area (see reference). Figure 5The DP-DA are adjacent. The second-second connection opening COP2-2 may be spaced apart from the second-first connection opening COP2-1, and the second upper resin opening UROP2 is placed therebetween. The second blocking opening BOP2', the second main opening MOP2' and the second upper resin opening UROP2 may be defined between the second-first connection opening COP2-1 and the second-second connection opening COP2-2.

[0184] The second blocking opening BOP2' can be defined by a second-first protruding blocking side surface PBS2-1, a second-first main blocking side surface MBS2-1, and a second-second protruding blocking side surface PBS2-2. The second-first protruding blocking side surface PBS2-1 can be adjacent to the second-first connecting opening COP2-1. The second-second protruding blocking side surface PBS2-2 can be adjacent to the second-second connecting opening COP2-2. The second-first protruding blocking side surface PBS2-1 can be connected to the second-first main blocking side surface MBS2-1 via the second-first sub-blocking side surface SBS2-1. The second-second protruding blocking side surface PBS2-2 can be connected to the second-first main blocking side surface MBS2-1 via the second-second sub-blocking side surface SBS2-2.

[0185] The second main opening MOP2' can be defined by the second-first protruding insulating side surface PIS2-1, the second-first main insulating side surface MIS2-1, and the second-second protruding insulating side surface PIS2-2. The second-first protruding insulating side surface PIS2-1 can be adjacent to the second-first connecting opening COP2-1. The second-second protruding insulating side surface PIS2-2 can be adjacent to the second-second connecting opening COP2-2. The second-first protruding insulating side surface PIS2-1 can be connected to the second-first main insulating side surface MIS2-1 through the second-first sub-insulating side surface SIS2-1. The second-second protruding insulating side surface PIS2-2 can be connected to the second-first main insulating side surface MIS2-1 through the second-second sub-insulating side surface SIS2-2.

[0186] Reference Figure 16 ,and Figure 12 The display panel shown is different; the first-first connection opening COP1-1 and the first-second connection opening COP1-2 can pass through the sixth insulating layer 60. Regarding... Figure 12The description of the first connection opening COP1 can be equivalently applied to the first-first connection opening COP1-1. A portion of the upper surface of the first additional conductive portion LCP1 can be exposed through the first-second connection opening COP1-2. The first bridge conductive pattern BCP1' can contact the first additional conductive portion LCP1 through the first-second connection opening COP1-2. The first bridge conductive pattern BCP1' can electrically connect the first additional conductive portion LCP1, the first pad conductive portion PCP1, and the first data conductive portion DCP1. When with Figure 12 Compared to the display panel shown, both the first-first connection opening COP1-1 and the first-second connection opening COP1-2 can be defined to penetrate the sixth insulating layer 60, thus increasing the area of ​​the first bridge conductive pattern BCP1' contacting the first conductive pattern CP1'. As a result, the transmission of electrical signals can be smoother. Similarly, the area of ​​the second bridge conductive pattern BCP2' contacting the second conductive pattern CP2' can be increased.

[0187] In the following text, reference will be made to Figures 17 to 25 Describes a method for manufacturing a display panel. (Referencing omitted) Figures 1 to 16 Details of the components described.

[0188] Figure 17 This is a flowchart illustrating a method for manufacturing a display panel (DP) according to one or more embodiments of the present disclosure. Figures 18 to 25 This is a view illustrating the process of manufacturing a display panel DP according to one or more embodiments of the present disclosure.

[0189] Reference Figure 17 A method for manufacturing a display panel may include the following steps: forming pad electrodes (S100); forming a preliminary second resin layer and a preliminary barrier layer (S110); forming a second resin layer and a barrier layer (S120); forming data lines (S130); forming conductive patterns (S140); forming a preliminary insulating layer (S150); etching a portion of the preliminary insulating layer to form an insulating layer (S160); and forming bridge conductive patterns (S170). As used herein, "forming" or variations thereof may suitably mean "providing" or "setting".

[0190] Reference Figure 18 and Figure 19 In the step of forming the pad electrode PD, the pad electrode PD can be formed on the first resin layer 110-B1. (Refer to...) Figure 12 The description of the first pad electrode PD1 can be applied equally to the pad electrode PD.

[0191] Reference Figure 20AIn the steps of forming the preliminary second resin layer P110-B2 and the preliminary barrier layer P10br, the preliminary second resin layer P110-B2 can be positioned on the first resin layer 110-B1, and the preliminary second resin layer P110-B2 can cover the pad electrode PD. The preliminary barrier layer P10br can be positioned on the preliminary second resin layer P110-B2. The preliminary second resin layer P110-B2 can be... Figure 12 The second resin layer 110-B2 described herein comprises the same material. The initial barrier layer P10br can be with Figure 12 The barrier layer 10br described herein comprises the same material.

[0192] Reference Figure 20B In the step of forming the second resin layer 110-B2 and the barrier layer 10br, an upper resin opening UROP can be formed through the second resin layer 110-B2 to expose a portion of the upper surface of the pad electrode PD. (Refer to...) Figure 12 The description of the first upper resin opening UROP1 is equivalently applicable to the upper resin opening UROP. A blocking opening BOP can be defined through the blocking layer 10br, such that the blocking opening BOP is stacked with the upper resin opening UROP, and the blocking opening BOP can be defined by the protruding blocking side surface PBS and the main blocking side surface MBS. Although the same etching process is performed in the process of forming the blocking opening BOP, because the second resin layer 110-B2 is etched to a greater extent than the initial blocking layer P10br, a portion of the second resin layer 110-B2 can be etched together, thus forming a reference. Figure 13 The over-etched region OEA is described.

[0193] Reference Figure 21 In the step of forming the data cable DL, it can be connected to the display area DP-NDA (refer to...). Figure 5 A data line DL is formed adjacent to the data line DL. The steps of forming the data line DL may include forming a fifth insulating layer 50 through which it defines a contact hole CA. One end of the fifth insulating layer 50 may be aligned with one end of the data line DL.

[0194] Reference Figure 22 In the step of forming the conductive pattern CP, the conductive pattern CP may include a pad conductive portion PCP located in the upper resin opening UROP and in contact with the pad electrode PD, and a data conductive portion DCP in contact with the data line DL through the contact hole CA. The conductive pattern CP may also include an additional conductive portion LCP spaced apart from the data conductive portion DCP. The pad conductive portion PCP may be located between the data conductive portion DCP and the additional conductive portion LCP. (See reference...) Figure 12 The description of the first conductive pattern CP1 can be applied equivalently to the conductive pattern CP. (See reference...) Figure 12 The descriptions of the first pad conductive portion PCP1, the first data conductive portion DCP1, and the first additional conductive portion LCP1 can be applied equally to the pad conductive portion PCP, the data conductive portion DCP, and the additional conductive portion LCP.

[0195] Reference Figure 23 In the step of forming the preliminary insulating layer P60, the preliminary insulating layer P60 can be combined with a reference. Figure 5 The sixth insulating layer 60 described comprises the same material. A preliminary insulating layer P60 may be positioned on the fifth insulating layer 50 and the conductive pattern CP, and the preliminary insulating layer P60 may cover the conductive pattern CP.

[0196] Reference Figure 24 In one or more embodiments, during the step of etching a portion of the initial insulating layer P60 to form the sixth insulating layer 60, a connection opening COP and a main opening may be formed through the sixth insulating layer 60, a portion of the data conductive portion DCP being exposed through the connection opening COP, and the main opening being superimposed with the upper resin opening UROP. The main opening may be defined by the main insulating side surface MIS and the protruding insulating side surface PIS. (Refer to...) Figure 12 The descriptions of the first connecting opening COP1 and the first main opening MOP1 can be applied equally to the connecting opening COP and the main opening.

[0197] Reference Figure 25 In the step of forming the bridge conductive pattern BCP, the bridge conductive pattern BCP can be positioned on the conductive pattern CP and the sixth insulating layer 60. The sixth insulating layer 60 can cover the boundary between the pad conductive portion PCP and the data conductive portion DCP, and the bridge conductive pattern BCP can be located on the sixth insulating layer 60 covering the boundary between the pad conductive portion PCP and the data conductive portion DCP. Therefore, the bridge conductive pattern BCP can be continuous and can electrically connect the pad conductive portion PCP and the data conductive portion DCP, thereby improving the reliability of the display panel.

[0198] Although embodiments of this disclosure have been described, it is understood that this disclosure should not be limited to these embodiments, and various changes and modifications can be made by those skilled in the art as described in the spirit and scope of this disclosure. Therefore, the subject matter disclosed should not be limited to any single embodiment described herein, and the scope of this disclosure should be determined according to the appended claims, in which its functional equivalents are included.

Claims

1. A display panel having a display area and a non-display area adjacent to the display area, and the display panel comprising: The substrate layer includes a first resin layer and a second resin layer, the first resin layer being stacked with the display area and the non-display area, the second resin layer being on top of the first resin layer and defining an upper resin opening that is stacked with the non-display area; A pad electrode is stacked between the first resin layer and the second resin layer, and is superimposed on the non-display area, with a portion of the upper surface of the pad electrode exposed through the upper resin opening; A driving element layer includes: a barrier layer on top of the second resin layer, defining a barrier opening superimposed on the upper resin opening; a data line on top of the barrier layer; a conductive pattern including a pad conductive portion in the upper resin opening and contacting the pad electrode and a data conductive portion contacting the data line; an insulating layer on top of the conductive pattern, defining a connection opening exposing a portion of the data conductive portion and defining a main opening superimposed on the upper resin opening; and a bridge conductive pattern on the conductive pattern and the insulating layer, contacting the pad conductive portion through the upper resin opening and contacting the data conductive portion through the connection opening; and The display element layer includes a light-emitting element, which is stacked on top of the second resin layer and superimposed on the display area. The transistors of the driving element layer are electrically connected to the light-emitting element and to the data lines. The blocking opening is defined by a protruding blocking side surface adjacent to the connecting opening, and by a main blocking side surface surrounding a portion of the upper resin opening in a plan view. The main opening is defined by a protruding insulating side surface adjacent to the connecting opening, and by a main insulating side surface that surrounds a portion of the upper resin opening in the plan view and overlaps with the main blocking side surface in the plan view. The protruding blocking side surface is located between the protruding insulating side surface and the connection opening.

2. The display panel of claim 1, further comprising a first substrate insulating layer, the first substrate insulating layer being located between the first resin layer and the second resin layer, and below a portion of the pad electrode.

3. The display panel of claim 2, further comprising a second substrate insulating layer, the second substrate insulating layer being located between the first substrate insulating layer and the second resin layer, and having a portion above the pad electrode.

4. The display panel as claimed in claim 3, wherein, The first substrate insulating layer and the second substrate insulating layer comprise silicon oxide.

5. The display panel as claimed in claim 1, wherein, In the plan view, the upper resin opening has a larger dimension than the connecting opening.

6. The display panel as claimed in claim 1, wherein, In the plan view, the upper resin opening has a smaller size than the main opening.

7. The display panel as claimed in claim 1, wherein, The insulating layer overlaps with the boundary between the pad conductive portion and the data conductive portion.

8. The display panel as claimed in claim 1, wherein, The distance from the protruding blocking side surface to the center of the upper resin opening is greater than the distance from the main blocking side surface to the center of the upper resin opening.

9. The display panel as claimed in claim 1, wherein, The barrier layer includes at least one of silicon oxide and silicon nitride.

10. The display panel as claimed in claim 1, wherein, The blocking opening is defined by the protruding blocking side surface, the main blocking side surface, and the sub-blocking side surface connecting the protruding blocking side surface and the main blocking side surface. Wherein, the protruding blocking side surface is parallel to the first direction, and The sub-blocking side surface is parallel to a second direction that intersects with the first direction.

11. The display panel as claimed in claim 1, wherein, The pad electrode is configured as a plurality of pad electrodes, which are spaced apart in a first direction.

12. The display panel as claimed in claim 11, wherein, The upper resin opening is configured as a plurality of upper resin openings, and a portion of the upper surface of the plurality of pad electrodes is exposed through the plurality of upper resin openings.

13. The display panel as claimed in claim 1, wherein, The connection opening is between the upper resin opening and the display area.

14. The display panel as claimed in claim 1, wherein, The upper resin opening is located between the connection opening and the display area.

15. The display panel as claimed in claim 1, wherein, The upper resin opening includes a first upper resin opening and a second upper resin opening. The second upper resin opening is spaced apart from the first upper resin opening in a fourth direction. The fourth direction intersects the first direction and the second direction, which intersects the first direction. The connection opening includes a first connection opening and a second connection opening. The first connection opening is spaced apart from the first upper resin opening in the second direction, and the second connection opening is spaced apart from the second upper resin opening in the opposite direction to the second direction.

16. The display panel as claimed in claim 1, wherein, The connection opening includes: First connecting opening, adjacent to the display area; and The first-second connection opening is spaced apart from the first-first connection opening in the plan view, and the upper resin opening is located between the first-first connection opening and the first-second connection opening.

17. An electronic device, the electronic device comprising: Flexible circuit board; as well as The display panel, on the flexible circuit board, has a display area and a non-display area adjacent to the display area, and includes: The substrate layer includes a first resin layer and a second resin layer, wherein the first resin layer is stacked with the display area and the non-display area and defines a lower resin opening, and the second resin layer is on top of the first resin layer and defines an upper resin opening that is stacked with the non-display area. A pad electrode is stacked between the first resin layer and the second resin layer, and is superimposed on the non-display area. A portion of the lower surface of the pad electrode contacts the flexible circuit board through the lower resin opening, and a portion of the upper surface of the pad electrode is exposed through the upper resin opening. A driving element layer includes: a barrier layer on top of the second resin layer, defining a barrier opening superimposed on the upper resin opening; a data line on top of the barrier layer; a conductive pattern including a pad conductive portion in the upper resin opening and contacting the pad electrode and a data conductive portion contacting the data line; an insulating layer on top of the conductive pattern, defining a connection opening exposing a portion of the data conductive portion and defining a main opening superimposed on the upper resin opening; and a bridge conductive pattern on the conductive pattern and the insulating layer, contacting the pad conductive portion through the upper resin opening and contacting the data conductive portion through the connection opening; and The display element layer includes a light-emitting element, which is located on the second resin layer, stacked with the display area, and electrically connected to the data line. The blocking opening is defined by a protruding blocking side surface adjacent to the connecting opening, and by a main blocking side surface surrounding a portion of the upper resin opening in a plan view. The main opening is defined by a protruding insulating side surface adjacent to the connecting opening, and by a main insulating side surface that surrounds a portion of the upper resin opening in the plan view and overlaps with the main blocking side surface in the plan view. The protruding insulating side surface is located between the protruding blocking side surface and the upper resin opening.

18. The electronic device of claim 17, wherein, The driving element layer also includes transistors electrically connected to the light-emitting element and electrically connected to the data line.

19. The electronic device of claim 17, wherein, The data line is superimposed on the display area and the non-display area.

20. A method for manufacturing a display panel, the method comprising the following steps: A pad electrode is disposed on the first resin layer; A preliminary second resin layer is disposed on the first resin layer, and the preliminary second resin layer covers the pad electrode; A preliminary barrier layer is provided on the preliminary second resin layer; A portion of the initial second resin layer is etched to form a second resin layer, the second resin layer defining an upper resin opening to expose a portion of the upper surface of the pad electrode; A portion of the initial barrier layer is etched to form a barrier layer that defines a barrier opening overlapping the upper resin opening; A data line is installed on the barrier layer; A conductive pattern is provided, the conductive pattern including a pad conductive portion in the upper resin opening and in contact with the pad electrode and a data conductive portion in contact with the data line; A preliminary insulating layer is formed on the conductive pattern; A portion of the initial insulating layer is etched to form an insulating layer over the conductive pattern, defining a connection opening that exposes a portion of the data conductive portion, and defining a main opening that overlaps with the upper resin opening; as well as A bridge conductive pattern is formed on the conductive pattern and the insulating layer to contact the pad conductive portion through the upper resin opening and the data conductive portion through the connection opening. The blocking opening is defined by a protruding blocking side surface adjacent to the connecting opening, and by a main blocking side surface surrounding a portion of the upper resin opening in a plan view. The main opening is defined by a protruding insulating side surface adjacent to the connecting opening and a main insulating side surface that surrounds a portion of the upper resin opening in a plan view and overlaps with the main blocking side surface. The protruding blocking side surface is located between the protruding insulating side surface and the connection opening.

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