Integrated thin-film resistor and preparation method thereof

Abstract

The invention discloses an integrated thin-film resistor and a preparation method thereof. The preparation method comprises the following steps: S1, planarizing an intermetallic dielectric in a front-layer process to form an oxide layer; s2, performing first SiON deposition on the oxide layer to form an isolation layer; s3, chromium-silicon deposition and TiN deposition are sequentially carried out on the isolation layer, and tempering is carried out after a chromium-silicon layer and a window layer are formed respectively; s4, carrying out SiON deposition on the window layer for the second time; and S5, performing width definition, length definition, integrated circuit contact hole definition and integrated circuit lead definition on the chromium-silicon thin-film resistor to obtain the chromium-silicon thin-film resistor. The thin-film resistor is improved on the basis of an existing manufacturing method, the resistance value of the integrated thin-film resistor generated through the reaction process can be accurately controlled, and compared with a diffusion resistor and an injection resistor, the integrated thin-film resistor has a lower temperature coefficient.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an integrated thin-film resistor and its fabrication method. Background Technology

[0002] There are several types of resistors in integrated circuits, including diffusion resistors, injection resistors, and thin film resistors.

[0003] Diffusion resistor fabrication is simple but has lower precision and greater parasitic effects. Common diffusion resistors include base region diffusion resistors, emitter region diffusion resistors, base region channel resistors, epitaxial layer resistors, and buried layer resistors. Diffusion resistors are often fabricated simultaneously with the diffusion process, and their resistance accuracy ΔR / R can be controlled within ±20%, with a resistance temperature coefficient typically around 2000 ppm / ℃. Ion implantation resistors offer better uniformity and repeatability, higher precision, and resistance values ​​that can vary widely, with sheet resistance ranging from 50 Ω to 500 KΩ / □, and a smaller resistance temperature coefficient.

[0004] The sheet resistance of ion implantation is inversely proportional to the implantation dose, exhibiting a good linear relationship. The resistance can be adjusted by controlling the ion implantation dose. A disadvantage of ion implantation is that the sheet resistance varies depending on the implantation junction depth. j The thickness of the implanted layer is relatively small (ranging from 0.1 to 0.8 μm), and the thickness of the implanted layer is greatly affected by the depletion layer, resulting in the resistance value increasing with the increase of the voltage across the resistor.

[0005] Thin-film resistors (TFRs) offer advantages over diffusion and implantation resistors, including lower temperature coefficients, smaller parasitic parameters, and a wider range of thin-film resistivity. Furthermore, TFRs obtained through deposition also exhibit higher accuracy. TFRs are categorized into three types based on the materials used: Ni-Cr alloys, Cr-Si alloys, and Cr-SiO alloys. Among these, Cr-SiO alloys are the most commonly used resistive materials in surface-mount devices, hybrid integrated circuits, and monolithic integrated circuits due to their moderate resistance range and wide applicability.

[0006] Currently, IC chip manufacturing processes include diffusion resistors and ion implantation resistors. Diffusion resistors have a simple process but lower precision and greater parasitic effects; ion implantation resistors have higher precision, but their temperature coefficient of resistance cannot meet production requirements, thus necessitating adjustments to the reaction process for improvement.

[0007] In view of this, the existing technology should be improved in order to solve the aforementioned technical problems. Summary of the Invention

[0008] To address the existing technical problems, this invention proposes an integrated thin-film resistor and its preparation method. Based on existing manufacturing methods, the thin-film resistor is improved. The integrated thin-film resistor generated by this reaction process can have its resistance value precisely controlled and has a lower temperature coefficient compared to diffusion resistors and implantation resistors.

[0009] According to one aspect of the present invention, a method for fabricating an integrated thin-film resistor is provided, comprising the following steps: S1. An oxide layer is formed after planarizing the intermetallic dielectric in the previous process. S2. An insulating layer is formed after the first SiON deposition on top of the oxide layer; S3. Chromium silicon and TiN are deposited sequentially on the isolation layer to form a chromium silicon layer and a window layer, respectively, and then tempered. S4. Perform a second SiON deposition above the window layer; S5. Define the width, length, integrated circuit contact hole, and integrated circuit lead of the chromium-silicon thin film resistor to obtain the chromium-silicon thin film resistor.

[0010] According to one embodiment of the present invention, the thickness of the oxide layer ranges from 1700 to 2000 Å.

[0011] According to one embodiment of the present invention, the thickness of the insulating layer ranges from 800 to 1200 Å.

[0012] According to one embodiment of the present invention, the insulating layer is at least one of Si3N4 thin film or SiON thin film.

[0013] According to one embodiment of the present invention, the thickness of the chromium-silicon layer is in the range of 60~80 Å, and the thickness of the window layer is 600~800 Å.

[0014] According to one embodiment of the present invention, the deposition thickness of the second SiON deposition is 200~400 Å.

[0015] According to one embodiment of the present invention, the broad definition includes photolithography and dry etching processes, and the long definition includes photolithography, dry etching, and wet etching processes.

[0016] According to one embodiment of the present invention, the height of the integrated circuit contact hole ranges from 6000 to 8000 Å.

[0017] According to another aspect of the present invention, an integrated thin-film resistor is provided, which is prepared by any of the methods described above.

[0018] According to one embodiment of the present invention, the sheet resistance of the chromium-silicon thin film resistor is in the range of 1000~1200Ω / □, and the temperature coefficient of the chromium-silicon thin film resistor is <15PPM / ℃.

[0019] By adopting the above technical solution, the present invention has the following advantages compared with the prior art: it improves the thin film resistor based on the existing manufacturing method, and the integrated thin film resistor generated by this reaction process can accurately control the resistance value and has a lower temperature coefficient compared with diffusion resistor and injection resistor. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some implementation examples of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 A schematic flowchart of a method for fabricating an integrated thin-film resistor according to an exemplary embodiment of the present invention is shown; Figure 2 A schematic diagram of step S1 of a method for fabricating an integrated thin-film resistor according to an exemplary embodiment of the present invention is shown; Figure 3 A schematic diagram of step S2 of a method for fabricating an integrated thin-film resistor according to an exemplary embodiment of the present invention is shown; Figure 4 A schematic diagram of step S3 of a method for fabricating an integrated thin-film resistor according to an exemplary embodiment of the present invention is shown; Figure 5 A schematic diagram of step S4 of a method for fabricating an integrated thin-film resistor according to an exemplary embodiment of the present invention is shown; Figure 6 A schematic diagram with a broad definition is shown of a method for fabricating an integrated thin-film resistor according to an exemplary embodiment of the present invention; Figure 7 A schematic diagram showing a long definition of a method for fabricating an integrated thin-film resistor according to an exemplary embodiment of the present invention is provided; Figure 8 A schematic diagram illustrating the definition of an integrated circuit contact hole in a method for fabricating an integrated thin-film resistor according to an exemplary embodiment of the present invention is shown. Figure 9 A schematic diagram of the integrated circuit lead definition is shown in a method for fabricating an integrated thin-film resistor according to an exemplary embodiment of the present invention. Detailed Implementation

[0022] The following detailed description of the embodiments is intended to exemplify the principles of the present invention, but should not be construed as limiting the scope of the invention. The present invention can be implemented in many different forms and is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

[0023] These embodiments are provided to make this disclosure thorough and complete, and to fully express the scope of the invention to those skilled in the art. It should be noted that, unless otherwise specifically stated, the relative arrangement of components and steps, material composition, numerical expressions, and values ​​set forth in these embodiments should be interpreted as merely exemplary and not as limiting.

[0024] It should be noted that, in the description of this invention, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicating orientation or positional relationships, are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0025] It should also be noted that, in the description of this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention depending on the specific circumstances. When a specific device is described as being located between a first device and a second device, an intermediary device may or may not be present between the specific device and the first or second device.

[0026] All terms used in this invention have the same meaning as understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in general dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant art, and not as idealized or highly formalized, unless expressly defined herein.

[0027] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0028] like Figure 1 As shown, the present invention provides a method for fabricating an integrated thin-film resistor, which specifically includes the following steps: S1. An oxide layer is formed after planarizing the intermetallic dielectric in the previous process. S2. An insulating layer is formed after the first SiON deposition on top of the oxide layer; S3. Chromium silicon and TiN are deposited sequentially on the isolation layer to form a chromium silicon layer and a window layer, respectively, and then tempered. S4. Perform a second SiON deposition above the window layer; S5. Define the width, length, integrated circuit contact hole, and integrated circuit lead of the chromium-silicon thin film resistor to obtain the chromium-silicon thin film resistor.

[0029] The broad definition of chromium-silicon thin film resistors includes photolithography and dry etching processes, while the long definition includes photolithography, dry etching, and wet etching processes.

[0030] like Figure 2 As shown, in step S1, based on the above embodiments, an oxide layer is formed after planarizing the inter-metal dielectric in the previous layer process. The thickness of the oxide layer ranges from 1700 to 2000 Å. Inter-metal dielectrics (IMDs) are planarized to achieve global planarization of the wafer surface. This is particularly important in multilayer metal wiring structures, where each layer requires strict planarization to ensure the accuracy of subsequent processes. Global planarization reduces interlayer unevenness, allowing subsequent processes such as photolithography and etching to be performed more precisely, thereby improving manufacturing accuracy and product yield.

[0031] The formed oxide layer can serve as a protective layer, improving the device's resistance to physical damage and chemical corrosion. It also possesses excellent insulating properties, helping to isolate different circuit layers and reduce leakage current and crosstalk. In this invention, the process window for oxide layer deposition is determined based on the characteristics of the manufacturing process, including parameters such as temperature, pressure, and gas flow rate, thereby determining the oxide layer thickness to be 1700–2000 Å. In some specific embodiments, the oxide layer thickness is 1800 Å.

[0032] A planarized surface helps reduce electric field concentration, thereby reducing electrical stress on the device and improving reliability.

[0033] like Figure 3As shown, based on the above embodiments, an insulating layer is formed after a first SiON deposition on the oxide layer, with a thickness ranging from 800 to 1200 Å. The insulating layer formed after SiON deposition exhibits excellent insulation properties. SiON deposition on the oxide layer further enhances the device's insulation performance, effectively isolating external impurities and charges, protecting internal circuits and components from damage. The insulating layer can slow down or prevent the oxidation process, extending the device's lifespan. In this invention, the thickness ranges from 800 to 1200 Å depending on actual needs. In some specific embodiments, the insulating layer thickness is 1000 Å.

[0034] Based on the above embodiments, the insulating layer is at least one of Si3N4 thin film or SiON thin film. Si3N4 is a high resistivity material, which can serve as an excellent insulating material to reduce leakage current between devices. It can remain stable at high temperatures, making it suitable for processes requiring high-temperature treatment. It can also effectively block moisture and gas, protecting devices from environmental influences.

[0035] SiON has a high dielectric constant, which can be used to improve the storage capacity of capacitors. Its dielectric constant is between that of SiO2 and Si3N4, which helps to reduce parasitic capacitance in integrated circuits and can also improve the reliability of devices during long-term operation, especially under high temperature and high pressure conditions.

[0036] like Figure 4 As shown, based on the above embodiments, the thickness of the chromium-silicon layer ranges from 60 to 80 Å, and the thickness of the window layer ranges from 600 to 800 Å.

[0037] Chromium is a very hard metal. Adding it to silicon to form a chromium-silicon layer can significantly improve the surface's wear resistance and provide additional protection against chemical corrosion to the silicon substrate. The addition of chromium helps regulate the stress state of the chromium-silicon layer, reducing stress caused by mismatched coefficients of thermal expansion. The thickness of the chromium-silicon layer in this invention ranges from 60 to 80 Å, and in some specific embodiments, the thickness is 70 Å.

[0038] The TiN contained in the window layer can act as a diffusion barrier to prevent mutual diffusion between different materials, which helps to reduce the risk of electrostatic discharge (ESD), protect sensitive semiconductor devices, reduce the coefficient of friction, and reduce wear on mechanical parts.

[0039] like Figure 5As shown, based on the above embodiments, the deposition thickness of the second SiON deposition is 200~400 Å. SiON can act as a stress buffer, reducing stress between the window layer and the silicon substrate and preventing device damage caused by stress. During patterning processes, SiON can provide better etching selectivity, facilitating the achievement of finer device structures. In some specific embodiments, the deposition thickness of the second SiON deposition is 300 Å.

[0040] like Figure 6 and 7 As shown, in some specific embodiments, the broad definition includes photolithography and dry etching, while the long definition includes photolithography, dry etching, and wet etching. Photolithography can transfer fine patterns from a photomask onto a semiconductor wafer, achieving micron- or even nanometer-scale feature sizes.

[0041] Dry etching can achieve anisotropic etching, that is, the etching rate differs in the vertical and horizontal directions, which helps to form structures with high aspect ratios and can also reduce chemical damage and stress to materials.

[0042] Wet etching typically uses low-cost chemical solutions, resulting in lower equipment and material costs compared to other techniques such as dry etching. By selecting appropriate chemical solutions, highly selective etching of specific materials, such as silicon, silicon oxide, or other metal layers, can be achieved. Wet etching is generally isotropic, meaning the etching rate is the same in all directions. This contributes to uniform material removal, and the etching rate can be controlled by adjusting solution concentration, temperature, or etching time to meet different process requirements.

[0043] like Figure 8 As shown, based on the above embodiments, the height of the integrated circuit contact holes ranges from 6000 to 8000 Å. Contact holes allow vertical electrical connections to be formed between different metal interconnect layers of an integrated circuit, forming the basis of multilayer interconnect technology. Precisely defining the location and size of contact holes allows for the implementation of more circuit elements and connections within a limited space, improving chip integration. Precisely defined contact holes help ensure alignment accuracy between layers, avoiding short circuits or open circuits. Optimizing the size and shape of contact holes can reduce resistance through them, thereby improving circuit performance. In some specific embodiments, the height of the integrated circuit contact holes is 7000 Å.

[0044] like Figure 9As shown, step S5 also includes integrated circuit lead definition. After the integrated circuit lead definition is completed, the final integrated thin-film resistor is obtained. Lead definition provides the necessary external connection points for each integrated circuit element, ensuring that electrical signals can enter and exit the chip. Precise lead definition allows for more connection points to be achieved on a limited chip surface, increasing interconnect density. Good lead definition helps reduce interference and attenuation during signal transmission, maintaining signal integrity. Lead definition allows complex integrated circuits to be divided into multiple functional modules, each connected to the outside via specific leads.

[0045] This invention also proposes an integrated thin-film resistor, which is prepared using any of the methods described above. The integrated thin-film resistor produced through this reaction process allows for precise control of its resistance value and exhibits a lower temperature coefficient compared to diffusion resistors and implantation resistors.

[0046] In some specific embodiments, the sheet resistance of the chromium-silicon thin-film resistor ranges from 1000 to 1200 Ω / □, and the temperature coefficient of the chromium-silicon thin-film resistor is <15 PPM / ℃. Sheet resistance, also known as sheet resistance, refers to the resistance between the edges of a square thin-film conductive material. A key characteristic of sheet resistance is that the edge-to-edge resistance is the same for any size square; whether the side length is 1 meter or 0.1 meter, the sheet resistance is identical. Therefore, the sheet resistance is only related to factors such as the thickness of the conductive film.

[0047] In the method for fabricating integrated thin-film resistors according to embodiments of the present invention, the resistance value of the thin-film resistor can be controlled more precisely, achieving high-precision resistance matching, which is particularly important for analog circuits and radio frequency applications. The integrated thin-film resistors produced by the process of the present invention have a lower temperature coefficient, meaning that the resistance value changes less with temperature, thereby improving the stability and reliability of the circuit at different temperatures. Due to the precise control of the resistance value and the reduction of the temperature coefficient, the performance of the thin-film resistor in high-frequency applications is improved, reducing phase shift and amplitude attenuation during signal transmission. Under harsh environmental conditions, such as high temperatures or environments with large temperature fluctuations, the low-temperature-coefficient integrated thin-film resistor can maintain its performance, reducing device failure rates. By precisely controlling the resistance value, reliance on expensive trimmers can be reduced, production costs can be lowered, and the production process can be simplified.

[0048] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A method for fabricating an integrated thin-film resistor, characterized in that, Includes the following steps: S1. An oxide layer is formed after planarizing the intermetallic dielectric in the previous process. S2. An insulating layer is formed after the first SiON deposition is performed on the oxide layer. S3. Chromium silicon and TiN are deposited sequentially on the isolation layer to form a chromium silicon layer and a window layer, respectively, and then tempered. S4. Perform a second SiON deposition above the window layer; S5. Define the width, length, integrated circuit contact hole, and integrated circuit lead of the chromium-silicon thin film resistor to obtain the chromium-silicon thin film resistor.

2. The method for preparing the integrated thin-film resistor according to claim 1, characterized in that, The thickness of the oxide layer ranges from 1700 to 2000 Å.

3. The method for preparing the integrated thin-film resistor according to claim 2, characterized in that, The thickness of the insulating layer ranges from 800 to 1200 Å.

4. The method for preparing an integrated thin-film resistor according to claim 2, characterized in that, The insulating layer is at least one of Si3N4 thin film or SiON thin film.

5. The method for preparing an integrated thin-film resistor according to claim 2, characterized in that, The thickness of the chromium-silicon layer ranges from 60 to 80 Å, and the thickness of the window layer ranges from 600 to 800 Å.

6. The method for preparing an integrated thin-film resistor according to claim 1, characterized in that, The thickness of the second SiON deposition is 200~400 Å.

7. The method for preparing an integrated thin-film resistor according to claim 1, characterized in that, The broad definition includes photolithography and dry etching processes, while the long definition includes photolithography, dry etching, and wet etching processes.

8. The method for preparing an integrated thin-film resistor according to claim 1, characterized in that, The height range of the contact hole for the integrated circuit is 6000~8000 Å.

9. An integrated thin-film resistor, characterized in that, It is prepared by the method described in any one of claims 1-8.

10. The integrated thin-film resistor according to claim 9, characterized in that, The sheet resistance of the chromium-silicon thin film resistor is in the range of 1000~1200Ω / □, and the temperature coefficient of the chromium-silicon thin film resistor is <15PPM / ℃.

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