Packaging method and packaging body for realizing cavity-divided shielding

Abstract

The invention provides a packaging method and a packaging body for realizing separated cavity shielding, and belongs to the technical field of semiconductor packaging, in the packaging method, a distance is reserved between the side wall of the end part of an isolation wall and the edge of a substrate, the isolation wall does not need to be cut in the technological process of forming the packaging body, and the problems of material deformation and cutter loss caused by cutting can be avoided. In the technical process, a coating layer at the side wall of the end part of an isolation wall is removed to form a groove, a shielding layer is in contact with the side wall of the isolation wall at the groove, and the shielding layer is also in contact with the top surface of the isolation wall and covers the top surface and the side wall of the coating layer, so that the shielding layer and the isolation wall form conformal shielding contact; a complete electromagnetic shielding structure can be formed for each cavity needing electromagnetic shielding, the situation that a shielding layer cannot make contact with an isolation wall due to the fact that the isolation wall and the edge of the substrate keep a safe distance does not exist, and the electromagnetic shielding performance of the packaging body is effectively improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging, and more particularly to a packaging method and package for achieving cavity shielding. Background Technology

[0002] Cavity shielding technology is mainly used to suppress electromagnetic interference, improve signal integrity, and enhance product reliability. It also optimizes product heat dissipation and is widely used in various products involving high frequency, high speed, radio frequency, and electromagnetic sensitivity, such as smart wearable devices, aerospace electronic equipment, and IoT modules.

[0003] Appendix Figure 1 The diagram shows a schematic of a package structure with an isolation wall in the prior art. The package includes: a substrate 10, a chip 11 disposed on the surface of the substrate 10, and an isolation wall 12 for isolating the chip 11. The above structure needs to be further formed into a package through a molding process to complete the package fabrication. In the above structure, the isolation wall 12 can be attached according to shielding requirements to separate different areas within the package to form a package for achieving cavity shielding.

[0004] In existing technologies, the isolation wall 12 needs to extend beyond the edge of the package to expose its sidewall, and the excess portion needs to be removed by cutting the finished product. This process has significant drawbacks: during cutting, due to the high hardness of the isolation wall material (such as metal), continuous cutting of the complete cross-section by the tool can easily cause local stress concentration, resulting in processing defects such as deformation and wire drawing at the material edge, affecting the appearance and dimensional accuracy of the package; at the same time, high-frequency, high-force cutting will accelerate blade wear, causing problems such as chipping and rolling, significantly shortening the tool life and increasing production costs; in addition, the stress generated during the cutting process may be transmitted to the interior of the package, causing potential damage to the chip or substrate, reducing the yield and reliability of the finished product.

[0005] If the sidewall of the isolation wall 12 does not extend beyond the edge of the package and maintains a safe distance from the edge, the different cavities within the package that need to be isolated cannot be completely shielded, and the sidewall of the isolation wall 12 cannot make contact with the conformal shielding of the product's exterior, ultimately affecting the overall shielding effect of the product. If the sidewall of the isolation wall 12 maintains a safe distance from the edge of the package and does not extend, although it can avoid material deformation and tool wear caused by cutting, it will lead to a systematic decline in shielding effectiveness. On the one hand, because the isolation wall does not fully extend to the edge, there is an electromagnetic coupling path between different functional cavities within the package, resulting in signal crosstalk between different functional cavities; on the other hand, the sidewall of the isolation wall cannot directly contact the conformal shielding structure (such as the metal shielding layer or the outer shell) of the product's exterior, forming a break in the shielding layer. High-frequency signals may leak through the break, severely weakening the overall electromagnetic protection capability. This design contradiction means that the isolation wall cannot achieve effective isolation of the physical boundary and also destroys the integrity of electromagnetic shielding. Especially in communication and radar scenarios with stringent shielding requirements, it may lead to a significant degradation or even failure of equipment performance.

[0006] Therefore, how to design a packaging method and package that can avoid material deformation and tool wear caused by cutting, while forming complete electromagnetic shielding, is a problem that existing technologies need to solve. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a packaging method and packaging body for achieving cavity shielding, which can avoid material deformation and tool wear caused by cutting, and can form complete electromagnetic shielding.

[0008] To address the aforementioned problems, this invention provides a packaging method for achieving cavity shielding. The packaging method includes: setting an isolation wall and chips on the upper surface of a substrate, wherein multiple chips are isolated by the isolation wall, and the end sidewalls of the isolation wall are at a distance from the edge of the substrate; forming a covering layer disposed on the upper surface of the substrate, covering the isolation wall and the chips, and exposing the top surface of the isolation wall; removing the covering layer covering the end sidewalls of the isolation wall to expose the end sidewalls of the isolation wall; and forming a shielding layer covering the top surface and sidewalls of the covering layer, and the shielding layer also covering the exposed top surface and end sidewalls of the isolation wall.

[0009] Optionally, the step of setting the isolation wall and the chip on the upper surface of the substrate further includes: attaching the isolation wall to the upper surface of the substrate by means of an adhesive layer.

[0010] Optionally, the step of setting the isolation wall and the chip on the upper surface of the substrate further includes: fixing the chip to the upper surface of the substrate by means of mounting or soldering.

[0011] Optionally, the step of setting the isolation wall and the chip on the upper surface of the substrate further includes: first setting the chip on the upper surface of the substrate, and then setting the isolation wall on the upper surface of the substrate; or, first setting the isolation wall on the upper surface of the substrate, and then setting the chip on the upper surface of the substrate.

[0012] Optionally, the step of setting the isolation wall and the chip on the upper surface of the substrate further includes: the isolation wall includes multiple branches, and the end sidewall of each branch is at a distance from the edge of the substrate.

[0013] Optionally, the step of setting the isolation wall and the chip on the upper surface of the substrate further includes: setting a plurality of the isolation walls on the upper surface of the substrate, wherein the end sidewall of each isolation wall is at a distance from the edge of the substrate.

[0014] Optionally, the step of forming the overlay further includes: molding to form the overlay.

[0015] Optionally, the molding process for forming the encapsulation layer further includes: forming a molding material layer using an injection molding process, the molding material layer being disposed on the upper surface of the substrate and encapsulating the isolation wall and the chip; thinning the molding material layer until the top surface of the isolation wall is exposed, with the remaining molding material layer serving as the encapsulation layer.

[0016] Optionally, the step of thinning the molding compound layer further includes: after thinning the molding compound layer to expose the top surface of the partition wall, continuing to thin the molding compound layer and the partition wall to a set height.

[0017] Optionally, the step of molding to form the overlay further includes: forming the overlay using a film-assisted injection molding process, wherein the film covers the top surface of the barrier wall; and removing the film to expose the top surface of the barrier wall.

[0018] Optionally, the step of removing the covering layer covering the end sidewall of the isolation wall further includes: removing the covering layer covering the end sidewall of the isolation wall by laser ablation, drilling, or cutting.

[0019] Optionally, the step of removing the covering layer covering the end sidewall of the isolation wall further includes: in a direction perpendicular to the extension of the isolation wall on the substrate, the removal width of the covering layer is greater than the width of the end sidewall of the isolation wall.

[0020] Optionally, the step of removing the covering layer covering the end sidewall of the isolation wall further includes: in a direction perpendicular to the extension of the isolation wall on the substrate, the width of the removal of the covering layer is equal to the width of the end sidewall of the isolation wall.

[0021] Optionally, the step of forming the shielding layer further includes: forming the shielding layer using the same material as the isolation wall.

[0022] Optionally, the step of forming the shielding layer further includes: the shielding layer being pre-formed, or the shielding layer being formed using a sputtering process.

[0023] Optionally, the substrate is divided into multiple substrate units; the step of setting the isolation wall and the chip on the upper surface of the substrate further includes: setting the isolation wall and the chip on the upper surface of the substrate in each substrate unit, wherein multiple chips are isolated by the isolation wall in the substrate unit, and the end sidewall of the isolation wall is a distance from the edge of the substrate unit; the step of forming a cover layer further includes: forming the cover layer in each substrate unit; the step of removing the cover layer covering the end sidewall of the isolation wall further includes: removing the cover layer covering the end sidewall of the isolation wall in the substrate unit; cutting along a dicing channel to form multiple independent packaging units, wherein the dicing channel passes through the area where the cover layer is removed; the step of forming a shielding layer further includes: forming the shielding layer in each packaging unit.

[0024] Optionally, the step of cutting along the cutting path further includes: the isolation wall being located outside the cutting path.

[0025] The present invention also provides a package for achieving cavity shielding, the package comprising: a substrate; a chip disposed on the upper surface of the substrate; an isolation wall disposed on the upper surface of the substrate, wherein a plurality of chips are isolated by the isolation wall, and the end sidewall of the isolation wall is at a distance from the edge of the substrate; a covering layer disposed on the upper surface of the substrate for covering the chips and the isolation wall, and exposing the top surface and end sidewall of the isolation wall; and a shielding layer covering the top surface and sidewall of the covering layer, and the shielding layer also covering the exposed top surface and end sidewall of the isolation wall.

[0026] Optionally, the isolation wall is attached to the upper surface of the substrate by an adhesive layer.

[0027] Optionally, the chip is attached to the upper surface of the substrate via an adhesive layer or soldered to the upper surface of the substrate via a solder layer.

[0028] Optionally, the isolation wall includes multiple branches, and the end sidewall of each branch is a distance from the edge of the substrate.

[0029] Optionally, the package includes a plurality of the isolation walls, each of the isolation walls having an end sidewall that is a distance from the edge of the substrate.

[0030] Optionally, the covering layer has grooves extending toward the substrate, the grooves exposing the end sidewalls of the isolation wall.

[0031] Optionally, in a direction perpendicular to the extension of the isolation wall on the substrate, the width of the trench is greater than the width of the end sidewall of the isolation wall.

[0032] Optionally, in a direction perpendicular to the extension of the isolation wall on the substrate, the width of the trench is equal to the width of the end sidewall of the isolation wall.

[0033] Optionally, the material of the partition wall is metal.

[0034] Optionally, the metal is selected from one of copper, nickel, silver and gold or an alloy thereof.

[0035] Optionally, the shielding layer and the isolation wall are made of the same material.

[0036] In the above technical solution, the end sidewall of the isolation wall is a certain distance from the edge of the substrate. During the process of forming the package, there is no need to cut the isolation wall, thus avoiding material deformation and tool wear caused by cutting. During the process, the covering layer at the end sidewall of the isolation wall is removed to form a groove. The shielding layer contacts the sidewall of the isolation wall at the groove, and the shielding layer also contacts the top surface of the isolation wall, covering the top surface and sidewall of the covering layer. This allows the shielding layer to form a conformal shielding contact with the isolation wall, enabling the formation of a complete electromagnetic shielding structure for each cavity requiring electromagnetic shielding. There is no situation where the shielding layer cannot contact the isolation wall due to the safe distance between the isolation wall and the edge of the substrate, effectively improving the electromagnetic shielding performance of the package. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Appendix Figure 1 The diagram shown is a schematic of a package structure with an isolation wall in the prior art;

[0039] Appendix Figure 2 The diagram shown is a schematic representation of the steps of the encapsulation method for achieving cavity shielding according to the first specific embodiment of the present invention;

[0040] Appendix Figure 3The figure shown is a three-dimensional structural diagram of the isolation wall distributed on the substrate in the first specific embodiment of the present invention;

[0041] Appendix Figure 4 The figure shown is a three-dimensional structural diagram of the coating layer formed in the first specific embodiment of the present invention;

[0042] Appendix Figure 5 The figure shown is a three-dimensional structural diagram of the removal of the covering layer on the end sidewall of the isolation wall in the first specific embodiment of the present invention;

[0043] Appendix Figure 6 The figure shown is a three-dimensional structural diagram of the shielding layer formed in the first specific embodiment of the present invention;

[0044] Appendix Figure 7 The figure shown is a three-dimensional structural diagram of the isolation wall distributed on the substrate in the second specific embodiment of the present invention;

[0045] Appendix Figure 8 The figure shown is a three-dimensional structural diagram of the package body in the second specific embodiment of the present invention;

[0046] Appendix Figure 9 The figure shown is a three-dimensional structural diagram of the isolation wall distributed on the substrate in the third specific embodiment of the present invention;

[0047] Appendix Figure 10 The figure shown is a three-dimensional structural diagram of the package body in the third specific embodiment of the present invention;

[0048] Appendix Figure 11 The figure shown is a three-dimensional structural diagram of the isolation wall distributed on the substrate in the fourth specific embodiment of the present invention;

[0049] Appendix Figure 12 The figure shown is a three-dimensional structural diagram of the package body in the fourth specific embodiment of the present invention;

[0050] Appendix Figure 13 The diagram shown is a top view of the distribution of the isolation walls on the substrate in the fifth specific embodiment of the present invention.

[0051] Appendix Figure 14 The diagram shown is a top view of the structure forming the coating layer in the fifth specific embodiment of the present invention;

[0052] Appendix Figure 15 The figure shown is a top view of the structure of removing the covering layer of the end sidewall of the isolation wall inside the substrate unit in the fifth specific embodiment of the present invention.

[0053] Appendix Figure 16 The figure shown is a top view of the structure after cutting along the cutting path in the fifth specific embodiment of the present invention;

[0054] Appendix Figure 17 The diagram shown is a top view of the shielding layer structure in the fifth specific embodiment of the present invention;

[0055] Appendix Figure 18 The diagram shown is a top view of the structure of removing the covering layer of the end sidewall of the isolation wall inside the substrate unit in the sixth specific embodiment of the present invention. Detailed Implementation

[0056] The following detailed description, in conjunction with the accompanying drawings, illustrates the specific implementation methods of the encapsulation method and encapsulation body for achieving cavity shielding provided by the present invention.

[0057] Appendix Figure 2 The diagram illustrates the steps of a packaging method for achieving cavity shielding according to a first specific embodiment of the present invention. The packaging method includes: step S20, setting an isolation wall and chips on the upper surface of a substrate, wherein multiple chips are isolated by the isolation wall, and the end sidewall of the isolation wall is a distance from the edge of the substrate; step S21, forming a covering layer, the covering layer being disposed on the upper surface of the substrate, covering the isolation wall and the chips, and exposing the top surface of the isolation wall; step S22, removing the covering layer covering the end sidewall of the isolation wall to expose the end sidewall of the isolation wall; step S23, forming a shielding layer, the shielding layer covering the top surface and sidewall of the covering layer, and the shielding layer also covering the exposed top surface and end sidewall of the isolation wall.

[0058] The packaging method is divided into a single-chip operation mode and a complete operation mode. In the single-chip operation mode, the substrate is pre-cut into independent units that meet the requirements of a single package, and then steps S20 to S23 are performed individually on each unit. This operation mode can meet the personalized needs of packages with different varieties or requiring differentiated processing. In the complete operation mode, the substrate remains intact, and all substrate units are fabricated simultaneously on the entire board (steps S20 to S22), then uniformly cut and separated to form packaging units, and then a shielding layer is formed individually for each packaging unit (step S23). This operation mode is beneficial for improving production efficiency and ensuring consistency between packages. (Appendix) Figure 3 ~Attached Figure 6 This is a process flow diagram of a packaging method for achieving cavity shielding according to a specific embodiment of the present invention. In the first embodiment, the packaging method is a single-chip operation mode.

[0059] As attached Figure 2 and appendix Figure 3 As shown, among which, appendix Figure 3The figure shown is a three-dimensional structural diagram of the isolation wall 32 distributed on the substrate 30 in the first specific embodiment of the present invention. In step S20, the isolation wall 32 and the chip 31 are disposed on the upper surface of the substrate 30. The multiple chips 31 are isolated by the isolation wall 32. The end sidewall of the isolation wall 32 is a distance away from the edge of the substrate 30.

[0060] In a first specific embodiment, the material of the substrate 30 is selected from silicon, glass, metal, and ceramic. Silicon substrates have excellent semiconductor compatibility, are suitable for integration with chip 31 to achieve high-density interconnection, and are often used in advanced packaging such as system-in-package (SiP). Glass substrates have good insulation, high flatness, and lower cost than silicon, making them suitable for packaging radio frequency devices or display driver chips, and reducing signal loss. Metal substrates (such as copper and aluminum) have extremely high thermal conductivity, which can quickly dissipate heat from chip 31, and are often used in high-heat-generating scenarios such as power devices or automotive electronics. Ceramic substrates (such as alumina and aluminum nitride) have high insulation, high reliability, and high temperature resistance, and their coefficient of thermal expansion matches that of chip 31 well, making them suitable for harsh environments such as aerospace and military. Substrates 30 made of different materials are combined with chip 31 and isolation wall 32 through processes such as lamination and bonding, which can specifically solve core problems such as heat dissipation, signal integrity, or environmental protection.

[0061] The chip 31 is disposed on the upper surface of the substrate 30. In a first specific embodiment, the chip 31 includes a logic chip responsible for data processing, a memory chip for data storage, a power chip for power conversion, a sensor chip for sensing environmental signals, a radio frequency chip supporting wireless communication, and a photonic chip integrating optical devices, etc. Different types of chips have varying requirements for electrical shielding, heat dissipation, mechanical stability, and environmental protection in their packaging. These requirements need to be specifically optimized through the collaborative design of the isolation wall 32 and the substrate 30 to meet diverse technical requirements such as logic control, data storage, power conversion, sensing and detection, wireless communication, and optoelectronic integration.

[0062] In this step, the chip 31 is fixed to the upper surface of the substrate 30 by means of mounting or soldering. In the first specific embodiment, in this step, the chip 31 is fixed to the upper surface of the substrate 30 by means of mounting.

[0063] Surface Mount Technology (SMT) enables the precise mounting of chip 31 onto substrate 30. SMT offers advantages such as high precision, high efficiency, and low cost, and primarily includes the following steps: uniformly applying solder paste to the pads of substrate 30 to provide soldering material for subsequent chip 31 mounting; precisely placing chip 31 onto the pads; and performing reflow soldering, where heating melts the solder paste to form reliable electrical and mechanical connections.

[0064] Soldering methods mainly include wire bonding, flip-chip bonding, chip-on-bump, and chip stacking technologies. Wire bonding is suitable for traditional packaging and has a lower cost. It mainly includes the following steps: fixing the chip 31 to the substrate 30 with conductive or non-conductive adhesive; using a bonding machine to heat / ultrasonic energy, soldering one end of a metal wire to the pad on the chip 31 and the other end to the pad on the substrate 30, forming an arc-shaped wire. Flip-chip bonding is used for soldering high-performance chips 31 and in high-density packaging. It has good heat dissipation and can achieve high-density packaging. It mainly includes the following steps: creating solder balls on the front side of the chip 31 using electroplating or ball-planting processes; flipping the chip 31 to align with the pads on the substrate 30; connecting the solder balls to the pads on the substrate 30 using reflow soldering or thermoforming; and underfilling the space between the chip 31 and the substrate 30 with epoxy resin to enhance reliability. Various functional packages have different requirements for the connection method between the chip 31 and the substrate 30, requiring targeted optimization to meet diverse technical requirements such as logic control, data storage, power conversion, sensing, wireless communication, and optoelectronic integration. For high-density integration requirements, chip-on-bump and chip stacking technologies can enable multi-layer chip interconnects.

[0065] The isolation wall 32 is disposed on the upper surface of the substrate 30. The material of the isolation wall 32 is a metal, selected from copper, aluminum, nickel, silver, and gold, or an alloy thereof. In the first specific embodiment, the material of the isolation wall 32 is copper. From an electrical performance perspective, copper has extremely high conductivity, second only to silver, which can improve the shielding effect of signals between chips 31, making it particularly suitable for high-frequency circuit packaging with stringent signal integrity requirements. In terms of heat dissipation, copper has excellent thermal conductivity, which, in addition to the shielding effect, can quickly conduct the heat generated by the chip 31 to the outside of the package, avoiding local overheating and improving the working stability and lifespan of the chip 31. In terms of mechanical properties, copper has good strength and ductility, is not easily deformed or broken, and can also withstand the pressure and stress during the packaging process. In addition, compared with precious metals such as gold and silver, copper is cheaper, which is conducive to large-scale production; compared with metals such as aluminum and nickel, copper performs better in terms of oxidation resistance and corrosion resistance, and can maintain the structural and performance stability of the isolation wall 32 for a long time in complex environments, ensuring the reliability of the package.

[0066] In a first embodiment, the isolation wall 32 is attached to the upper surface of the substrate 30 via an adhesive layer. In this first embodiment, an adhesive layer is first applied to the substrate 30, and then the isolation wall 32 is fixed to the adhesive layer. The adhesive layer can be a conductive adhesive, epoxy resin adhesive, acrylic adhesive, silicone, polyimide adhesive, thermal interface material, etc. Different packages have different requirements for the adhesive layer. If conductivity is required, a conductive adhesive can be selected as the adhesive layer; if the bonding strength between the isolation wall 32 and the substrate 30 needs to be improved, an epoxy resin adhesive or a polyimide adhesive can be selected as the adhesive layer; if flexibility or cushioning is required, silicone or acrylic adhesive can be selected as the adhesive layer; if it needs to be used in a high-temperature environment, silicone or polyimide adhesive can be selected as the adhesive layer; if thermal conductivity is required, a thermal interface material can be selected as the adhesive layer. In one specific embodiment, the isolation wall 32 is electrically connected to the substrate 30 and grounded through the substrate 30. This allows the electromagnetic shielding structure formed by the isolation wall 32 and the subsequent shielding layer in the package formed using the packaging method of the present invention to be grounded through the substrate 30, thereby achieving the electromagnetic shielding function. In other specific embodiments, the isolation wall 32 is merely fixed to the substrate 30 and is not electrically connected. The electromagnetic shielding structure formed by the isolation wall 32 and the shielding layer is grounded through the shielding layer and the substrate 30, thereby achieving the electromagnetic shielding function.

[0067] The shape of the isolation wall 32 can be designed according to the cavity requirements of the package. The shape of the isolation wall 32 can be linear, L-shaped, cross-shaped, etc. In a first specific embodiment, the isolation wall 32 is linear, which is disposed in the middle of the substrate 30 and extends along the Y direction on the substrate 30, dividing the substrate 30 into two regions. Multiple chips 31 are isolated by the isolation wall 32 and are respectively disposed in the two regions of the substrate 30. Along the extension direction of the substrate 30 (as shown in the Y direction), the isolation wall 32 has a first end 321 and a second end 322 disposed opposite to each other. The sidewall of the first end 321 is located within the edge of the substrate 30 and is at a first distance H1 from the edge of the substrate 30. The sidewall of the second end 322 is located within the edge of the substrate 30 and is at a second distance H2 from the edge of the substrate 30. The first distance H1 and the second distance H2 can be set according to the requirements of the package. In a first embodiment, the first distance H1 and the second distance H2 are equal; in another embodiment, in order to accommodate the distribution of devices in different regions of the substrate 30, the first distance H1 and the second distance H2 are not equal.

[0068] In some specific embodiments, in this step, the isolation wall includes multiple branches, and in the extension direction of each branch along the substrate, the end sidewall of each branch is a distance from the edge of the substrate. The distances of the end sidewalls of different branches from the edge of the substrate may be the same or different.

[0069] As attached Figure 7 As shown, this is a three-dimensional structural diagram of the isolation wall distributed on the substrate in the second specific embodiment of the present invention. The isolation wall 42 is L-shaped and has two branches, dividing the substrate 40 into two regions. In the first branch along the extension direction of the substrate 40, the isolation wall 42 has a first end 421. The sidewall of the first end 421 is located within the edge of the substrate 40 and is at a first distance H1 from the edge of the substrate 40. In the second branch along the extension direction of the substrate 40, the isolation wall 42 has a second end 422. The sidewall of the second end 422 is located within the edge of the substrate 40 and is at a second distance H2 from the edge of the substrate. The first distance H1 and the second distance H2 may be the same or different.

[0070] As attached Figure 9 The diagram shows a three-dimensional structural representation of the partition walls distributed on the substrate in a third embodiment of the present invention. The partition wall 52 is cross-shaped with four branches, dividing the substrate 50 into four regions. Along the extension direction of the first branch along the substrate 50, the partition wall 52 has a first end 521, the sidewall of which is located within the edge of the substrate 50 and at a first distance from the edge of the substrate 50. Along the extension direction of the second branch along the substrate 50, the partition wall 52 has a second end 522, the sidewall of which is located within the edge of the substrate 50 and at a first distance from the edge of the substrate 50. The partition wall 52 has a third end 523 located within the edge of the substrate 52 and at a third distance from the edge of the substrate 52. In the direction of extension of the third branch along the substrate 50, the partition wall 52 has a fourth end 524 located within the edge of the substrate 50 and at a fourth distance from the edge of the substrate 50. The first distance, the second distance, the third distance, and the fourth distance may be the same or different.

[0071] In one specific embodiment, in this step, a plurality of isolation walls are formed on the upper surface of the substrate, and the end sidewall of each isolation wall is spaced a distance from the edge of the substrate. The plurality of isolation walls are arranged separately from each other. (See attached diagram) Figure 11The diagram shown is a three-dimensional structural schematic of the isolation walls distributed on the substrate in the fourth embodiment of the present invention. Two isolation walls 62 are disposed on the upper surface of the substrate 60. The two isolation walls 62 are separated from each other and arranged in parallel, dividing the substrate 60 into three regions, each of which is provided with the chip 61. In another embodiment, the multiple isolation walls 60 may also be arranged in a non-parallel manner.

[0072] The process of setting the isolation wall and chip on the upper surface of the substrate can adopt different implementation sequences according to actual needs. For example, different implementation sequences can be adopted based on the interface bonding strength requirements, whether there is a risk of material contamination between processes, thermal expansion coefficient matching design, and whether the mechanical strength standards of the final package structure are met. In a first specific embodiment, the step of setting the isolation wall 32 and chip 31 on the upper surface of the substrate 30 further includes: first setting the chip 31 on the upper surface of the substrate 30, and then setting the isolation wall 32 on the upper surface of the substrate 30, so as to avoid the isolation wall 32 interfering with the subsequent chip 31 mounting accuracy, which is particularly suitable for scenarios where the chip 31 is small in size or has high mounting accuracy requirements. In another specific embodiment, the isolation wall 32 is set on the upper surface of the substrate 30 first, and then the chip 31 is set on the upper surface of the substrate 30 to strictly define the position of the chip 31. In another specific embodiment, some chips 31 are set on the upper surface of the substrate 30 first, then the isolation wall 32 is set on the upper surface of the substrate 30, and finally the remaining chips 31 are set on the upper surface of the substrate 30.

[0073] In a first embodiment, this step further includes integrating passive devices on the upper surface of the substrate 30 to improve circuit functionality and optimize electrical performance. The passive devices mainly include three categories of basic components: capacitors (for power supply decoupling and signal filtering), inductors (for impedance matching and energy storage), and resistors (for current limiting and signal conditioning). The passive devices can be precisely mounted on pre-defined pads on the substrate 30 using surface mount technology (SMT), or embedded passive components can be directly formed on the surface of the substrate 30 using thin-film deposition. In the first embodiment, the passive device integration process is completed before chip 31 is mounted. In another embodiment, the passive devices are integrated after chip 31 is mounted.

[0074] As attached Figure 2 and appendix Figure 4 As shown, among which, appendix Figure 4 The diagram shown is a three-dimensional structural schematic of the coating layer formed in the first specific embodiment of the present invention. In step S21, a coating layer 33 is formed. The coating layer 33 is disposed on the upper surface of the substrate 30, covering the isolation wall 32 and the chip 31, and exposing the top surface of the isolation wall 32. The end sidewalls of the isolation wall 32 are covered by the coating layer 33.

[0075] In one specific embodiment, the step of forming the encapsulation layer 33 further includes: molding to form the encapsulation layer 33. The material of the encapsulation layer 33 is a molding compound. Molding compounds are abundant and inexpensive, and their molding process is simple, making them suitable for large-scale mass production and effectively reducing packaging costs.

[0076] In a first specific embodiment, the step of molding to form the covering layer 33 further includes:

[0077] A molding compound layer is formed using an injection molding process. This molding compound layer is disposed on the upper surface of the substrate 30 and covers the isolation wall 32 and the chip 31. The molding compound layer also covers the top surface and end sidewalls of the isolation wall 32. In this step, the device to be molded is placed in a metal mold cavity; molten plastic material (such as ABS, PC, PP, etc.) is injected into the closed metal mold cavity; after cooling and solidification, the mold is opened and the product is removed.

[0078] After the molding compound layer is formed, it is thinned until the top surface of the isolation wall 32 is exposed, and the remaining molding compound layer serves as the covering layer 33. In this step, one or more of the following processes can be used to thin the molding compound layer: mechanical grinding, chemical mechanical polishing, laser ablation, and plasma etching. For example, mechanical grinding can be used for rough thinning first, followed by chemical mechanical polishing for fine finishing.

[0079] In a first specific embodiment, the step of thinning the molding compound layer further includes: thinning the molding compound layer until the top surface of the isolation wall 32 is exposed, and then continuing to thin the molding compound layer and the isolation wall 32 to a set height to form a flat surface. Continuing to thin the molding compound layer and the isolation wall 32 to the set height can control the overall thickness of the package, meet the requirements of ultra-thin packaging, ensure that the top surface of the isolation wall 32 is at the same height as the surface of the overlay layer 33, improve surface flatness, avoid defects caused by step differences in subsequent processes (e.g., the process of forming a shielding layer), balance the difference in the coefficient of thermal expansion (CTE) between the molding compound and the isolation wall 32, reduce the risk of warpage, and optimize the mechanical properties, electrical characteristics, and compatibility with subsequent processes of the package.

[0080] In another specific embodiment, the step of molding to form the covering layer 33 further includes:

[0081] The coating layer 33 is formed using a film-assisted molding (FAM) process, with the film covering the top surface of the isolation wall 32. This step mainly includes: attaching the film to the top surface of the isolation wall 32; placing the structure with the film attached into the mold cavity; injecting molding compound into the mold to form the coating layer 33, where the top surface of the isolation wall 32 is covered by the film, isolating the molding compound, but the molding compound does not cover the top surface of the isolation wall 32. The film is then removed to expose the top surface of the isolation wall 32. In this step, processes such as mechanical peeling, laser ablation, chemical dissolution, and thermal decomposition can be used to remove the film.

[0082] The film-assisted injection molding process can directly form a coating layer 33 that meets the set requirements by precisely controlling the film pre-setting and injection molding process. It can also ensure that the top surface of the isolation wall 32 is precisely exposed outside the coating layer 33, completely avoiding the subsequent thinning process required in the traditional process. This not only significantly simplifies the manufacturing process, but also eliminates quality problems such as surface damage and uneven thickness that may be caused by the thinning process.

[0083] As attached Figure 2 and appendix Figure 5 As shown, among which, appendix Figure 5 The figure shown is a three-dimensional structural diagram of removing the covering layer covering the end sidewall of the isolation wall in the first specific embodiment of the present invention. In step S22, the covering layer 33 covering the end sidewall of the isolation wall 32 is removed to expose the end sidewall of the isolation wall 32.

[0084] In this step, the top surface of the isolation wall 32 is exposed to the covering layer 33. Using the top surface of the isolation wall 32 as a reference, the covering layer 33 covering the end sidewall of the isolation wall 32 can be removed. The area where the covering layer 33 is removed forms a trench 331, which exposes the end sidewall of the isolation wall 32. In a direction perpendicular to the connection surface between the isolation wall 32 and the substrate 30, the trench 331 penetrates the covering layer 33 to the substrate 30, exposing a portion of the upper surface of the substrate 30.

[0085] The end sidewall of the isolation wall 32 is located in the groove 331 of the covering layer 33. Since the isolation wall 32 does not protrude from the covering layer 33, there is no need to cut the isolation wall 32 during the process of forming the package, which can avoid material deformation and tool wear caused by cutting.

[0086] In this step, the covering layer 33 covering all end sidewalls of the isolation wall 32 is removed. (See attached image) Figure 3As shown, in the first specific embodiment, the isolation wall 32 is in the shape of a straight line, and the covering layer 33 covering the first end sidewall and the second end sidewall of the isolation wall 32 is removed, as shown in the attached figure. Figure 7 As shown in the second specific embodiment, the isolation wall 42 is L-shaped, and the covering layer covering the sidewalls of the first end 421 and the second end 422 of the isolation wall 42 is removed, as shown in the attached figure. Figure 9 As shown, in the third specific embodiment, the isolation wall 52 is cross-shaped, and the covering layer 52 covering the side wall of the first end 521, the side wall of the second end 522, the side wall of the third end 523, and the side wall of the fourth end 524 of the isolation wall 52 is removed.

[0087] In a first embodiment, the step of removing the covering layer 33 covering the end sidewall of the isolation wall 32 further includes: removing the covering layer 33 covering the end sidewall of the isolation wall 32 using laser ablation, drilling, or cutting processes. In the first embodiment, the encapsulation method is a single-piece operation mode, and the area of ​​the covering layer 33 to be removed is exposed on the side of the structure, so the covering layer 33 covering the end sidewall of the isolation wall 32 can be removed using laser ablation or cutting processes.

[0088] In a first specific embodiment, in the direction perpendicular to the extension of the partition wall 32 on the substrate 30, as shown in the attached... Figure 5 In the X direction, the removal width of the covering layer 33 is greater than the width of the end sidewall of the isolation wall 32, so as to avoid material residue of the covering layer 33, which would affect the contact between the subsequently formed shielding layer and the isolation wall 32, and ensure that the end sidewall of the isolation wall 32 is completely exposed, thereby increasing the contact area between the subsequently formed shielding layer and the isolation wall 32 and improving the shielding performance.

[0089] In another specific embodiment, the step of removing the covering layer covering the end sidewall of the isolation wall further includes: in the direction perpendicular to the extension of the isolation wall on the substrate 30, the width of the covering layer removed is equal to the width of the end sidewall of the isolation wall, so as to reduce the amount of covering layer removed, maximize the structural support function of the covering layer, avoid excessive removal that would lead to a decrease in the mechanical strength of the package, and reduce the risk of package warpage.

[0090] As attached Figure 2 and appendix Figure 6 As shown, among which, appendix Figure 6 The diagram shown is a three-dimensional structural schematic of the shielding layer formed in the first specific embodiment of the present invention. In step S23, a shielding layer 34 is formed. The shielding layer 34 covers the top surface and sidewalls of the covering layer 33, and also covers the exposed top surface and end sidewalls of the isolation wall 32. (See attached diagram.) Figure 6 The top surface and end sidewalls of the isolation wall 32 are shown in dashed lines.

[0091] In this step, the shielding layer 34 is formed within the trench 331 and contacts the end sidewall of the isolation wall 32 located within the trench 331. The shielding layer 34 also contacts the top surface of the isolation wall 32 and covers the top surface and sidewall of the covering layer 33, creating a conformal shielding contact between the shielding layer 34 and the isolation wall 32. This ensures a complete electromagnetic shielding structure for each chamber requiring electromagnetic shielding, preventing situations where the shielding layer 34 cannot contact the isolation wall 32 due to a safe distance between the isolation wall 32 and the edge of the substrate 30. Conformal shielding emphasizes the tight fit between the shielding layer 34 and the isolation wall 32, forming a continuous shielding structure through seamless connection, effectively blocking external electromagnetic interference while preventing internal signal leakage. In some embodiments, the shielding layer 34 also covers the sidewall of the substrate 30 and is electrically connected to the sidewall of the substrate 30, and is grounded through the substrate 30. This allows the electromagnetic shielding structure formed by the isolation wall 32 and the shielding layer 34 in the package formed using the packaging method of the present invention to be grounded through the substrate 30, thereby achieving electromagnetic shielding. In other embodiments, the shielding layer 34 is not electrically connected to the sidewall of the substrate 30. When the package is mounted on an external substrate (e.g., a printed circuit board), the bottom of the shielding layer is electrically connected to the external substrate and is grounded through the external substrate. This allows the electromagnetic shielding structure formed by the isolation wall 32 and the shielding layer 34 to be grounded through the external substrate, thereby achieving electromagnetic shielding.

[0092] In the first specific embodiment, the shielding layer 34 is formed using the same material as the isolation wall 32. Using the same material as the isolation wall 32 to form the shielding layer 34 makes its fabrication easier, eliminates interfacial barriers between different materials, improves metallurgical compatibility between materials, reduces the risk of interfacial reactions, and enhances connection strength and reliability. Regarding performance consistency, the matching thermal expansion coefficients of the same materials effectively reduce stress concentration caused by expansion differences during temperature changes, preventing problems such as warping and cracking of the package. Simultaneously, the uniformity of materials ensures the synergy between the shielding layer 34 and the isolation wall 32 in electromagnetic shielding, heat dissipation, and other functions, optimizing the overall performance of the package and ensuring the stable operation of the chip 31 in complex environments.

[0093] In a first embodiment, the shielding layer 34 is made of metal, selected from copper, aluminum, nickel, silver, and gold, or an alloy thereof. In the first embodiment, both the shielding layer 34 and the isolation layer are made of copper to reduce costs, effectively improve the signal shielding effect between the chips 31, and quickly conduct the heat generated by the chips 31 during operation to the outside of the package.

[0094] In some specific embodiments, the step of forming the shielding layer 34 further includes: the shielding layer 34 being pre-formed, or the shielding layer 34 being formed by a sputtering process.

[0095] In a first embodiment, the shielding layer 34 is formed using a sputtering process. The sputtering process can form a shielding layer 34 of uniform and controllable thickness on the surface of the covering layer 33, and it also ensures that the shielding layer 34 is uniformly formed on the surface of the isolation wall 32 exposed above the covering layer 33. This design is particularly important in fields sensitive to electromagnetic environments, such as high-frequency signal processing and 5G communication. It not only reduces signal crosstalk and ensures stable operation of the chip 31, but also improves the package's resistance to electromagnetic pulses. Furthermore, the conformal shielding structure formed by the shielding layer 34 and the isolation wall 32, in conjunction with the substrate 30 and the chip 31, further enhances the mechanical protection performance of the package, resisting external physical impacts and environmental corrosion.

[0096] In another specific embodiment, the shielding layer 34 is pre-formed. Materials such as metal are processed into the required geometric shape using precision stamping or etching processes. In this step, the shielding layer 34 is fitted onto the covering layer 33. The shielding layer 34 is fixed to the substrate 30 or to the surface of the covering layer 33 by means of conductive adhesive bonding or laser welding. This pre-forming method is suitable for applications requiring high mechanical strength or complex three-dimensional structures.

[0097] Appendix Figure 13 ~Attached Figure 16 This is a process flow diagram of the packaging method for achieving cavity shielding according to the fifth embodiment of the present invention. In the fifth embodiment, the packaging method is a whole-system operation mode.

[0098] As attached Figure 13 As shown, attached Figure 13 The diagram shown is a top view of the distribution of isolation walls on a substrate in the fifth embodiment of the present invention. The substrate 70 is divided into multiple substrate units 701. The isolation wall 72 and the chip 71 are provided on the upper surface of the substrate 70 in each substrate unit 701. In the substrate unit 701, multiple chips 71 are isolated by the isolation wall 72. The end sidewall of the isolation wall 72 is a distance from the edge of the substrate unit 701.

[0099] In the fifth embodiment, the substrate 70 is a single board divided into multiple regularly arranged substrate units 701, each substrate unit 701 having standardized geometric dimensions and functional area divisions. The isolation walls 72 and the chips 71 are distributed identically on all the substrate units 701 to facilitate batch operation by automated equipment. The isolation walls 72 and the chips 71 are disposed on the upper surface of each substrate unit 701. The arrangement of the isolation walls 72 and the chips 71 can refer to the arrangement of the isolation walls and the chips in the single-chip operation mode.

[0100] As attached Figure 14 As shown, attached Figure 14 The diagram shown is a top view of the structure of the cladding layer formed in the fifth embodiment of the present invention. A cladding layer 73 is formed, which is disposed on the upper surface of the substrate 70, covering the isolation wall 72 and the chip 71, and exposing the top surface of the isolation wall 72. In this step, each substrate unit 701 forms the cladding layer 73, and the cladding layer 73 covers the entire substrate 70. (See attached diagram.) Figure 4 The top surface of the isolation wall 72 is shown in dashed lines.

[0101] In one specific embodiment, the step of forming the coating layer 73 further includes: molding to form the coating layer 73. The molding method may refer to the molding method in a single-piece operation mode.

[0102] In a fifth embodiment, the method of molding to form the encapsulation layer 73 includes: forming a molding material layer using an injection molding process, the molding material layer encapsulating all the isolation walls 72 and the chip 71, and covering the top surface and end sidewalls of all the isolation walls 72. The molding material layer is then thinned to expose the top surface of all the isolation walls 72. In the fifth embodiment, after thinning the molding material layer to expose the top surface of the isolation walls 72, the molding material layer and the isolation walls 72 are further thinned to a predetermined height to form a flat surface.

[0103] In another specific embodiment, the method of molding to form the covering layer 73 includes: forming the covering layer 73 using a film-assisted injection molding process. In this method, the top surfaces of all the partition walls 72 are covered by a film, and the molding compound does not cover the top surfaces of the partition walls 72. After removing the film, the top surfaces of all the partition walls 72 are exposed.

[0104] As attached Figure 15 As shown, attached Figure 15The diagram shown is a top view of the structure of removing the covering layer covering the end sidewall of the isolation wall 72 inside the substrate unit 701 in the fifth embodiment of the present invention. In this step, the covering layer 73 covering the end sidewall of the isolation wall 72 inside the substrate unit 701 is removed to expose the end sidewall of the isolation wall 72 located on each substrate unit 701.

[0105] The step of removing the covering layer 73 covering the end sidewall of the isolation wall 72 further includes: removing the covering layer 73 covering the end sidewall of the isolation wall 72 by laser ablation, drilling, or cutting. In the fifth specific embodiment, the encapsulation method is an overall operation mode. If the area where the covering layer 73 needs to be removed is blocked by other units, then the covering layer 73 covering the end sidewall of the isolation wall 72 can be removed by laser ablation or drilling.

[0106] In the fifth embodiment, the isolation wall 72 is a straight line extending along the Y direction. The end sidewalls of the two isolation walls 72 located on two adjacent substrate units 701 in the Y direction are arranged opposite each other. The distance between the two end sidewalls is the maximum distance that the removal process can perform. Therefore, during the removal operation, the covering layer 73 between the end sidewalls of the two isolation walls 72 is completely removed to further prevent the covering layer 73 material from remaining on the end sidewalls of the isolation walls 72. This also provides a larger execution space for the removal operation, a more relaxed tolerance range for the removal process, and significantly reduces the process difficulty. In the fifth embodiment, after removing the covering layer 73, a trench 731 is formed. The trenches 731 corresponding to the end sidewalls of the two isolation walls 72 located on two adjacent substrate units 701 in the Y direction are connected.

[0107] As attached Figure 16 As shown, attached Figure 16 The diagram shown is a top view of the structure after cutting along the cutting path in the fifth specific embodiment of the present invention. The cutting is performed along the cutting path to form multiple independent encapsulation units. The cutting path passes through the area where the covering layer 73 is removed.

[0108] In this step, the cutting channel is positioned between adjacent substrate units 701. A mechanical cutting process is used along the cutting channel to cut the cladding layer 73 and the substrate 70, forming multiple independent encapsulation units. The cutting channel passes through the area where the cladding layer 73 is removed, exposing the end sidewall of the isolation wall 72 in the formed encapsulation unit. In the fifth embodiment, the isolation wall 72 is located outside the cutting channel. During the cutting process along the cutting channel, the isolation wall 72 is not cut, thus avoiding material deformation and tool wear caused by cutting.

[0109] As attached Figure 17 As shown, attached Figure 17 The diagram shown is a top view of the shielding layer formed in the fifth embodiment of the present invention. In this step, each of the encapsulation units forms the shielding layer 74. The method for forming the shielding layer 74 can refer to the method for forming the shielding layer 74 in the single-chip operation mode. (See attached diagram.) Figure 17 The top surface of the isolation wall 72 is shown in dashed lines.

[0110] Depending on the shape and arrangement of the isolation wall 72, the end sidewalls of the isolation wall 72 located on two adjacent substrate units 701 may be arranged opposite to each other or not opposite to each other. The groove 731 formed in the step of removing the covering layer 73 may also be an independent groove or a groove that runs through two adjacent substrate units 701.

[0111] As attached Figure 13 As shown, the isolation wall 72 is a straight line extending along the Y direction. The end sidewalls of the two isolation walls 72 located on two adjacent substrate units 701 in the Y direction are arranged opposite each other, as shown in the attached figure. Figure 15 As shown, in the step of removing the covering layer 73 covering the end sidewall of the isolation wall 72 within the substrate unit 701, the grooves 731 at the end sidewalls of the two isolation walls 72 located on two adjacent substrate units 701 in the Y direction are connected to form a through groove.

[0112] In some specific embodiments, the isolation wall is L-shaped, with its two sides extending along the X and Y directions respectively. The end sidewalls of the two isolation walls located on two adjacent substrate units in the X direction are not opposite each other, and the end sidewalls of the two isolation walls located on two adjacent substrate units in the Y direction are also not opposite each other. (Refer to the attached diagram.) Figure 7 As attached Figure 18 As shown, this is a top view of the structure of removing the covering layer covering the end sidewall of the isolation wall in the substrate unit 801 in the sixth specific embodiment of the present invention. In the step of removing the covering layer 83 covering the end sidewall of the isolation wall 82 in the substrate unit 801, the groove 831 at the end sidewall of each isolation wall 82 is an independent groove.

[0113] The packaging method of the present invention provides an isolation wall with a safe distance from the substrate on the upper surface of the substrate. During the process of forming the package, there is no need to cut the isolation wall, which can avoid material deformation and tool wear caused by cutting. Before forming the shielding layer, the cover layer at the end sidewall of the isolation wall is removed to expose the end sidewall of the isolation wall, so that the formed shielding layer can contact the end sidewall of the isolation wall. This can form a complete electromagnetic shielding structure for each cavity that requires electromagnetic shielding, and there will be no situation where the shielding layer cannot contact the isolation wall due to the safe distance between the isolation wall and the edge of the substrate.

[0114] The present invention also provides a package formed using the above-described encapsulation method. (See attached image.) Figure 3 ~Attached Figure 6 As shown, the package for cavity shielding of the present invention includes a substrate 30, a chip 31, an isolation wall 32, a covering layer 33, and a shielding layer 34.

[0115] The substrate 30 is made of any material selected from silicon, glass, metal, and ceramic. Different substrate materials are selected for the substrate 30 according to the requirements of the package. Substrates 30 of different materials are combined with the chip 31 and the isolation wall 32 through processes such as lamination and bonding, which can specifically address core issues such as heat dissipation, signal integrity, or environmental protection.

[0116] The chip 31 is disposed on the upper surface of the substrate 30. In a first embodiment, the chip 31 includes a logic chip for data processing, a memory chip for data storage, a power chip for power conversion, a sensor chip for sensing environmental signals, a radio frequency chip for supporting wireless communication, and a photonic chip integrating optical devices. The chip 31 can be attached to the upper surface of the substrate 30 via an adhesive layer or soldered to the upper surface of the substrate 30 via a solder layer. In a fifth embodiment, the chip 31 is attached to the upper surface of the substrate 30 via an adhesive layer.

[0117] The isolation wall 32 is disposed on the upper surface of the substrate 30, and the plurality of chips 31 are isolated by the isolation wall 32. The end sidewall of the isolation wall 32 is at a distance from the edge of the substrate 30. In a first embodiment, the isolation wall 32 is attached to the upper surface of the substrate 30 by an adhesive layer.

[0118] The shape of the partition wall 32 can be designed according to the cavity requirements of the package. The shape of the partition wall 32 can be straight, L-shaped, cross-shaped, etc., as shown in the attached figure. Figure 3 As shown, the isolation wall 32 is in a straight line shape, as illustrated in the attached diagram. Figure 7 As shown in the attached diagram, the isolation wall is L-shaped. Figure 9As shown, the isolation wall is cross-shaped. In some specific embodiments, the isolation wall includes multiple branches, and the end sidewall of each branch is a certain distance from the edge of the substrate.

[0119] In one specific embodiment, the package includes a plurality of the isolation walls, each isolation wall having an end sidewall that is a distance from the edge of the substrate. (See attached diagram) Figure 11 As shown, two isolation walls are disposed on the upper surface of the substrate. The two isolation walls are separated from each other and arranged in parallel, dividing the substrate into three regions, each of which is provided with the chip 31. In another specific embodiment, multiple isolation walls may also be arranged in a non-parallel manner.

[0120] In a first embodiment, the material of the partition wall 32 is a metal. The metal is selected from one of copper, nickel, silver, and gold, or an alloy thereof. In the first embodiment, the material of the partition wall 32 is copper.

[0121] The encapsulation layer 33 is disposed on the upper surface of the substrate 30, and is used to encapsulate the chip 31 and the isolation wall 32, exposing the top surface and end sidewalls of the isolation wall 32. The encapsulation layer 33 is made of molding compound. Molding compound raw materials are abundant and inexpensive, and the molding process is simple, making it suitable for large-scale mass production and effectively reducing packaging costs.

[0122] In the region corresponding to the end sidewall of the isolation wall 32, the covering layer 33 has a groove 331 extending toward the substrate 30. The groove 331 exposes the end sidewall of the isolation wall 32, and the end sidewall of the isolation wall 32 is located at the bottom of the groove 331. In the fifth embodiment, in the direction perpendicular to the extension of the isolation wall 32 on the substrate 30 (as shown by the X direction in the figure), the width of the groove 331 is greater than the width of the end sidewall of the isolation wall 32. The end sidewall of the isolation wall 32 is completely exposed to the groove 331 to avoid residual material of the covering layer 33 when the groove 331 is formed, which would affect the contact between the subsequently formed shielding layer 34 and the isolation wall 32. This also ensures that the end sidewall of the isolation wall 32 is completely exposed, increasing the contact area between the subsequently formed shielding layer 34 and the isolation wall 32, and improving the shielding performance.

[0123] In another specific embodiment, in the direction perpendicular to the extension of the isolation wall on the substrate, the width of the trench 331 is equal to the width of the end sidewall of the isolation wall, so as to reduce the amount of the covering layer 33 removed when forming the trench 331, maximize the structural support function of the covering layer 33, avoid excessive removal leading to a decrease in the mechanical strength of the package, and reduce the risk of package warpage.

[0124] The shielding layer 34 covers the top surface and sidewalls of the covering layer 33, and the shielding layer 34 also covers the exposed top surface and end sidewalls of the isolation wall 32. Figure 6 The top surface and end sidewalls of the isolation wall 32 are shown in dashed lines. The shielding layer 34 covers the inner wall of the trench 331 and contacts the end sidewall of the isolation wall 32 located in the trench 331. The shielding layer 34 also contacts the top surface of the isolation wall 32 and covers the top surface and sidewalls of the covering layer 33, so that the shielding layer 34 and the isolation wall 32 form a conformal shielding contact. This can form a complete electromagnetic shielding structure for each cavity that requires electromagnetic shielding, and there will be no situation where the shielding layer 34 cannot contact the isolation wall 32 due to the safe distance between the isolation wall 32 and the edge of the substrate 30.

[0125] The shielding layer 34 is made of a metal, selected from copper, aluminum, nickel, silver, and gold, or an alloy thereof. In the fifth embodiment, the shielding layer 34 and the isolation wall 32 are made of the same material, which can eliminate the interface barrier between different materials, improve the metallurgical compatibility between materials, reduce the risk of interface reaction, and improve the connection strength and reliability. Furthermore, the matching thermal expansion coefficients of the same materials can effectively reduce stress concentration caused by expansion differences during temperature changes, avoiding problems such as warping and cracking of the package. At the same time, the uniformity of materials can ensure the synergy between the shielding layer 34 and the isolation wall 32 in electromagnetic shielding, heat dissipation, and other functions, optimize the overall performance of the package, and ensure the stable operation of the chip 31 in complex environments.

[0126] As attached Figure 6 As shown, in this specific embodiment, the isolation wall 32 is in the shape of a straight line. The covering layer 33 forms two oppositely arranged grooves 331 on the first end sidewall and the second end sidewall of the isolation wall 32. Each groove 331 exposes the end sidewall of the isolation wall 32. The shielding layer 34 covers the inner wall of the groove, thereby forming a conformal shielding contact with the isolation wall 32.

[0127] As attached Figure 7 and appendix Figure 8 As shown, among which, appendix Figure 8 The diagram shown is a three-dimensional structural schematic of the encapsulation body according to a second specific embodiment of the present invention. In this embodiment, the isolation wall 42 is L-shaped, and the covering layer forms grooves 431 on the sidewalls of the first end 421 of the first branch and the second end 422 of the second branch of the L-shape. Each groove 431 exposes the end sidewall of the isolation wall 42, and the shielding layer 44 covers the inner wall of the groove 431, thereby forming a conformal shielding contact with the isolation wall 42. (See attached diagram.) Figure 16 The top surface and end sidewalls of the isolation wall 42 are shown in dashed lines.

[0128] As attached Figure 9 and appendix Figure 10 As shown, among which, appendix Figure 10 The diagram shown is a three-dimensional structural schematic of the encapsulation body according to a third specific embodiment of the present invention. In this embodiment, the isolation wall 52 is cross-shaped. The covering layer forms grooves 531 on the sidewalls of the first end 521 of the first branch, the second end 522 of the second branch, the third end 523 of the third branch, and the fourth end 524 of the fourth branch. Each groove 531 exposes the end sidewall of the isolation wall 52. The shielding layer 54 covers the inner wall of the groove 531, thereby forming a conformal shielding contact with the isolation wall 52. (See attached diagram.) Figure 17 The top surface and end sidewalls of the isolation wall 52 are shown in dashed lines.

[0129] As attached Figure 11 and appendix Figure 12 As shown, among which, appendix Figure 12 The diagram shown is a three-dimensional structural schematic of the package body according to a fourth specific embodiment of the present invention. In this embodiment, two isolation walls 62 are provided on the upper surface of the substrate 60. The two isolation walls 62 are separated from each other and arranged in parallel. A groove 631 is formed at the end sidewall of each isolation wall 62, and each groove 631 exposes the end sidewall of the isolation wall 62. The shielding layer 64 covers the inner wall of the groove 631, thereby forming a conformal shielding contact with the isolation wall 62. (See attached diagram.) Figure 12 The top surface and end sidewalls of the isolation wall 62 are shown in dashed lines.

[0130] In the package of the present invention, the shielding layer is in contact with the isolation wall to form an electromagnetic shielding structure composed of the isolation wall and the shielding layer. In one specific embodiment, the isolation wall is electrically connected to the substrate and grounded through the substrate, thereby enabling the electromagnetic shielding structure to be grounded through the substrate and achieving the electromagnetic shielding function. In another specific embodiment, the shielding layer is electrically connected to the side wall of the substrate and grounded through the substrate, thereby enabling the electromagnetic shielding structure to be grounded through the substrate and achieving the electromagnetic shielding function. In yet another specific embodiment, when the package is mounted on an external substrate (e.g., a printed circuit board), the bottom of the shielding layer is electrically connected to the external substrate and grounded through the external substrate, thereby enabling the electromagnetic shielding structure to be grounded through the external substrate and achieving the electromagnetic shielding function.

[0131] In the package of the present invention, the isolation wall has a safe distance from the substrate, the covering layer has a corresponding groove at the end sidewall of the isolation wall, the groove exposes the end of the sidewall of the isolation wall, the surface of the covering layer also exposes the top surface of the isolation wall, the shielding layer covers the surface of the covering layer and also covers the inner wall of the groove, thereby forming a conformal shielding contact with the top surface and end sidewall of the isolation wall, which can form a complete electromagnetic shielding structure for each cavity that requires electromagnetic shielding, and there will be no situation where the shielding layer cannot contact the isolation wall due to the safe distance between the isolation wall and the edge of the substrate.

[0132] It should be noted that the terms "comprising" and "having," and their variations, used in this invention document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context; it should be understood that such use of data can be interchanged where appropriate. The term "one or more" depends at least in part on the context and can be used to describe features, structures, or characteristics in a singular sense, or in a plural sense to describe combinations of features, structures, or characteristics. The term "based on" can be understood as not necessarily intended to express an exclusive set of factors, but can instead, also at least in part on the context, allow for the presence of other factors that are not necessarily explicitly described. Furthermore, embodiments and features in embodiments of this invention can be combined with each other without conflict. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar / identical parts between embodiments can be referred to mutually.

[0133] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A packaging method for achieving cavity shielding, characterized in that, include: An isolation wall and chips are disposed on the upper surface of a substrate, and multiple chips are isolated by the isolation wall. The end sidewall of the isolation wall is a distance from the edge of the substrate. A covering layer is formed, which is disposed on the upper surface of the substrate, covering the isolation wall and the chip, and exposing the top surface of the isolation wall; Remove the covering layer covering the end sidewall of the isolation wall to expose the end sidewall of the isolation wall; A shielding layer is formed, which covers the top surface and sidewalls of the covering layer, and also covers the exposed top surface and end sidewalls of the isolation wall.

2. The packaging method according to claim 1, characterized in that, The step of setting the isolation wall and the chip on the upper surface of the substrate further includes: attaching the isolation wall to the upper surface of the substrate by means of an adhesive layer.

3. The packaging method according to claim 1, characterized in that, The step of setting the isolation wall and the chip on the upper surface of the substrate further includes: fixing the chip on the upper surface of the substrate by means of mounting or soldering.

4. The packaging method according to claim 1, characterized in that, The step of setting the isolation wall and the chip on the upper surface of the substrate further includes: first setting the chip on the upper surface of the substrate, and then setting the isolation wall on the upper surface of the substrate; or, first setting the isolation wall on the upper surface of the substrate, and then setting the chip on the upper surface of the substrate.

5. The packaging method according to claim 1, characterized in that, The step of setting an isolation wall and a chip on the upper surface of the substrate further includes: the isolation wall includes multiple branches, and the end sidewall of each branch is at a distance from the edge of the substrate.

6. The packaging method according to claim 1, characterized in that, The step of setting the isolation wall and the chip on the upper surface of the substrate further includes: setting a plurality of the isolation walls on the upper surface of the substrate, wherein the end sidewall of each isolation wall is at a distance from the edge of the substrate.

7. The packaging method according to claim 1, characterized in that, The step of forming the coating layer further includes: molding to form the coating layer.

8. The packaging method according to claim 7, characterized in that, The step of molding to form the overlay further includes: A molding compound layer is formed using an injection molding process. The molding compound layer is disposed on the upper surface of the substrate and covers the isolation wall and the chip. The molding material layer is thinned until the top surface of the partition wall is exposed, and the remaining molding material layer serves as the covering layer.

9. The packaging method according to claim 8, characterized in that, The step of thinning the molding compound layer further includes: after thinning the molding compound layer to expose the top surface of the partition wall, continuing to thin the molding compound layer and the partition wall to a set height.

10. The packaging method according to claim 7, characterized in that, The step of molding to form the overlay further includes: The coating layer is formed using a film-assisted injection molding process, and the film covers the top surface of the isolation wall. Remove the film to expose the top surface of the isolation wall.

11. The packaging method according to claim 1, characterized in that, The step of removing the covering layer covering the end sidewall of the isolation wall further includes: removing the covering layer covering the end sidewall of the isolation wall by laser ablation, drilling, or cutting.

12. The packaging method according to claim 1, characterized in that, The step of removing the covering layer covering the end sidewall of the isolation wall further includes: in a direction perpendicular to the extension of the isolation wall on the substrate, the width of the removal of the covering layer is greater than the width of the end sidewall of the isolation wall.

13. The packaging method according to claim 1, characterized in that, The step of removing the covering layer covering the end sidewall of the isolation wall further includes: in a direction perpendicular to the extension of the isolation wall on the substrate, the width of the removal of the covering layer is equal to the width of the end sidewall of the isolation wall.

14. The packaging method according to claim 1, characterized in that, The step of forming the shielding layer further includes: forming the shielding layer using the same material as the isolation wall.

15. The packaging method according to claim 1, characterized in that, The step of forming the shielding layer further includes: the shielding layer being pre-formed, or the shielding layer being formed using a sputtering process.

16. The packaging method according to claim 1, characterized in that, The substrate is divided into multiple substrate units; The step of setting the isolation wall and the chip on the upper surface of the substrate further includes: setting the isolation wall and the chip on the upper surface of the substrate of each substrate unit, wherein multiple chips are isolated by the isolation wall within the substrate unit, and the end sidewall of the isolation wall is at a distance from the edge of the substrate unit. The step of forming the cladding layer further includes: forming the cladding layer in each of the substrate units; The step of removing the covering layer covering the end sidewall of the isolation wall further includes: removing the covering layer covering the end sidewall of the isolation wall within the substrate unit; Cutting is performed along the cutting path to form multiple independent encapsulation units, the cutting path passing through the area where the encapsulation layer is removed; The step of forming the shielding layer further includes: each of the encapsulation units forming the shielding layer.

17. The packaging method according to claim 16, characterized in that, The step of cutting along the cutting path further includes: the isolation wall being located outside the cutting path.

18. A package for achieving cavity shielding, characterized in that, include: substrate; A chip is disposed on the upper surface of the substrate; An isolation wall is disposed on the upper surface of the substrate, and multiple chips are isolated by the isolation wall. The end sidewall of the isolation wall is a distance from the edge of the substrate. A covering layer is disposed on the upper surface of the substrate to cover the chip and the isolation wall, and exposes the top surface and end sidewalls of the isolation wall; A shielding layer that covers the top surface and sidewalls of the covering layer, and also covers the exposed top surface and end sidewalls of the isolation wall.

19. The package according to claim 18, characterized in that, The isolation wall is attached to the upper surface of the substrate by an adhesive layer.

20. The package according to claim 18, characterized in that, The chip is attached to the upper surface of the substrate via an adhesive layer or soldered to the upper surface of the substrate via a solder layer.

21. The package according to claim 18, characterized in that, The isolation wall includes multiple branches, and the end sidewall of each branch is a distance from the edge of the substrate.

22. The package according to claim 18, characterized in that, The package includes a plurality of the isolation walls, and the end sidewall of each isolation wall is at a distance from the edge of the substrate.

23. The package according to claim 18, characterized in that, The covering layer has grooves extending toward the substrate, the grooves being exposed at the end sidewalls of the isolation wall.

24. The package according to claim 23, characterized in that, In the direction perpendicular to the extension of the isolation wall on the substrate, the width of the groove is greater than the width of the end sidewall of the isolation wall.

25. The package according to claim 23, characterized in that, In the direction perpendicular to the extension of the isolation wall on the substrate, the width of the groove is equal to the width of the end sidewall of the isolation wall.

26. The package according to claim 18, characterized in that, The isolation wall is made of metal.

27. The package according to claim 26, characterized in that, The metal is selected from one of copper, nickel, silver and gold or an alloy thereof.

28. The package according to claim 18, characterized in that, The shielding layer and the isolation wall are made of the same material.

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