Energetic device and preparation method thereof

Abstract

The invention provides an energetic device and a preparation method thereof. The device comprises a silicon substrate, a thermal excitation energetic layer, a heating electrode and an energetic material layer, the thermal excitation energetic layer is arranged on the silicon substrate and comprises a plurality of irregular micro-nano pores and a strong oxidant crystal substance filled in the micro-nano pores; the energetic material layer is arranged on the thermal excitation energetic layer; the heating electrode comprises a high-resistance thermal excitation area, a low-resistance electric signal wire area and an interconnection conductive column. The high-resistance thermal excitation region is arranged on the surface, deviating from the silicon substrate, of the thermal excitation energetic layer; the low-resistance electric signal wire area is arranged on the surface, deviating from the thermal excitation energetic layer, of the silicon substrate; and the interconnection conductive column sequentially penetrates through the silicon substrate and the thermal excitation energetic layer and is electrically connected with the high-resistance thermal excitation region and the low-resistance electric signal wire region respectively. The device solves the problem that the time from electrothermal excitation to detonation response is too long, and has remarkable advantages in the aspect of detonation response; the arrangement of the heating electrode improves the overall performance of the energetic device.

Description

Technical Field

[0001] This invention belongs to the field of energetic device technology, specifically relating to an energetic device and its preparation method. Background Technology

[0002] When existing chips or devices are integrated with semiconductor energetic devices, the semiconductor energetic devices can perform functions such as destruction and providing power in specific scenarios. Domestic and international research faces several technical challenges, particularly the excessively long response time from electrothermal excitation to detonation of energetic devices. Existing technologies primarily focus on the thermal sensitivity of energetic materials and the design and layout of heating electrodes. Extensive research and analysis have revealed that the long temperature conduction path from the heating electrode to the energetic material due to the existing device structure prevents heat from being quickly and effectively transferred to the energetic material after electrothermal excitation, resulting in an excessively long detonation response time.

[0003] Studies have shown that thermally excited energetic layers can be deposited on the surface of silicon substrates, and the thermally excited energetic layers are in direct and close contact with the heating electrodes at the microscopic level, which can significantly improve the problem of excessively long response time from electrothermal excitation to detonation of energetic devices.

[0004] However, further careful study revealed that the heating electrode structure, in order to increase current transmission, has a wide wiring structure with a single line located on the surface of the thermally excited energetic layer. This structure blocks and hinders the subsequent filling of the strong oxidant, resulting in insufficient and non-dense energetic material, uneven energy density distribution, and poor surface uniformity of the thermally excited energetic layer, thus affecting the overall performance of the device.

[0005] To address the aforementioned problems, it is necessary to propose a rationally designed and effective energetic device and its fabrication method. Summary of the Invention

[0006] The present invention aims to solve at least one of the technical problems existing in the prior art, and to provide an energetic device and a method for its fabrication.

[0007] One aspect of the present invention provides an energetic device, comprising a silicon substrate, a thermally excited energetic layer, a heating electrode, and an energetic material layer; The thermally excited energetic layer is disposed on the silicon substrate, and the thermally excited energetic layer includes a plurality of irregular micro-nano pores and strong oxidant crystals filling the micro-nano pores; The energetic material layer is disposed on the thermally activated energetic layer; The heating electrode includes a high-resistance thermal excitation region, a low-resistance electrical signal wire region, and interconnecting conductive pillars; wherein... The high thermal resistance excitation region is disposed on the surface of the thermally excited energy layer opposite to the silicon substrate; The low-resistance electrical signal conductor region is disposed on the surface of the silicon substrate away from the thermally excited energy-containing layer; The interconnecting conductive pillars pass through the silicon substrate and the thermally excited energetic layer in sequence, and are electrically connected to the high-resistance thermally excited region and the low-resistance electrical signal conductor region, respectively.

[0008] Optionally, a plurality of the micro / nano pores are disposed on the surface of the silicon substrate; wherein, The pore size of the micro-nano pores ranges from 0.1 μm to 5 μm, and the pore depth ranges from 50 μm to 150 μm.

[0009] Optionally, the high thermal resistance excitation region is a single-layer or multi-layer metal structure made of at least one of chromium, nickel, titanium, platinum, and gold; wherein, The thickness of the metal layer in the high thermal resistance excitation region ranges from 1 μm to 5 μm, and the linewidth of the high thermal resistance excitation region ranges from 0.05 mm to 2 mm.

[0010] Optionally, the low-resistance electrical signal conductor region is a metal or multilayer metal structure made of at least one of copper, chromium, nickel, titanium, platinum, and gold; wherein, The thickness of the metal layer in the low-resistance electrical signal conductor region ranges from 1 μm to 5 μm, and the linewidth of the low-resistance electrical signal conductor region ranges from 0.05 mm to 2 mm.

[0011] Optionally, the interconnecting conductive pillar is a through-silicon via (TSV), and the TSV diameter ranges from 25 μm to 500 μm.

[0012] Another aspect of the present invention provides a method for fabricating an energetic device, the method comprising: A silicon substrate is provided, wherein a plurality of interconnecting conductive pillars are formed throughout the thickness of the silicon substrate; Multiple irregular micro-nano pores are formed on the surface of the silicon substrate; A high-resistance thermal excitation region electrically connected to the interconnect conductive pillars is formed on the plurality of micro-nano pores, and a low-resistance electrical signal wire region electrically connected to the interconnect conductive pillars is formed on the surface of the silicon substrate opposite to the micro-nano pores, wherein the high-resistance thermal excitation region, the low-resistance electrical signal wire region and the interconnect conductive pillars together constitute a heating electrode; Strong oxidant crystals are filled into the micro-nano pores to form a thermally activated energy layer; An energetic material layer is formed by coating the surfaces of the thermally excited energetic layer and the high thermal resistance excitation region with a gel-like energetic material.

[0013] Optionally, a plurality of irregular micro / nano pores are formed on the surface of the silicon substrate, including: The silicon substrate is cleaned and dried; The dried silicon substrate is placed in an electrolytic cell, and a mixed solution of hydrofluoric acid and anhydrous ethanol is added to the electrolytic cell to electrochemically etch the surface of the silicon substrate to form a plurality of micro-nano pores on the surface of the silicon substrate.

[0014] Optionally, the process of forming the interconnecting conductive pillars includes: Multiple through-holes penetrating the thickness of the silicon substrate are formed using an aperture-opening process; The through-hole is filled with conductive material to form the interconnecting conductive pillars; The process of forming the high thermal resistance excitation region includes: placing a first mask on the surface of a silicon substrate, exposing the target micro / nano pore region through the patterned openings of the first mask; and using a physical vapor deposition process to directionally sputter metal material through the openings of the first mask to form a high thermal resistance excitation region on the surface of the micro / nano pores. The process of forming the low-resistance electrical signal conductor region includes: placing a second mask on the surface of the silicon substrate away from the micro-nano apertures, exposing the conductor region pattern through the patterned openings of the second mask; and sputtering a highly conductive metal layer through the openings of the second mask to form the low-resistance electrical signal conductor region.

[0015] Optionally, filling the micro / nano pores with strong oxidant crystals to form a thermally excited energetic layer includes: The intermediate structure containing the multiple micro-nano pores and the heating electrode is cleaned and dried. The intermediate structure is evacuated to remove air bubbles from the micro-nano pores; The intermediate structure was placed in a saturated sodium perchlorate ethanol solution and ultrasonically immersed and filled. The intermediate structure after soaking and filling is placed in an oven for low-temperature drying to remove the ethanol solvent, so that sodium perchlorate can recrystallize in the micro-nano pores to form strong oxidant crystals, thereby forming the thermally activated energetic layer.

[0016] Optionally, the step of coating the surfaces of the thermally excited energetic layer and the high-thermal-resistance excitation region with a gel-like energetic material to form an energetic material layer includes: A gel-like energetic material is coated onto the surfaces of the thermally activated energetic layer and the high thermal resistance activation region using a screen printing coating process, and then dried and cured to form the energetic material layer.

[0017] The present invention relates to an energetic device and its fabrication method. In this energetic device, the thermally excited energetic layer and the heating electrode are in direct and close contact at the microscopic level. After electrothermal excitation, heat is rapidly and effectively applied to the irregular micro-nano pores in which the heating electrode is in direct contact. The silicon in the micro-nano pores reacts rapidly with the strong oxidant crystals, causing a rapid explosion, which in turn detonates the energetic material layer above. This energetic device structure improves the problem of excessively long response time from electrothermal excitation to detonation, and has significant advantages in detonation response (reaching the millisecond level). At the same time, it reduces the deterioration of the energetic material caused by the inability to rapidly detonate and thermally decompose, ensuring the release of energy.

[0018] The present invention discloses an energetic device and its fabrication method. The heating electrode in the energetic device includes a high-resistance thermal excitation region, a low-resistance electrical signal conductor region, and interconnecting conductive pillars. The low-resistance electrical signal conductor region is disposed on the surface of the silicon substrate opposite to the thermally excited energetic layer and is electrically connected to the high-resistance thermal excitation region disposed on the thermally excited energetic layer via the interconnecting conductive pillars. While meeting the requirements for current signal transmission in the rapid heating function of the heating electrode, this reduces the area of ​​the heating electrode covering the thermally excited energetic layer. This solves the problem of obstruction hindering subsequent strong oxidant filling, resulting in a more uniform energetic material filling area below all heating electrode leads. Simultaneously, it reduces the large-area wiring on the surface of the thermally excited energetic layer, improving its surface uniformity and thus improving the overall performance of the device. Furthermore, the low-resistance electrical signal conductor region of the heating electrode is disposed on the surface of the silicon substrate to lead out the signal, improving the electrical connectivity of the energetic device and facilitating modular and array-based packaging. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of an energetic device in the prior art; Figure 2 This is a plan view of an energetic device according to an embodiment of the present invention; Figure 3 for Figure 2 Cross-sectional views of region A and region B in a medium-energy device; Figure 4 This is a top view of an energetic device according to another embodiment of the present invention; Figure 5 This is a bottom view of an energetic device according to another embodiment of the present invention; Figure 6 for Figure 4 A cross-sectional view of region E in a medium-energy device; Figure 7 for Figure 4 Cross-sectional views of regions C and D in a medium-energy device; Figure 8 This is a schematic flowchart of a method for fabricating an energetic device according to another embodiment of the present invention; Figures 9 to 13This is a schematic diagram of the process flow of a method for fabricating an energetic device according to another embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] like Figure 1 The diagram shows a schematic of an existing energetic device structure, consisting of a silicon substrate 1, a heating electrode 2, and a gel-like energetic material 3. The invention of the gel-like energetic material allows it to be directly coated and cured onto the surface of the heating electrode 2, representing a significant breakthrough compared to other existing technologies. However, thorough research has revealed that the temperature transfer from the heating electrode 2 to the core porous silicon and oxidant crystals of the gel-like energetic material 3 is still relatively slow. This means that after electrothermal excitation, heat cannot be quickly and effectively applied to the energetic material, resulting in an excessively long detonation response time. Furthermore, because the energetic material cannot detonate quickly, it undergoes thermal decomposition during the temperature rise process, leading to partial deterioration and a reduction in the overall energy release of the device.

[0022] To address the aforementioned problems, this invention innovatively proposes an energetic device and its preparation method, which solves both the problem of excessively long response time from electrothermal excitation to detonation of energetic devices and the problem of heating electrode obstructing subsequent filling of strong oxidant crystals, thus making the filling of energetic materials more uniform.

[0023] Specifically, such as Figure 2 and Figure 3 As shown, in one embodiment, the present invention provides an energetic device structure, including a silicon substrate 10, a heating electrode 20, an energetic material layer 30, and a thermally excited energetic layer 40.

[0024] A thermally activated energetic layer 40 is disposed on a silicon substrate 10. An energetic material layer 30 is disposed on the thermally activated energetic layer 40. Wherein, for example... Figure 12 As shown, the thermally excited energetic layer 40 includes multiple irregular micro-nano pores 41 and strong oxidant crystals filling the micro-nano pores 41. That is, the strong oxidant crystals fill the micro-nano pores 41 at the micro-nano scale and are tightly bonded to form the thermally excited energetic layer 40.

[0025] The heating electrode 20 is located above the thermally excited energetic layer 40. The heating electrode 20 includes a high-resistance thermal excitation region 201 and a low-resistance electrical signal conductor region 202. Specifically, since the heating electrode 20 is disposed on the thermally excited energetic layer 40, after electrothermal excitation, heat is rapidly and effectively applied to the irregular micro- and nano-pores 41 on the thermally excited energetic layer 40 that are actually in direct contact with the heating electrode 20. The silicon in the micro- and nano-pores 41 reacts rapidly with the strong oxidant crystals in the micro- and nano-pores 41, causing a rapid explosion, which in turn detonates the energetic material layer 30 above. By setting the thermally excited energetic layer 40, this semiconductor energetic device structure has the advantages of rapid response and large energy release.

[0026] like Figure 2 and Figure 3 As shown in this embodiment, under the functional requirement of rapid heating of the heating electrode 20, the lead width at the low-resistance electrical signal wire area 202 is relatively large, which in turn blocks and hinders the subsequent filling of strong oxidant. This results in insufficient and non-dense filling of the energetic material in a part of the area below the heating electrode, leading to uneven energy density distribution and poor surface uniformity of the thermally excited energetic layer, which in turn affects the overall performance of the device.

[0027] In response to this, such as Figures 4 to 7 As shown, in another embodiment of the present invention, the heating electrode 20 includes a high-resistance thermal excitation region 201, a low-resistance electrical signal conductor region 202, and an interconnecting conductive pillar 203; wherein, the high-resistance thermal excitation region 201 is disposed on the surface of the thermally excited energetic layer 40 away from the silicon substrate 10; the low-resistance electrical signal conductor region 202 is disposed on the surface of the silicon substrate 10 away from the thermally excited energetic layer 40; the interconnecting conductive pillar 203 sequentially penetrates the silicon substrate 10 and the thermally excited energetic layer 40, and is electrically connected to the high-resistance thermal excitation region 201 and the low-resistance electrical signal conductor region 202, respectively.

[0028] Specifically, such as Figure 6 As shown, in this embodiment, the high-resistivity thermal excitation region 201 of the heating electrode 20 is disposed on the upper surface of the thermally excited energetic layer 40, and the low-resistivity electrical signal conductor region 202 is disposed on the lower surface of the silicon substrate 10. The high-resistivity thermal excitation region 201 and the low-resistivity electrical signal conductor region 202 are electrically connected by interconnecting conductive pillars 203. The relatively large low-resistivity electrical signal conductor region 202 is not disposed on the surface of the thermally excited energetic layer 40. This solves the problem of obstructing the subsequent filling of strong oxidant, making the energetic material formed under all heating electrode leads more uniform. At the same time, it reduces the large-area wiring on the surface of the thermally excited energetic layer, improves its surface uniformity, and thus improves the overall performance of the device.

[0029] Because the high-thermal-resistance excitation region 201 of the heating electrode 20 is disposed on the thermally excited energetic layer 40, after electrothermal excitation, heat is rapidly and effectively applied to the irregular micro- and nano-pores 41 on the thermally excited energetic layer 40 that are actually in direct contact with the high-thermal-resistance excitation region 201. The silicon in the micro- and nano-pores 41 reacts rapidly with the strong oxidant crystals in the micro- and nano-pores 41, causing a rapid explosion, which in turn detonates the energetic material layer 30 above. By setting the thermally excited energetic layer 40, this semiconductor energetic device structure has the advantages of fast response and large energy release.

[0030] The energetic device of the present invention has a thermally excited energetic layer in direct and close contact with the heating electrode at the microscopic level. After electrothermal excitation, heat is rapidly and effectively applied to the irregular micro-nano pores in which the heating electrode is in direct contact. The silicon in the micro-nano pores reacts rapidly with the strong oxidant crystals, quickly detonating and thus detonating the energetic material layer above. This energetic device structure improves the problem of excessively long response time from electrothermal excitation to detonation, and has significant advantages in detonation response (reaching the millisecond level). At the same time, it reduces the deterioration of the energetic material caused by the inability to quickly detonate and thermally decompose, ensuring the release of energy.

[0031] The energetic device of the present invention includes a heating electrode comprising a high-resistivity thermal excitation region, a low-resistivity electrical signal conductor region, and interconnecting conductive pillars. The low-resistivity electrical signal conductor region is disposed on the surface of the silicon substrate opposite to the thermally excited energetic layer and is electrically connected to the high-resistivity thermal excitation region disposed on the thermally excited energetic layer through the interconnecting conductive pillars. This fundamentally avoids the problem that a wide low-resistivity electrical signal conductor region would obstruct the subsequent filling of micro-nano pores beneath it by strong oxidants, resulting in insufficient and non-dense energetic material with uneven energy density distribution. This makes the energetic material formed under all heating electrode leads more uniform, while reducing the large-area wiring on the surface of the thermally excited energetic layer, improving its surface uniformity, and thus improving the overall performance of the device. In addition, the low-resistivity electrical signal conductor region of the heating electrode is disposed on the surface of the silicon substrate to lead out the signal, improving the electrical connectivity of the energetic device and facilitating modular and array packaging of the energetic device.

[0032] For example, such as Figure 10 As shown, multiple micro- and nano-pores 41 are disposed on the surface of the silicon substrate 10. The pore size of the micro- and nano-pores 41 ranges from 0.1 μm to 5 μm, and the pore depth ranges from 50 μm to 150 μm. The micro- and nano-pores 41 belong to a micro- and nano-scale pore structure.

[0033] It should be noted that this embodiment does not specifically limit the size of the micro-nano pores 41, and can be selected according to actual needs. Furthermore, the shape of the micro-nano pores 41 is also not specifically limited, and can be selected according to actual needs.

[0034] For example, the high thermal resistance excitation region 201 is a single-layer or multi-layer metal structure made of at least one of chromium, nickel, titanium, platinum, and gold; wherein the thickness of the metal layer in the high thermal resistance excitation region 201 ranges from 1 μm to 5 μm, and the linewidth of the high thermal resistance excitation region 201 ranges from 0.05 mm to 2 mm. Specifically, in this embodiment, the high thermal resistance excitation region 201 is a chromium metal structure with a chromium metal layer thickness of 3 μm and a linewidth of 500 μm.

[0035] For example, the low-resistance signal conductor region 202 is a metal or multilayer metal structure of at least one of copper, chromium, nickel, titanium, platinum, and gold; wherein the metal layer thickness of the low-resistance signal conductor region 202 ranges from 1 μm to 5 μm, and the linewidth of the low-resistance signal conductor region 202 ranges from 0.05 mm to 2 mm. Specifically, in this embodiment, the low-resistance signal conductor region 202 is a chromium and copper multilayer metal structure with a metal layer thickness of 5 μm and a linewidth of 1.5 mm.

[0036] It should be noted that in this embodiment, the materials used for the high-resistance thermal excitation region 201 and the low-resistance electrical signal conductor region 202 can be the same or different, and can be selected according to actual needs.

[0037] For example, the interconnecting conductive post 203 is a through-silicon via (TSV), with a diameter ranging from 25 μm to 500 μm. A TSV is a composite interconnect structure comprising a copper conductor and an insulating / barrier layer, enabling vertical electrical connections.

[0038] Specifically, in this embodiment, the diameter of the through-silicon via (TSV) ranges from 25 μm to 500 μm, suitable for monocrystalline or polycrystalline silicon wafers with diameters of 300 μm to 500 μm, to accommodate different aspect ratios and current carrying requirements. More preferably, to balance process feasibility and current carrying capacity, the diameter range is 25 μm to 200 μm. The lower limit (25 μm) ensures that the TSV has a sufficient cross-sectional area to safely and efficiently conduct the operating current required for the heating electrode, avoiding overheating or failure due to excessive current density; it also avoids the "voids" or "closures" that are easily generated by deep filling of small holes (high aspect ratio). The upper limit (200 μm) comprehensively considers process cost and compatibility. This size limit is compatible with the mature and relatively inexpensive deep silicon etching (DRIE) process capabilities, avoiding stress warping, cracks, and interface failures caused by differences in thermal expansion coefficients due to excessively large apertures; at the same time, it avoids the high-cost and highly difficult special processing technologies required for ultra-large TSVs, which is conducive to achieving low-cost mass production of devices.

[0039] For example, in this embodiment, copper can be used as the conductor for the interconnect conductive post 203. On the one hand, it has excellent conductivity to meet the current carrying capacity required by the heating electrode for subsequent electrical connection. On the other hand, more importantly, copper conductors have excellent resistance to the hydrofluoric acid (HF) wet etching process necessary for the subsequent fabrication of micro-nano pores on the silicon substrate. This effectively avoids the risk of the through silicon via (TSV) structure being corroded and damaged in the micro-nano structure fabrication steps, ensuring the reliability and yield of device manufacturing. It should be noted that the heating electrode 20 provided in this embodiment of the invention is a composite structure, mainly addressing the issues of material filling in subsequent processes and surface uniformity of the thermally excited energetic layer 40 in the region below it. Therefore, the shape of the lines or grids in the high-resistivity thermal excitation region 201 and the low-resistivity electrical signal conductor region 202, as well as the cross-sectional shape and number of the interconnecting conductive pillars 203, are not unique. They can be designed and varied according to the actual thermal excitation requirements of the energetic material in the device. For example, the shape of the lines or grids in the high-resistivity thermal excitation region 201 and the low-resistivity electrical signal conductor region 202 can be solid, curved, or polygonal, etc., and the cross-sectional shape of the interconnecting conductive pillars 203 can be elliptical, polygonal, etc. Furthermore, according to the performance requirements of the heating electrode, such as using porous TSVs to increase the upper limit of the current passing through the heating electrode, all of these fall within the scope of protection of this patent.

[0040] For example, in this embodiment, the energetic material layer 30 can be a gel-like energetic material layer, which is coated and cured on the surface of the thermally activated energetic layer 40 and the high thermal resistance activation region 201. That is, the energetic material layer 30 uses a gel-like energetic material, which is a material formed by filling silicon powder with oxidant crystals after porous preparation and mixing with shellac. It can be integrated with the device structure through coating, printing, curing, or other methods.

[0041] It should be noted that in this embodiment, the energetic material layer 30 can also be made of other energetic materials. This embodiment does not impose specific limitations and can be selected according to actual needs.

[0042] For example, in this embodiment, the strong oxidizing agent crystal can be sodium perchlorate crystal. Of course, other types of crystals can also be used as long as they have strong oxidizing properties. This embodiment does not specifically limit the type of strong oxidizing agent crystal, and it can be selected according to actual needs.

[0043] For example, in this embodiment, the silicon substrate 10 can be a monocrystalline silicon wafer or a polycrystalline silicon wafer (or a thinned version). Specifically, the silicon substrate 10 can be a currently mainstream 4-inch to 12-inch monocrystalline silicon wafer or polycrystalline silicon wafer with a thickness of 300 μm to 500 μm.

[0044] It should be noted that this embodiment does not specifically limit the material of the silicon substrate 10, and it can be selected according to actual needs.

[0045] like Figure 8 As shown, another aspect of the present invention provides a method for fabricating an energetic device, S100, the method comprising: S110. A silicon substrate is provided, wherein a plurality of interconnecting conductive pillars are formed throughout the thickness of the silicon substrate.

[0046] like Figure 9 As shown, a silicon substrate 10 is provided. In this embodiment, the silicon substrate 10 can be a monocrystalline silicon wafer or a polycrystalline silicon wafer (or a thinned version). Specifically, the silicon substrate 10 can be a currently mainstream 4-inch to 12-inch monocrystalline silicon wafer or polycrystalline silicon wafer with a thickness of 300 μm to 500 μm.

[0047] During the production process, the surface of the silicon substrate 10 may be contaminated or contain impurity ions. Common contaminants include organic matter, oil, metal ions, particulate impurities, and Si oxides. The silicon substrate 10 is immersed in anhydrous ethanol solution (C2H5OH) and ultrasonically cleaned for 5 minutes to remove surface organic impurities using the principle of like dissolves like. Then, the silicon substrate 10 is immersed in 5% HF (volume fraction) for 10 minutes to dissolve and remove surface oxides and metal ions. Finally, it is rinsed with deionized water and dried at room temperature. The cleaned and ready-to-use silicon substrate 10 can be stored in methanol.

[0048] Among them, such as Figure 9 As shown, the specific process of forming multiple interconnected conductive pillars 203 can be as follows: First, a plurality of through-holes penetrating the thickness of the silicon substrate 10 are formed using an opening process.

[0049] Specifically, the via pattern was defined using photolithography. A 15 μm thick positive photoresist was spin-coated, and after solvent removal via pre-baking, a 60 μm circular window was exposed using an i-line lithography machine (365 nm). After development to form a precise pattern, the image was baked and cured. Deep silicon reactive ion etching (DRIE) was then performed, using a Bosch process to cycle through SF6 etching and C4F8 passivation to create a 60 μm via on a 500 μm silicon substrate. The penetration depth was controlled by laser interferometry endpoint detection, and process parameters were optimized to suppress the sidewall scalloping effect. After etching, oxygen plasma ashing and wet cleaning were performed to remove residues.

[0050] Next, conductive material is filled into the through-hole to form the interconnecting conductive pillar.

[0051] Specifically, a 1.0 μm Si3N4 insulating layer was deposited conformally on the inner wall of the via using PECVD. Subsequently, a Ta / TaN double-layer barrier structure (50 nm each) was sputtered using ionized PVD, with bias sputtering technology ensuring continuity of coverage between the deep hole sidewalls and the hole bottom. A 500 nm–1 μm copper seed layer was then sputtered on top, the quality of which directly determines the subsequent electroplating effect. During the electroplating filling stage, an acidic copper sulfate system (containing accelerator / inhibitor / leveling additives) was used, employing a pulsed reverse electroplating process: while depositing copper with forward current, a reverse current was periodically applied to dissolve the deposits at the hole openings, driving bottom-up, hole-free filling (average current density 1–3 ASD, time 5 hours). Finally, chemical mechanical polishing was performed: first, an alkaline polishing solution was used to remove the surface copper layer until the Ta / TaN barrier layer was exposed; then, the polishing solution was changed to remove the barrier layer down to the silicon surface, achieving global planarization and forming interconnect conductive pillars 203.

[0052] S120, Multiple irregular micro-nano pores are formed on the surface of the silicon substrate.

[0053] like Figure 10 As described above, an irregular micro / nano pore structure 41 is fabricated on one side of the silicon substrate 10 using an etching process. The silicon substrate is based on a currently mainstream 4-inch to 12-inch single-crystal silicon wafer with a thickness of 500 μm. The irregular micro / nano pores 41 are part of the thermally excited energetic layer 40 of this invention and are located on one side surface of the silicon substrate 10. They belong to the micro / nano scale pore structure, with a pore diameter of 0.1 μm to 5 μm and a depth of 50 μm to 150 μm. In this embodiment of the invention, an electrochemical etching process is used according to structural design requirements. The main fabrication process is as follows: The specific process of forming multiple irregular micro / nano pores 41 on the surface of the silicon substrate 10 in step S120 can be as follows: 1) The silicon substrate 10 is cleaned and dried.

[0054] Specifically, during the production process, the surface of silicon wafers may become contaminated or contain impurity ions. Common contaminants include organic matter, oil, metal ions, particulate impurities, and Si oxides. The silicon substrate 10 is immersed in anhydrous ethanol (C2H5OH) solution and ultrasonically cleaned for 5 minutes to remove surface organic impurities using the principle of like dissolves like. Then, the silicon substrate 10 is immersed in 5% HF (volume fraction) for 10 minutes to dissolve and remove surface oxides and metal ions. Finally, it is rinsed with deionized water and dried at room temperature. The cleaned, ready-to-use silicon substrate can be stored in methanol.

[0055] 2) Place the dried silicon substrate 10 in an electrolytic cell, add a mixed solution of hydrofluoric acid and anhydrous ethanol to the electrolytic cell, and electrochemically etch the surface of the silicon substrate 10 to form a plurality of micro-nano pores 41 on the surface of the silicon substrate 10.

[0056] Specifically, the cleaned silicon substrate 10 is placed in an electrolytic cell. A 3:1 mixture of HF and anhydrous ethanol (C2H5OH) is injected into the electrolytic cell. HF etches the Si wafer, while C2H5OH acts as a surface activator, accelerating the removal of H2 from the Si wafer. This ensures sufficient contact between the Si wafer and the HF acid, speeding up the etching reaction and improving the uniformity of the etching. A Pt sheet electrode connected to the cathode of the electrochemical workstation is then placed in the electrolyte, thus forming an electrolytic circuit. The etching current density is determined by controlling the current of the electrochemical workstation, and the etching reaction time can also be controlled as needed. Ultimately, the etching process forms on the surface of the silicon substrate 10. Figure 10 The plurality of micro-nano pores 41 shown.

[0057] It should be noted that the pore size of the formed micro-nano pores 41 ranges from 0.1 μm to 5 μm, and the pore depth ranges from 50 μm to 150 μm. The micro-nano pores 41 belong to the micro-nano scale pore structure.

[0058] It should be noted that this embodiment does not specifically limit the size of the micro-nano pores 41, and can be selected according to actual needs. Furthermore, the shape of the micro-nano pores 41 is also not specifically limited, and can be selected according to actual needs.

[0059] 3) Cleaning, drying and storage.

[0060] After the corrosion reaction was completed, the sample was washed with methanol several times to remove the electrolyte on and inside the Si wafer. It was then dried in a drying oven at 60°C for 2 hours and wrapped in weighing paper for storage.

[0061] S130. A high-resistance thermal excitation region electrically connected to the interconnect conductive pillar is formed on the plurality of micro-nano pores, and a low-resistance electrical signal wire region electrically connected to the interconnect conductive pillar is formed on the surface of the silicon substrate opposite to the micro-nano pores, wherein the high-resistance thermal excitation region, the low-resistance electrical signal wire region and the interconnect conductive pillar together constitute a heating electrode.

[0062] Specifically, such as Figure 11 As shown, the process of forming the high thermal resistance excitation region 201 in step S130 may include: A first mask is placed on the surface of a silicon substrate, and the target micro / nano pore region is exposed through the patterned openings of the first mask. A physical vapor deposition process is used to directionally sputter metal material through the openings of the first mask to form a high thermal resistance excitation region 201 on the surface of the micro / nano pores.

[0063] Specifically, the process of forming the low-resistance electrical signal conductor region 202 in step S130 may include: A second mask is placed on the surface of the silicon substrate opposite to the micro-nano pores, and the patterned opening of the second mask exposes the wire area pattern; a highly conductive metal layer is sputtered through the opening of the second mask to form a low-resistance electrical signal wire area 202.

[0064] The sputtering process is as follows: First, a high-purity chromium or copper target is fixed to the magnetron sputtering head, and then the substrate and photomask are placed inside the sputtering cavity. Subsequently, the vacuum chamber is evacuated to ≤10°C. -4 A high vacuum of 0.1 Pa is used to reduce residual gas contamination of the thin film. During sputtering, argon gas is introduced as the working gas and maintained at a pressure of 0.1 Pa to 10 Pa. A glow discharge is initiated by applying a negative high voltage of hundreds to thousands of volts to the target, ionizing the argon gas to form plasma. After the argon ions bombard the target surface, metal atoms or atomic clusters are sputtered out, passing through the opening area of ​​the mask, and finally deposited as a film on the substrate surface. The DC controlled sputtering power is 150 W for chromium metal and 300 W for copper metal.

[0065] The above process needs to be repeated for the preparation of the heating electrode 20 with a multilayer metal structure. Different sputtering process parameters are selected for different metals, which is understandable to experts in the industry and will not be elaborated here.

[0066] In this embodiment, a plurality of interconnecting conductive pillars 203 extending through the thickness of the silicon substrate 10 are first formed. Then, a plurality of irregular micro-nano pores 41 are formed on the surface of the silicon substrate 10. A high-resistance thermal excitation region 201 is formed on the micro-nano pores 41. Finally, a low-resistance electrical signal conductor region 202 is formed on the lower surface of the silicon substrate 10, thereby forming a heating electrode 20. This can ensure the protection of the micro-nano pores 41 during the fabrication of the heating electrode 20 and improve the reliability of the formed thermally excited energetic layer 40.

[0067] S140. Fill the micro-nano pores with strong oxidant crystals to form a thermally activated energetic layer.

[0068] In step S140, the specific steps for forming the thermally excited energetic layer 40 can be as follows: 1) The intermediate structure having multiple micro-nano pores and the heating electrode is cleaned and dried.

[0069] Specifically, the intermediate structure with multiple micro-nano pores 41 and heating electrode 20 is cleaned, and then the intermediate structure is placed in a drying oven at 60 °C to dry, ensuring that the surface is clean.

[0070] 2) Vacuum the intermediate structure to remove air bubbles from the micro-nano pores.

[0071] Specifically, the polytetrafluoroethylene beaker and intermediate structure are placed in a vacuum chamber and a vacuum is drawn to remove air bubbles from the micro-nano pores 41.

[0072] 3) The intermediate structure was placed in a saturated sodium perchlorate ethanol solution and ultrasonically filled.

[0073] Specifically, the intermediate structure is placed horizontally in a PTFE beaker. A saturated sodium perchlorate-ethanol solution is added to the PTFE beaker, ensuring that the solution completely immerses the sample. The PTFE beaker is then placed in the working tank of an ultrasonic cleaner, ensuring that the ultrasonic waves are evenly applied to the solution and the intermediate structure. The ultrasonic cleaner is then started, and the ultrasonic frequency is set to 20 Hz to 200 Hz, the power to 60 W to 100 W, and the ultrasonic treatment time to 10 to 40 minutes.

[0074] 4) The intermediate structure after soaking and filling is placed in an oven for low-temperature drying to remove the ethanol solvent, so that sodium perchlorate can recrystallize in the micro-nano pores to form strong oxidant crystals, thereby forming the thermally activated energetic layer.

[0075] After ultrasonic treatment, the intermediate structure is removed from the solution and dried in an oven at a low temperature (60°C) to remove the ethanol solvent, ensuring that sodium perchlorate recrystallizes within the micro-nano pores to form strong oxidant crystals, thereby forming... Figure 12 The thermally excited energetic layer 40 is shown.

[0076] It should be noted that other types of crystals can also be used for strong oxidizing agents, as long as they possess strong oxidizing properties. This embodiment does not specifically limit the type of strong oxidizing agent crystals; they can be selected according to actual needs.

[0077] It should be further noted that, in this embodiment, since the relatively large low-resistivity electrical signal conductor region 202 in the previously formed heating electrode 20 is located on the lower surface of the silicon substrate 10, it does not cover the micro-nano pores. The high-resistivity thermal excitation region 201 is formed on the micro-nano pores. Due to the narrow linewidth of the high-resistivity thermal excitation region 201, the saturated sodium perchlorate ethanol solution can completely penetrate into all micro-nano pores from the sides, thereby making the strong oxidant crystals formed in the area below the leads of all heating electrodes 20 more uniform, improving the overall performance of the device.

[0078] S150, A gel-like energetic material is coated on the surface of the thermally excited energetic layer and the high thermal resistance excitation region to form an energetic material layer.

[0079] Specifically, a gel-like energetic material is coated onto the surfaces of the thermally activated energetic layer 40 and the high-thermal-resistance activation region 201 using a screen printing coating process, and then dried and cured to form a gel-like energetic material. Figure 13 The energetic material layer 30 shown forms a complete semiconductor energetic device structure.

[0080] The energetic device fabrication method of the present invention forms a thermally excited energetic layer that is in direct and close contact with a heating electrode at the microscopic level. After electrothermal excitation, heat is rapidly and effectively applied to the irregular micro-nano pores in direct contact with the heating electrode. The silicon in the micro-nano pores reacts rapidly with the strong oxidant crystals, quickly detonating and thus detonating the energetic material layer above. This energetic device structure improves the problem of excessively long response time from electrothermal excitation to detonation, and has significant advantages in detonation response (reaching the millisecond level). At the same time, it reduces the deterioration of the energetic material caused by the inability to quickly detonate and thermally decompose, ensuring the release of energy.

[0081] The method for fabricating energetic devices according to the present invention forms a heating electrode comprising a high-resistivity thermal excitation region, a low-resistivity electrical signal conductor region, and interconnecting conductive pillars. The low-resistivity electrical signal conductor region is formed on the surface of the silicon substrate away from the thermally excited energetic layer and is electrically connected to the high-resistivity thermal excitation region disposed on the thermally excited energetic layer through the interconnecting conductive pillars. This fundamentally avoids the problem that a wide low-resistivity electrical signal conductor region would obstruct the subsequent filling of micro-nano pores beneath it by strong oxidants, resulting in insufficient and non-dense energetic material with uneven energy density distribution. This makes the energetic material filled in the area below all heating electrode leads more uniform, while reducing the large-area wiring on the surface of the thermally excited energetic layer, improving its surface uniformity, and thus improving the overall performance of the device. In addition, the low-resistivity electrical signal conductor region of the heating electrode is disposed on the surface of the silicon substrate to lead out the signal, improving the electrical connectivity of the energetic device and facilitating modular and array packaging of the energetic device.

[0082] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. An energetic device, characterized in that, It includes a silicon substrate, a thermally activated energetic layer, a heating electrode, and an energetic material layer; The thermally excited energetic layer is disposed on the silicon substrate, and the thermally excited energetic layer includes a plurality of irregular micro-nano pores and strong oxidant crystals filling the micro-nano pores; The energetic material layer is disposed on the thermally activated energetic layer; The heating electrode includes a high-resistance thermal excitation region, a low-resistance electrical signal wire region, and interconnecting conductive pillars; wherein... The high thermal resistance excitation region is disposed on the surface of the thermally excited energy layer opposite to the silicon substrate; The low-resistance electrical signal conductor region is disposed on the surface of the silicon substrate away from the thermally excited energy-containing layer; The interconnecting conductive pillars pass through the silicon substrate and the thermally excited energetic layer in sequence, and are electrically connected to the high-resistance thermally excited region and the low-resistance electrical signal conductor region, respectively.

2. The energetic device according to claim 1, characterized in that, Multiple micro / nano pores are disposed on the surface of the silicon substrate; wherein, The pore size of the micro-nano pores ranges from 0.1 μm to 5 μm, and the pore depth ranges from 50 μm to 150 μm.

3. The energetic device according to claim 1, characterized in that, The high thermal resistance excitation region is a single-layer or multi-layer metal structure made of at least one of chromium, nickel, titanium, platinum, and gold; wherein, The thickness of the metal layer in the high thermal resistance excitation region ranges from 1 μm to 5 μm, and the linewidth of the high thermal resistance excitation region ranges from 0.05 mm to 2 mm.

4. The energetic device according to any one of claims 1 to 3, characterized in that, The low-resistance electrical signal conductor region is a metal or multilayer metal structure composed of at least one of copper, chromium, nickel, titanium, platinum, and gold; wherein, The thickness of the metal layer in the low-resistance electrical signal conductor region ranges from 1 μm to 5 μm, and the linewidth of the low-resistance electrical signal conductor region ranges from 0.05 mm to 2 mm.

5. The energetic device according to any one of claims 1 to 3, characterized in that, The interconnecting conductive pillars are through-silicon vias (TSVs), and the diameter of the TSVs ranges from 25 μm to 500 μm.

6. A method for fabricating an energetic device, characterized in that, The method includes: A silicon substrate is provided, wherein a plurality of interconnecting conductive pillars are formed throughout the thickness of the silicon substrate; Multiple irregular micro-nano pores are formed on the surface of the silicon substrate; A high-resistance thermal excitation region electrically connected to the interconnect conductive pillars is formed on the plurality of micro-nano pores, and a low-resistance electrical signal wire region electrically connected to the interconnect conductive pillars is formed on the surface of the silicon substrate opposite to the micro-nano pores, wherein the high-resistance thermal excitation region, the low-resistance electrical signal wire region and the interconnect conductive pillars together constitute a heating electrode; Strong oxidant crystals are filled into the micro-nano pores to form a thermally activated energy layer; An energetic material layer is formed by coating the surfaces of the thermally excited energetic layer and the high thermal resistance excitation region with a gel-like energetic material.

7. The method according to claim 6, characterized in that, The formation of multiple irregular micro / nano pores on the surface of the silicon substrate includes: The silicon substrate is cleaned and dried; The dried silicon substrate is placed in an electrolytic cell, and a mixed solution of hydrofluoric acid and anhydrous ethanol is added to the electrolytic cell to electrochemically etch the surface of the silicon substrate to form a plurality of micro-nano pores on the surface of the silicon substrate.

8. The method according to claim 6, characterized in that, The process of forming the interconnecting conductive pillars includes: Multiple through-holes penetrating the thickness of the silicon substrate are formed using an aperture-opening process; The through-hole is filled with conductive material to form the interconnecting conductive pillars; The process of forming the high thermal resistance excitation region includes: placing a first mask on the surface of a silicon substrate, exposing the target micro / nano pore region through the patterned openings of the first mask; and using a physical vapor deposition process to directionally sputter metal material through the openings of the first mask to form a high thermal resistance excitation region on the surface of the micro / nano pores. The process of forming the low-resistance electrical signal conductor region includes: placing a second mask on the surface of the silicon substrate away from the micro-nano apertures, exposing the conductor region pattern through the patterned openings of the second mask; and sputtering a highly conductive metal layer through the openings of the second mask to form the low-resistance electrical signal conductor region.

9. The method according to claim 6, characterized in that, The process of filling the micro / nano pores with strong oxidant crystals to form a thermally activated energetic layer includes: The intermediate structure containing the multiple micro-nano pores and the heating electrode is cleaned and dried. The intermediate structure is evacuated to remove air bubbles from the micro-nano pores; The intermediate structure was placed in a saturated sodium perchlorate ethanol solution and ultrasonically immersed and filled. The intermediate structure after soaking and filling is placed in an oven for low-temperature drying to remove the ethanol solvent, so that sodium perchlorate can recrystallize in the micro-nano pores to form strong oxidant crystals, thereby forming the thermally activated energetic layer.

10. The method according to claim 6, characterized in that, The process of coating the surfaces of the thermally excited energetic layer and the high-thermal-resistance excited region with a gel-like energetic material to form an energetic material layer includes: A gel-like energetic material is coated onto the surfaces of the thermally activated energetic layer and the high thermal resistance activation region using a screen printing coating process, and then dried and cured to form the energetic material layer.

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