Preparation method of monocrystalline silicon nano film for nano photon technology

Abstract

The invention relates to a preparation method of a monocrystalline silicon nano film for a nano photon technology, and belongs to the field of silicon-based nano material preparation. The method comprises the following steps: carrying out ultrasonic cleaning on an oriented monocrystalline silicon substrate; a porous silicon sacrificial layer with porosity distributed in a gradient manner is prepared on the back surface through pulse electrochemical etching; after hydrogen plasma passivation treatment, a monocrystalline silicon nano film is deposited on the surface at a low temperature; then, selectively etching the porous silicon sacrificial layer by using a surfactant compound solution, stripping to form a complete monocrystalline silicon nano film, and transferring the complete monocrystalline silicon nano film to a target substrate through surface tension or a heating fitting mode; and finally, the stability of the film surface can be improved through silane passivation, and the residual substrate can be recycled for multiple times after being cleaned.

Description

Technical Field

[0001] This invention belongs to the field of silicon-based nanomaterial preparation, specifically relating to a method for preparing single-crystal silicon nanofilms for nanophotonics technology. Background Technology

[0002] Single-crystal silicon, with its superior optical properties—extremely high refractive index, extremely low near-infrared optical loss, and mature micro / nano fabrication technology—has become an indispensable core material platform for constructing high-performance integrated photonic devices. Especially in the field of nanophotonics, its ability to utilize the interaction between light and subwavelength structures provides a physical basis for designing high-density, low-power, and novel functional photonic chips. Currently, widely used silicon photonics technologies largely rely on the SOI (Silicon-on-Insulator) platform, which achieves strong optical field confinement of optical waveguides by growing or bonding a single-crystal silicon thin film on a buried oxide (BOX) layer of silicon dioxide (SiO2).

[0003] However, the fixed thickness of the silicon film in the SOI structure makes it difficult to meet the customized film thickness requirements of photonic crystals, interference devices, etc., and the buried layer structure limits the flexibility of thermal management and vertical stacking.

[0004] Existing methods for preparing single-crystal silicon nanofilms mainly include: 1. Smart Cut Technology: This technology achieves thin film transfer by inducing delamination through hydrogen ion implantation. Its main challenges lie in the difficulty of precisely controlling the thickness uniformity of the release layer, the potential for crystal damage during implantation and annealing processes, and the fact that the final film thickness is still limited by the initial implantation depth and bonding process, resulting in limited customization and high costs for large-area uniformity control.

[0005] 2. CMP polishing and epitaxy: Path A, grinding and polishing of bulk silicon wafers to reduce thickness: This process is prone to introducing surface damage, stress and thickness gradient, making it extremely difficult and time-consuming to achieve high thickness uniformity, atomic-level surface roughness (RMS) and high crystal quality of large-area ultrathin silicon films, resulting in low yield and significantly increased cost.

[0006] Path B involves CMP polishing of the epitaxially grown silicon layer surface. The core challenge of this path lies in refining the surface roughness (RMS) to the atomic level and removing subsurface damage while maintaining large-area flatness. Although the epitaxial layer itself has good crystal quality and thickness uniformity, the fine polishing process increases the number of steps and costs.

[0007] 3. Bonding-to-Lift Method: As disclosed in Chinese Invention Application CN1710152A, silicon is bonded to a substrate with a sacrificial layer, and then the sacrificial layer is etched to release the silicon film. This method is highly dependent on the selective etching characteristics of the sacrificial layer material, which may introduce residual contamination or damage to the silicon film. More importantly, the released silicon film usually needs to be transferred and bonded to the target functional substrate a second time. This process is complex and prone to film damage or introducing interface defects, limiting its universality and ease of application on various heterogeneous substrates.

[0008] Especially in the process of constructing fine structures such as photonic crystals and subwavelength gratings, higher requirements are placed on the thickness uniformity, surface roughness, and crystallization defect rate of silicon films.

[0009] In summary, although single-crystal silicon nanofilms hold great potential for advancing next-generation high-performance, multifunctional silicon-based photonic nanodevices, existing fabrication techniques generally suffer from key bottlenecks such as complex processes, high costs, insufficient thickness control precision, poor large-area uniformity, low yield, and difficulty in compatibility with diverse functional substrates. These shortcomings severely restrict the flexible design and reliable fabrication of silicon-based photonic nanostructures for specific applications.

[0010] Therefore, developing a novel single-crystal silicon nanofilm preparation technology that combines ease of processing, cost-effectiveness, high-precision controllable film thickness, excellent crystal quality and surface properties, and wide applicability to various substrates has become a core and urgent issue for breaking through the current barriers to silicon-based nanophotonics technology and realizing its wider application. Summary of the Invention

[0011] To address the shortcomings of existing technologies, this invention provides a method for preparing single-crystal silicon nanofilms for nanophotonics technology, thereby solving the problems mentioned in the background section.

[0012] To achieve the above objectives, the present invention provides the following technical solution: A method for preparing a single-crystal silicon nanofilm for nanophotonics technology includes the following steps: S1 Substrate Cleaning: The <100> oriented monocrystalline silicon substrate was ultrasonically cleaned in acetone, anhydrous ethanol and deionized water in sequence, and then dried with nitrogen. Electrochemical preparation of S2 porous silicon sacrificial layer: An electrolyte of HF aqueous solution: ethanol = 1 ml: 1 ml was applied to the back side of the substrate, and B(OH)3 with a concentration of 0.01–0.05 M was added. A two-stage pulsed current was applied, stage one: 10 mA / cm 2 Phase 1: 2 s on / 1 s off, 10 s; Phase 2: 20 mA / cm 2Etching was performed for 1 second on and 1 second off, followed by 20 seconds, to form a porous silicon sacrificial layer with a total thickness of 800 nm and a porosity gradient distribution from 30% to 60%. S3 In-situ hydrogen plasma passivation: The substrate is flipped and placed in the LPCVD chamber and treated for 1–5 min at 300–400 °C, 80–120 W and H2 flow rate of 100 sccm to remove surface oxides and form hydrogen passivation on the top of the porous silicon sacrificial layer. S4 Low Temperature Si 1-x Ge x Epitaxial growth: SiH4, GeH4, and H2 gases were introduced at 600℃ and 10 Torr, with gas flow rates controlled within the ranges of 10–30 sccm, 0.2–1 sccm, and 150–250 sccm, respectively, to sequentially deposit Si. 1-x Ge x The stress-controlled buffer layer and the single-crystal Si functional layer are epitaxially grown with a total thickness of 50–300 nm, and the resulting composite structure constitutes a single-crystal silicon nanofilm. S5 Surfactant-assisted wet stripping: Immerse the back side of the substrate in an etching solution of HF∶H2O∶H2O2∶CTAB∶Triton X-100 = 1 ml∶10 ml∶0.05 ml∶0.01 ml∶0.005 ml for 2–3 min to achieve selective dissolution of the porous silicon sacrificial layer and strip out the complete single-crystal silicon nanofilm. S6 Nanofilm Transfer and Bonding: The peeled single-crystal silicon nanofilm is floated and transferred to the surface of the target substrate, bonded by surface tension or light heating and air-dried; S7 Adhesive removal and surface passivation: When using adhesive, remove it by soaking in acetone, and then wash it in sequence with acetone, ethanol and deionized water; otherwise, directly perform in-situ passivation of silane on the surface of the single crystal silicon nanofilm. S8 Substrate Recycling and Reuse: After cleaning and drying the remaining silicon substrate, steps S2–S5 can be repeated for the next preparation.

[0013] As one embodiment, in step S2, the pore size and porosity gradient are controlled by pulsed electrochemical conditions to improve the mechanical strength and peeling efficiency of the porous silicon sacrificial layer; In step S3, the temperature, power, and time of the hydrogen plasma treatment can be adjusted appropriately to balance the passivation effect with the stability of the porous silicon sacrificial layer structure. In step S4, the epitaxial deposition time t is linearly related to the thickness of the single-crystal silicon nanofilm, and can be arbitrarily adjusted within the range of 50–300 nm. The deposition rate remains constant, ensuring thickness uniformity. The bonding of monocrystalline silicon nanofilms can be supplemented with mild heating at ≤80℃ or vacuum bonding to achieve higher bonding strength.

[0014] This invention provides a method for preparing single-crystal silicon nanofilms for nanophotonics technology. It has the following beneficial effects: 1. Precisely adjustable film thickness: Through the linear relationship between epitaxial growth time and film thickness, the thickness can be arbitrarily set within the range of 50–300 nm, fully meeting the personalized requirements of different nanophotonic structures for film thickness.

[0015] 2. High-quality single-crystal crystallization: in-situ hydrogen plasma passivation and Si 1-x Ge x By combining buffer layer stress regulation, the lattice matching degree and film uniformity of the epitaxial layer are significantly improved, and the obtained film has a consistent orientation, no polycrystalline regions, and a surface roughness of <0.5 nm.

[0016] 3. Low-damage, high-integrity exfoliation: Gradient porous silicon sacrificial layer combined with wet etching using CTAB / Triton X-100 dual surfactants achieves high-speed selective dissolution of the porous silicon sacrificial layer while simultaneously exfoliating the dense epitaxial layer with zero damage, thus preparing a complete large-size nanofilm.

[0017] 4. Recyclable substrate: After the sacrificial layer is etched, the remaining substrate can be restored to a smooth surface by simple cleaning. The preparation steps can be repeated multiple times, and the number of times it can be reused is ≥5 times, which greatly reduces material and process costs.

[0018] 5. Simplified and cost-reduced: It avoids the complex processes of traditional Smart Cut injection and stripping, CMP polishing, and high-temperature bonding. All processes are completed below 650°C, significantly reducing equipment investment and energy consumption, and increasing yield and mass production potential.

[0019] 6. Flexible substrate compatibility: The fabricated nanofilms can be transferred and bonded to various target substrates such as glass, polyimide, and SOI through surface tension or adhesive methods, making them suitable for diverse nanophotonic integration platforms.

[0020] 7. Closed-loop integration of the entire process: From substrate cleaning, sacrificial layer preparation, epitaxial deposition, wet stripping to transfer bonding and substrate recycling, a complete fabrication process chain that is continuous, scalable, and industrializable is formed. Attached Figure Description

[0021] Figure 1 This is a flowchart of the present invention; Figure 2 The current curves during the pulsed electrochemical etching process are shown for each of the five cycles of use of the substrate in Example 1. Detailed Implementation

[0022] To enable those skilled in the art to understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort should fall within the scope of protection of the present invention.

[0023] The present invention will now be described in detail with reference to the accompanying drawings: Example 1 (refer to) Figure 1 and Figure 2 In this embodiment, a 100 nm single-crystal silicon nanofilm was prepared and transferred to a glass substrate. The specific implementation method is as follows: Step 1: Substrate cleaning Take a 100 mm diameter (100) oriented monocrystalline silicon wafer with no obvious scratches on the surface, place it in a beaker containing 100 mL of acetone, and ultrasonically clean it for 5 minutes. Then remove the silicon wafer, shake off the residual solution, and place it in a beaker containing 100 mL of anhydrous ethanol, and ultrasonically clean it for 5 minutes. After removing and shaking off the solution again, place the silicon wafer in a beaker containing 100 mL of deionized water to complete the final 5-minute ultrasonic cleaning. Finally, remove the silicon wafer, blow the surface dry with high-purity nitrogen gas, and set it aside for later use.

[0024] Step 2: Preparation of porous silicon sacrificial layer First, 0.5 mL of platinum paste was uniformly sprayed onto the back of the silicon wafer and dried in an oven at 100°C for 10 min to form a good conductive film. Then, 100 mL of electrolyte was prepared: 50 mL of 49% HF aqueous solution was mixed with 50 mL of anhydrous ethanol, and 0.25 g of B(OH)3 was added, stirring thoroughly until dissolved. The back of the silicon wafer was used as the anode, and the platinum electrode as the cathode, with a 1 cm gap between them. The prepared electrolyte was then poured into the etching tank to ensure that the back of the silicon wafer was completely submerged.

[0025] The etching process is performed in two stages using pulsed electrochemical treatment: Phase 1: Apply 10 mA / cm 2 Current density, 100 mm diameter single-crystal silicon wafer area 78.5 cm² 2 The corresponding current is 785 mA. The etching is performed for 10 s with a 2 s on / 1 s off mode to obtain a primary porous layer with a porosity of 30% and a thickness of 300 nm. Phase 2: Switch to 20 mA / cm 2 The current density was 1.57 A on a 100 mm diameter single-crystal silicon wafer, and the etching continued for 20 s in a 1 s on / 1 s off mode to form a secondary porous layer with a porosity of 60% and a thickness of 500 nm.

[0026] After etching, immediately rinse the residual etching solution with 100 mL of deionized water and blow dry with nitrogen to obtain a gradient porous silicon sacrificial layer with a total thickness of 800 nm and a porosity that gradually increases from 30% to 60%.

[0027] Step 3: In-situ hydrogen plasma passivation After flipping the silicon wafer so that the porous silicon sacrificial layer faces upwards and placing it on the LPCVD chamber tray, first evacuate the chamber to 10°C. -2 Torr and heat to 350°C; then keep H2 gas flowing into the chamber at a flow rate of 100 sccm and start radio frequency plasma treatment at 100 W for 2 min; after treatment, turn off the plasma and allow the chamber to cool naturally to room temperature, then the silicon wafer can be removed.

[0028] Step 4: Low Temperature 4Si 1-x Ge x Epitaxial growth The passivated silicon wafer was placed back into the LPCVD chamber, evacuated, and heated to 600°C. The chamber pressure was then stabilized at 10 Torr. Subsequently, SiH4, 20 sccm, GeH4, 0.5 sccm, and H2, 200 sccm were introduced, with the volume ratio of GeH4 to SiH4 being 2.5%. The atmosphere was maintained for 5 min, and a 100 nm thick single-crystal silicon nanofilm was deposited at a rate of 20 nm / min.

[0029] After deposition is complete, turn off all gas sources and allow the chamber to cool naturally to room temperature before removing the silicon wafer.

[0030] Step 5: Dual surfactant-assisted peeling Prepare the stripping etching solution: HF∶H2O∶H2O2∶CTAB∶Triton X-100 = 1ml∶10ml∶0.05ml∶0.01ml∶0.005ml. Take 10 mL of 49% HF aqueous solution, 100 mL of deionized water, 0.5 mL of 30% H2O2, 0.1 mL of 10 g / L CTAB solution, and 0.05 mL of Triton X-100, and mix them thoroughly.

[0031] The back of the silicon wafer was placed in the etching solution and immersed for 2.5 minutes. The porous silicon sacrificial layer was observed to dissolve, and the monocrystalline silicon nanofilm was automatically peeled off and floated on the liquid surface.

[0032] Use tweezers to extract the membrane into deionized water and gently rinse it to remove any etching residue.

[0033] Step 6: Transfer and bonding of single-crystal silicon nanofilms Take a pre-cleaned flat glass slide, 25 mm × 25 mm in size, and immerse it in deionized water to keep the surface moist. Then, use tweezers or slide clips to gently move the nanofilm floating on the water surface to the center of the slide, and use the surface tension of the water to make it automatically and evenly adhere. Finally, let it stand at room temperature for 10 minutes to air dry, so that the monocrystalline silicon nanofilm adheres firmly to the glass slide.

[0034] Step 7 Surface passivation The passivation solution was prepared as follows: 2 mL of trimethoxysilane (MTMS) was added to 100 mL of anhydrous ethanol and stirred until homogeneous to obtain a 2% passivation solution. The laminated glass substrate was then immersed in this solution for 1 min, removed, and the surface was dried with high-purity nitrogen gas, thus completing the in-situ silane passivation of the nanofilm. The single-crystal silicon nanofilm on the substrate was then allowed to air dry at room temperature to fully evaporate any residual moisture on the surface, yielding the final single-crystal silicon nanofilm sample.

[0035] Step 8: Substrate Recycling and Reuse The residual silicon substrate is immersed in acetone for 5 min to remove organic residues, then rinsed in anhydrous ethanol and deionized water for 5 min each, and the surface is dried with nitrogen. After visual inspection or surface roughness test confirms that there are no porous silicon sacrificial layer residues, the substrate can be prepared by repeating steps 2-5 for ≥5 cycles, and the overall performance change is less than 5%.

[0036] The prepared single-crystal silicon nanofilms were tested for film thickness, surface roughness, exfoliation integrity, and cycle performance. Film thickness measurement: The bonded and passivated sample was placed on the sample stage of an ellipsometer (JAWoollam M-2000), ensuring the stage was clean and level. A 632.8 nm monochromatic light source was selected, with an incident angle of 70°. Measurements were taken sequentially at the sample center and four equidistant points, recording the values ​​Ψ and Δ at each point. After measurement, the film thickness at each point was obtained by fitting the built-in Si / SiO2 model, and the arithmetic mean of the five thicknesses was taken. The standard deviation was calculated, and the final film thickness was 100 nm.

[0037] Surface roughness measurement: The sample was fixed on the stage of an atomic force microscope (AFM), model Bruker Dimension Icon, with a silicon probe selected and operating in tapping mode. The scanning area was set to 5µm × 5µm, the scanning resolution to 512 × 512 pixels, and the scanning rate to 1 Hz. After one scan, the height map was corrected for planarity using software, and the Ra value of the entire area was extracted. The scans were repeated three times and averaged, finally yielding Ra = 0.4 nm. This value is far lower than the Ra index commonly found in similar processes, verifying that the method of this invention can still achieve high crystallinity consistency and excellent interface integrity under low-temperature deposition and wet exfoliation conditions, thus possessing a high level of surface smoothness control capability.

[0038] Integrity assessment of the detached monocrystalline silicon nanofilm: The floating, detached nanofilm, along with the water surface, was gently transferred to a high-transmittance glass slide and observed under a Nikon LV100ND optical microscope. Using 10× and 20× objectives, ten fields of view were taken, including the center and edges of the sample. ImageJ image analysis software was used to binarize and segment the intact area in each image against the total area, and the ratio of intact area was calculated. The arithmetic mean of the integrity ratios from the ten images yielded an average detachment integrity of 96.7%, thus confirming that the detachment integrity was better than 96%.

[0039] Cyclic performance: To verify the reusability of the substrate, after the initial preparation of the single-crystal silicon nanofilm, steps 2 to 5 were repeated sequentially on the remaining substrate for a total of 5 cycles. The following key parameters were recorded:

[0040] Table 1 The data above show that after five fabrication cycles, the etching behavior, sacrificial layer structure, and lift-off behavior of the substrate remained stable, with an overall performance change of less than 3%, verifying that the process has good reusability and process stability.

[0041] The current curves for etching cycles 1-5 are referenced. Figure 2 The peak current response, current plateau value, and switching response time were highly consistent each time, and the fluctuation range did not exceed ±0.1 mA / cm. 2 This indicates that the substrate surface condition, conductivity consistency, and sacrificial layer formation process did not undergo significant changes. Therefore, it can be concluded that the silicon substrate used in this invention exhibits stable electrochemical behavior during multiple cycle fabrication processes and can effectively support closed-loop process designs that can be used for ≥5 cycles.

[0042] Example 2 provides a method for preparing a 250 nm single-crystal silicon nanofilm and transferring it to a polyimide film. The specific implementation method is as follows: Following the procedure of Example 1, the only difference is that the deposition time is extended to 12 min in step 4 to obtain a 250 nm thick monocrystalline silicon nanofilm; a 25 mm × 25 mm polyimide (PI) film carrier is used in step 6; the PI film is attached to a heating stage and preheated at 60 °C for 10 min to stabilize its surface temperature; the monocrystalline silicon nanofilm floating on the surface of deionized water is gently moved to the center of the preheated PI film with tweezers, and the surface tension of the water is used to make the monocrystalline silicon nanofilm flat and adhere to the surface of the PI film; the PI film and the monocrystalline silicon nanofilm are kept at 60 °C for another 10 min to promote reliable adhesion between the monocrystalline silicon nanofilm and the PI film; after removal, it is allowed to cool naturally at room temperature to obtain a 250 nm monocrystalline silicon nanofilm firmly attached to the polyimide carrier.

[0043] The single-crystal silicon nanofilm was tested according to the method in Example 1. The test results were as follows: film thickness: 250 nm; surface roughness: 0.45 nm; peel integrity: 95.3%; polyimide adhesion strength: peel stress > 0.1 MPa.

[0044] The above Examples 1 and 2 fully demonstrate the beneficial effects of the present invention, namely, "precisely adjustable film thickness, high crystal quality, low-damage complete peeling, substrate recyclability, mild and low-cost process, and flexible substrate compatibility".

[0045] Comparative Example 1 provides a method for preparing 220 nm single-crystal silicon nanofilms using the Smart Cut method, and the specific implementation is as follows: A 220 nm single-crystal silicon nanofilm was prepared using a typical Smart Cut process and then transferred to a silicon substrate. The following experiments were conducted under the same laboratory conditions as in Example 1, and all silicon substrates used were 100 mm in diameter, <100> oriented monocrystalline silicon wafers.

[0046] 1. Substrate thermal oxidation Two silicon wafers were used as the donor and acceptor wafers, respectively. They were cleaned and placed in a horizontal tube furnace. After being heated to 1100℃, they were oxidized in the horizontal tube furnace for 14 min with a pure oxygen flow of 2 L / min to grow a 220 nm thick thermal silicon oxide (SiO2) layer on the surface of the silicon wafers.

[0047] At this point, both the donor and acceptor silicon wafers have obtained a 220 nm thick SiO2 layer. 2. Perform RCA cleaning on both silicon wafers. (1) SC-1: Two silicon wafers with a 220 nm thick thermal silicon oxide (SiO2) layer grown on their surface were ultrasonically cleaned for 10 min in a 75°C water bath by mixing 30 mL of concentrated ammonia (28% NH4OH aqueous solution), 30 mL of hydrogen peroxide (30% H2O2 aqueous solution), and 150 mL of deionized water. (2) DI water rinse: Rinse 3 times with 500 mL of deionized water, 1 min each time; (3) SC-2: In a 75℃ water bath, mix 30 mL of concentrated hydrochloric acid (i.e., an aqueous solution with a mass concentration of 37% HCl), 30 mL of hydrogen peroxide solution (i.e., an aqueous solution with a mass concentration of 30% H2O2), and 150 mL of deionized water, and ultrasonically clean for 10 min. (4) Rinse with 500 mL of deionized water 3 times, 1 min each time, and then blow dry with nitrogen.

[0048] 3. Hydrogen ion implantation One of the donor silicon wafers was placed in an ion implanter with its oxide layer facing upwards, and H+ ions were implanted at room temperature using an energy of 45 keV. + Bundle, injection dose 5×10 16 ions / cm 2 The scanning rate is 5 cm / s to ensure uniform injection.

[0049] The acceptor silicon wafer is not implanted; only its 220 nm SiO2 is retained. 4. Surface activation before bonding (1) The donor silicon wafer after hydrogen ion implantation and the acceptor silicon wafer with 220 nm SiO2 grown on the surface were activated by plasma in 100 mL of deionized water at room temperature: O2 flow rate 200 sccm, chamber pressure 0.5 Torr, RF power 100 W, processing time 60 s; (2) After activation, rinse with 500 mL of deionized water and dry with nitrogen.

[0050] 5. Wafer bonding Two activated silicon wafers were placed face-to-face on a clean bench, and a pressure of 1,000 N was gently applied and maintained for 5 minutes. Then, they were annealed at 200°C under a 2 L / min N2 atmosphere for 2 hours to strengthen the bonding interface.

[0051] At this point, the 220 nm SiO2 layers of the donor silicon wafer and the acceptor silicon wafer have formed an integrated BOX (buried oxide) structure through "SiO2–SiO2" bonding.

[0052] 6. Low-temperature thermal peeling The bonded wafer pair is placed in a tube furnace and held at 550°C for 30 minutes under N2 flow at a rate of 2 L / min to induce micro-fission and separation in the hydrogen-injected region. After completion, it is gently pried apart, leaving the upper 220 nm thick single-crystal silicon film on the acceptor silicon wafer.

[0053] What remains on the acceptor wafer is a 220 nm thick single-crystal silicon nanofilm above the hydrogen implantation layer in the donor silicon wafer. The 220 nm SiO2 layers of the donor and acceptor silicon wafers are bonded together by "SiO2–SiO2" to form an integrated BOX structure that remains on the acceptor wafer, forming the buried oxide layer in the SOI structure.

[0054] 7. Chemical Mechanical Polishing (CMP) To remove the rough layer on the separation surface, CMP was performed on the single-crystal silicon nanofilm on the acceptor silicon wafer: Use 500 mL of polishing slurry containing 5 wt% colloidal silica. Polishing time: 300 rpm, 4 psi, 5 min; After the procedure, rinse with 200 mL of deionized water, sonicate with 50 mL of isopropanol for 5 min, rinse again, and dry with nitrogen.

[0055] 8. Film thickness measurement The polished sample was placed in an ellipsometer JAWoollam M-2000 with a light source wavelength of 632.8 nm and an incident angle of 70°. Measurements were taken at 5 points, including the center and four corners, and the average was calculated. The thickness of the single-crystal silicon nanofilm was found to be 220 nm.

[0056] 9. Thin film transfer to target silicon substrate In practice, the acceptor silicon wafer is the target silicon substrate, and the single-crystal silicon nanofilm has been transferred. If it is necessary to transfer to other silicon-based carriers, the target carrier can be bonded to the acceptor before step 5.

[0057] Following the method in Example 1, the roughness and peeling rate of the comparative single-crystal silicon nanofilm were measured. The results were: roughness: 2 nm; peeling integrity: 70%; cracks appeared in multiple areas of the single-crystal silicon nanofilm; the substrate was scrapped at one time and could not be recycled.

[0058] This is a comparative analysis table of key performance parameters between "Example 1" and "Comparative Example 1". It can be clearly seen from the table that the present invention is superior to the existing process in terms of film smoothness, peel integrity, structural stability and material utilization efficiency, and has significant technological progress.

[0059]

[0060] Table 2 Compared with the comparative example, the single-crystal silicon nanofilm prepared by this invention exhibits significant advantages in surface flatness, exfoliation integrity, structural stability, and resource utilization efficiency. First, its surface roughness is only 0.4 nm, far lower than the 2 nm of the comparative example, indicating that the single-crystal silicon nanofilm obtained by this invention has a smoother surface, which is beneficial for subsequent construction of high-precision nanophotonic structures. Second, the exfoliation integrity is as high as 96.7%, significantly better than the 70% of the comparative example, indicating that the single-crystal silicon nanofilm maintains structural integrity during the exfoliation process, making it suitable for large-area, high-uniformity integrated applications. Furthermore, the single-crystal silicon nanofilm prepared by this invention exhibits good structural continuity, with no obvious cracks observed, avoiding the risk of surface rupture due to localized stress concentration. More importantly, the gradient porosity sacrificial layer and mild wet exfoliation system used enable the complete recycling and reuse of the silicon substrate at least five times without subsequent high-temperature repair or re-grinding, significantly reducing overall preparation costs and material consumption, and possessing higher process sustainability and industrial application prospects.

[0061] Through systematic comparative experiments in Examples 1, 2, and Comparative Example 1, the significant technical advantages of this invention in preparing single-crystal silicon nanofilms were fully verified, as detailed below: Precisely adjustable film thickness: In Examples 1 and 2, single-crystal silicon nanofilms with thicknesses of 100 nm and 250 nm were prepared by adjusting the epitaxial deposition time, respectively. The film thickness uniformity was good, and the average deviation at five points was controlled within ±2 nm. This proves that the low-temperature epitaxial growth process used in this invention has good linear controllability and can meet the diverse thickness requirements in the range of 50–300 nm.

[0062] High-quality single-crystal crystallization: In the examples, in-situ hydrogen plasma passivation and Si were introduced. 1-x Ge x The buffer layer stress regulation mechanism results in a high lattice matching degree between the deposited layer and the porous silicon sacrificial layer. The surface roughness Ra of the single-crystal silicon nanofilm measured by AFM is 0.4 nm and 0.45 nm, which is far better than the Ra=2 nm obtained by the comparative Smart Cut method. This significantly improves the crystal integrity and surface smoothness of the single-crystal silicon nanofilm.

[0063] Low-damage, high-integrity peeling: In this example, a gradient porous silicon sacrificial layer and a CTAB / Triton X-100 dual surfactant etching system were used to achieve selective dissolution within 2.5 min. Statistical analysis of multiple images showed that the average peeling integrity reached 96.7% and 95.3%, which was significantly higher than the 70% of the comparative example. No large-area cracks or delamination were observed, effectively reducing the risk of structural damage.

[0064] The substrate is recyclable: In Example 1, the single-crystal silicon substrate was recycled 5 times. The changes in electrochemical etching stability, peeling time and peeling integrity were all less than 3%, which verified that the substrate can be reused ≥5 times without the need for complex cleaning and reconstruction, which greatly reduces material consumption and unit cost; while the comparative donor substrate was scrapped after one peeling.

[0065] Simplified and cost-reduced: Compared with Smart Cut technology, this invention does not involve high-energy injection, long-term high-temperature heat treatment and CMP mechanical polishing. All process temperatures do not exceed 650°C, the overall process is greatly simplified, energy consumption is lower, equipment requirements are more relaxed, and it has higher potential for mass production and cost-effectiveness.

[0066] Flexible substrate compatibility: Example 1 successfully bonded a single-crystal silicon nanofilm to a glass substrate, while Example 2 achieved the bonding of a single-crystal silicon nanofilm to a PI (polyimide) flexible substrate after preheating treatment, demonstrating the excellent adaptability of the process of the present invention to a variety of rigid and flexible substrates, which is convenient for expansion to multiple types of photonic integration platforms.

[0067] The entire process is integrated in a closed loop: from silicon wafer cleaning, conductive coating, sacrificial layer etching, epitaxial growth, wet stripping, transfer bonding, surface passivation to substrate recycling and reuse, this invention forms a complete closed-loop process chain; experimental data show that each step has good stability and compatibility, significantly improving the industrial scale-up potential and environmental friendliness of the overall process.

[0068] In summary, the measured data and process flow in the embodiments effectively confirm the seven beneficial effects proposed by the present invention, highlighting the comprehensive advantages of this method in terms of process control precision, structural integrity, material utilization efficiency and industrialization prospects, and demonstrating significant innovation and practical value.

[0069] It should be particularly noted that the various embodiments listed in this specification and accompanying drawings are intended to illustrate the technical solutions and advantages of the present invention, and not to limit the scope of protection of the present invention. Without departing from the core ideas and technical effects of the present invention, those skilled in the art can make any form of improvement, substitution, combination, or modification to the structural arrangement, process parameters, material selection, control logic, etc., of the described embodiments; any obvious changes based on the same concept should be considered equivalent solutions of the present invention and should be included within the scope of protection defined by the claims of the present invention. The actual scope of protection of the present invention is determined by the appended claims and should be correctly understood in conjunction with the specification and accompanying drawings.

Claims

1. A method for preparing a single-crystalline silicon nanomembrane for nanophotonics, characterized by, The method comprises the following steps: S1. Substrate cleaning: A <100> oriented single crystal silicon substrate is sequentially cleaned in acetone, anhydrous ethanol and deionized water under ultrasonic wave, and then dried by nitrogen blowing; S2. Preparation of porous silicon sacrificial layer: A platinum slurry is uniformly sprayed on the back surface of the substrate, an electrolyte of HF aqueous solution: ethanol = 1 ml: 1 ml is used, B(OH)3 is added to form an etching solution, and a two-stage pulse current etching is applied to form a porous silicon sacrificial layer with a total thickness of 800 nm and a porosity gradient distribution of 30%→60%; S3. In-situ hydrogen plasma passivation: The substrate is turned over and placed in an LPCVD chamber, and is subjected to plasma treatment at 350°C, 100W, and a H2 flow rate of 100sccm for 2min; S4. Low temperature Si 1-x Ge x Epitaxial growth: SiH4, GeH4 and H2 gases are introduced at 600 °C and 10 Torr, with gas flow controlled in the ranges of 10-30 sccm, 0.2-1 sccm and 150-250 sccm, respectively, to sequentially deposit Si 1-x Ge x The stress-adjusting buffer layer and the single-crystal Si functional layer are epitaxially grown to a total thickness of 50-300 nm, and the obtained composite structure constitutes a single-crystal silicon nanomembrane; S5. Surfactant-assisted wet stripping: The back surface of the substrate is immersed in an etching solution of HF:H2O:H2O2:CTAB:Triton X-100 = 1ml:10ml:0.05ml:0.01ml:0.005ml for 2-3min to achieve selective dissolution of the porous silicon sacrificial layer, and the complete single crystal silicon nanomembrane is separated out; S6. Nanomembrane transfer and lamination: The separated single crystal silicon nanomembrane is floated to the surface of the target substrate, and is laminated and air-dried by surface tension; S7. Adhesive removal and surface passivation: When an adhesive is used, it is removed by immersion in acetone, and then sequentially cleaned with acetone, ethanol and deionized water, otherwise the single crystal silicon nanomembrane surface is directly passivated by silane in-situ; S8. Substrate recycling and recycling: The remaining silicon substrate is cleaned and can be repeatedly executed for the next preparation.

2. The method for preparing a single-crystal silicon nanofilm for nanophotonics technology according to claim 1, characterized in that, The two-stage pulse current etching in step S2 is as follows: First stage current density 10 mA / cm 2 2 s on / 1 s off, etch 10 s; Second stage current density 20 mA / cm 2 1 s on / 1 s off, etch 20 s.

3. A method for preparing a single-crystalline silicon nanomembrane for nanophotonics according to claim 1, characterized by, The B(OH)3 concentration in the etching solution of step S2 is 0.01-0.05 M to achieve light boron doping of the porous silicon sacrificial layer.

4. The method for preparing a single-crystal silicon nanofilm for nanophotonics technology according to claim 1, characterized in that, The hydrogen plasma treatment power in step S3 is 80-120 W, the temperature is 300-400°C, and the treatment time is 1-5min.

5. The method of claim 1, wherein the single crystal silicon nanomembrane for nanophotonics is prepared by the steps of: The volume ratio of GeH4 to SiH4 in the step S4 is 1% - 3% to form Si 1-x Ge x Stress regulating buffer layer. ​ 6. The method of claim 1, wherein the single crystal silicon nanomembrane for nanophotonics is prepared by the steps of: The epitaxial deposition time t in step S4 has a linear relationship with the thickness of the single crystal silicon nanomembrane, which can be arbitrarily adjusted within the range of 50-300 nm. ​ 7. The method of claim 1, wherein the single crystal silicon nanomembrane is prepared by a process comprising: The target substrate includes but is not limited to glass, polyimide film or other photonic integrated platform materials. ​ 8. The method of claim 1, wherein the single-crystalline silicon nanomembrane for nanophotonics is prepared by the steps of: After completing step S8, the substrate can be kept clean and recycled for more than five times by simple cleaning and drying. ​

Images