A method for detecting hot spots in photolithography based on edge level positioning

Abstract

The application discloses a photolithography hotspot detection method based on edge level positioning. First, an integrated circuit layout is constructed as a graph structure, wherein each node corresponds to an edge of a polygon in the integrated circuit layout, and the edge corresponds to the connection relationship between the nodes; an edge type is introduced, the edge type includes an adjacent edge, a graphic edge and a space edge; edge features and node features are extracted, a complete graph structure is constructed, and the complete graph structure is input into a pre-trained machine learning model to output a hotspot prediction result of each node. The method discloses discarding the method of rasterizing the layout into an image or cutting into a rectangle, directly using the most basic geometric elements constituting the layout to construct the nodes of the graph, and further realizing high-precision positioning and non-Manhattan layout support, and providing the possibility of accurately mapping hotspots to specific problem edges.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a method for detecting photolithographic hotspots based on edge-level positioning. Background Technology

[0002] Photolithography hotspots refer to specific patterns or areas in the photolithography process of integrated circuits where the actual pattern formed on the wafer differs significantly from the design layout due to a mismatch between the design pattern and the photolithography process. This can potentially lead to decreased circuit yield or reliability issues. As process nodes evolve, the number of patterns increases exponentially, increasing the probability of introducing photolithography hotspots into the design. These hotspots can cause bridging, open circuits, and other problems; therefore, hotspot detection is becoming increasingly important.

[0003] Currently, mainstream hotspot detection schemes mainly fall into three categories: lithography simulation, pattern matching, and machine learning. Lithography simulation methods, by accurately modeling the lithography process, can identify potential hotspots relatively accurately; however, they consume enormous computational resources, especially at advanced process nodes, significantly extending the overall design cycle as design scale rapidly increases. Pattern matching methods rely on known hotspot databases, achieving rapid detection by searching regions in the layout that match the hotspot patterns in the database. While highly efficient, their detection capability is limited by the completeness of existing hotspot databases, and they are insufficient for identifying novel or unknown hotspots. In contrast, machine learning-based methods exhibit unique advantages. For example, some methods construct the hotspot detection task as an object detection problem, introducing the Faster R-CNN model to achieve simultaneous detection and localization of multiple hotspots in large-scale layouts; other works propose a two-stage detection framework, using hotspot location information as an explicit supervision signal in the first stage to guide the model to focus on the local geometry that triggers the hotspot, and then making classification decisions in the second stage. However, these computer vision-based improvements still have significant limitations in achieving accurate hotspot localization: they typically rely on image representations and can only perform coarse-grained hotspot localization using bounding boxes. Limited by the precision loss of raster representation, these methods struggle to accurately map hotspots to specific problem boundaries within the layout, failing to provide the precise geometric information needed for design repair. This becomes a key bottleneck restricting their practical application. Furthermore, these methods are typically limited by fixed input sizes, making it difficult to flexibly adapt to layout areas of different sizes or aspect ratios. Therefore, although vision-based solutions have promoted detection automation to some extent, their large model parameter count and high computational resource consumption remain prominent issues, hindering their efficient deployment at the entire chip level.

[0004] Against this backdrop, graph neural networks (GNNs), with their lighter structure and better fit to the nature of graph topology, are gradually becoming a new direction worth exploring. Summary of the Invention

[0005] The first objective of this invention is to address the shortcomings of existing technologies by providing a lithographic hotspot detection method based on edge-level localization. This method transforms the integrated circuit layout into a graph structure with rich geometric and topological information, and achieves efficient and accurate hotspot detection and localization through this structure, while simultaneously considering detection efficiency, recognition accuracy, and localization accuracy.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A method for detecting lithographic hotspots based on edge-level localization includes the following steps:

[0008] The integrated circuit layout is constructed as a graph structure G=(V,E,R), where V is the set of nodes, each node corresponds to an edge of a polygon in the integrated circuit layout; E is the set of edges, which correspond to the connection relationships between nodes; and R is the set of edge types, including adjacent edges, graphic edges, and spatial edges. An adjacent edge is defined as: two edges that are adjacent to each other in the same polygon; a graphic edge is defined as: two polygon edges that are separated by layout graphic material in space; and a spatial edge is defined as: two polygon edges that are separated by blank areas in space.

[0009] Edge and node features are extracted to construct a complete graph structure, which is then input into a pre-trained machine learning model to output the hotspot prediction results for each node.

[0010] Furthermore, the node features include the geometric length of the polygonal edge, the orientation angle of the polygonal edge in the layout, and the number of all other polygonal edges located within the sampling frame corresponding to that edge.

[0011] Furthermore, a sampling frame is defined with each node as the center. For any target node, other nodes within the sampling frame are checked. If there is layout graphic material between the target node and a node within the frame, the two corresponding nodes are connected using graphic edges; if there is a blank area between them, the two corresponding nodes are connected using spatial edges.

[0012] Furthermore, for adjacent edges, their edge characteristics are determined by the included angle between the two adjacent polygon edges connected by that edge;

[0013] For both graphical and spatial edges, their edge characteristics are represented by a triple f(f1, f2, f3):

[0014] f1 (angle difference): The directional angle difference between the two sides;

[0015] f2 (overlap length): The length of the overlapping portion of the two edges in their projection area;

[0016] f3 (projection distance): the minimum distance between two sides.

[0017] Furthermore, the sampling frame is constructed as follows: it is extended by a distance hB on both sides along the node normal direction, and at the same time, it is extended by a distance hC at both ends along the node tangent direction, where hB and hC are both preset thresholds based on the feature size of the technology node, and the technology node is the process size in integrated circuit manufacturing.

[0018] Furthermore, the machine learning model employs a graph neural network (GNN) model.

[0019] A second objective of this invention is to provide an integrated circuit layout hotspot detection system for implementing the above-described method, comprising:

[0020] The layout construction module constructs the integrated circuit layout as a graph structure, where the nodes of the graph structure are defined as edges of polygons, and the edges of the graph structure are defined as the connection relationships between nodes, including adjacent edges, graphical edges, and spatial edges.

[0021] The hotspot detection module inputs the graph structure into a pre-trained machine learning model and outputs the hotspot prediction result for each node.

[0022] A third object of the present invention is to provide an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above-described method.

[0023] A fourth object of the present invention is to provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method.

[0024] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0025] This invention proposes a novel layout representation method based on fine-grained graph structures, using this as input for machine learning models. This fundamentally solves the problems of information loss, insufficient accuracy, and unclear physical meaning in existing technologies for digitally representing layouts. Specifically, this invention abandons methods that rasterize the layout into images or divide it into rectangles. Instead, it directly uses the most basic geometric elements constituting the layout to construct the graph nodes, thereby achieving high-precision positioning and support for non-Manhattan layouts. It refines the analysis granularity from "region level" (bounding boxes) or "tile level" (rectangles) to "geometric element level" (edges), making it possible to accurately map hotspots to specific problem edges.

[0026] Furthermore, this invention uses graphic edges and spatial edges to characterize the two key geometric information that determine the lithography yield: line width and spacing. Therefore, the model can directly learn the geometric constraints that are strongly related to the causes of hot spots, which greatly improves the accuracy of detection and the ability to predict unknown hot spots. It also has higher learning efficiency and stronger generalization ability. Attached Figure Description

[0027] Figure 1 This is a flowchart of the present invention.

[0028] Figure 2 The diagram shows the graph construction of the layout, where (a) is the layout, (b) is the sampling frame, and (c) is the edge type display result. Detailed Implementation

[0029] The present invention will be further described below with reference to the embodiments.

[0030] like Figure 1 As shown, this invention provides a method for detecting lithographic hotspots based on edge-level localization, comprising the following steps:

[0031] 1. Graphical structure modeling of the map

[0032] This invention models the layout as a graph structure G = (V, E, R), where:

[0033] V is a set of nodes, where each node corresponds to an edge of a polygon in the graph. Unlike existing technologies that divide the graph into rectangles as nodes, this invention directly uses the edges of polygons as the basic units of the graph. This allows the invention to naturally support and represent graphs with non-Manhattan geometry, while laying the foundation for achieving refined hotspot localization.

[0034] E is a set of edges, representing the connections between nodes.

[0035] R is a set of edge types. This invention defines three edge types with explicit physical meanings to accurately describe the geometric layout relationships of the map:

[0036] (1) Adjacent edges: Two edges that are adjacent at the beginning and end in the same polygon. These edges define the outline structure of the polygon itself.

[0037] (2) Graphic edge: Connects two polygonal edges that are spatially separated by the graphic material of the layout. This edge type is used to represent the line width information of the layout. When the line width is too small, it is very easy to cause lithographic hot spots.

[0038] (3) Spatial Edge: Connects two polygonal edges separated by a blank area in space. This edge type is used to represent the spacing information of the map. When the spacing is too small, it is also a major factor leading to the formation of hotspots.

[0039] In the graph structure, the edge types include at least two of the following: adjacent edges, graphical edges, and spatial edges; among them, the construction of graphical edges and spatial edges is a key step in this invention, and the specific method is as follows:

[0040] like Figure 2 As shown, a sampling frame is defined centered on each polygonal edge (i.e., each node) in the layout. The generation of this sampling frame depends on two preset thresholds hB and hC based on the feature size of the technical node: extending a distance hB on both sides along the normal direction of the edge, and extending a distance hC on both ends along the tangent direction of the edge.

[0041] For any target edge, examine other polygon edges within its sampling frame. If there is layout graphic material between the target edge and one side of the frame, connect the corresponding two nodes using a graphic edge; if there is a blank area between them, connect the corresponding two nodes using a spatial edge. In this way, key geometric relationships within a local area are encoded into the graph structure.

[0042] 2. Feature representation of nodes and edges

[0043] To enable effective machine learning, this invention designs feature vectors with clear physical meaning for nodes and edges in the graph.

[0044] Node features are represented using the following three features:

[0045] Length: The geometric length of the edge segment of the polygon.

[0046] Angle: The orientation angle of the polygon's edge in the layout, normalized to the range of 0 to 180 degrees.

[0047] Surrounding edge density: The number of all other polygon edges located within this edge sampling frame. This feature is used to quantify local graphic density to reflect the effect of optical proximity effect.

[0048] Edge features are designed according to different edge types:

[0049] For an adjacent edge, its characteristics are determined by the included angle between the two adjacent polygonal edges that the edge connects to.

[0050] For graph edges and spatial edges, their characteristics are represented by a triple f(f1, f2, f3):

[0051] f1 (angle difference): The directional angle difference between the two sides.

[0052] f2 (overlap length): The length of the overlapping portion of the two edges in their projection area.

[0053] f3 (projection distance): the minimum distance between two sides.

[0054] All length and distance information in the features must be normalized to ensure the stability of model training.

[0055] 3. Input the graph structure containing nodes, edges, edge types, node features, and edge features into the graph neural network (GNN) model to obtain the hotspot prediction results.

[0056] The above embodiments are not intended to limit the present invention, and the present invention is not limited to the above embodiments. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, all technical solutions obtained by equivalent substitution or equivalent transformation fall within the protection scope of the present invention.

Claims

1. A method for detecting lithographic hotspots based on edge-level localization, characterized in that, Includes the following steps: The integrated circuit layout is constructed as a graph structure G=(V,E,R), where V is the set of nodes, each node corresponding to an edge of a polygon in the integrated circuit layout; E is the set of edges, which correspond to the connection relationships between nodes; and R is the set of edge types, including adjacent edges, graphic edges, and spatial edges. An adjacent edge is defined as connecting two edges that are adjacent to each other in the same polygon; a graphic edge is defined as connecting two polygon edges that are spatially separated by the layout graphic material; and a spatial edge is defined as connecting two polygon edges that are spatially separated by a blank area. For adjacent edges, their characteristics are determined by the included angle between the two adjacent polygon edges that the edge connects to. For both graphical and spatial edges, their edge characteristics are represented by a triple f(f1, f2, f3): f1 is defined as the angle difference, which is the difference in direction angle between two sides; f2 is defined as the overlap length, which is the length of the overlapping part of two sides in their projection area; f3 is defined as the projection distance, which is the minimum distance between two sides. Edge features and node features are extracted to construct a complete graph structure, which is then input into a pre-trained machine learning model to output the hotspot prediction results for each node; the machine learning model adopts a graph neural network (GNN) model.

2. The lithographic hotspot detection method based on edge-level positioning according to claim 1, characterized in that, The node features include the geometric length of the polygonal edge, the orientation angle of the polygonal edge in the layout, and the number of all other polygonal edges located within the sampling frame corresponding to that edge.

3. The lithographic hotspot detection method based on edge-level positioning according to claim 1, characterized in that, Define a sampling frame centered on each node. For any target node, check other nodes within the sampling frame. If there is layout graphic material between the target node and a node within the frame, connect the two nodes using graphic edges; otherwise, connect the two nodes using spatial edges.

4. The lithographic hotspot detection method based on edge-level positioning according to claim 3, characterized in that, In a graph structure, edge types include at least two of the following: adjacent edges, graph edges, and spatial edges.

5. The lithographic hotspot detection method based on edge-level positioning according to claim 1, characterized in that, The sampling frame is constructed by extending a distance hB on both sides along the node normal direction and extending a distance hC on both ends along the node tangent direction, where hB and hC are preset thresholds based on the feature size of the technical node.

6. An integrated circuit layout hotspot detection system implementing the method as described in any one of claims 1-5, characterized in that, include: The layout construction module constructs the integrated circuit layout as a graph structure, where the nodes of the graph structure are defined as edges of polygons, and the edges of the graph structure are defined as the connection relationships between nodes, including adjacent edges, graphical edges, and spatial edges. The hotspot detection module inputs the graph structure into a pre-trained machine learning model and outputs the hotspot prediction result for each node.

7. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the method as described in any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, It stores a computer program thereon, which, when executed by a processor, implements the steps of the method as described in any one of claims 1-5.

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