Hot plug test device and test method

Abstract

The invention provides a hot plug test device and a test method, and relates to the technical field of computers, in particular to the technical field of vehicle-mounted equipment test. The hot plug test device comprises a control module used for acquiring a command of a test mode and generating a corresponding test signal according to the command of the test mode; wherein the test mode comprises at least one of the following modes: a power supply transient interruption mode, a reset transient interruption mode, a bus transient interruption mode and a complete separation mode; and the link transient interruption injection module is electrically connected with the control module and is used for controlling the on-off of the PCIe RP node and / or the PCIe EP node of the device to be tested according to the test signal.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and more particularly to the field of vehicle-mounted equipment testing technology, specifically to a hot-swap testing device and testing method. Background Technology

[0002] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard. It features high-speed, point-to-point, dual-channel, high-bandwidth transmission and supports hot-plugging. PCIe hot-plugging allows for the safe insertion or removal of PCIe devices while the system is running without powering off. In related technologies, testing the PCIe hot-plugging functionality is typically required. Summary of the Invention

[0003] This disclosure provides a hot-plug testing device and testing method.

[0004] According to one aspect of this disclosure, a hot-plug testing apparatus is provided, comprising: a control module, configured to acquire a command for a test mode and generate a corresponding test signal according to the command for the test mode; wherein the test mode includes at least one of the following: a power interruption mode, a reset interruption mode, a bus interruption mode, and a complete disconnection mode; and a link interruption injection module, electrically connected to the control module, configured to control the on / off state of the PCIe RP node and / or PCIe EP node of the device under test according to the test signal.

[0005] In some embodiments, the control module is used to send corresponding test signals to at least two links of the link interruption injection module; the test signals correspond to at least two of the power interruption mode, reset interruption mode, and bus interruption mode, and the number of test mode types corresponding to the test signals is the same as the number of links in the link interruption injection module that receive the test signals.

[0006] In some embodiments, the link interruption injection module includes: a first link, a second link, and a third link, wherein the first link, the second link, and the third link are electrically connected to the control module; wherein, the first link is used to control the PCIe EP of the device under test to interrupt the power signal according to the test signal corresponding to the power interruption mode; the second link is used to control the PCIe EP of the device under test to interrupt the reset signal according to the test signal corresponding to the reset interruption mode; and the third link is used to control the PCIe RP node and / or the PCIe EP node to interrupt the bus signal according to the test signal corresponding to the bus interruption mode.

[0007] In some embodiments, the link interruption injection module further includes: a first connector electrically connected to the PCIe RP node of the device under test and electrically connected to the third link; and a second connector electrically connected to the PCIe EP node of the device under test and electrically connected to the first link, the second link, and the third link, respectively.

[0008] In some embodiments, the first link includes a first digital switch; the second link includes a second digital switch.

[0009] In some embodiments, the third link includes a high-speed I / O switch chip, which is electrically connected to the first connector via a first transmit signal line and a first receive signal line, and electrically connected to the second connector via a second transmit signal line and a second receive signal line.

[0010] In some embodiments, the control module includes a CAN transceiver and a USRT serial communication submodule, so as to communicate with the host computer through one of the CAN transceiver and the USRT serial communication submodule.

[0011] In some embodiments, the control module includes an MCU.

[0012] In some embodiments, the hot-plug test apparatus includes multiple link interruption injection modules, which are used to connect to multiple devices under test.

[0013] In some embodiments, the hot-plug testing device includes multiple control modules, each of which is connected to a multiple link transient injection module.

[0014] In some embodiments, the hot-plug testing device further includes: a PCIe switch, the upstream port of the PCIe switch being connected to the control module, the PCIe switch having multiple downstream ports, and the multiple downstream ports being respectively connected to multiple link interruption injection modules.

[0015] According to another aspect of this disclosure, a hot-plug testing method based on the hot-plug testing device described in any of the foregoing claims is provided, comprising: acquiring a command for a test mode through a control module, and generating a corresponding test signal according to the command for the test mode; wherein the test mode includes at least one of the following: power interruption mode, reset interruption mode, bus interruption mode, and complete disconnection mode; and controlling the on / off state of the PCIe RP node and / or PCIe EP node of the device under test according to the test signal through a link interruption injection module.

[0016] In some embodiments, the link transient interruption injection module includes: a first link, a second link, and a third link; the step of controlling the on / off state of the PCIe RP node and / or PCIe EP node of the device under test according to the test signal via the link transient interruption injection module includes at least one of the following: controlling the PCIe EP node of the device under test to transiently interrupt the power signal according to the test signal corresponding to the power transient interruption mode via the first link; controlling the PCIe EP node of the device under test to transiently interrupt the reset signal according to the test signal corresponding to the reset transient interruption mode via the second link; and controlling the PCIe RP node and / or PCIe EP node to transiently interrupt the bus signal according to the test signal corresponding to the bus transient interruption mode via the third link.

[0017] The hot-plug testing device provided in this embodiment can automatically test the signal interruption of PCIe devices and can realize multiple test modes to cover one or more scenarios where the signal interruption occurs, thus achieving both high hot-plug testing efficiency and high test coverage.

[0018] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0019] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein: Figure 1 This is a schematic diagram of the structure of a hot-plug testing apparatus according to an embodiment of the present disclosure; Figure 2 This is an application scenario diagram of a hot-plug testing apparatus according to an embodiment of the present disclosure; Figure 3 This is an application scenario diagram of a hot-plug testing apparatus according to another embodiment of the present disclosure; Figure 4 This is an application scenario diagram of a hot-plug testing apparatus according to yet another embodiment of the present disclosure; Figure 5 This is a schematic diagram of the structure of a hot-plug testing apparatus according to another embodiment of the present disclosure; Figure 6 This is a schematic flowchart of a hot-plug testing method according to an embodiment of the present disclosure.

[0020] Reference numerals: 110-Control module; 111-MCU; 112-CAN transceiver; 120-Link interruption injection module; 121-First digital switch; 122-Second digital switch; 123-High-speed I / O switch chip; 124-First connector; 125-Second connector; 210-PCIe RP node; 220-PCIe EP node; 300-Host computer. Detailed Implementation

[0021] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0022] With the development of automotive intelligence, more and more in-vehicle devices support high-speed signal transmission based on PCIe. For example, in-vehicle ECUs (Electronic Control Units) communicate with other devices via the PCIe bus and use hot-swappable technology. However, during vehicle operation, due to the vehicle's own structure and road conditions, in-vehicle devices often face complex vibration scenarios, which can affect the connection between the PCIe bus and its corresponding PCIe interfaces, thus affecting signal transmission. In related technologies, manual plugging and unplugging is commonly used to verify the usability and reliability of hot-swappable designs for in-vehicle devices. However, manual plugging and unplugging suffers from low testing efficiency and incomplete test coverage, such as difficulty in reproducing transient anomalies under vibration conditions.

[0023] This embodiment provides a hot-swap testing device that can automatically test the signal interruption of PCIe-supporting devices, improve the efficiency of hot-swap testing, and realize multiple test modes to cover scenarios where one or more signals of the device are interrupted due to vibration.

[0024] The structure, function, and implementation process of the hot-plug testing device in this embodiment will be illustrated below with reference to the accompanying drawings.

[0025] The hot-plug testing device provided in this embodiment can be connected in series with the PCIe bus of an in-vehicle device to simulate hot-plug control of the PCIe bus. It is understood that the application scenarios of the hot-plug testing device in this embodiment are not limited to in-vehicle devices, but can also be applied to other PCIe-enabled electronic devices. For ease of description, devices supporting PCIe will be referred to as PCIe devices below.

[0026] Please refer to Figure 1The hot-plug testing device provided in this embodiment includes a control module 110 and a link transient injection module 120. The control module 110 and the link transient injection module 120 are electrically connected. The control module 110 and the link transient injection module 120 can be integrated or set up independently.

[0027] Please refer to Figure 2 The control module 110 is connected to the host computer 300 for communication. It is used to obtain test mode commands from the host computer 300, parse the obtained commands, set the test cycle, and generate corresponding test signals to send to the corresponding links of the link interruption injection module 120.

[0028] The test modes include at least one of the following: power interruption mode, reset interruption mode, bus interruption mode, and complete disconnection mode. The above-mentioned interruption mode can be understood as: a controllable and brief interruption of the system signal for a very short time (e.g., microseconds to milliseconds) to simulate occasional faults in real vibration scenarios, thereby verifying the recovery capability of PCIe devices under abnormal conditions.

[0029] In power interruption mode, this embodiment can simulate a transient interruption of the power signal of a PCIe device. In reset interruption mode, this embodiment can simulate a transient interruption of the reset (PCIe_Reset) signal of a PCIe device. In bus interruption mode, this embodiment can simulate a transient interruption of the data transmission signals (e.g., signal pairs TX / RX) of a PCIe device. In fully disconnected mode, this embodiment can simulate transient interruptions of the power signal, reset signal, and data transmission signals of a PCIe device.

[0030] The link interruption injection module 120 is electrically connected to the control module 110 via the control bus. It is used to control the on / off state of the PCIe RP (Root Port) node 210 and / or PCIe EP (Endpoint) node 220 of the device under test according to the test signal, so as to realize hot-plug simulation test.

[0031] In this context, the PCIe RP node 210 is the starting point of the PCIe topology (located at the top layer of the PCIe topology). It is typically integrated into the CPU, chipset, or PCIe switch, or connected to the switch via a bus or directly to the PCIe EP node 220. It is used to initiate bus enumeration, configure, and manage downstream devices. A typical PCIe topology includes the PCIe RP node 210, which is directly or indirectly connected to at least one PCIe EP node 220 via the PCIe bus.

[0032] PCIe EP node 220 is a terminal device (such as a graphics card, solid-state drive, or network card) in the PCIe topology. It is located at the top and bottom layers of the PCIe topology and only receives or sends data through the PCIe bus to perform specific functions (such as data transmission and calculation).

[0033] For example, the link interruption injection module 120 can control the instantaneous drop or interruption of the power supply voltage of the PCIe EP node 220 according to the test signal corresponding to the power interruption mode, so as to detect the recovery capability of the PCIe EP node 220 after the power interruption, such as whether it can save key data at the moment of power failure, whether it can be initialized normally after the voltage is restored, and the initialization time.

[0034] The link interruption injection module 120 can pull the level of the reset pin of the PCIe EP node 220 low according to the test signal corresponding to the reset interruption mode, so as to detect the recovery capability of the PCIe EP node 220 after the reset interruption, such as whether the link can be rebuilt and data transmission resumed after an unexpected reset, and the reset duration.

[0035] The link interruption injection module 120 can disconnect at least one of the PCIe EP node 220 and PCIe RP node 210 from the PCIe bus according to the test signal corresponding to the bus interruption mode, so as to detect the recovery capability of the above nodes after the bus interruption, such as detecting whether the above nodes can renegotiate the speed and width after the link is restored.

[0036] The hot-plug testing apparatus of this embodiment is used in scenarios where PCIe EP node 220 is tested. PCIe RP node 210 can obtain relevant information about PCIe EP node 220 and obtain evaluation results. For example, in one test mode, during the process of PCIe EP node 220 disconnecting and reconnecting and initializing, PCIe RP node 210 will obtain relevant information. If it is determined that PCIe EP node 220 has successfully completed initialization based on the obtained information, then PCIe EP node 220 is confirmed to have passed the test; otherwise, PCIe EP node 220 is determined to have failed the test.

[0037] In the scenario of testing PCIe RP node 210, PCIe RP node 210 can obtain information such as link rate, channel width and PCIe EP node 220 status after link recovery, and determine whether PCIe RP node 210 has passed the test based on the above information. For example, if the information obtained after link recovery is consistent with the information before link disconnection, the test is confirmed to have passed.

[0038] The hot-plug testing device provided in this embodiment, by setting up a control module 110 and a link interruption injection module 120, allows the control module 110 to acquire test mode commands and generate corresponding test signals according to the test mode commands, which are then sent to the link interruption injection module 120. The link interruption injection module 120 controls the on / off state of the PCIe RP (Root Port) node and / or PCIe EP (Endpoint) node of the device under test according to the test signals, thereby realizing at least one of the following test modes: power interruption mode, reset interruption mode, bus interruption mode, and complete disconnection mode. Through the above settings, this embodiment can automatically test the signal interruption conditions of PCIe devices and can realize multiple test modes, covering scenarios where one or more signals experience interruptions, thus achieving both high hot-plug testing efficiency and high test coverage.

[0039] In some embodiments, the link interruption injection module 120 includes multiple links; wherein at least two links correspond to different test signal types. For example, the control module 110 is configured to send corresponding test signals to at least two links of the link interruption injection module 120. The test signals correspond to at least two of the following: power interruption mode, reset interruption mode, and bus interruption mode. The number of test mode types corresponding to the test signals is the same as the number of links in the link interruption injection module 120 receiving test signals.

[0040] For example, if a momentary drop or interruption in the power supply voltage of PCIe EP node 220 occurs simultaneously with a low level pull-down of the reset pin of PCIe EP node 220, then control module 110 can send a test signal corresponding to the power interruption mode to one link of link interruption injection module 120 and a test signal corresponding to the reset interruption mode to the other link.

[0041] For example, if a momentary drop or interruption in the power supply voltage of PCIe EP node 220 occurs simultaneously with the disconnection of at least one of PCIe EP node 220 and PCIe RP node 210 from the PCIe bus, then control module 110 can send a test signal corresponding to the power interruption mode to one link of link interruption injection module 120 and a test signal corresponding to the bus interruption mode to the other link.

[0042] This embodiment, through the above settings, facilitates flexible combination testing of test modes, covering various scenarios where signals experience transient interruptions, thereby improving test coverage.

[0043] In some embodiments, the link interruption injection module 120 includes a first link, a second link, and a third link. The first link, the second link, and the third link are connected in parallel. The first link, the second link, and the third link are electrically connected to the control module 110.

[0044] The first link is used to control the PCIe EP of the device under test to momentarily disconnect the power signal according to the test signal corresponding to the power interruption mode. The second link is used to control the PCIe EP of the device under test to momentarily disconnect the reset signal according to the test signal corresponding to the reset interruption mode.

[0045] Please refer to Figure 3 In some examples, the first link includes a first digital switch 121. The second link includes a second digital switch 122. The first digital switch 121 and the second digital switch 122 support switching speeds at the microsecond or even nanosecond level, respectively, which can meet the timing requirements of transient interruptions, facilitating precise control and rapid response. Moreover, the first digital switch 121 and the second digital switch 122 can be directly controlled by the control module 110 without the need for external drive circuits, which simplifies the circuit design of the hot-swap test device. In addition, the first digital switch 121 and the second digital switch 122 also have low on-resistance, controllable self-heating, and no mechanical contacts, making them suitable for high-frequency testing.

[0046] In other examples, at least one of the first link and the second link may also include a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) or a solid-state relay, as long as it can meet the control requirements for power interruption or reset interruption.

[0047] The third link is used to control the PCIe RP node 210 and / or PCIe EP node 220 to interrupt the bus signal according to the test signal corresponding to the bus interruption mode.

[0048] In some examples, the high-speed I / O switch chip 123 is electrically connected to the first connector 124 via a first transmit signal line and a first receive signal line, and is electrically connected to the second connector 125 via a second transmit signal line and a second receive signal line. The first and second transmit signal lines are used to receive transient interruption commands corresponding to the injected test signal; the first and second receive signal lines can be used to acquire response signals.

[0049] In this example, the high-speed I / O switch chip 123 has low insertion loss, which helps ensure signal integrity, and low latency, which can meet the instantaneous interruption requirement. In addition, the use of separate transmission and reception paths can improve anti-interference capability, and the high-speed I / O switch chip 123 can independently control the on / off state of the transmission and reception paths, thereby simulating a failure scenario in either the transmission or reception path, improving the flexibility and coverage of the test.

[0050] In other embodiments, the third link may also include an optocoupler switch, etc., as long as it can meet the control requirements for the momentary interruption of the PCIe bus.

[0051] In the power interruption mode, the control signal sends the test signal corresponding to the power interruption mode to the first link, so as to control the momentary drop or interruption of the power supply voltage of the PCIe EP node 220 through the first link.

[0052] In reset interrupt mode, the control signal sends the test signal corresponding to the reset interrupt mode to the second link, so as to pull the level of the reset pin of PCIe EP node 220 low through the second link.

[0053] In the bus interruption mode, the control signal sends the test signal corresponding to the bus interruption mode to the third link to disconnect at least one of the PCIe EP node 220 and PCIe RP node 210 from the PCIe bus via the third link.

[0054] Optionally, the control module 110 is used to send corresponding test signals to at least two of the first link, the second link, and the third link. For example, the control module 110 is used to send corresponding test signals to the first link and the second link, or the control module 110 is used to send corresponding test signals to the first link and the third link, or the control module 110 is used to send corresponding test signals to the first link, the second link, and the third link, or the control module 110 is used to send corresponding test signals to one of the first link, the second link, and the third link. Of course, the control module 110 can also send corresponding test signals to one of the first link, the second link, and the third link.

[0055] This embodiment sets up one-to-one links for the test signals corresponding to the power interruption mode, the reset interruption mode, and the bus interruption mode, which can avoid cross-interference, reliably and flexibly combine test modes, cover multiple scenarios of signal interruption, and improve test flexibility and test coverage.

[0056] In some embodiments, the link interruption injection module 120 further includes: a first connector 124 electrically connected to the PCIe RP node 210 of the device under test via a PCIe bus and electrically connected to the third link; and a second connector 125 electrically connected to the PCIe EP node 220 of the device under test via a PCIe bus and electrically connected to the first link, the second link and the third link respectively.

[0057] Optionally, the first connector 124 and the second connector 125 may have high-frequency connectors, such as connectors that support transmission rates of 32GT / s and above.

[0058] In this embodiment, the first connector 124 and the second connector 125 are compatible with a wide variety of PCIe devices, making the hot-swap test device highly flexible and facilitating the rapid replacement of the PCIe device to be tested.

[0059] In other embodiments, the first link, the second link, and the third link may also be directly connected to the PCIe device under test.

[0060] Please refer to Figure 4 In some embodiments, the control module 110 includes a CAN transceiver 112 and a USRT serial communication submodule, which communicate with the host computer 300 via either the CAN transceiver 112 or the USRT serial communication submodule. Depending on the actual situation of the host computer 300, when the host computer 300 supports CAN transmission, the control module 110 communicates with the host computer 300 via the CAN transceiver 112; when the host computer 300 supports USRT transmission, the control module 110 communicates with the host computer 300 via the USRT serial communication submodule. Thus, this embodiment can adapt to various hardware environments and has high flexibility; furthermore, the dual communication channels can serve as backups for each other.

[0061] Please refer to Figure 4 In some embodiments, the control module 110 includes an MCU 111. The MCU 111 supports online upgrades, expands its functions without hardware modifications, enables parallel task processing, improves response efficiency, meets the combined testing requirements of various transient interruption modes, and has fault self-diagnosis and recovery functions to ensure operational reliability.

[0062] Please refer to Figure 5 In some embodiments, the hot-plug test apparatus includes multiple link interruption injection modules 120, which are used to connect to multiple PCIe devices under test. Each link interruption injection module 120 corresponds one-to-one with a PCIe device under test, enabling simultaneous synchronous or independent testing of multiple PCIe devices.

[0063] In some examples, the hot-plug test apparatus includes multiple control modules 110, each corresponding to a link interruption injection module 120. When testing at least two PCIe devices, at least two control modules 110 can be configured, each connected to the PCIe RP node 210 and / or PCIe EP node 220 of the PCIe device via its corresponding link interruption injection module 120. The number of control modules 110 is greater than or equal to the number of PCIe devices under test. At least two control modules 110 can communicate with the same host computer 300, or at least two control modules 110 can communicate with different host computers 300.

[0064] In other words, when the hot-swap test device is applied to a multi-PCIe device testing scenario, the hot-swap test device can include multiple test branches, which can be connected in parallel and communicate with the same host computer 300; wherein, the test branch includes a control module 110 and a link interruption injection module 120.

[0065] For example, if the current test scenario requires testing two PCIe devices simultaneously, the hot-swap test device may include two control modules 110. The two control modules 110 are respectively connected to the host computer 300, and the two control modules 110 are respectively connected to independent link interruption injection modules 120. The two link interruption injection modules 120 are respectively connected to the test nodes of the two PCIe devices.

[0066] In this example, each test branch operates independently, which can trigger transient tests of different devices simultaneously, and helps to reduce signal attenuation and interference risks. A single branch failure will not affect the testing of other devices.

[0067] In other examples, the hot-plug test apparatus further includes a PCIe switch, which acts as an expansion device, providing multiple downstream ports to connect to the PCIe device under test, facilitating the testing of multiple PCIe devices. For example, the upstream port of the PCIe is connected to the control module 110, and the PCIe has multiple downstream ports, each connected to multiple link transient injection modules 120. This example enables the expansion of ports at a low cost, allowing for synchronous or independent testing of multiple PCIe devices.

[0068] This embodiment is applicable to testing scenarios involving multiple PCIe devices, enabling synchronous or independent testing of multiple PCIe devices, which helps improve testing efficiency.

[0069] In other embodiments, the PCIe switch can also be connected between the link and connector of the link transient injection module 120 to facilitate synchronous testing of multiple PCIe devices.

[0070] When using the hot-plug testing device provided in this embodiment, if the MCU receives a power interruption mode command from the host computer, the MCU controls the first digital switch to turn on and off with a period of T1. If the MCU receives a reset interruption mode command from the host computer, the MCU controls the second digital switch to turn on and off with a period of T2. If the MCU receives a bus interruption mode command from the host computer, the MCU controls the high-speed I / O switch chip to turn on and off with a period of T3. If the MCU receives a complete disconnection mode command from the host computer, the MCU controls the first digital switch to turn on and off with a period of T1, controls the second digital switch to turn on and off with a period of T2, and controls the high-speed I / O switch chip to turn on and off with a period of T3. T1, T2, and T3 can be set according to actual needs; they can be the same or different.

[0071] During the testing phase, relevant information about the PCIe device, such as information that characterizes its recovery capability, can also be sent to the MCU via the corresponding link, and then sent from the MCU to the host computer.

[0072] After the test is completed, the MCU can send feedback information to the host computer to indicate that the test is complete; in addition, the feedback information may also include test results and other information.

[0073] It is understood that the parts of the above embodiments that do not describe the hot-plug testing device can be achieved using various technical solutions that are now and will be known to those skilled in the art, and will not be described in detail here.

[0074] This embodiment also provides a hot-plug testing method, implemented based on the hot-plug testing device in any of the foregoing embodiments. The similarities to the foregoing embodiments will not be repeated here.

[0075] Please refer to Figure 6 The hot-plug testing method in this embodiment includes: Step S610: Obtain the test mode command through the control module, and generate the corresponding test signal according to the test mode command; wherein, the test mode includes at least one of the following: power interruption mode, reset interruption mode, bus interruption mode, and complete disconnection mode; Step S620: Control the on / off state of the PCIe RP node and / or PCIe EP node of the device under test according to the test signal through the link transient interruption injection module.

[0076] In some embodiments, the link transient injection module includes: a first link, a second link, and a third link. The link transient injection module controls the on / off state of the PCIe RP node and / or PCIe EP node of the device under test according to the test signal, including at least one of the following: The first link controls the PCIe EP node of the device under test to momentarily disconnect the power signal according to the test signal corresponding to the power interruption mode. The second link controls the PCIe EP node of the device under test to momentarily disconnect the reset signal according to the test signal corresponding to the reset momentary disconnection mode. The third link controls the PCIe RP node and / or PCIe EP node to momentarily disconnect the bus signal according to the test signal corresponding to the bus interruption mode.

[0077] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0078] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0079] In this disclosure, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0080] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this disclosure. To simplify the disclosure, the components and arrangements of specific examples have been described above. Of course, these are merely examples and are not intended to limit the scope of this disclosure.

[0081] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A hot plug test device, comprising: a control module configured to obtain a test mode command and generate a corresponding test signal according to the test mode command; wherein the test mode comprises at least one of a power transient mode, a reset transient mode, a bus transient mode, and a complete disconnection mode; a link transient injection module electrically connected to the control module and configured to control the on-off of a PCIe RP node and / or a PCIe EP node of a device under test according to the test signal.

2. The hot plug testing device of claim 1, wherein, The control module is configured to send corresponding test signals to at least two links of the link transient injection module. The test signal corresponds to at least two of the power transient mode, the reset transient mode, and the bus transient mode, and the number of test mode types corresponding to the test signal is the same as the number of links in the link transient injection module that receive the test signal.

3. The hot plug testing device of claim 1, wherein, The link transient injection module comprises: a first link, a second link, and a third link, which are electrically connected to the control module; wherein the first link is configured to control the power signal transient of the PCIe EP of the device under test according to the test signal corresponding to the power transient mode; the second link is configured to control the reset signal transient of the PCIe EP of the device under test according to the test signal corresponding to the reset transient mode; and the third link is configured to control the bus signal transient of the PCIe RP node and / or the PCIe EP node according to the test signal corresponding to the bus transient mode.

4. The hot plug testing device of claim 3, wherein, The link transient injection module further comprises: a first connector electrically connected to the PCIe RP node of the device under test and electrically connected to the third link; a second connector electrically connected to the PCIe EP node of the device under test and electrically connected to the first link, the second link, and the third link.

5. The hot plug testing device of claim 3, wherein, The first link comprises a first digital switch; the second link comprises a second digital switch.

6. The hot plug test device of claim 4, wherein, The third link comprises a high-speed IO switch chip, which is electrically connected to the first connector through a first transmission signal line and a first reception signal line, and is electrically connected to the second connector through a second transmission signal line and a second reception signal line.

7. The hot-plug test device of claim 1, wherein, The control module comprises a CAN transceiver and a USRT serial communication submodule, so as to be connected to an upper computer through one of the CAN transceiver and the USRT serial communication submodule. And / or, the control module comprises an MCU.

8. The hot-plug test device of claim 1, wherein, The hot plug test device comprises a plurality of link transient injection modules, and the plurality of link transient injection modules are configured to be connected to a plurality of devices under test.

9. The hot-plug test device of claim 8, wherein, The hot plug test device comprises a plurality of control modules, and the plurality of control modules are connected to the plurality of link transient injection modules.

10. The hot-plug test apparatus of claim 8, wherein, The hot plug test device further comprises: a PCIe switch, an upstream port of the PCIe switch is connected to the control module, and a plurality of downstream ports of the PCIe switch are connected to the plurality of link transient injection modules.

11. A hot plug test method based on the hot plug test device of any one of claims 1 to 10, comprising: obtaining a test mode command by the control module, and generating a corresponding test signal according to the test mode command; wherein the test mode comprises at least one of: a power transient mode, a reset transient mode, a bus transient mode, and a complete disconnection mode; controlling the on-off of the PCIe RP node and / or the PCIe EP node of the device under test by the link transient injection module according to the test signal.

12. The hot plug testing method of claim 11, wherein, The link transient injection module comprises: a first link, a second link, and a third link. The controlling the on-off of the PCIe RP node and / or the PCIe EP node of the device under test by the link transient injection module according to the test signal comprises at least one of: controlling the PCIe EP node of the device under test to perform power signal transient according to the test signal corresponding to the power transient mode through the first link; controlling the PCIe EP node of the device under test to perform reset signal transient according to the test signal corresponding to the reset transient mode through the second link; controlling the PCIe RP node and / or the PCIe EP node to perform bus signal transient according to the test signal corresponding to the bus transient mode through the third link.

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