Reconfigurable Ising machine based on FeFET construction, chip

Abstract

The application relates to the technical field of integrated circuit design, and discloses a reconfigurable Ising device and a chip based on FeFET construction. The application provides a reconfigurable Ising device, which comprises a calculation array part and a spin updating part. The calculation array part comprises N columns of Ising calculation columns based on FeFET construction, supports flexible setting of mutual relationships between different spins, and can realize mapping of a complex irregular spin network; the architecture of the application supports simultaneous calculation of multiple spin interaction relationships, and directly compares voltages to obtain spin results, thereby reducing timing overhead and additional hardware overhead of setting adders; according to the Ising model, the array is built based on FeFET, hardware overhead can be further reduced, and related coefficients can be long-term stored and read-write consumption can be reduced due to the non-volatility of FeFET.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, more particularly, it relates to: 1. A reconfigurable Ising machine based on FeFET; 2. A CIM chip designed based on the reconfigurable Ising machine. BACKGROUND

[0002] Ising machine is a new type of computing architecture based on Ising model, which can gradually converge the system energy to the ground state through simulating spin interaction and annealing process, and thus obtain the optimized solution, providing a new way for quickly solving combinatorial optimization problems and quadratic unconstrained binary optimization (QUBO) problems.

[0003] Ising machine can be divided into two categories according to the hardware topology structure. One is the locally connected Ising machine, which can be easily expanded through chip-to-chip interconnection, but it lacks flexibility to embed more extensive combinatorial optimization problems (COP). The other is the fully connected Ising machine, which can map any COP, but it has significant hardware overhead in spin interconnection and coefficient memory, making it difficult to expand. SUMMARY

[0004] Therefore, it is necessary to provide a reconfigurable Ising machine based on FeFET and a chip in view of the problems of existing Ising machine unbalanced COP mapping and hardware overhead.

[0005] The present application adopts the following technical solutions:

[0006] In a first aspect, the present application provides a reconfigurable Ising machine based on FeFET, comprising: a computing array part, a spin update part.

[0007] The computing array part comprises: N columns of Ising computing columns based on FeFET; N> = 2.

[0008] n∈[1,N]; the nth column of Ising computing column comprises: 1 spin storage unit, 7 coefficient storage units, 1 XNOR unit, 1 voltage generation unit.

[0009] The spin storage unit is used to store 1bit spin state; the 7 coefficient storage units are connected with the spin storage unit in the same column, and are used to store 7bit data bits of 8bit related coefficients and output a single-column shared voltage Vcm representing a signed accumulation result based on charge sharing during spin calculation; the XNOR unit is connected with the 7 coefficient storage units in the same column, and is used to store 1bit sign bit of 8bit related coefficients and perform XNOR operation during spin calculation to selectively discharge the 7 coefficient storage units in the same column. The voltage generation unit is used to provide a single-column reference voltage Vref during spin calculation.

[0010] Wherein, in each round of spin calculation, the M-column Ising calculation column related to the target spin storage unit works, and the Vcm of the M-column is charge-shared to form the total shared voltage VCM representing the effective field of the spin, and the Vref of the M-column is charge-shared to form the total reference voltage VREF representing 0; M≤N.

[0011] The spin updating unit is configured to compare VCM and VREF to obtain a new spin state, and update the new spin state to the target spin storage unit.

[0012] The implementation of the reconfigurable Ising machine based on FeFET is according to the method or process of the embodiment of the present disclosure.

[0013] In the second aspect, the present disclosure discloses a CIM chip adopting the circuit layout of the reconfigurable Ising machine based on FeFET as disclosed in the first aspect.

[0014] The implementation of the CIM chip is according to the method or process of the embodiment of the present disclosure.

[0015] Compared with the prior art, the present disclosure has the following beneficial effects:

[0016] The present disclosure provides a reconfigurable Ising machine, the calculation array unit of which comprises N columns of Ising calculation columns based on FeFET, supports flexible setting of the mutual relationship between different spins, and can realize mapping of a complex irregular spin network; the architecture of the present disclosure supports simultaneous calculation of multiple spin interaction relationships, and directly compares voltages to obtain spin results, thereby reducing timing overhead and additional hardware overhead of setting adders; the present disclosure builds an array based on FeFET according to the Ising model, which can further reduce hardware overhead, and benefits from the non-volatility of FeFET, which can save relevant coefficients for a long time and reduce read-write consumption. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0018] Figure 1 The architecture diagram of the reconfigurable Ising machine based on FeFET provided for Embodiment 1 of the present disclosure;

[0019] Figure 2 The circuit diagram of the spin storage unit in the present disclosure; Figure 1

[0020] Figure 3 The circuit diagram of the spin storage unit in the present disclosure; Figure 1 ​Circuit diagram of the coefficient storage unit;

[0021] Figure 4 For Figure 1 Circuit diagram of the coefficient storage unit;

[0022] Figure 5 For Figure 1 Circuit diagram of the coefficient storage unit;

[0023] Figure 6 For Figure 1 Circuit diagram of the coefficient storage unit. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0025] It should be noted that when a component is referred to as being "mounted on" another component, it can be directly on the other component or there can be a middle component. When a component is referred to as being "disposed on" another component, it can be directly disposed on the other component or there can be a middle component. When a component is referred to as being "fixed on" another component, it can be directly fixed on the other component or there can be a middle component.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing the specific embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0027] First of all, it should be noted that the reconfigurable Ising device designed in the present application is designed according to the Ising model. The Hamiltonian of the Ising model is mapped according to the circuit structure (designed according to the formula of the Ising model) to spontaneously solve the combinatorial optimization problem, and the spin is flipped, and the iterative calculation is continuously carried out, so as to reach the state of minimum system energy.

[0028] Specifically, for the Ising model, the overall Hamiltonian is represented as:

[0029] ;

[0030] In the formula, H σ represents the overall Hamiltonian of the Ising model;σ i denotes the spin value at the i th lattice point; σ j denotes the spin value at the j th lattice point; J i,j denotes the coupling strength between the spin at the i th lattice point and the spin at the j th lattice point; h i denotes the external magnetic field strength at the i th lattice point.

[0031] Then, the Hamiltonian corresponding to the i th spin is represented as:

[0032] ;

[0033] In the formula, denotes the Hamiltonian corresponding to the i th spin; S i denotes the effective field (referred to as spin effective field for short) to which the spin at the i th lattice point is subjected.

[0034] wherein, σ i satisfies:

[0035] .

[0036] From the above formula, to make minimum, only need to make S i and σ i the product minimum - that is, make the product negative. Therefore, the reconfigurable Ising device of the present application only needs to calculate the value of S i , and judge its positive and negative.

[0037] Embodiment 1

[0038] Referring to the above: , then S i can be rewritten as: . That is, S i contains J i,j , σ j , h i , 1, a total of four objects (wherein,J i,j Generally need multiple, σ j , h i , 1 only need 1), and there are product, accumulation, addition.

[0039] In theory, the reconfigurable Ising device of the application first designs the corresponding storage part for these objects, and realizes the calculation logic of S i by charging and discharging in the form of voltage. h i If the 1 multiplied by σ i is regarded as a special case of taking 1, then, S i In fact, it is J i,j , h i (both can be regarded as correlation coefficients) and σ j the multiplication and accumulation calculation.

[0040] Therefore, based on the above mechanism, referring to Figure 1 , the embodiment 1 provides a circuit structure diagram of a reconfigurable Ising device constructed based on FeFET, which comprises: a calculation array part, a spin update part.

[0041] I. The calculation array part comprises: N columns of Ising calculation columns constructed based on FeFET; N≥2. In this embodiment 1, N is recommended to be 28. Of course, N can also take other values, such as 24, 30, etc. It should be noted that the present reconfigurable Ising device supports flexible setting of the mutual relationship between different spins, so the N columns of Ising calculation columns can be freely set according to the different requirements of the spin network, that is, in each round of spin calculation, M columns of Ising calculation columns related to the target spin storage unit work. Of course, M≤N, that is, the highest support N columns of Ising calculation columns work at the same time. For example, when N=28, M can be taken as 28, that is, 28 columns of Ising calculation columns work at the same time, and the corresponding scenario is: the target spin needs 27 J i,j , 1 h i , that is, 27 columns of Ising calculation columns in 28 columns calculate , 1 column of Ising calculation column calculates h i ×1. M can also be taken as 27, that is, 27 columns of Ising calculation columns work at the same time, and the remaining 1 column of Ising calculation column is discarded, and the corresponding scenario is: the target spin needs 26 J i,j , 1 hi That is, 26 columns of 27 columns of Ising calculation columns calculate out , 1 column of Ising calculation columns calculates out h i X1. M can also take 7, that is, 7 columns of Ising calculation columns work at the same time, and then 4 rounds of spin calculation are needed to traverse 28 columns of Ising calculation columns, and the corresponding scenario of each round of spin calculation is: the target spin needs 6 J i,j , 1 h i That is, 6 columns of 7 columns of Ising calculation columns calculate out , 1 column of Ising calculation columns calculates out h i X1.

[0042] As shown in Figure 1 , the structure of each column of Ising calculation columns is the same, and then taking the nth (n ∈ [1, N]) column of Ising calculation columns as an example for description - it includes: 1 spin storage unit, 7 coefficient storage units, 1 XOR unit, 1 voltage generation unit. It should be noted that the spin storage unit, the coefficient storage unit, the XOR unit, and the voltage generation unit are all based on FeFET and will be stored and programmed before spin calculation.

[0043] The units of the Ising calculation column will be introduced in detail as follows:

[0044] ①, the spin storage unit is used to store 1 bit spin state (that is, σ j ).

[0045] Referring to Figure 2 , the spin storage unit is designed to include: 2 N-type FeFET transistors N7-N8.

[0046] The source of N7 is connected to node X3, the gate is connected to word line SWL, and the drain is connected to bit line SBL;

[0047] The source of N8 is connected to node X3, the gate is connected to word line SWLB, and the drain is connected to bit line SBLB;

[0048] The spin storage units located in the same row share the same bit line SBL and the same bit line SBLB.

[0049] Then, as shown in Figure 2 , for a single spin storage unit, N7 and N8 form complementary storage. If you want to store 1 (that is, σ jIf the value of the spin storage unit is 1 (i.e. Vcm is positive), then N7 is programmed to low resistance state, N8 is programmed to high resistance state - SBL, SBLB are set to 0, SWLB is set to programming voltage V1, SWL is set to programming voltage V0; if the value of the spin storage unit is 0 (i.e. Vcm is negative), then N7 is programmed to high resistance state, N8 is programmed to low resistance state - SBL, SBLB are set to 0, SWL is set to programming voltage V1, SWLB is set to programming voltage V0. σ j If the value of the spin storage unit is 1 (i.e. Vcm is positive), then N7 is programmed to low resistance state, N8 is programmed to high resistance state - SBL, SBLB are set to 0, SWLB is set to programming voltage V1, SWL is set to programming voltage V0; if the value of the spin storage unit is 0 (i.e. Vcm is negative), then N7 is programmed to high resistance state, N8 is programmed to low resistance state - SBL, SBLB are set to 0, SWL is set to programming voltage V1, SWLB is set to programming voltage V0.

[0050] It should be noted that, since N-type FeFET transistor is adopted, V0 < V1.

[0051] ②, 7 coefficient storage units are connected with the spin storage units in the same column, used for storing 8bit related coefficients (i.e. J i,j or h i ) weighted 7bit data bits (i.e. J i,j or h i ) and outputting a single-column shared voltage Vcm representing signed accumulation result based on charge sharing during spin calculation.

[0052] Referring to Figure 3 , the coefficient storage unit is designed to include: 2 N-type FeFET transistors N5-N6, 1 NMOS transistor NM1, 1 capacitor C1, 2 switches Q1-Q2.

[0053] The gate of N5 is connected with the word line WL, and the source is connected with node X1;

[0054] The gate of N6 is connected with the word line WLB, and the source is connected with node X2;

[0055] The gate of NM1 is connected with node X3, the source is connected with the drain of N5 and the drain of N6, and the drain is connected with the first end of C1 and the first end of Q1; the second end of C1 is grounded VSS; the second end of Q1 is connected with the first end of Q2; the second end of Q2 is used for outputting Vcm;

[0056] The second ends of Q2 in the same row are connected together, used for charge sharing of Vcm of multiple columns;

[0057] The coefficient storage units in the same column share the same node X1, the same node X2, the same node X3 and the same switch Q2; the coefficient storage units in the same row share the same word line WL and the same word line WLB.

[0058] Then, as Figure 3As shown, for a single coefficient storage unit, N5, N6 form complementary storage. Then, similar to the spin storage unit: if N5 is programmed to a low resistance state and N6 is programmed to a high resistance state, X1, X2 are set to 0, WL is set to a programming voltage V1, and WLB is set to a programming voltage V0, then N5, N6 complementarily store 1; if N7 is programmed to a high resistance state and N8 is programmed to a low resistance state, X1, X2 are set to 0, WLB is set to a programming voltage V1, and WL is set to a programming voltage V0, then N5, N6 complementarily store 0.

[0059] It should be noted in combination with the above description: if the coefficient storage unit of a certain column of Ising calculation columns stores J i,j , then the spin storage unit of the column of Ising calculation columns can store 1 or 0 according to the actual situation of spin calculation; if the coefficient storage unit of a certain column of Ising calculation columns stores h i , then the spin storage unit of the column of Ising calculation columns should only store 1.

[0060] It should be noted that the present application provides 7 coefficient storage units to provide 7bit capacity, which can cover the J i,j or h i value range of the existing Ising model. Moreover, considering the 7bit weight distribution, the corresponding charge storage ratio should be 1:2:4:8:16:32:64, that is, the charge storage distribution of the seven C1s in each column of Ising columns along the direction from top to bottom. Therefore, there are the following requirements in hardware design first: in each column of Ising columns along the direction from top to bottom: the C1 capacitance value of the first row is 4C, the C1 capacitance value of the second row is 2C, and the C1 capacitance value of the last 5 rows is C; C represents a unit capacitance value. Subsequently, the voltage values of the 7 C1s in a single column are adjusted by pre-charging, so that the C1s of the first to third rows are pre-charged to VDD (i.e. the power supply voltage value), and the C1s of the fourth to seventh rows are pre-charged to VDD / 2, VDD / 4, VDD / 8, VDD / 16, respectively. In this way, the ratio of the product of the voltage and the capacitance of the 7 C1s in a single column represents the charge storage amount, and the ratio conforms to 1:2:4:8:16:32:64.

[0061] ③, the XNOR unit is connected with the 7 coefficient storage units in the same column, and is used for storing 1bit sign bit (i.e. J i,j or h i of 8bit related coefficients (i.e. J i,j or h i ), and performing XNOR operation during spin calculation to selectively discharge the 7 coefficient storage units in the same column.

[0062] Referring to Figure 4 , the XOR unit is designed to include: 4 N-type FeFET transistors N1-N4.

[0063] The gate of N1 is connected with a word line WLL1, and the source is connected with a node X1;

[0064] The gate of N2 is connected with a word line WLR1, and the source is connected with a node X2;

[0065] The gate of N3 is connected with a word line WLL0, the source is connected with the drain of N1, and the drain is connected with a bit line BLL;

[0066] The gate of N4 is connected with a word line WLR0, the source is connected with the drain of N2, and the drain is connected with a bit line BLR;

[0067] XOR units in the same row share the same word line WLL0, the same word line WLL1, the same word line WLR0, and the same word line WLR1.

[0068] Then, as shown in Figure 4 , for a single XOR unit, it can store 0 (i.e. the sign bit is positive) or 1 (i.e. the sign bit is negative). If N1 and N4 are programmed to be in a low resistance state, N2 and N3 are programmed to be in a high resistance state, BLL and BLR are set to 0, WLL1 and WLR0 are set to a programming voltage V1, and WLL0 and WLR1 are set to a programming voltage V0, the XOR unit stores 0. If N1 and N4 are programmed to be in a high resistance state, N2 and N3 are programmed to be in a low resistance state, BLL and BLR are set to 0, WLL1 and WLR0 are set to a programming voltage V0, and WLL0 and WLR1 are set to a programming voltage V1, the XOR unit stores 1.

[0069] ④, the voltage generating unit is used to provide a single column reference voltage Vref during spin calculation.

[0070] Referring to Figure 5 , the voltage generating unit is designed to include: 4 N-type FeFET transistors N9-N12, 1 capacitor C2, and 1 switch Q3.

[0071] The gate of N9 is connected with a word line WLL3, and the source is connected with a node X4;

[0072] The gate of N10 is connected with a word line WLR3, and the source is connected with a node X5;

[0073] The gate of N11 is connected with a word line WLL2, and the source is connected with the drain of N9;

[0074] The gate of N12 is connected with a word line WLR2, and the source is connected with the drain of N10;

[0075] The first terminal of C2 is grounded to VSS, and the second terminal is connected to the drain of N11, the drain of N12, and the first terminal of Q3; the second terminal of Q3 is used to output Vref.

[0076] The second ends of Q3 in the same row are connected together to share the charge of Vref across multiple columns;

[0077] Voltage generation units located in the same row share the same word line WLL2, the same word line WLL3, the same word line WLR2, and the same word line WLR3.

[0078] So, if Figure 5 As shown, for a single voltage generation unit, N9~N12 form the same structure as N1~N4 of the XOR unit; C2 does not store charge for the time being.

[0079] Based on the above-mentioned computing array design, during each round of spin calculation, the M columns of Ising computing columns associated with the target spin memory cell are activated, and the Vcm of the M columns are used to form a total shared voltage VCM through charge sharing, and the Vref of the M columns are used to form a total reference voltage VREF through charge sharing.

[0080] Specifically, the spin calculation process can be divided into the following steps:

[0081] ① Perform column multiplication:

[0082] If a column of the Ising calculation column involved in the work is stored σ j If the value is positive, then during spin calculation, SWL and SWLB are set to 0 (the N-type FeFET transistor in the low-resistance state is turned on, and the N-type FeFET transistor in the high-resistance state is turned off), SBL is set to VDD, and SBLB is set to VSS. X3 of this Ising calculation column is pulled to VDD, thereby turning on the 7 NM1s in this column; at the same time, WLL1 and WLR1 in the XOR cell of this Ising calculation column are set to VDD, and WLL0, WLR0, BLL, and BLR are set to VSS. Then, this XOR cell performs an XOR calculation with 1:

[0083] Ⅰ. If the XOR calculation result is 0, then X2 discharges to VSS through N2 and N4. C1 in the coefficient storage cell stored as 1 in the Ising calculation column will share charge at node X1, and C1 in the coefficient storage cell stored as 0 in the Ising calculation column will leak charge at node X2.

[0084] II. If the XOR calculation result is 1, then X1 discharges to VSS through N1 and N3. C1 in the coefficient storage cell stored as 1 in the Ising calculation column will leak charge at node X1, and C1 in the coefficient storage cell stored as 0 in the Ising calculation column will share charge at node X2.

[0085] If the result of the spin calculation is 1, then the X3 of the Ising computation column under work is pulled to VDD, thereby turning on the 7 NM1 of the column; at the same time, the WLL1, WLR1 in the XNOR unit of the Ising computation column are pulled to VSS, and the WLL0, WLR0, BLL, BLR are pulled to VDD, so that the XNOR unit performs XNOR calculation with 1: σ j If the result of the spin calculation is 1, then the X3 of the Ising computation column under work is pulled to VDD, thereby turning on the 7 NM1 of the column; at the same time, the WLL1, WLR1 in the XNOR unit of the Ising computation column are pulled to VSS, and the WLL0, WLR0, BLL, BLR are pulled to VDD, so that the XNOR unit performs XNOR calculation with 1:

[0086] Ⅲ、If the result of the XNOR calculation is 0, then X2 is discharged to VSS through N2 and N4, and the C1 in the coefficient storage unit of the Ising computation column under work which stores 1 will perform charge sharing at the X1 node, and the C1 in the coefficient storage unit of the Ising computation column under work which stores 0 will appear charge leakage at the X2 node.

[0087] Ⅳ、If the result of the XNOR calculation is 1, then X1 is discharged to VSS through N1 and N3, and the C1 in the coefficient storage unit of the Ising computation column under work which stores 1 will perform charge leakage at the X1 node, and the C1 in the coefficient storage unit of the Ising computation column under work which stores 0 will appear charge sharing at the X2 node.

[0088] ②、Column charge sharing operation:

[0089] The X3 of the Ising computation column under work is pulled to VSS, thereby turning off the 7 NM1 of the column; then Q1 is turned on, so that the 7 C1 of the column perform charge sharing to generate the Vcm of the column, which represents the 8-bit calculation result with a sign bit (i.e. J i,j × σ j or h i ×1) of the column; then Q2 is turned on, so that the Vcm of the M columns perform charge sharing to generate the VCM, which represents the accumulated result with a sign (i.e. ).

[0090] ③、Generate reference voltage operation:

[0091] For the column of Ising calculation involved in the work, first disconnect Q3, the voltage generating unit of the column and the same or unit of the column do the same operation, then, if the same or calculation result of the voltage generating unit is 0, C2 will leak to 0 through X4 node; if the same or calculation result of the voltage generating unit is 1, C2 will be charged to 127×VDD / 176≈3VDD / 4 through X5; in this way, the first end of Q3 generates the Vref of the column. Then turn on Q3, make the Vref of M column charge sharing, to generate VREF, which represents the signed accumulation of 0 result.

[0092] II. The spin update unit is used to compare VCM and VREF to obtain a new spin state, and update it to the target spin storage unit.

[0093] Referring to Figure 6 , the spin update unit includes a digital-to-analog converter, an analog-to-digital converter, and a spin updater.

[0094] The output end of the digital-to-analog converter is connected to the second end of Q2 through switch S0. The digital-to-analog converter is used to adjust the weight of 7-bit data bit, that is, to pre-charge the 7 C1s of a single column to the corresponding level as a pre-charge circuit. Specifically, for a column of Ising column, keep the 7 NM1s of the column off, turn on Q2 and S0, and along the direction from top to bottom: first turn on the Q1s of the first to third rows, and keep the Q1s of the other four rows off, the digital-to-analog converter pre-charges the three C1s of the first to third rows to VDD; then turn off the Q1s of the first to third rows, turn on the Q1 of the fourth row, and keep the Q1s of the other three rows off, the digital-to-analog converter pre-charges the C1 of the fourth row to VDD / 2; in turn, the digital-to-analog converter pre-charges the C1 of the fifth row to VDD / 4, the C1 of the sixth row to VDD / 8, and the C1 of the seventh row to VDD / 16.

[0095] Of course, the digital-to-analog converter can also be replaced by other pre-charge circuits, but it needs to meet the above pre-charge requirements.

[0096] The input end one of the analog-to-digital converter is connected to the second end of Q2, and the input end two is connected to the second end of Q3; the analog-to-digital converter is used to compare VCM and VREF to obtain a new spin state.

[0097] Referring to the above, VCM represents S i , VREF represents 0, then compare them, the positive and negative of the result is S i If the comparison result is positive, it means S i > 0, σ i= +1; if the comparison result is negative, it means S i < 0, σ i = -1; if the comparison result is equal, it means S i = 0, σ i = +1 or -1.

[0098] The output end of the analog-digital converter is connected to the spin updater connected to the target spin storage unit, so that the new spin state is overwritten into the target spin storage unit through the spin updater. It should be noted that the target spin storage unit is in other reconfigurable Ising machine, which can also be used as a data source for spin calculation and update of other spin storage units.

[0099] It should be noted that, considering that M < N, only M column Ising calculation columns will exist column waste. When M is much smaller than N, the waste of a large number of calculation columns will limit the overall running efficiency. Therefore, in this embodiment 1, the spin update part adopts a register design combined with data selection design, which specifically includes: 1 data distributor, W registers, 1 data selector, 1 peripheral overwrite circuit; W ≥ 1.

[0100] Referring to Figure 6 , the input end of the data distributor is connected to the output end of the analog-digital converter; the input end of the wth register is connected to the wth output end of the data distributor, and the output end is connected to the wth input end of the data selector; the output end of the data selector is connected to the target spin storage unit through the peripheral overwrite circuit; w ∈ [1, W]. Among them, considering that the most classic connection mode of Ising model is two-dimensional square connection, W is recommended to be: the left integer of N / 5. In this embodiment 1, when N = 28, W is 5.

[0101] Then, the N column Ising calculation columns can be divided into V groups (it should be noted that it is not mandatory to divide all N columns, and there can be a remainder), each group containing M column Ising calculation columns; V ≤ W. In this way, in each round of spin calculation, the corresponding M column Ising calculation columns are calculated in order from 1 to V; after completing a group of M column Ising calculation columns, the data distributor selects a register and temporarily stores the new spin state in the register; after all groups of calculation are completed, the V registers correspond to V new spin states temporarily stored; then, the data selector selects a register, and outputs the new spin state temporarily stored in the register to the peripheral overwrite circuit, and the peripheral overwrite circuit writes the new spin state into the corresponding target spin storage unit based on the pairing rule, until the data selector traverses the V registers, that is, all spin updates are completed. In this way, the waste of calculation columns is reduced, and the calculation density is improved.

[0102] Embodiment 2

[0103] This embodiment 2 discloses a CIM chip which adopts the circuit layout of the reconfigurable Ising machine based on FeFET disclosed above. The mode of packaging into a chip is more conducive to the popularization and application of the circuit above.

[0104] Of course, the circuit layout of the reconfigurable Ising machine based on FeFET can also be designed into a module, and the corresponding pin can be designed into a terminal when designed into a module.

[0105] The technical features of the above embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, but as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the present disclosure.

[0106] The above embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of the present application. Therefore, the scope of the patent of the present application should be subject to the appended claims.

Claims

1. A reconfigurable Ising device based on FeFET, characterized in that, It includes: The computation array comprises: N columns of Ising computation columns constructed based on FeFET; N≥2; where n∈[1,N]; the nth Ising computation column includes: One spin memory unit is used to store 1 bit of spin state; Seven coefficient storage units are connected to spin storage units in the same column to store 7-bit data bits of 8-bit correlation coefficients and, during spin calculation, to output a single-column shared voltage Vcm based on charge sharing to characterize the signed accumulation result. One XOR cell, which is connected to seven coefficient storage cells in the same column, is used to store the 1-bit sign bit of the 8-bit correlation coefficient and to perform an XOR operation during spin calculation to selectively discharge the seven coefficient storage cells in the same column. One voltage generation unit is used to provide a single-column reference voltage Vref during spin calculations; In each round of spin calculation, the M columns of Ising calculation columns associated with the target spin storage unit are activated, and the Vcm of the M columns are used to form a total shared voltage VCM characterizing the effective spin field through charge sharing, and the Vref of the M columns are used to form a total reference voltage VREF characterizing 0 through charge sharing; M≤N; as well as The spin update unit is used to: compare VCM and VREF to obtain a new spin state and update it to the target spin memory cell.

2. The reconfigurable Ising device based on FeFET according to claim 1, characterized in that, The spin memory cell includes: two N-type FeFET transistors N7~N8; N7 has its source connected to node X3, its gate connected to word line SWL, and its drain connected to bit line SBL. N8 has a source connection node X3, a gate connection word line SWLB, and a drain connection bit line SBLB. Spin memory cells located in the same row share the same bit line SBL and the same bit line SBLB.

3. The reconfigurable Ising device based on FeFET according to claim 2, characterized in that, The coefficient storage unit includes: two N-type FeFET transistors N5~N6, one NMOS transistor NM1, one capacitor C1, and two switches Q1~Q2; N5's gate is connected to word line WL, and its source is connected to node X1; N6's gate is connected to word line WLB, and its source is connected to node X2; The gate of NM1 is connected to node X3, the source is connected to the drain of N5 and the drain of N6, and the drain is connected to the first terminal of C1 and the first terminal of Q1; the second terminal of C1 is grounded to VSS; the second terminal of Q1 is connected to the first terminal of Q2; the second terminal of Q2 is used to output Vcm. The second ends of Q2 located in the same row are connected together to share the charge of Vcm across multiple columns; Coefficient storage units located in the same column share the same node X1, the same node X2, the same node X3, and the same switch Q2; coefficient storage units located in the same row share the same word line WL and the same word line WLB.

4. The reconfigurable Ising device based on FeFET according to claim 3, characterized in that, In each column of the Ising column, from top to bottom: the capacitance value of C1 in the first row is 4C, the capacitance value of C1 in the second row is 2C, and the capacitance value of C1 in the following 5 rows is C; C represents the unit capacitance value. Furthermore, C1 in rows 1 to 3 is precharged to VDD, and C1 in rows 4 to 7 is precharged to VDD / 2, VDD / 4, VDD / 8, and VDD / 16 respectively; VDD represents the power supply voltage value.

5. The reconfigurable Ising device based on FeFET according to claim 4, characterized in that, The XOR unit includes: four N-type FeFET transistors N1~N4; N1's gate is connected to word line WLL1, and its source is connected to node X1; N2's gate is connected to word line WLR1, and its source is connected to node X2; The gate of N3 is connected to the word line WLL0, the source is connected to the drain of N1, and the drain is connected to the bit line BLL. The gate of N4 is connected to the word line WLR0, the source is connected to the drain of N2, and the drain is connected to the bit line BLR. The same word line WLL0, WLL1, WLR0, and WLR1 are shared by the same XOR cells in the same row.

6. The reconfigurable Ising device based on FeFET according to claim 5, characterized in that, The voltage generation unit includes: four N-type FeFET transistors N9~N12, one capacitor C2, and one switch Q3; N9's gate is connected to word line WLL3, and its source is connected to node X4; N10's gate is connected to word line WLR3, and its source is connected to node X5; The gate of N11 is connected to the word line WLL2, and the source is connected to the drain of N9; The gate of N12 is connected to the word line WLR2, and the source is connected to the drain of N10; The first terminal of C2 is grounded to VSS, and the second terminal is connected to the drain of N11, the drain of N12, and the first terminal of Q3; the second terminal of Q3 is used to output Vref. The second ends of Q3 in the same row are connected together to share the charge of Vref across multiple columns; Voltage generation units located in the same row share the same word line WLL2, the same word line WLL3, the same word line WLR2, and the same word line WLR3.

7. The reconfigurable Ising device based on FeFET according to claim 6, characterized in that, The spin update unit includes: one digital-to-analog converter, one analog-to-digital converter, and one spin updater; The output of the digital-to-analog converter is connected to the second terminal of Q2 via switch S0; the digital-to-analog converter is used to adjust the weight of the 7-bit data bits. The first input terminal of the analog-to-digital converter is connected to the second terminal of Q2, and the second input terminal is connected to the second terminal of Q3; the analog-to-digital converter is used to compare VCM and VREF to obtain a new spin state; The output of the analog-to-digital converter is connected to the spin updater, which is connected to the target spin memory unit.

8. The reconfigurable Ising device based on FeFET according to claim 7, characterized in that, The spin updater includes: 1 data distributor, W registers, 1 data selector, and 1 external repeater circuit; W ≥ 1; The input of the data distributor is connected to the output of the analog-to-digital converter; the input of the w-th register is connected to the w-th output of the data distributor, and the output is connected to the w-th input of the data selector; the output of the data selector is connected to the target spin memory unit through an external rewriting circuit; w∈[1,W].

9. The reconfigurable Ising device based on FeFET according to claim 8, characterized in that, N=28, W=5.

10. A CIM chip, characterized in that, The circuit layout of the reconfigurable Isinger based on FeFET is adopted as described in any one of claims 1-9.

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