Semiconductor laser and preparation method thereof

Abstract

The invention provides a semiconductor laser and a preparation method thereof. The preparation method comprises the following steps: forming a lower limiting layer on one side of a semiconductor substrate layer along a first direction; a ridge-shaped structure is formed on the side, away from the semiconductor substrate layer, of a part of the lower limiting layer, the ridge-shaped structure comprises a lower waveguide layer, an active layer, an upper waveguide layer, a grating layer and a cover layer which are sequentially stacked in the first direction, and the cover layer is located on the side, away from the upper waveguide layer, of the grating layer; an insulating epitaxial layer is formed on the side, away from the semiconductor substrate layer, of the lower limiting layer, the insulating epitaxial layer is located on the side, away from the semiconductor substrate layer, of the ridge-shaped structure and on the two sides, in the slow axis direction, of the ridge-shaped structure, and the thermal conductivity of the insulating epitaxial layer is larger than that of the active layer; an opening is formed in the insulating epitaxial layer, the opening exposes the cover layer, and the size of the opening in the slow axis direction is larger than that of the ridge-shaped structure in the slow axis direction; an upper confinement layer is formed in the opening.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor laser and its fabrication method. Background Technology

[0002] Semiconductor lasers include quantum cascade lasers (QCLs). QCLs emit wavelengths covering the mid-to-far infrared band and, due to their small size, high conversion efficiency, and tunable wavelength, show broad application prospects in infrared countermeasures, space optical communication, and gas sensing. Particularly in special environments such as coal mines, the demand for real-time, high-precision detection of trace gases is increasing, driving the development of low-power, wavelength-locked, and narrow-linewidth light sources. Distributed feedback (DFB) quantum cascade lasers (DFB-QCLs), with their excellent single-mode characteristics and wavelength stability, have become key devices for meeting the needs of such applications. Summary of the Invention

[0003] The technical problem to be solved by the present invention is how to reduce the leakage current channel in a semiconductor laser, thereby providing a semiconductor laser and its fabrication method.

[0004] This application provides a semiconductor laser, comprising: forming a lower confinement layer on one side of a semiconductor substrate along a first direction; forming a ridge structure on a portion of the lower confinement layer away from the semiconductor substrate, the ridge structure comprising a lower waveguide layer, an active layer, an upper waveguide layer, a grating layer, and a capping layer sequentially stacked in the first direction, the capping layer being located on the side of the grating layer away from the upper waveguide layer; forming an insulating epitaxial layer on the side of the lower confinement layer away from the semiconductor substrate, the insulating epitaxial layer being located on the side of the ridge structure away from the semiconductor substrate and on both sides of the ridge structure in the slow axis direction, the thermal conductivity of the insulating epitaxial layer being greater than the thermal conductivity of the active layer; forming an opening in the insulating epitaxial layer, the opening exposing the capping layer, the size of the opening in the slow axis direction being greater than the size of the ridge structure in the slow axis direction; and forming an upper confinement layer in the opening.

[0005] Optionally, forming a ridge structure on the side of a portion of the lower confinement layer opposite to the semiconductor substrate includes: forming an initial ridge structure on the side of a portion of the lower confinement layer opposite to the semiconductor substrate, the initial ridge structure including an initial lower waveguide layer, an initial active layer, an initial upper waveguide layer, an initial grating layer, and an initial capping layer; etching the initial ridge structure to form the ridge structure, to form the upper waveguide layer from the initial upper waveguide layer, to form the active layer from the initial active layer, to form the lower waveguide layer from the initial lower waveguide layer, to form the grating layer from the initial lower waveguide layer, and to form the capping layer from the initial capping layer.

[0006] Optionally, the initial capping layer has a dimension of 500nm-1000nm in the first direction.

[0007] Optionally, the initial ridge structure further includes a first initial semiconductor cutoff layer, which is located between the initial upper waveguide layer and the initial grating layer; the material of the first initial semiconductor cutoff layer is different from the material of the initial upper waveguide layer and different from the material of the initial grating layer; during the etching process of the initial ridge structure, the first initial semiconductor cutoff layer is also formed into a first semiconductor cutoff layer.

[0008] Optionally, the fabrication method further includes: forming a mask layer on the side of the initial ridge structure opposite to the semiconductor substrate; wherein etching the initial ridge structure includes: etching the initial ridge structure using the mask layer as a mask; wherein the fabrication method further includes: removing the mask layer before forming the insulating epitaxial layer.

[0009] Optionally, during the formation of the insulating epitaxial layer, the portion of the insulating epitaxial layer located on the side of the ridge structure opposite to the semiconductor substrate has a size of 1μm-3μm in the first direction.

[0010] Optionally, the upper confinement layer is further formed on the side of the insulating epitaxial layer surrounding the opening that faces away from the semiconductor substrate layer; the process for forming the upper confinement layer is an epitaxial process.

[0011] Optionally, the preparation method further includes forming a contact layer on the side of the upper limiting layer opposite to the capping layer.

[0012] Optionally, the process for forming the opening is anisotropic dry etching process.

[0013] Optionally, the fabrication method further includes: forming a second semiconductor cutoff layer, the second semiconductor cutoff layer being located on the side of the capping layer opposite to the grating layer, the material of the second semiconductor cutoff layer being different from the material of the capping layer; wherein forming the opening includes: performing a first etching using an anisotropic dry etching process; after the first etching, performing a second etching using a wet etching process until the second semiconductor cutoff layer is exposed; wherein the fabrication method further includes: removing the second semiconductor cutoff layer using a wet etching process before forming the insulating epitaxial layer.

[0014] This application also provides a semiconductor laser, comprising: a semiconductor substrate layer; a lower confinement layer located on one side of the semiconductor substrate layer along a first direction; a ridge structure located on the side of a portion of the lower confinement layer opposite to the semiconductor substrate layer, the ridge structure comprising a lower waveguide layer, an active layer, an upper waveguide layer, a grating layer, and a capping layer sequentially stacked in the first direction, the capping layer being located on the side of the grating layer opposite to the upper waveguide layer; an upper confinement layer located on the side of the capping layer opposite to the grating layer and in contact with the capping layer, the dimension of the upper confinement layer in the slow axis direction being larger than the dimension of the ridge structure in the slow axis direction; and an insulating epitaxial layer located on both sides of the ridge structure and the upper confinement layer in the slow axis direction, the thermal conductivity of the insulating epitaxial layer being greater than the thermal conductivity of the active layer.

[0015] Optionally, the size of the capping layer in the first direction is 500nm-1000nm.

[0016] Optionally, the material of the capping layer is different from the material of the upper waveguide layer.

[0017] Optionally, the material of the cover layer is the same as the material of the upper limiting layer.

[0018] Optionally, the semiconductor laser further includes a first semiconductor cutoff layer, which is located between the upper waveguide layer and the grating layer. The material of the first semiconductor cutoff layer is different from the material of the upper waveguide layer and different from the material of the grating layer.

[0019] Optionally, the upper limiting layer includes a first portion and a second portion, the first portion and the cover layer having an overlapping area in the first direction, the second portion being located on the side of the first portion in the slow axis direction and connected to the first portion, and the connecting surface of the first portion and the second portion being spaced apart from the cover layer in the first direction.

[0020] Optionally, the surface of the upper limiting layer facing the semiconductor substrate is flush with the surface of the capping layer facing away from the semiconductor substrate.

[0021] Optionally, the portion of the insulating epitaxial layer located on both sides of the upper confining layer in the slow axis direction has a dimension of 1μm-3μm along the first direction.

[0022] The technical solution of this invention has the following beneficial effects: The semiconductor laser provided by this invention has a capping layer located on the side of the grating layer away from the upper waveguide layer. The insulating epitaxial layer is located not only on both sides of the ridge structure along the slow axis but also on the side of the ridge structure away from the semiconductor substrate. The insulating epitaxial layer has a relatively large growth thickness in the first direction, resulting in a flatter surface on the side of the insulating epitaxial layer away from the semiconductor substrate, reducing growth defects in the insulating epitaxial layer. During the formation of the opening in the insulating epitaxial layer, the capping layer protects the grating layer and the active layer. Furthermore, the size of the opening in the slow axis direction is larger than the size of the ridge structure in the slow axis direction. The bottom surface of the portion of the opening located on both sides of the ridge structure in the slow axis direction has high flatness, or the lowest point of the bottom surface of the opening is far away from the active layer and the grating layer in the slow axis direction, further protecting the grating layer and the active layer from etching damage and reducing the occurrence of leakage current conduction. Attached Figure Description

[0023] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 This is a flowchart illustrating the fabrication process of a semiconductor laser according to an embodiment of this application; Figures 2 to 8 This is a structural diagram illustrating the fabrication process of a semiconductor laser according to one embodiment; Figures 9 to 16 This is a structural diagram illustrating the fabrication process of a semiconductor laser according to another embodiment. Detailed Implementation

[0025] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0027] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0028] One embodiment of the present invention provides a method for fabricating a semiconductor laser, with reference to... Figure 1 ,include: S1: A lower confinement layer is formed on one side of the semiconductor substrate layer along the first direction; S2: A ridge structure is formed on the side of the lower confinement layer away from the semiconductor substrate layer. The ridge structure includes a lower waveguide layer, an active layer, an upper waveguide layer, a grating layer and a capping layer stacked sequentially in the first direction. The capping layer is located on the side of the grating layer away from the upper waveguide layer. S3: An insulating epitaxial layer is formed on the side of the lower confinement layer away from the semiconductor substrate layer. The insulating epitaxial layer is located on the side of the ridge structure away from the semiconductor substrate layer and on both sides of the ridge structure in the slow axis direction. The thermal conductivity of the insulating epitaxial layer is greater than that of the active layer. S4: An opening is formed in the insulating epitaxial layer, the opening exposing the capping layer, the size of the opening in the slow axis direction being larger than the size of the ridge structure in the slow axis direction; S5: An upper confinement layer is formed in the opening.

[0029] In this embodiment, the capping layer is located on the side of the grating layer away from the upper waveguide layer. The insulating epitaxial layer is located not only on both sides of the ridge structure in the slow axis direction, but also on the side of the ridge structure away from the semiconductor substrate. The insulating epitaxial layer has a large growth thickness in the first direction, making the surface of the insulating epitaxial layer away from the semiconductor substrate relatively flat, reducing growth defects in the insulating epitaxial layer. During the formation of the opening in the insulating epitaxial layer, the capping layer can protect the grating layer and the active layer. Furthermore, the size of the opening in the slow axis direction is larger than the size of the ridge structure in the slow axis direction. The bottom surface of the portion of the opening located on both sides of the ridge structure in the slow axis direction has high flatness, or the lowest point of the bottom surface of the opening is far away from the active layer and the grating layer in the slow axis direction, further protecting the grating layer and the active layer from etching damage and reducing the occurrence of leakage current conduction.

[0030] In some embodiments, forming a ridge structure on the side of a portion of the lower confinement layer opposite to the semiconductor substrate includes: forming an initial ridge structure on the side of a portion of the lower confinement layer opposite to the semiconductor substrate, the initial ridge structure including an initial lower waveguide layer, an initial active layer, an initial upper waveguide layer, an initial grating layer, and an initial capping layer; etching the initial ridge structure to form the ridge structure, to form the upper waveguide layer from the initial upper waveguide layer, to form the active layer from the initial active layer, to form the lower waveguide layer from the initial lower waveguide layer, to form the grating layer from the initial lower waveguide layer, and to form the capping layer from the initial capping layer.

[0031] In one embodiment, the difference between the size of the opening in the slow axis direction and the size of the ridge structure in the slow axis direction is 5 micrometers to 30 micrometers, for example, 5 micrometers, 10 micrometers, 15 micrometers, 20 micrometers, 25 micrometers, or 30 micrometers. This balances the need for greater protection of the ridge structure with reduced etching costs.

[0032] In this embodiment, a quantum cascade semiconductor laser is used as an example to illustrate the semiconductor light-emitting structure. The quantum cascade semiconductor laser includes a mid-infrared quantum cascade semiconductor laser.

[0033] Figures 2 to 8 This is a structural diagram illustrating the fabrication process of a semiconductor laser according to an embodiment.

[0034] refer to Figure 2 A lower confinement layer 110 is formed on one side of the semiconductor substrate 100 along a first direction; an initial ridge structure is formed on a portion of the lower confinement layer 110 away from the semiconductor substrate 100, the initial ridge structure including an initial lower waveguide layer 120, an initial active layer 130, an initial upper waveguide layer 140, an initial grating layer 160 and an initial capping layer 170.

[0035] The initial ridge structure forms continuously within the same extensional chamber.

[0036] In this embodiment, the semiconductor substrate 100 is an InP substrate. It should be noted that in other embodiments, the semiconductor substrate 100 may be made of other materials.

[0037] In this embodiment, the material of the lower confinement layer 110 is InP doped with conductive ions.

[0038] In this embodiment, the initial lower waveguide layer 120 is made of In doped with conductive ions. x1 Ga 1-x1 As. The initial upper waveguide layer 140 is made of In doped with conductive ions. x1 Ga 1-x1 As.

[0039] In this embodiment, the initial active layer 130 is a superlattice structure. The initial active layer 130 includes several stacked initial sub-active layer groups. The initial sub-active layer group includes a first initial sub-active layer unit to the Mth initial sub-active layer unit stacked sequentially from bottom to top, where M is an integer greater than or equal to 2. Any mth initial sub-active layer unit includes a mth initial lower sub-active layer and a mth initial upper sub-active layer stacked from bottom to top, where m is an integer greater than or equal to 1 and less than or equal to M. The material of the mth initial lower sub-active layer is In. x Ga (1-x) As, the material of the initial m-th upper sub-active layer is In. y Al (1-y) As.

[0040] In one embodiment, x is 0.53 to 0.8, and y is 0.2 to 0.5.

[0041] In this embodiment, the material of the initial grating layer 160 includes In x2 Ga (1-x2) As.

[0042] In this embodiment, the material of the initial capping layer 170 includes InP doped with conductive ions.

[0043] In this embodiment, the conductive ion is, for example, a Si ion.

[0044] In one embodiment, the initial capping layer 170 has a dimension of 500nm-1000nm in the first direction, such as 500nm, 800nm ​​or 1000nm.

[0045] In one embodiment, the initial ridge structure further includes a first initial semiconductor cutoff layer 150, which is located between the initial upper waveguide layer 140 and the initial grating layer 160. The material of the first initial semiconductor cutoff layer 150 is different from the material of the initial upper waveguide layer 140 and different from the material of the initial grating layer 160.

[0046] In one embodiment, the material of the first initial semiconductor cutoff layer 150 is InP.

[0047] In one embodiment, the first initial semiconductor cutoff layer 150 has a dimension of 10nm-50nm in the first direction, such as 10nm, 20nm, 30nm, 40nm or 50nm.

[0048] In one embodiment, the size of the first initial semiconductor cutoff layer 150 in the first direction is smaller than the size of the initial upper waveguide layer 140 in the first direction and smaller than the size of the initial grating layer 160 in the first direction.

[0049] refer to Figure 3 The initial ridge structure is etched to form a ridge structure, so that the initial upper waveguide layer 140 forms an upper waveguide layer 141, the initial active layer 130 forms an active layer 131, the initial lower waveguide layer 120 forms a lower waveguide layer 121, the initial grating layer 160 forms a grating layer 161, and the initial capping layer 170 forms a capping layer 171.

[0050] The ridge structure includes a lower waveguide layer 121, an active layer 131, an upper waveguide layer 141, a grating layer 161, and a capping layer 171.

[0051] During the etching process of the initial ridge structure, a first semiconductor cutoff layer 151 is also formed from the first initial semiconductor cutoff layer 150. The ridge structure also includes the first semiconductor cutoff layer 151, which is located between the upper waveguide layer 141 and the grating layer 161. The material of the first semiconductor cutoff layer 151 is different from the material of the upper waveguide layer 141 and the material of the grating layer 161.

[0052] In one embodiment, the fabrication method further includes: forming a mask layer 180 on the side of the initial ridge structure away from the semiconductor substrate layer; wherein etching the initial ridge structure includes: etching the initial ridge structure using the mask layer 180 as a mask.

[0053] The initial ridge structure was etched using a dry plasma etching process, which included anisotropic dry plasma etching. Dry plasma etching ensures good sidewall perpendicularity of the ridge structure, particularly the active layer 131. Furthermore, it reduces lateral damage to the ridge structure.

[0054] In one embodiment, the material of the lower waveguide layer 121 is In doped with conductive ions. x1 Ga 1-x1 As. The upper waveguide layer 141 is made of In doped with conductive ions. x1 Ga 1-x1 As.

[0055] In one embodiment, the active layer 131 is a superlattice structure, comprising a plurality of stacked sub-active layer groups. Each sub-active layer group includes, from bottom to top, a first sub-active layer unit to the Mth sub-active layer unit, where M is an integer greater than or equal to 2. Any mth sub-active layer unit includes, from bottom to top, a lower mth sub-active layer and an upper mth sub-active layer, where m is an integer greater than or equal to 1 and less than or equal to M. The material of the lower mth sub-active layer is In. x Ga (1-x) As, the material of the m-th sub-active layer is In. y Al (1-y)As.

[0056] In one embodiment, the material of the grating layer 161 includes In x2 Ga (1-x2) As.

[0057] In this embodiment, the material of the capping layer 171 includes InP doped with conductive ions.

[0058] In one embodiment, the capping layer 171 has a dimension of 500nm-1000nm in the first direction, such as 500nm, 800nm ​​or 1000nm.

[0059] In one embodiment, the capping layer 171 is larger in size in the first direction than the grating layer 161 and the upper waveguide layer 141 in the first direction. The capping layer 171 is thicker in the first direction, which allows it to better protect the grating layer and the active layer during the subsequent formation of openings in the insulating epitaxial layer.

[0060] In one embodiment, the material of the first semiconductor cutoff layer 151 is InP.

[0061] In one embodiment, the first semiconductor cutoff layer 151 has a dimension of 10nm-50nm in the first direction, such as 10nm, 20nm, 30nm, 40nm or 50nm.

[0062] In one embodiment, the dimension of the first semiconductor cutoff layer 151 in the first direction is smaller than the dimension of the upper waveguide layer 141 in the first direction and smaller than the dimension of the grating layer 161 in the first direction. The first semiconductor cutoff layer 151 has a relatively small impact on the resistance of the semiconductor laser.

[0063] The thermal conductivity of the active layer 131 along the plane perpendicular to the first direction is greater than the thermal conductivity of the active layer 131 along the first direction.

[0064] In one embodiment, the active layer 131 has a dimension of 2 to 6 micrometers in the slow axis direction, for example, 2 micrometers, 3 micrometers, 4 micrometers, 5 micrometers, or 6 micrometers. Because the active layer 131 has a smaller dimension in the slow axis direction, the degree of heat dissipation from the side is improved, thus reducing the junction temperature of the active layer 131 during operation. The electro-optical conversion efficiency of the semiconductor laser gradually increases as the width of the active layer 131 in the slow axis direction decreases. The smaller dimension of the active layer 131 in the slow axis direction results in a lower threshold current.

[0065] In one embodiment, the dimension of the surface of the active layer 131 facing the upper waveguide layer 141 in the slow axis direction is equal to the dimension of the surface of the upper waveguide layer 141 facing the active layer 131 in the slow axis direction, and the dimension of the surface of the active layer 131 facing the lower waveguide layer 121 in the slow axis direction is equal to the dimension of the surface of the lower waveguide layer 121 facing the active layer 131 in the slow axis direction. That is, no additional process is required to laterally etch the active layer 131, and there is no need to recess the active layer 131 relative to the upper waveguide layer 141 and the lower waveguide layer 121 in the slow axis direction to reduce leakage current paths.

[0066] refer to Figure 4 Remove the mask layer by 180°.

[0067] refer to Figure 5 An insulating epitaxial layer 190 is formed on the side of the lower limiting layer 110 away from the semiconductor substrate layer 100. The insulating epitaxial layer 190 is located on the side of the ridge structure away from the semiconductor substrate layer 100 and on both sides of the ridge structure in the slow axis direction. The thermal conductivity of the insulating epitaxial layer 190 is greater than that of the active layer 131.

[0068] After removing the mask layer 180, an insulating epitaxial layer 190 is formed.

[0069] In one embodiment, the process of forming the insulating epitaxial layer 190 includes an epitaxial growth process.

[0070] In one embodiment, the portion of the insulating epitaxial layer 190 located on the side of the ridge structure opposite to the semiconductor substrate layer 100 has a dimension of 1μm-3μm in a first direction, such as 1μm, 2μm or 3μm.

[0071] In one embodiment, the insulating epitaxial layer 190 is made of Fe-doped InP. The insulating epitaxial layer 190 is non-conductive, and charge carriers in the active layer 131 do not pass through the insulating epitaxial layer 190.

[0072] In one embodiment, the molar concentration of Fe doping in the material of the insulating epitaxial layer 190 is 1 × 10⁻⁶. 16 atom / cm 3 ~1×10 18 atom / cm 3 The reason for doping the insulating epitaxial layer with Fe is that Fe is a dominant element in InP materials, which can effectively bind the free electrons in the intrinsic InP material, thus transforming the InP material from an intrinsic semiconductor material into a semi-insulating material.

[0073] In one embodiment, the insulating epitaxial layer 190 is formed using an MOCVD (metal-organic chemical vapor deposition) apparatus. Growing the insulating epitaxial layer 190 in an MOCVD apparatus allows for good growth selectivity and reduces voids.

[0074] The insulating epitaxial layer 190 is located not only on both sides of the ridge structure in the slow axis direction, but also on the side of the ridge structure away from the semiconductor substrate 100. The insulating epitaxial layer 190 has a large growth thickness in the first direction, which makes the surface of the insulating epitaxial layer 190 away from the semiconductor substrate 100 relatively flat, reducing growth defects in the insulating epitaxial layer 190.

[0075] Because the insulating epitaxial layer 190 has a large growth thickness in the first direction, after the insulating epitaxial layer 190 is formed, there will be no large depression on the side of the insulating epitaxial layer 190 facing away from the semiconductor substrate layer 100. The insulating epitaxial layer 190 effectively isolates the grating layer 161 from the external environment and the active layer 131 from the external environment, and does not expose the grating layer 161 and the active layer 131, preventing the grating layer 161 and the active layer 131 from being oxidized and contaminated, thus providing ideal interface conditions for subsequent processes.

[0076] refer to Figure 6 An opening 191 is formed in the insulating epitaxial layer 190, the opening 191 exposes the capping layer 171, and the size of the opening 191 in the slow axis direction is larger than the size of the ridge structure in the slow axis direction.

[0077] In one embodiment, the process for forming the opening 191 is an anisotropic dry etching process. Due to the use of anisotropic dry etching, the etching endpoint of the opening 191 needs to be strictly controlled.

[0078] During the formation of opening 191, capping layer 171 protects grating layer 161 and active layer 131 from etching damage. During the formation of opening 191, a portion of capping layer 171 may be consumed in the first direction. If the etching precision is well controlled, capping layer 171 may not be consumed in the first direction during the formation of opening 191.

[0079] The size of the opening 191 in the slow axis direction is larger than that of the ridge structure in the slow axis direction. The bottom surface of the portion of the opening 191 located on both sides of the ridge structure in the slow axis direction has high flatness. The opening 191 makes it difficult to expose the grating layer 161 and the active layer 131, thus protecting the grating layer 161 and the active layer 131 from etching damage and reducing the occurrence of leakage current conduction.

[0080] refer to Figure 7 An upper confinement layer 200 is formed in the opening 191.

[0081] The upper confinement layer 200 is also formed on the side of the insulating epitaxial layer 190 surrounding the opening 191, facing away from the semiconductor substrate layer 100; the process for forming the upper confinement layer 200 is an epitaxial process. Since the upper confinement layer 200 does not need to be etched, the process is simplified.

[0082] An upper confinement layer 200 is formed in the opening 191. The upper confinement layer 200 is strictly confined in the opening 191, forming a unique current channel and reducing the possibility of leakage at the edge of the active layer 131.

[0083] In one embodiment, the material of the upper limiting layer 200 is the same as that of the capping layer 171, thereby improving the growth quality of the upper limiting layer 200.

[0084] In one embodiment, the material of the upper confinement layer 200 may be InP doped with conductive ions.

[0085] In another embodiment, the material of the upper limiting layer 200 is different from the material of the cover layer 171.

[0086] refer to Figure 8 A contact layer 210 is formed on the side of the upper limiting layer 200 opposite to the cover layer 171.

[0087] In some embodiments, the contact layer 210 is InP doped with conductive ions, and the doping concentration of the contact layer 210 is greater than the doping concentration of the upper confinement layer 200.

[0088] In this embodiment, the method further includes: forming a front electrode layer on the side of the contact layer 210 opposite to the upper confinement layer 200; and forming a back electrode layer on the side of the semiconductor substrate layer 100 opposite to the lower confinement layer 110.

[0089] Figures 9 to 16 This is a structural diagram illustrating the fabrication process of a semiconductor laser according to another embodiment.

[0090] refer to Figure 9 A lower confinement layer 110 is formed on one side of the semiconductor substrate 100 along a first direction; an initial ridge structure is formed on a portion of the lower confinement layer 110 away from the semiconductor substrate 100, the initial ridge structure including an initial lower waveguide layer 120, an initial active layer 130, an initial upper waveguide layer 140, an initial grating layer 160, and an initial capping layer 170; a second initial semiconductor cutoff layer 300 is formed, the second initial semiconductor cutoff layer 300 being located on the side of the initial capping layer 170 away from the initial grating layer 160.

[0091] The initial ridge structure forms continuously within the same extensional chamber.

[0092] In this embodiment, the semiconductor substrate 100 is an InP substrate. It should be noted that in other embodiments, the semiconductor substrate 100 may be made of other materials.

[0093] In this embodiment, the materials of the initial lower waveguide layer 120, the initial upper waveguide layer 140, the initial active layer 130, the initial grating layer 160, and the initial capping layer 170 are the same as those in the previous embodiment.

[0094] In one embodiment, the initial capping layer 170 has a dimension of 500nm-1000nm in the first direction, such as 500nm, 800nm ​​or 1000nm.

[0095] In one embodiment, the initial ridge structure further includes a first initial semiconductor cutoff layer 150, which is located between the initial upper waveguide layer 140 and the initial grating layer 160. The material of the first initial semiconductor cutoff layer 150 is different from the material of the initial upper waveguide layer 140 and different from the material of the initial grating layer 160.

[0096] In one embodiment, the material of the first initial semiconductor cutoff layer 150 is InP.

[0097] In one embodiment, the first initial semiconductor cutoff layer 150 has a dimension of 10nm-50nm in the first direction, such as 10nm, 20nm, 30nm, 40nm or 50nm.

[0098] In one embodiment, the size of the first initial semiconductor cutoff layer 150 in the first direction is smaller than the size of the initial upper waveguide layer 140 in the first direction and smaller than the size of the initial grating layer 160 in the first direction.

[0099] In one embodiment, the material of the second initial semiconductor cutoff layer 300 is different from the material of the initial capping layer 170.

[0100] In one embodiment, the material of the second initial semiconductor cutoff layer 300 is In x3 Ga 1-x3 As.

[0101] In one embodiment, the second initial semiconductor cutoff layer 300 has a size smaller in the first direction than the initial capping layer 170, the initial upper waveguide layer 140, and the initial grating layer 160.

[0102] In one embodiment, the second initial semiconductor cutoff layer 300 has a dimension of 10nm-50nm, for example, 30nm, in the first direction.

[0103] refer to Figure 10The initial ridge structure and the second initial semiconductor cutoff layer 300 are etched to form the ridge structure and the second initial semiconductor cutoff layer 300 is formed into the second semiconductor cutoff layer 310.

[0104] During the etching process of the initial ridge structure, the initial upper waveguide layer 140 is formed into an upper waveguide layer 141, the initial active layer 130 is formed into an active layer 131, the initial lower waveguide layer 120 is formed into a lower waveguide layer 121, the initial grating layer 160 is formed into a grating layer 161, and the initial capping layer 170 is formed into a capping layer 171. During the etching process of the initial ridge structure, the first initial semiconductor cutoff layer 150 is also formed into a first semiconductor cutoff layer 151.

[0105] The ridge structure includes a lower waveguide layer 121, an active layer 131, an upper waveguide layer 141, a grating layer 161, and a capping layer 171. The ridge structure also includes a first semiconductor cutoff layer 151. The first semiconductor cutoff layer 151 is located between the upper waveguide layer 141 and the grating layer 161, and the material of the first semiconductor cutoff layer 151 is different from the material of the upper waveguide layer 141 and also different from the material of the grating layer 161.

[0106] The second semiconductor cutoff layer 310 is located on the side of the capping layer 171 away from the grating layer 161, and the material of the second semiconductor cutoff layer 310 is different from the material of the capping layer 171.

[0107] In one embodiment, the size of the second semiconductor cutoff layer 310 in the first direction is smaller than the size of the capping layer 171 in the first direction, smaller than the size of the upper waveguide layer 141 in the first direction, and smaller than the size of the grating layer 161 in the first direction.

[0108] In one embodiment, the fabrication method further includes: forming a mask layer on the side of the initial ridge structure opposite to the semiconductor substrate layer; specifically, forming a mask layer on the side of the second initial semiconductor cutoff layer 300 opposite to the initial ridge structure; wherein etching the initial ridge structure includes: etching the initial ridge structure using the mask layer as a mask. Specifically, etching the initial ridge structure and the second initial semiconductor cutoff layer 300 using the mask layer as a mask.

[0109] The initial ridge structure and the second initial semiconductor cutoff layer 300 are etched using a dry plasma etching process, which includes anisotropic dry plasma etching. The dry plasma etching process ensures good sidewall perpendicularity of the ridge structure and the active layer 131. Furthermore, it reduces lateral damage to the ridge structure.

[0110] In one embodiment, the fabrication method further includes: etching the initial ridge structure and the second initial semiconductor cutoff layer 300 using the mask layer as a mask, and then removing the mask layer.

[0111] In one embodiment, the materials of the lower waveguide layer 121, the upper waveguide layer 141, the active layer 131, and the grating layer 161 are as described in the foregoing embodiments.

[0112] In this embodiment, the material of the capping layer 171 includes InP doped with conductive ions.

[0113] In one embodiment, the capping layer 171 has a dimension of 500nm-1000nm in the first direction, such as 500nm, 800nm ​​or 1000nm.

[0114] In one embodiment, the capping layer 171 is larger in size in the first direction than the grating layer 161 and the upper waveguide layer 141 in the first direction. The capping layer 171 is thicker in the first direction, which allows it to better protect the grating layer and the active layer during the subsequent formation of openings in the insulating epitaxial layer.

[0115] In one embodiment, the material of the first semiconductor cutoff layer 151 is InP.

[0116] In one embodiment, the first semiconductor cutoff layer 151 has a dimension of 10nm-50nm in the first direction, such as 10nm, 20nm, 30nm, 40nm or 50nm.

[0117] In one embodiment, the size of the first semiconductor cutoff layer 151 in the first direction is smaller than the size of the upper waveguide layer 141 in the first direction and smaller than the size of the grating layer 161 in the first direction.

[0118] In one embodiment, the material of the second semiconductor cutoff layer 310 is different from the material of the capping layer 171.

[0119] In one embodiment, the material of the second semiconductor cutoff layer 310 is In x3 Ga 1-x3 As.

[0120] In one embodiment, the second semiconductor cutoff layer 310 has a dimension of 10nm-50nm, for example, 30nm, in the first direction.

[0121] The thermal conductivity of the active layer 131 along the plane perpendicular to the first direction is greater than the thermal conductivity of the active layer 131 along the first direction.

[0122] In one embodiment, the active layer 131 has a size of 2 to 6 micrometers in the slow axis direction, for example, 2 micrometers, 3 micrometers, 4 micrometers, 5 micrometers or 6 micrometers.

[0123] In one embodiment, the dimension of the surface of the active layer 131 facing the upper waveguide layer 141 in the slow axis direction is equal to the dimension of the surface of the upper waveguide layer 141 facing the active layer 131 in the slow axis direction, and the dimension of the surface of the active layer 131 facing the lower waveguide layer 121 in the slow axis direction is equal to the dimension of the surface of the lower waveguide layer 121 facing the active layer 131 in the slow axis direction. That is, no additional process is required to laterally etch the active layer 131, and there is no need to recess the active layer 131 relative to the upper waveguide layer 141 and the lower waveguide layer 121 in the slow axis direction to reduce leakage current paths.

[0124] refer to Figure 11 An insulating epitaxial layer 190 is formed on the side of the lower limiting layer 110 away from the semiconductor substrate layer 100. The insulating epitaxial layer 190 is located on the side of the ridge structure away from the semiconductor substrate layer 100 and on both sides of the ridge structure in the slow axis direction. The thermal conductivity of the insulating epitaxial layer 190 is greater than that of the active layer 131.

[0125] After removing the mask layer, an insulating epitaxial layer 190 is formed.

[0126] In one embodiment, the process of forming the insulating epitaxial layer 190 includes an epitaxial growth process.

[0127] In one embodiment, the portion of the insulating epitaxial layer 190 located on the side of the ridge structure opposite to the semiconductor substrate layer 100 has a dimension of 1μm-3μm in a first direction, such as 1μm, 2μm or 3μm.

[0128] In one embodiment, the insulating epitaxial layer 190 is made of Fe-doped InP. The insulating epitaxial layer 190 is non-conductive, and charge carriers in the active layer 131 do not pass through the insulating epitaxial layer 190.

[0129] In one embodiment, the molar concentration of Fe doping in the material of the insulating epitaxial layer 190 is 1 × 10⁻⁶. 16 atom / cm 3 ~1×10 18 atom / cm 3 The reason for doping the insulating epitaxial layer with Fe is that Fe is a dominant element in InP materials, which can effectively bind the free electrons in the intrinsic InP material, thus transforming the InP material from an intrinsic semiconductor material into a semi-insulating material.

[0130] In one embodiment, the insulating epitaxial layer 190 is formed using an MOCVD (metal-organic chemical vapor deposition) apparatus. Growing the insulating epitaxial layer 190 in an MOCVD apparatus allows for good growth selectivity and reduces voids.

[0131] The insulating epitaxial layer 190 is located not only on both sides of the ridge structure in the slow axis direction, but also on the side of the ridge structure away from the semiconductor substrate 100. The insulating epitaxial layer 190 has a large growth thickness in the first direction, which makes the surface of the insulating epitaxial layer 190 away from the semiconductor substrate 100 relatively flat, reducing growth defects in the insulating epitaxial layer 190.

[0132] Because the insulating epitaxial layer 190 has a large growth thickness in the first direction, after the insulating epitaxial layer 190 is formed, there will be no large depression on the side of the insulating epitaxial layer 190 facing away from the semiconductor substrate layer 100. The insulating epitaxial layer 190 effectively isolates the grating layer 161 from the external environment and the active layer 131 from the external environment, and does not expose the grating layer 161 and the active layer 131, preventing the grating layer 161 and the active layer 131 from being oxidized and contaminated, thus providing ideal interface conditions for subsequent processes.

[0133] refer to Figure 12 and Figure 13 An opening 191 is formed in the insulating epitaxial layer 190, the opening 191 exposes the capping layer 171, and the size of the opening 191 in the slow axis direction is larger than the size of the ridge structure in the slow axis direction.

[0134] refer to Figure 12 The first etching is performed using anisotropic dry etching process.

[0135] The first etching forms a first sub-opening in the insulating epitaxial layer 190. The first sub-opening does not expose the second semiconductor cutoff layer 310, nor does it expose the ridge structure, thus reducing the precision requirement for the etching endpoint of the first sub-opening.

[0136] refer to Figure 13 After the first etching, a wet etching process is used for the second etching until the second semiconductor cutoff layer 310 is exposed.

[0137] The second etching forms a second sub-opening in the insulating epitaxial layer 190. The second sub-opening is located on the side of the first sub-opening facing the semiconductor substrate layer 100 along the first direction, and the second sub-opening is connected to the first sub-opening. The first sub-opening and the second sub-opening constitute an opening 191.

[0138] In this embodiment, a wet etching process is used for the second etching until the second semiconductor stop layer 310 is exposed. The second semiconductor stop layer 310 serves as an etching stop layer, protecting the grating layer. The second semiconductor stop layer 310, acting as an etching stop layer, significantly increases the etching time redundancy, effectively protecting the grating layer and active layer, enlarging the process window, improving reliability, and making the entire manufacturing process more stable and reliable. This ensures a high degree of consistency in the ridge structure across different batches, providing a solid foundation for mass production.

[0139] In this embodiment, during the process of forming an opening in the insulating epitaxial layer, the capping layer can protect the grating layer 161 and the active layer 131.

[0140] After the second etching process using wet etching, a portion of the opening 191 extends to both sides of the ridge structure, and the bottom surface of the opening 191 is uneven. The size of the opening in the slow axis direction is larger than the size of the ridge structure in the slow axis direction. Even with the uneven bottom surface of the opening 191, the lowest point of the bottom surface of the opening 191 is still far away from the active layer 131 and the grating layer 161 in the slow axis direction. This improves the flatness of the portion of the bottom surface of the opening 191 near the grating layer 161 and the active layer 131, making it difficult for the opening 191 to expose the grating layer 161 and the active layer 131. This protects the grating layer 161 and the active layer 131 from etching damage and reduces the occurrence of leakage current conduction.

[0141] Because a second semiconductor cutoff layer 310 is provided, it is not necessary to increase the etching time margin by increasing the size of the capping layer 171 in the first direction. This reduces the etching difficulty during the formation of the ridge structure.

[0142] refer to Figure 14 The second semiconductor cutoff layer 310 is removed by a wet etching process.

[0143] After the second semiconductor cutoff layer 310 is removed, the insulating epitaxial layer 190 located at the bottom of the opening 191 and close to the sidewalls on both sides of the ridge structure in the slow axis direction has a larger size in the first direction, which can protect the ridge structure.

[0144] refer to Figure 15 An upper confinement layer 200 is formed in the opening 191.

[0145] The upper confinement layer 200 is also formed on the side of the insulating epitaxial layer 190 surrounding the opening 191 that is away from the semiconductor substrate layer 100; the process for forming the upper confinement layer 200 is an epitaxial process.

[0146] An upper confinement layer 200 is formed in the opening 191. The upper confinement layer 200 is strictly confined in the opening 191, forming a unique current channel and reducing the possibility of leakage at the edge of the active layer 131.

[0147] refer to Figure 16 A contact layer 210 is formed on the side of the upper limiting layer 200 opposite to the cover layer 171.

[0148] In some embodiments, the contact layer 210 is InP doped with conductive ions, and the doping concentration of the contact layer 210 is greater than the doping concentration of the upper confinement layer 200.

[0149] In this embodiment, the method further includes: forming a front electrode layer on the side of the contact layer 210 opposite to the upper confinement layer 200; and forming a back electrode layer on the side of the semiconductor substrate layer 100 opposite to the lower confinement layer 110.

[0150] Another embodiment of this application also provides a semiconductor laser, see reference. Figure 8 and Figure 16 The semiconductor laser includes a semiconductor substrate layer 100, a lower confinement layer 110, a ridge structure, an upper confinement layer 200, and an insulating epitaxial layer 190. The lower confinement layer 110 is located on one side of the semiconductor substrate layer 100 along the first direction; the ridge structure is located on the side of the lower confinement layer 110 away from the semiconductor substrate layer 100, and the ridge structure includes a lower waveguide layer 121, an active layer 131, an upper waveguide layer 141, a grating layer 161 and a capping layer 171 stacked sequentially in the first direction, and the capping layer 171 is located on the side of the grating layer 161 away from the upper waveguide layer 141; the upper confinement layer 200 is located on the side of the capping layer 171 away from the grating layer 161 and is in contact with the capping layer 171, and the size of the upper confinement layer 200 in the slow axis direction is larger than the size of the ridge structure in the slow axis direction; the insulating epitaxial layer 190 is located on both sides of the ridge structure and the upper confinement layer 200 in the slow axis direction, and the thermal conductivity of the insulating epitaxial layer 190 is greater than the thermal conductivity of the active layer 131.

[0151] In this embodiment, the capping layer is located on the side of the grating layer facing away from the upper waveguide layer. The insulating epitaxial layer is located not only on both sides of the ridge structure in the slow axis direction, but also on both sides of the upper confinement layer 200 in the slow axis direction. The insulating epitaxial layer has a larger growth thickness in the first direction, reducing growth defects in the insulating epitaxial layer. The capping layer protects the grating layer and the active layer. Furthermore, the size of the upper confinement layer 200 in the slow axis direction is larger than the size of the ridge structure in the slow axis direction; therefore, the portion of the upper confinement layer 200 located on both sides of the ridge structure in the slow axis direction and near the bottom surface of the ridge structure has high flatness. This protects the grating layer and the active layer from etching damage and reduces the occurrence of leakage current conduction.

[0152] In one embodiment, the capping layer 171 has a dimension of 500nm-1000nm in the first direction, such as 500nm, 800nm ​​or 1000nm.

[0153] In one embodiment, the material of the capping layer 171 is different from the material of the upper waveguide layer.

[0154] In one embodiment, the material of the lower waveguide layer 121 is In doped with conductive ions. x1 Ga 1-x1 As. The upper waveguide layer 141 is made of In doped with conductive ions. x1 Ga 1-x1 As.

[0155] In this embodiment, the material of the capping layer 171 includes InP doped with conductive ions.

[0156] In one embodiment, the capping layer 171 is larger in size in the first direction than the grating layer 161 and the upper waveguide layer 141 in the first direction. The capping layer 171 is thicker in the first direction, thus providing better protection for the grating layer and the active layer.

[0157] In one embodiment, the material of the upper limiting layer 200 is the same as that of the capping layer 171, thereby improving the growth quality of the upper limiting layer 200.

[0158] In one embodiment, the material of the upper confinement layer 200 may be InP doped with conductive ions.

[0159] In another embodiment, the material of the upper limiting layer 200 is different from the material of the cover layer 171.

[0160] In one embodiment, the active layer 131 is a superlattice structure, comprising a plurality of stacked sub-active layer groups. Each sub-active layer group includes, from bottom to top, a first sub-active layer unit to the Mth sub-active layer unit, where M is an integer greater than or equal to 2. Any mth sub-active layer unit includes, from bottom to top, a lower mth sub-active layer and an upper mth sub-active layer, where m is an integer greater than or equal to 1 and less than or equal to M. The material of the lower mth sub-active layer is In. x Ga (1-x) As, the material of the m-th sub-active layer is In. y Al (1-y) As.

[0161] In one embodiment, the material of the grating layer 161 includes In x2 Ga (1-x2) As.

[0162] The thermal conductivity of the active layer 131 along the plane perpendicular to the first direction is greater than the thermal conductivity of the active layer 131 along the first direction.

[0163] In one embodiment, the active layer 131 has a dimension of 2 to 6 micrometers in the slow axis direction, for example, 2 micrometers, 3 micrometers, 4 micrometers, 5 micrometers, or 6 micrometers. Because the active layer 131 has a smaller dimension in the slow axis direction, the degree of heat dissipation from the side is improved, thus reducing the junction temperature of the active layer 131 during operation. The electro-optical conversion efficiency of the semiconductor laser gradually increases as the width of the active layer 131 in the slow axis direction decreases. The smaller dimension of the active layer 131 in the slow axis direction results in a lower threshold current.

[0164] In one embodiment, the dimension of the surface of the active layer 131 facing the upper waveguide layer 141 in the slow axis direction is equal to the dimension of the surface of the upper waveguide layer 141 facing the active layer 131 in the slow axis direction, and the dimension of the surface of the active layer 131 facing the lower waveguide layer 121 in the slow axis direction is equal to the dimension of the surface of the lower waveguide layer 121 facing the active layer 131 in the slow axis direction. That is, no additional process is required to laterally etch the active layer 131, and there is no need to recess the active layer 131 relative to the upper waveguide layer 141 and the lower waveguide layer 121 in the slow axis direction to reduce leakage current paths.

[0165] In one embodiment, the semiconductor laser further includes a first semiconductor cutoff layer 151, which is located between the upper waveguide layer 141 and the grating layer 161. The material of the first semiconductor cutoff layer 151 is different from the material of the upper waveguide layer 141 and the material of the grating layer 161.

[0166] In one embodiment, the first semiconductor cutoff layer 151 has a dimension of 10nm-50nm in the first direction, such as 10nm, 20nm, 30nm, 40nm or 50nm.

[0167] In one embodiment, the material of the first semiconductor cutoff layer 151 is InP.

[0168] In one embodiment, the size of the first semiconductor cutoff layer 151 in the first direction is smaller than the size of the upper waveguide layer 141 in the first direction and smaller than the size of the grating layer 161 in the first direction.

[0169] In one embodiment, the portion of the insulating epitaxial layer 190 located on the side of the ridge structure opposite to the semiconductor substrate layer 100 has a dimension of 1μm-3μm in a first direction, such as 1μm, 2μm or 3μm.

[0170] In one embodiment, the insulating epitaxial layer 190 is made of Fe-doped InP. The insulating epitaxial layer 190 is non-conductive, and charge carriers in the active layer 131 do not pass through the insulating epitaxial layer 190.

[0171] In one embodiment, the molar concentration of Fe doping in the material of the insulating epitaxial layer 190 is 1 × 10⁻⁶. 16 atom / cm 3 ~1×10 18 atom / cm 3 The reason for doping the insulating epitaxial layer with Fe is that Fe is a dominant element in InP materials, which can effectively bind the free electrons in the intrinsic InP material, thus transforming the InP material from an intrinsic semiconductor material into a semi-insulating material.

[0172] In one embodiment, the portion of the insulating epitaxial layer 190 located on both sides of the upper limiting layer 200 in the slow axis direction has a dimension of 1μm-3μm along the first direction, for example, 1μm, 2μm or 3μm.

[0173] In one embodiment, reference Figure 8 The surface of the upper confinement layer 200 facing the semiconductor substrate layer 100 is flush with the surface of the capping layer 171 facing away from the semiconductor substrate layer 100. The high flatness of the bottom surface of the upper confinement layer 200 on both sides of the ridge structure in the slow axis direction protects the grating layer and active layer from etching damage and reduces the occurrence of leakage current conduction.

[0174] In one embodiment, reference Figure 16 The upper confinement layer 200 includes a first portion and a second portion. The first portion and the capping layer 171 have overlapping areas in the first direction. The second portion is located on the side of the first portion in the slow axis direction and is connected to the first portion. The connection surface between the first portion and the second portion is spaced apart from the capping layer 171 in the first direction. This improves the protection capability of the upper confinement layer 200 for the grating layer and the active layer.

[0175] The central region of the second part protrudes towards the semiconductor substrate 100 relative to the edge region of the second part. The edge regions of the second part are located on both sides of the central region of the second part in the slow axis direction. The lowest point of the bottom surface of the second part is far away from the grating layer and the active layer in the slow axis direction. The high flatness of the bottom surface of the edge region of the second part improves the protection capability of the grating layer and the active layer.

[0176] A portion of the insulating epitaxial layer 190 is located on the side of the second portion opposite to the first portion. Another portion of the insulating epitaxial layer 190 is located between the second portion and the lower limiting layer 110.

[0177] refer to Figure 8 and Figure 6 The second part has dimensions ranging from 5 to 30 micrometers in the slow axis direction, such as 5, 10, 15, 20, 25, or 30 micrometers. This balances the need for greater protection of the ridge structure with reduced cost.

[0178] In this embodiment, the semiconductor laser also includes a contact layer 210, which is located on the side of the upper limiting layer 200 opposite to the capping layer 171.

[0179] In some embodiments, the contact layer 210 is InP doped with conductive ions, and the doping concentration of the contact layer 210 is greater than the doping concentration of the upper confinement layer 200.

[0180] In this embodiment, the semiconductor laser further includes a front electrode layer and a back electrode layer. The front electrode layer is located on the side of the contact layer 210 away from the upper confinement layer 200; the back electrode layer is located on the side of the semiconductor substrate layer 100 away from the lower confinement layer 110.

[0181] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A method of manufacturing a semiconductor laser, characterized by, The preparation method comprises the following steps: forming a lower limiting layer on one side of a semiconductor substrate layer along a first direction; forming a ridge-shaped structure on the side of part of the lower limiting layer away from the semiconductor substrate layer, the ridge-shaped structure comprising a lower waveguide layer, an active layer, an upper waveguide layer, a grating layer and a cover layer stacked in sequence along the first direction, the cover layer being located on the side of the grating layer away from the upper waveguide layer; forming an insulating epitaxial layer on the side of the lower limiting layer away from the semiconductor substrate layer, the insulating epitaxial layer being located on the side of the ridge-shaped structure away from the semiconductor substrate layer and on both sides of the ridge-shaped structure in a slow axis direction, the thermal conductivity of the insulating epitaxial layer being greater than the thermal conductivity of the active layer; forming an opening in the insulating epitaxial layer, the opening exposing the cover layer, the size of the opening in the slow axis direction being greater than the size of the ridge-shaped structure in the slow axis direction; forming an upper limiting layer in the opening.

2. The method of claim 1, wherein the semiconductor laser is a vertical cavity surface emitting laser (VCSEL). The ridge-shaped structure formed on the side of part of the lower limiting layer away from the semiconductor substrate layer comprises: forming an initial ridge-shaped structure on the side of part of the lower limiting layer away from the semiconductor substrate layer, the initial ridge-shaped structure comprising an initial lower waveguide layer, an initial active layer, an initial upper waveguide layer, an initial grating layer and an initial cover layer; etching the initial ridge-shaped structure to form the ridge-shaped structure, the initial upper waveguide layer forming the upper waveguide layer, the initial active layer forming the active layer, the initial lower waveguide layer forming the lower waveguide layer, the initial grating layer forming the grating layer and the initial cover layer forming the cover layer.

3. The method of claim 2, wherein the semiconductor laser is a vertical cavity surface emitting laser (VCSEL). The size of the initial cover layer in the first direction is 500 nm-1000 nm.

4. The method of claim 2, wherein the semiconductor laser is a vertical cavity surface emitting laser (VCSEL). The initial ridge-shaped structure further comprises a first initial semiconductor cutoff layer, the first initial semiconductor cutoff layer being located between the initial upper waveguide layer and the initial grating layer; the material of the first initial semiconductor cutoff layer is different from the material of the initial upper waveguide layer and the material of the initial grating layer; In the process of etching the initial ridge-shaped structure, the first initial semiconductor cutoff layer forms a first semiconductor cutoff layer.

5. The method of claim 2, wherein the semiconductor laser is a vertical cavity surface emitting laser (VCSEL). The preparation method further comprises: forming a mask layer on the side of the initial ridge-shaped structure away from the semiconductor substrate layer; wherein etching the initial ridge-shaped structure comprises etching the initial ridge-shaped structure with the mask layer as a mask; wherein the preparation method further comprises: removing the mask layer before forming the insulating epitaxial layer.

6. The method of claim 1, wherein the semiconductor laser is a vertical cavity surface emitting laser (VCSEL). In the process of forming the insulating epitaxial layer, the size of the part of the insulating epitaxial layer located on the side of the ridge-shaped structure away from the semiconductor substrate layer in the first direction is 1 μm-3 μm.

7. The method of claim 1, wherein the semiconductor laser is a vertical cavity surface emitting laser (VCSEL). The upper limiting layer is further formed on the side of the insulating epitaxial layer around the opening away from the semiconductor substrate layer; the process of forming the upper limiting layer is an epitaxial process.

8. The method of claim 1, wherein the semiconductor laser is a vertical cavity surface emitting laser (VCSEL). The preparation method further comprises: forming a contact layer on the side of the upper limiting layer away from the cover layer.

9. The method of claim 1, wherein the semiconductor laser is a vertical cavity surface emitting laser (VCSEL). The process of forming the opening is an anisotropic dry etching process.

10. The method of claim 1, wherein the semiconductor laser is a vertical cavity surface emitting laser (VCSEL). The preparation method further comprises: forming a second semiconductor stop layer on a side of the cap layer away from the grating layer, the material of the second semiconductor stop layer being different from the material of the cap layer; The forming of the opening comprises: performing first etching by using an anisotropic dry etching process; and after the first etching, performing second etching by using a wet etching process until the second semiconductor stop layer is exposed. The preparation method further comprises: before forming the insulating epitaxial layer, removing the second semiconductor stop layer by using a wet etching process.

11. A semiconductor laser, characterized by comprising: The semiconductor laser further comprises: a semiconductor substrate layer; a lower limiting layer on a side of the semiconductor substrate layer along a first direction; a ridge-shaped structure on a side of part of the lower limiting layer away from the semiconductor substrate layer, the ridge-shaped structure comprising, in sequence along the first direction, a lower waveguide layer, an active layer, an upper waveguide layer, a grating layer, and a cap layer, the cap layer being on a side of the grating layer away from the upper waveguide layer; an upper limiting layer on a side of the cap layer away from the grating layer and in contact with the cap layer, the upper limiting layer having a dimension in a slow axis direction greater than a dimension of the ridge-shaped structure in the slow axis direction; an insulating epitaxial layer on both sides of the ridge-shaped structure and the upper limiting layer in the slow axis direction, the insulating epitaxial layer having a thermal conductivity greater than a thermal conductivity of the active layer.

12. The semiconductor laser of claim 11, wherein, The cap layer has a dimension in the first direction of 500 nm to 1000 nm.

13. The semiconductor laser of claim 11, wherein, The material of the cap layer is different from the material of the upper waveguide layer.

14. The semiconductor laser of claim 11, wherein, The material of the cap layer is the same as the material of the upper limiting layer.

15. The semiconductor laser of claim 11, wherein, The semiconductor laser further comprises a first semiconductor stop layer between the upper waveguide layer and the grating layer, the material of the first semiconductor stop layer being different from the material of the upper waveguide layer and different from the material of the grating layer.

16. The semiconductor laser of claim 11, wherein, The upper limiting layer comprises a first portion and a second portion, the first portion and the cap layer having an overlapping area in the first direction, the second portion being on a side of the first portion in the slow axis direction and connected to the first portion, a connecting surface of the first portion and the second portion being spaced apart from the cap layer in the first direction.

17. The semiconductor laser of claim 11, wherein, A side surface of the upper limiting layer facing the semiconductor substrate layer is flush with a side surface of the cap layer away from the semiconductor substrate layer.

18. The semiconductor laser of claim 11, wherein, A portion of the insulating epitaxial layer on both sides of the upper limiting layer in the slow axis direction has a dimension in the first direction of 1 μm to 3 μm.

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