A power tube driving circuit and a driver
By connecting a transmission gate in series with the source of the power transistor, the problem of slow response speed in traditional power transistor drive circuits is solved, enabling the development of high-frequency switching power supplies and reducing the footprint of the bootstrap capacitor.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NORTH-CHINA INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2025-10-22
- Publication Date
- 2026-05-08
AI Technical Summary
Traditional power transistor drive circuits have a large gate capacitance, resulting in a slow response speed, which limits the development of switching power supplies towards higher frequencies.
By connecting a transmission gate in series with the source of the power transistor, the transmission gate is driven, reducing the Miller plateau effect and reducing the area occupied by the bootstrap capacitor, thus achieving on-chip integration.
This improves the response speed and output signal frequency of the drive circuit, while reducing the overall space cost of the device.
Smart Images
Figure CN121441264B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic circuit technology, and in particular to a power transistor drive circuit and driver. Background Technology
[0002] The power transistor driver circuit is the core unit for load control and is widely used in applications such as control and modulation of switching power supplies. The power transistor driver circuit controls the switching of the transistors in the switching power supply and their on-time through the output signal, thereby regulating the output voltage of the switching power supply.
[0003] With the development of switching power supplies, there is a need for power transistor drive circuits to respond quickly and increase the frequency of the output signal to meet the requirements of the high-frequency development of switching power supplies. However, in the traditional method of using power transistor drive circuits to drive power transistors, the gate capacitance is often large due to the large rated power of the power transistors. This results in a long Miller plateau caused by the gate capacitance, which seriously affects the response speed of the power transistors and the switching power supply, thus restricting the development of switching power supplies towards higher frequencies. Summary of the Invention
[0004] This application provides a power transistor drive circuit and driver to solve the problem of slow response speed of the power transistor drive circuit and improve the frequency of the output signal of the drive circuit.
[0005] In a first aspect, embodiments of this application provide a power transistor driving circuit, including a transmission gate driving module, a transmission gate module, a bootstrap module, and a power transistor;
[0006] The first end of the bootstrap module is used to connect to the first power supply, and the second end of the bootstrap module is connected to the control terminal of the power transistor. The bootstrap module is used to drive the power transistor.
[0007] The first end of the transmission gate driver module is used to receive pulse signals, and the second end of the transmission gate driver module is connected to the control end of the transmission gate module. The transmission gate driver module is used to drive the transmission gate module to be in an on state or an off state according to the pulse signals.
[0008] The input terminal of the power transistor is used to connect to the second power supply, the output terminal of the power transistor is connected to the input terminal of the transmission gate module, and the output terminal of the transmission gate module is used to connect to the device to be driven.
[0009] In one possible implementation, the bootstrap module includes a bootstrap diode and a bootstrap capacitor;
[0010] The anode of the bootstrap diode is used to connect to the first power supply;
[0011] The cathode of the bootstrap diode is connected to the control terminal of the power transistor and the positive terminal of the bootstrap capacitor.
[0012] The positive terminal of the bootstrap capacitor is also connected to the positive terminal of the power supply of the transmission gate driver module;
[0013] The negative terminal of the bootstrap capacitor is connected to the output terminal of the transmission gate module and the negative terminal of the power supply of the transmission gate driver module.
[0014] In one possible implementation, the bootstrap module further includes a current-limiting resistor;
[0015] The cathode of the bootstrap diode is connected to the control terminal of the power transistor and the positive terminal of the bootstrap capacitor through the current-limiting resistor.
[0016] In one possible implementation, the transmission gate module includes a first switch and a second switch;
[0017] The input terminals of the first and second switching transistors are connected and serve as the input terminals of the transmission gate module.
[0018] The output terminals of the first and second switching transistors are connected and serve as the output terminals of the transmission gate module.
[0019] The output terminal of the transmission gate driver module is connected to the control terminal of the first switch and the control terminal of the second switch.
[0020] In one possible implementation, the first switch is an N-type switch and the second switch is a P-type switch;
[0021] Alternatively, the first switch is a P-type switch and the second switch is an N-type switch.
[0022] In one possible implementation, the driving circuit further includes a discharge tube driving module and a discharge tube;
[0023] The first end of the discharge tube driving module is used to receive the pulse signal, and the second end of the discharge tube driving module is connected to the control end of the discharge tube; the discharge tube driving module is used to drive the discharge tube to be in a conducting state or a turning-off state according to the pulse signal.
[0024] The input end of the discharge tube is connected to the output end of the transmission gate module;
[0025] The output terminal of the discharge tube is used for grounding.
[0026] In one possible implementation, the power transistor drive circuit further includes a level shifting module;
[0027] The input terminal of the level shifting module is used to receive the pulse signal;
[0028] The output of the level shifting module is connected to the first end of the transmission gate driver module.
[0029] In one possible implementation, the voltage of the second power supply is higher than the voltage of the first power supply;
[0030] The positive terminal of the low-voltage power supply of the level shifting module is used to connect to the first power supply;
[0031] The positive terminal of the high-voltage power supply of the level transfer module is used to connect to the positive terminal of the bootstrap capacitor;
[0032] The negative terminal of the power supply of the level shifting module is used to connect to the negative terminal of the bootstrap capacitor.
[0033] In one possible implementation, the driving circuit further includes an input stage module and a level shifting module;
[0034] The input terminal of the input stage module is used to receive the pulse signal;
[0035] The output of the input stage module is connected to the first end of the transmission gate driver module through the level shifting module.
[0036] Secondly, embodiments of this application provide a driver, including the power transistor drive circuit described in the first aspect or any possible implementation thereof.
[0037] The beneficial effects of the embodiments in this application compared with the prior art are:
[0038] In this embodiment, the first end of the bootstrap module is connected to a first power supply, and the second end is connected to the control terminal of the power transistor. The bootstrap module drives the power transistor, allowing it to be in a normally open state. The first end of the transmission gate driver module receives pulse signals, and the second end is connected to the control terminal of the transmission gate module. The transmission gate driver module can drive the transmission gate module. Due to the small gate capacitance and relatively small Miller plateau of the transmission gate module, a fast response can be achieved. The input terminal of the power transistor is connected to a second power supply, and the output terminal is connected to the input terminal of the transmission gate module. The output terminal of the transmission gate module is connected to the device to be driven. When the power transistor is normally open, the output signal can be modulated by controlling the transmission gate module, thereby improving the response speed of the driving circuit and increasing the frequency of the output signal. This application, by connecting the power transistor in series with the transmission gate module, transfers the output of the preceding driving module from the control terminal of the power transistor to the control terminal of the transmission gate, effectively reducing the Miller plateau effect caused by the gate capacitance of the high-power transistor and increasing the frequency of the driver's output signal. Attached Figure Description
[0039] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0040] Figure 1 This is a schematic diagram of the module structure of a traditional power transistor driver circuit;
[0041] Figure 2 This is a schematic diagram of the module structure of a power transistor drive circuit provided in an embodiment of this application;
[0042] Figure 3 This is a schematic diagram of the power transistor drive circuit provided in another embodiment of this application;
[0043] Figure 4 This is a schematic diagram of the structure of the input-level module provided in an embodiment of this application;
[0044] Figure 5 This is a schematic diagram of the level transfer module provided in an embodiment of this application;
[0045] Figure 6 This is a schematic diagram of the signals in the input stage module and level shifting module provided in the embodiments of this application;
[0046] Figure 7 This is a schematic diagram of the transmission gate driver module provided in an embodiment of this application;
[0047] Figure 8 This is a schematic diagram of the signals and output signals of the drive transmission gate module and the discharge tube provided in the embodiments of this application;
[0048] Figure 9 This is a schematic diagram of the simulation waveform of the power transistor drive circuit provided in the embodiments of this application. Detailed Implementation
[0049] To enable those skilled in the art to better understand this solution, the technical solutions in the embodiments of this solution will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this solution, not all of them. Based on the embodiments of this solution, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this solution.
[0050] The term "comprising" and any other variations thereof in the specification, claims, and accompanying drawings of this invention mean "including but not limited to," and are intended to cover a non-exclusive inclusion, not limited to the examples listed herein. Furthermore, the terms "first" and "second," etc., are used to distinguish different objects, not to describe a specific order.
[0051] The high-voltage NMOS driver mainly includes digital logic control, temperature and voltage protection, a level transfer module, and a final-stage power drive section. The final-stage power drive section primarily comprises a bootstrap capacitor and an output drive section. The inventors have discovered that as switching power supplies develop towards higher frequencies, the frequency requirements of the modulation system for these power supplies are also continuously increasing. When using a traditional drive structure that directly drives the final-stage power transistor using the output drive section, such as… Figure 1 As shown, the power transistor driver module directly drives the power transistor Q1. Because the rated power of the power transistor is relatively high, its gate capacitance is often also large, resulting in a long Miller plateau and a slow response speed, hindering the development of switching power supplies towards higher frequencies. Furthermore, the gate turn-on of the power transistor requires a large current, resulting in a correspondingly large bootstrap capacitor, typically in the microampere range. This leads to a huge footprint for the bootstrap capacitor, which is usually a discrete component, making on-chip integration difficult. Therefore, it is necessary to consider a new power transistor driver circuit.
[0052] To improve the response speed of power transistors, this embodiment connects a transmission gate in series with the source of the power transistor, converting the driving method of driving the power transistor gate into driving the transmission gate gate. Since the gate capacitance of the transmission gate is relatively small, the Miller plateau effect can be reduced, thereby increasing the frequency of the output signal and improving the response speed of the power transistor. Simultaneously, converting the driving method to drive the transmission gate gate effectively reduces the load requirements of the preceding drive stage, thus reducing the required bootstrap capacitor value, decreasing the footprint of the bootstrap capacitor, achieving on-chip integration, and reducing the overall device space cost.
[0053] To make the objectives, technical solutions, and advantages of this application clearer, the following description will be provided in conjunction with the accompanying drawings and specific embodiments.
[0054] Figure 2 The schematic diagram of the module structure of the power transistor drive circuit provided in the embodiments of this application is described in detail below:
[0055] The power transistor driving circuit provided in this application includes a transmission gate driving module, a transmission gate module, a bootstrap module, and a power transistor. The first terminal of the bootstrap module is connected to a first power supply, and the second terminal of the bootstrap module is connected to the control terminal of the power transistor. The bootstrap module drives the power transistor Q1. The first terminal of the transmission gate driving module receives a pulse signal, and the second terminal of the transmission gate driving module is connected to the control terminal of the transmission gate module. The transmission gate driving module drives the transmission gate module to be in an on or off state according to the pulse signal. The input terminal of the power transistor Q1 is connected to a second power supply, the output terminal of the power transistor Q1 is connected to the input terminal of the transmission gate module, and the output terminal of the transmission gate module is connected to the device to be driven.
[0056] Here, the power transistor Q1 can be a switching transistor such as a bipolar transistor or a metal-oxide-semiconductor field-effect transistor (MOS transistor). The first power supply can be a low-voltage power supply, and the second power supply can be a high-voltage power supply, with the voltage of the second power supply being higher than that of the first power supply. The device to be driven can be the component that needs to be driven in the switching power supply, such as the power transistor in the switching power supply.
[0057] Figure 2 In the diagram, VDD represents the first power input terminal, used to connect to the first power supply, and VB represents the second power input terminal, used to connect to the second power supply. The control terminal of power transistor Q1 is connected to the first power supply via a bootstrap module, and the input terminal of power transistor Q1 is connected to the second power supply. This means that when the first power supply is on, power transistor Q1 is always driven to conduct, and the gate capacitance of power transistor Q1 is always fully charged, unaffected by pulse signals. Therefore, power transistor Q1 will not experience a Miller plateau with changes in pulse signals, thus not affecting its response speed.
[0058] The output of power transistor Q1 is connected to the input of the transmission gate module. The output of the transmission gate module is used to connect to the device to be driven; that is, the output of the transmission gate module is the signal output terminal OUT of the power transistor driver circuit, used to output the drive signal to drive the device to be driven. In this embodiment, the output of the power transistor is not directly used as the signal output terminal OUT of the power transistor driver circuit to output the drive signal. Instead, the drive signal is output through the transmission gate module. By controlling the conduction and cutoff of the transmission gate module, the high and low levels in the drive signal output from the signal output terminal OUT are changed, that is, the frequency of the output drive signal is controlled.
[0059] When the transmission gate module is in the ON state, the second power supply output terminal VB, power transistor Q1, and transmission gate module are connected, both power transistor Q1 and transmission gate module are turned on, and the signal output terminal OUT outputs a high-level drive signal. When the transmission gate module is in the OFF state, the transmission gate module is disconnected, there is no current path between the input and output terminals of power transistor Q1, and the signal output terminal OUT outputs a low-level drive signal.
[0060] Figure 2 In the diagram, IN represents the signal input terminal of the power transistor driver circuit, used to input pulse signals. The transmission gate driver module can drive the transmission gate module to either be in a conducting or turning-off state based on the pulse signal. For example, when the pulse signal is high, the transmission gate driver module can drive the transmission gate module to be in a conducting state, causing the signal output terminal OUT of the power transistor driver circuit to output a high-level drive signal. When the pulse signal is low, the transmission gate driver module can drive the transmission gate module to be in a turning-off state, causing the signal output terminal OUT of the power transistor driver circuit to output a low-level drive signal.
[0061] Since the transmission gate module is connected to the second power supply through power transistor Q1, and power transistor Q1 still bears the power, the transmission gate module mainly functions as a switch control. Therefore, the gate capacitance in the transmission gate module is relatively small. When driving the transmission gate module, the gate capacitance in the transmission gate module can be charged quickly, resulting in less of the Miller plateau effect. Furthermore, the gate capacitance in power transistor Q1 is in a fully charged state, preventing the generation of a small Miller plateau, thereby improving the overall frequency characteristics of the device.
[0062] Optionally, the transmission gate module includes a first switch T1 and a second switch T2; the input terminal of the first switch T1 and the input terminal of the second switch T2 are connected and serve as the input terminal of the transmission gate module; the output terminal of the first switch T1 and the output terminal of the second switch T2 are connected and serve as the output terminal of the transmission gate module; the output terminal of the transmission gate drive module is connected to the control terminal of the first switch T1 and the control terminal of the second switch T2.
[0063] In this embodiment, a transmission gate module is set up by a first switch T1 and a second switch T2. The transmission gate driving module controls the first switch T1 and the second switch T2 to turn on and off, so that the transmission gate module is turned on or off, effectively transmitting and isolating signals, and realizing the output of driving signals.
[0064] Specifically, when both the first switch T1 and the second switch T2 are turned off, the transmission gate module is disconnected, and the input and output of the transmission gate module are in a high-impedance state. When at least one of the first switch T1 and the second switch T2 is turned on, the transmission gate module is turned on, and the input and output of the transmission gate module are in a low-impedance state.
[0065] Here, the first switch T1 can be an N-type switch and the second switch T2 can be a P-type switch; or, the first switch T1 can be a P-type switch and the second switch T2 can be an N-type switch. The first switch T1 and the second switch T2 can be transistors or MOSFETs, etc.
[0066] In this embodiment, the first end of the bootstrap module is connected to a first power supply, and the second end is connected to the control terminal of the power transistor. The bootstrap module drives the power transistor, allowing it to be in a normally open state. The first end of the transmission gate driver module receives pulse signals, and the second end is connected to the control terminal of the transmission gate module. The transmission gate driver module can drive the transmission gate module. Due to the small gate capacitance and relatively small Miller plateau of the transmission gate module, a fast response can be achieved. The input terminal of the power transistor is connected to a second power supply, and the output terminal is connected to the input terminal of the transmission gate module. The output terminal of the transmission gate module is connected to the device to be driven. When the power transistor is normally open, the output signal can be modulated by controlling the transmission gate module, thereby improving the response speed of the driving circuit and increasing the frequency of the output signal. This application, by connecting the power transistor in series with the transmission gate module, transfers the output of the preceding driving module from the control terminal of the power transistor to the control terminal of the transmission gate, effectively reducing the Miller plateau effect caused by the gate capacitance of the high-power transistor and increasing the frequency of the driver's output signal.
[0067] In some embodiments, such as Figure 2 As shown, the bootstrap module includes a bootstrap diode D1 and a bootstrap capacitor C1; the anode of the bootstrap diode D1 is used to connect to the first power supply; the cathode of the bootstrap diode D1 is connected to the control terminal of the power transistor Q1 and the positive terminal of the bootstrap capacitor C1; the positive terminal of the bootstrap capacitor C1 is also connected to the positive terminal of the power supply of the transmission gate driver module; the negative terminal of the bootstrap capacitor C1 is connected to the output terminal of the transmission gate module and the negative terminal of the power supply of the transmission gate driver module.
[0068] In this embodiment, the first power supply is connected to the positive terminal of the bootstrap capacitor C1 via a bootstrap diode D1, allowing the bootstrap capacitor C1 to be charged. After the bootstrap capacitor C1 is fully charged, the voltage of its positive terminal to ground is the voltage of the first power supply, while the voltage of its negative terminal to ground is 0V. That is, the voltage of the positive terminal of the bootstrap capacitor C1 relative to its negative terminal is the voltage of the first power supply.
[0069] When the transmission gate module is turned on, the second power supply is connected to the negative terminal of the bootstrap capacitor through the power transistor Q1 and the transmission gate module, which raises the voltage at the negative terminal of the bootstrap capacitor C1. At this time, the voltage of the negative terminal of the bootstrap capacitor C1 to ground is equal to the voltage of the second power supply. Since the voltage across the capacitor cannot change abruptly, the voltage of the positive terminal of the bootstrap capacitor C1 to ground is the sum of the voltages of the first power supply and the second power supply.
[0070] Here, due to the reverse cutoff effect of diode D1, the positive terminal of bootstrap capacitor C1 can be kept at the sum of the voltage of the first power supply and the voltage of the second power supply, ensuring that the voltage is stable for a long time.
[0071] Furthermore, the power supply capability of the bootstrap module depends on the size of the bootstrap capacitor. In this embodiment, the output of the pre-stage driver is transferred from the gate of the power transistor Q1 to the transmission gate. The transmission gate driver module only supplies power to the transmission gate switch. Since the transmission gate switch is small in size and fast in speed, the requirement for the output current of the pre-stage can be reduced while ensuring frequency characteristics. Therefore, the transmission gate driver module does not need excessive current output capability, and the capacitance requirement of the bootstrap capacitor C1 as the power supply can also be reduced accordingly. This reduces the area occupied by the bootstrap capacitor, achieves on-chip integration, and reduces the overall device space cost.
[0072] Optionally, the bootstrap module also includes a current-limiting resistor R1. The cathode of the bootstrap diode D1 is connected to the control terminal of the power transistor Q1 and the positive terminal of the bootstrap capacitor C1 through the current-limiting resistor R1.
[0073] In this embodiment, a current-limiting resistor R1 is provided in the bootstrap module to limit the magnitude of the current in the branch, preventing excessive current from burning out the connected components. Accordingly, after the bootstrap capacitor C1 is fully charged, the voltage to ground at the positive terminal of the bootstrap capacitor C1 is determined by the voltage of the first power supply and the resistance value of the current-limiting resistor R1.
[0074] In some embodiments, the driving circuit further includes a discharge tube driving module and a discharge tube Q2; the first end of the discharge tube driving module is used to receive pulse signals, and the second end of the discharge tube driving module is connected to the control terminal of the discharge tube Q2; the discharge tube driving module is used to drive the discharge tube Q2 to be in a conducting state or a turning-off state according to the pulse signals; the input terminal of the discharge tube Q2 is connected to the output terminal of the transmission gate module; the output terminal of the discharge tube Q2 is used to ground.
[0075] In this embodiment, the discharge tube Q2 can be a switching tube such as a transistor or a MOSFET, used to control whether the negative terminal of the bootstrap capacitor C1 and the output terminal of the transmission gate module are grounded.
[0076] Here, when the discharge tube Q2 is in the on state, the negative terminal of the bootstrap capacitor C1 and the output terminal of the transmission gate module are grounded, and the output terminal OUT of the power tube drive circuit outputs a low level; when the discharge tube Q2 is in the on state, the negative terminal of the bootstrap capacitor C1 and the output terminal of the transmission gate module are not grounded, and the output terminal OUT of the power tube drive circuit outputs a high level.
[0077] Based on this, when the transmission gate module is not conducting, the discharge transistor Q2 is conducting, charging the bootstrap capacitor C1, and the output terminal OUT of the power transistor driver circuit outputs a low level. When the transmission gate module is conducting and the discharge transistor Q2 is not conducting, the bootstrap capacitor C1 performs bootstrap voltage boosting, supplying power to the transmission gate driver module to continuously drive the transmission gate module, causing the output terminal OUT of the power transistor driver circuit to output a high level.
[0078] In some embodiments, the driving circuit further includes a level shifting module; the input of the level shifting module is used to receive pulse signals; the output of the level shifting module is connected to the first end of the transmission gate driving module.
[0079] In this embodiment, the driving circuit is also equipped with a level shifting module. The level shifting module can identify pulse signals and convert low-voltage pulse signals into corresponding high-voltage signals so that the subsequent transmission gate driving module can use the high-voltage signals to drive the transmission gate module.
[0080] Optionally, the voltage of the second power supply is higher than that of the first power supply; the positive terminal of the low-voltage power supply of the level transfer module is used to connect to the first power supply; the positive terminal of the high-voltage power supply of the level transfer module is used to connect to the positive terminal of the bootstrap capacitor; and the negative terminal of the power supply of the level transfer module is used to connect to the negative terminal of the bootstrap capacitor.
[0081] Here, a first power supply is used as the low-voltage power supply for the level transfer module, and a bootstrap capacitor is used as the high-voltage power supply for the level transfer module, so as to provide low-voltage and high-voltage power supplies for the level transfer module and ensure the normal operation of the level transfer module.
[0082] In other embodiments, see Figure 3 The schematic diagram of the module structure of the power transistor driving circuit provided in another embodiment is shown. The driving circuit also includes an input stage module and a level shifting module. The input terminal of the input stage module is used to receive pulse signals. The output terminal of the input stage module is connected to the first terminal of the transmission gate driving module through the level shifting module.
[0083] In this embodiment, the pulse signal input at the signal input terminal IN of the power transistor driver circuit is first transmitted to the input stage module. The input stage module processes the pulse signal to provide a stable and clean signal source for the subsequent level shifting module.
[0084] Here, the level shifting module is mainly used to boost the voltage of the signal from the low voltage at the front end to the high voltage required by the transmission gate module, so as to ensure that the transmission gate module can be reliably turned on and off. For details, please refer to the description in the above embodiments.
[0085] In addition, such as Figure 3 The positive terminal of the input stage module shown is used to connect to the first power supply, which then powers the input stage module.
[0086] Optionally, the driving circuit also includes a discharge tube driving module and a discharge tube; the first end of the discharge tube driving module is connected to the output end of the input stage module, and the second end of the discharge tube driving module is connected to the control end of the discharge tube; the discharge tube driving module is used to drive the discharge tube to be in a conducting state or a turning-off state; the input end of the discharge tube is connected to the output end of the transmission gate module; the output end of the discharge tube is used for grounding.
[0087] In this embodiment, the signal processed by the input stage module is transmitted to the discharge tube drive module so that the discharge tube drive module can control the discharge tube to turn on or off according to the stable signal. For specific control, please refer to the description in the above embodiment.
[0088] In some feasible embodiments, see Figure 4 The schematic diagram of the input stage module shown is shown. The input stage module includes nine NOT gates and two NAND gates. The nine NOT gates are INV1, INV2, INV3, INV4, INV5, INV6, INV7, INV8 and INV9. The two NAND gates are NAND1 and NAND2.
[0089] The input stage module mainly includes two branches. In one branch, the first NOT gate INV1, the second NOT gate INV2, the third NOT gate INV3, and the fourth NOT gate INV4 are connected in sequence. The input terminal of the first NOT gate INV1 is used to input pulse signals. The output terminal of the fourth NOT gate INV4 is connected to the first input terminal of the first NAND gate NAND1, and the output terminal of the first NOT gate INV1 is also connected to the second input terminal of the first NAND gate NAND1. The output terminal of the first NAND gate NAND1 is connected to the input terminal of the fifth NOT gate INV5.
[0090] In another branch, the sixth NOT gate INV6, the seventh NOT gate INV7, and the eighth NOT gate INV8 are connected in sequence; the input terminal of the sixth NOT gate INV6 is used to input pulse signals; the output terminal of the eighth NOT gate INV8 is connected to the first input terminal of the second NAND gate NAND2, the second input terminal of the second NAND gate NAND2 is also used to input pulse signals, and the output terminal of the second NAND gate NAND2 is connected to the input terminal of the ninth NOT gate INV9.
[0091] The output of the third NOT gate INV3 is grounded through the first capacitor C11, and the output of the seventh NOT gate INV7 is grounded through the second capacitor C12. When the output of the third NOT gate INV3 is high, the first capacitor C11 is charged, making the voltage across C11 the same as the high-level voltage. When the output of the seventh NOT gate INV7 is high, the second capacitor C12 is charged, making the voltage across C12 the same as the high-level voltage, thus extending the low-level duration. Correspondingly, when the output of the third NOT gate INV3 is low, the first capacitor C11 is discharged, allowing the input of the fourth NOT gate INV4 to remain high, extending the high-level duration. When the output of the seventh NOT gate INV7 is low, the second capacitor C12 is discharged, allowing the input of the eighth NOT gate INV8 to remain high, extending the high-level duration.
[0092] To facilitate the explanation of signal changes, the signals at nodes a, b, c, and d in the output stage module are selected for illustration. The output stage module includes four output terminals for transmitting four signals to the level shifting module: the input pulse signal (its corresponding port is designated as the first output terminal); the signal at node b (node b is designated as the second output terminal b); the signal at node c (node c is designated as the third output terminal c); and the signal at node d (node d is designated as the fourth output terminal d). Specifically, node a is the end connected to the output of the second capacitor C12 and the seventh NOT gate INV7; node b is the output of the first NOT gate (i.e., the second output terminal b); node c is the output of the ninth NOT gate INV9 (i.e., the third output terminal c); and node d is the output of the fifth NOT gate INV5 (i.e., the fourth output terminal d).
[0093] For the first branch, refer to Figure 6The waveform of the signal shown is as follows: When the pulse signal is high, the high-level pulse signal passes sequentially through the first NOT gate INV1, the second NOT gate INV2, the third NOT gate INV3, and the fourth NOT gate INV4. The first NOT gate INV1 outputs a low-level signal, the third NOT gate INV3 outputs a low-level signal, and the first capacitor C11 begins to discharge. Therefore, the input signal to the fourth NOT gate INV4 is high, and the output signal is low. When the first capacitor C11 discharges to a certain extent and no longer meets the requirement of a high level, the input signal to the fourth NOT gate INV4 becomes low, and the output signal becomes high, which can extend the high-level output time. The input signal to the fourth NOT gate INV4 and the output signal of the first NOT gate INV1 are input to the first NAND gate NAND1. The first NAND gate NAND1 outputs a high-level signal, which is then input to the fifth NOT gate INV5. The fifth NOT gate INV5 outputs a low-level signal. That is, when the pulse signal is high, the second output terminal b outputs a low-level signal, and the fourth output terminal d outputs a low-level signal.
[0094] When the pulse signal is low, it passes sequentially through the first NOT gate INV1, the second NOT gate INV2, the third NOT gate INV3, and the fourth NOT gate INV4. The first NOT gate INV1 outputs a high-level signal, the third NOT gate INV3 outputs a high-level signal, and the first capacitor C11 begins charging. While the first capacitor C11 is charging, the input to the fourth NOT gate INV4 is a low-level signal, and at this time, the fourth NOT gate INV4 outputs a high-level signal. The high-level signal output from the fourth NOT gate INV4 and the high-level signal output from the first NOT gate INV1 are input to the first NAND gate NAND1. The first NAND gate NAND1 outputs a low-level signal, and correspondingly, the fifth NOT gate INV5 outputs a high-level signal. When the first capacitor C11 has charged to a certain level, the input to the fourth NOT gate INV4 is a high-level signal, and at this time, the fourth NOT gate INV4 outputs a low-level signal. The signal input to the fourth NOT gate INV4 and the signal output from the first NOT gate INV1 are input to the first NAND gate NAND1. The first NAND gate NAND1 outputs a high-level signal, which is then input to the fifth NOT gate INV5. The fifth NOT gate INV5 outputs a low-level signal. That is, when the pulse signal is low, the second output terminal b outputs a high-level signal, and the fourth output terminal d first outputs a high-level signal, followed by a low-level signal. The length of the high-level signal output by the fourth output terminal d is determined by the capacitance value of the first capacitor C11.
[0095] For the second branch, refer to Figure 6The waveform of the signal shown is as follows: When the pulse signal is high, the high-level pulse signal passes sequentially through the sixth NOT gate INV6, the seventh NOT gate INV7, and the eighth NOT gate INV8. The seventh NOT gate INV7 outputs a high-level signal, and the second capacitor C12 begins to charge. While the second capacitor C12 is charging, the input to the eighth NOT gate INV8 is a low-level signal, and at this time, the eighth NOT gate INV8 outputs a high-level signal. The high-level signal output by the eighth NOT gate INV8 and the high-level pulse signal are input to the second NAND gate NAND2. The second NAND gate NAND2 outputs a low-level signal, and correspondingly, the ninth NOT gate INV9 outputs a high-level signal. When the second capacitor C12 is charged to a certain extent, the input to the eighth NOT gate INV8 is a high-level signal, and at this time, the eighth NOT gate INV8 outputs a low-level signal. The second NAND gate NAND2 outputs a high-level signal, and the ninth NOT gate INV9 outputs a low-level signal. That is, when the pulse signal is high, node a first outputs a low-level signal, and then outputs a high-level signal, as shown below. Figure 6 In this circuit, the signal at node a is a low-level signal when it is below a preset voltage and a high-level signal when it is above a preset voltage. The corresponding output of the eighth NOT gate INV8 (i.e., node a') first outputs a high-level signal, then a low-level signal. Similarly, the third output c first outputs a high-level signal, then a low-level signal. The length of the low-level signal output at node a and the length of the high-level signal output at the third output c are determined by the capacitance value of the second capacitor C12.
[0096] When the pulse signal is low, it passes sequentially through the sixth NOT gate (INV6), the seventh NOT gate (INV7), and the eighth NOT gate (INV8). The seventh NOT gate (INV7) outputs a low-level signal, the second capacitor (C12) begins to discharge, and the eighth NOT gate (INV8) outputs a low-level signal after its input becomes high. When the first capacitor discharges to a certain level and no longer meets the high-level requirement, the input signal to the eighth NOT gate (INV8) becomes low, and the output signal becomes high. The second NAND gate (NAND2) outputs a high-level signal, and the ninth NOT gate (INV9) outputs a low-level signal. In other words, when the pulse signal is low, node a outputs a high-level signal followed by a low-level signal. Correspondingly, the output terminal of the eighth NOT gate (INV8) (node a') first outputs a low-level signal, followed by a high-level signal. The third output terminal (c) outputs a low-level signal. The length of the high-level signal output by node a is determined by the capacitance value of the second capacitor (C12).
[0097] See Figure 5The schematic diagram shown illustrates the structure of the level shifting module. The module includes fourteen switching transistors, five NOT gates, and three resistors. The fourteen switching transistors are designated as follows: Fifth switch T5, Sixth switch T6, Seventh switch T7, Eighth switch T8, Ninth switch T9, Tenth switch T10, Eleventh switch T11, Twelfth switch T12, Thirteenth switch T13, Fourteenth switch T14, Fifteenth switch T15, Sixteenth switch T16, Seventeenth switch T17, and Eighteenth switch T18. The five NOT gates are designated as Eleventh NOT gate INV11, Twelfth NOT gate INV12, Thirteenth NOT gate INV13, Fourteenth NOT gate INV14, and Fifteenth NOT gate INV15.
[0098] like Figure 5 In this context, IN, b, c, and d represent the signals input to the output terminals of the corresponding input stage modules at those positions. For example, Figure 5 The IN part in the code represents the input pulse signal. Figure 5 In this context, 'b' represents the signal input to the second output terminal 'b' of the input stage module described above. Figure 5 In this context, 'c' represents the signal input to the third output terminal 'c' of the input stage module mentioned above. Figure 5 In this context, d represents the signal input to the fourth output terminal d of the input stage module mentioned above. Figure 5 In this context, VBST represents the positive terminal of the high-voltage power supply of the level transfer module, which is used to connect to the positive terminal of the bootstrap capacitor. Figure 5 VDD in the diagram represents the positive terminal of the low-voltage power supply of the level transfer module, which is used to connect to the first power supply VDD. Figure 5 In this context, VS represents the negative terminal of the high-voltage power supply of the level shifting module. The level shifting module primarily converts signals powered by a low-voltage power supply into signals powered by a high-voltage power supply. Specifically, it can boost the "GND~VDD" input signals into "VS~VBST" drive signals.
[0099] The level shifting module includes nodes 1, 2, 3, and 4. Node 2 corresponds to the control terminal of the eighteenth switch, and node 4 corresponds to the control terminal of the seventeenth switch. The signal at node 2 is obtained from the signal at node 1, and the signal at node 4 is obtained from the signal at node 3. For example... Figure 5As shown, the signal at node 1 passes through the eleventh NOT gate INV11 and the twelfth NOT gate INV12 to obtain the signal at node 2 as input. The signal at node 3 passes through the fourteenth NOT gate INV14 and the fifteenth NOT gate INV15 to obtain the signal at node 4 as input. Furthermore, the output of the twelfth NOT gate INV12 is also connected to the input of the thirteenth NOT gate INV13, with the output of the thirteenth NOT gate INV13 serving as the output of the level shifting module. The signal output by the thirteenth NOT gate INV13 is the signal output from the level shifting module to the transmission gate driver module.
[0100] Here, the four input signals are first used to control the conduction and cutoff of the fifth switch T5, the sixth switch T6, the seventh switch T7, and the eighth switch T8, thereby causing corresponding changes in the signals at nodes 1 and 3 in the level transfer module. Then, through the eleventh NOT gate INV11, the twelfth NOT gate INV12, the fourteenth NOT gate INV14, and the fifteenth NOT gate INV15, the changes in the signals at nodes 2 and 4 are obtained, realizing the signal changes in the level transfer module, and thus obtaining the signal output at the output terminal OUT' of the level transfer module.
[0101] See Figure 6 When the pulse signal input to the IN terminal is high, the fifth switch T5 is turned on, resulting in a low-level signal at node 1, and correspondingly, a low-level signal at node 2. Simultaneously, with a low-level signal at node b, the sixth switch T6 is turned off, resulting in a high-level signal at node 3, and correspondingly, a high-level signal at node 4. Furthermore, the output terminal OUT' of the level transfer module outputs a high-level signal.
[0102] When the pulse signal input at input terminal IN is low, the fifth switch T5 is turned off, resulting in a high-level signal at node 1, and correspondingly, a high-level signal at node 2. Simultaneously, the high-level signal at node b turns on the sixth switch T6, resulting in a low-level signal at node 3, and correspondingly, a low-level signal at node 4. Furthermore, the output terminal OUT' of the level transfer module outputs a low-level signal.
[0103] in addition, Figure 6 The schematic diagram is only used to reflect the signal phase switching and the logical relationship between signals. In actual circuits, there is a certain delay time (nanosecond level) between each signal.
[0104] See Figure 7The schematic diagram shown is of the transmission gate driver module, which includes seven NOT gates and two switching transistors. The seven NOT gates are the twenty-first NOT gate INV21, the twenty-second NOT gate INV22, the twenty-third NOT gate INV23, the twenty-fourth NOT gate INV24, the twenty-fifth NOT gate INV25, the twenty-sixth NOT gate INV26, and the twenty-seventh NOT gate INV27. The two switching transistors are the third switching transistor T3 and the fourth switching transistor T4.
[0105] The input terminal of the 21st NOT gate INV21 serves as the input terminal IN' of the transmission gate driver module, used to input the signal output by the level shift module. The 21st NOT gate INV21, the 22nd NOT gate INV22, the 23rd NOT gate INV23, and the 24th NOT gate INV24 are connected in sequence. The output terminal of the 24th NOT gate INV24 is connected to the control terminal of the third switch T3. The input terminal of the third switch T3 is connected to the power supply of the transmission gate driver module, i.e., the positive terminal of the bootstrap capacitor C1. The output terminal of the third switch T3 is connected to the input terminal of the 27th NOT gate INV27 and the input terminal of the fourth switch T4.
[0106] The output of the 22nd NOT gate INV22 is also connected in sequence to the 25th NOT gate INV25 and the 26th NOT gate INV26. The output of the 26th NOT gate INV26 is connected to the control terminal of the fourth switch transistor T4. The output of the fourth switch transistor T4 is grounded.
[0107] The connection point between the output of the third switch T3 and the input of the fourth switch T4 serves as the first output terminal OUT1 of the transmission gate driver module, and the output terminal of the twenty-seventh NOT gate INV27 serves as the second output terminal OUT2 of the transmission gate driver module. The first output terminal OUT1 and the second output terminal OUT2 are respectively connected to the control terminals of the first switch T1 and the second switch T2 in the transmission gate to control the conduction and cutoff of the first switch T1 and the second switch T2, thereby realizing the conduction and cutoff of the transmission gate.
[0108] In addition, the structure of the discharge tube drive module can be referred to Figure 7 The structure shown is the same as or similar to that of the transmission gate drive module. Taking an example where the first switch T1 in the transmission gate is an NMOS transistor, the second switch T2 is a PMOS transistor, and the discharge transistor is a high-voltage NMOS transistor, when the first output terminal OUT1 of the transmission gate drive module is connected to the first switch T1 and the second output terminal OUT2 is connected to the second switch T2, the second output terminal OUT2 of the discharge transistor drive module serves as the output terminal of the module, used to drive the discharge transistor Q2, thus realizing the coordination between the discharge transistor Q2, the transmission gate module, and the bootstrap capacitor C1.
[0109] like Figure 8As shown, when the signal output from the first output terminal OUT1 of the transmission gate driver module is low, the signal output from the second output terminal OUT2 is high, the transmission gate is closed, the discharge tube driver module outputs a high-level signal to drive the discharge tube to open, and at this time the OUT port of the power tube driver circuit is a low-level signal, i.e., a "0" level. When the signal output from the first output terminal OUT1 of the transmission gate driver module is high, the signal output from the second output terminal OUT2 is low, the transmission gate is open, the discharge tube driver module outputs a low-level signal to drive the discharge tube to close, and at this time the OUT port of the power tube driver circuit is a high-level signal, i.e., a "1" level.
[0110] In actual circuits, there is a dead time of about 50ns between the gate drive signal and the discharge tube drive signal. Figure 8 The dashed line indicates that this is to prevent the simultaneous application of large currents from burning out the chip or load.
[0111] In some specific embodiments, see Figure 9 The diagram shows a simulation waveform of the power transistor drive circuit. Figure 9 The solid yellow line represents the input square wave modulation signal with a pulse width of 5ns and an amplitude of 0~5V. The dashed red line represents the output waveform of a traditional power transistor driver circuit, in which the bootstrap capacitor has a capacitance of 1μF and the load is a 1Ω resistor. Figure 9 As can be seen from the diagram, due to the large gate capacitance of the driving transistor, the output waveform exhibits a Miller plateau of approximately 1ns, and the overall rise time is also around 3ns. The blue solid line represents the output waveform of the power transistor driving circuit provided in this application embodiment. The bootstrap capacitor in this power transistor driving circuit has a capacitance of 30nF, and the load is a 1Ω resistor. The output waveform almost does not have a Miller plateau, and the overall rise time is shortened to less than 0.3ns. Furthermore, the requirement for the bootstrap capacitor value is significantly reduced, enabling on-chip integration.
[0112] right Figure 1 The implementation of the traditional power transistor drive circuit architecture and the power transistor drive circuit architecture provided in the embodiments of this application are compared in detail, as shown in Table 1 below.
[0113] Table 1 Comparison of Implementation Status
[0114]
[0115] As can be seen, compared with the traditional power transistor gate driving method, the power transistor driving circuit provided in this application transfers the output of the previous stage driver from the power transistor gate to the transmission gate by connecting the power transistor source stage in series. This effectively reduces the load capacity requirement of the previous stage driver and the capacitance requirement of the bootstrap capacitor, thereby significantly reducing the overall device space cost. At the same time, it reduces the Miller plateau effect caused by the gate capacitance of the high-power transistor, improves the frequency characteristics of the overall device, and can increase the driving signal frequency to 200MHz.
[0116] In this embodiment, the first end of the bootstrap module is connected to a first power supply, and the second end is connected to the control terminal of the power transistor. The bootstrap module drives the power transistor, allowing it to be in a normally open state. The first end of the transmission gate driver module receives pulse signals, and the second end is connected to the control terminal of the transmission gate module. The transmission gate driver module can drive the transmission gate module. Due to the small gate capacitance and relatively small Miller plateau of the transmission gate module, a fast response can be achieved. The input terminal of the power transistor is connected to a second power supply, and the output terminal is connected to the input terminal of the transmission gate module. The output terminal of the transmission gate module is connected to the device to be driven. When the power transistor is normally open, the output signal can be modulated by controlling the transmission gate module, thereby improving the response speed of the driving circuit and increasing the frequency of the output signal. This application, by connecting the power transistor in series with the transmission gate module, transfers the output of the preceding driving module from the control terminal of the power transistor to the control terminal of the transmission gate, effectively reducing the Miller plateau effect caused by the gate capacitance of the high-power transistor and increasing the frequency of the driver's output signal. Meanwhile, the transmission gate driver module only supplies power to the transmission gate switch. Since the switching transistor of the transmission gate is small in size and fast in speed, the output current requirement of the front stage can be reduced while ensuring frequency characteristics. The capacitance requirement of the bootstrap capacitor, which serves as the power supply for the transmission gate driver module, can also be reduced accordingly. This reduces the area occupied by the bootstrap capacitor, enables on-chip integration, and reduces the overall space cost of the device.
[0117] This application also provides a driver and a switching power supply. For details not described in detail herein, please refer to the corresponding circuit embodiments described above.
[0118] In some embodiments, the driver may include the power transistor drive circuit as described in any of the above embodiments.
[0119] In some embodiments, the switching power supply may include a driver as described in the above embodiment, which can drive the switching transistors in the switching power supply.
[0120] Here, the switching power supply can be the power supply for the power amplifier.
[0121] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0122] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A power transistor drive circuit, characterized in that, It includes a transmission gate driver module, a transmission gate module, a bootstrap module, and a power transistor; The first end of the bootstrap module is used to connect to the first power supply, and the second end of the bootstrap module is connected to the control terminal of the power transistor. The bootstrap module is used to drive the power transistor. The first end of the transmission gate driver module is used to receive pulse signals, and the second end of the transmission gate driver module is connected to the control end of the transmission gate module. The transmission gate driver module is used to drive the transmission gate module to be in an on state or an off state according to the pulse signals. The input terminal of the power transistor is used to connect to the second power supply, the output terminal of the power transistor is connected to the input terminal of the transmission gate module, and the output terminal of the transmission gate module is used to connect to the device to be driven. The bootstrap module includes a bootstrap diode and a bootstrap capacitor; The anode of the bootstrap diode is used to connect to the first power supply; The cathode of the bootstrap diode is connected to the control terminal of the power transistor and the positive terminal of the bootstrap capacitor. The positive terminal of the bootstrap capacitor is also connected to the positive terminal of the power supply of the transmission gate driver module; The negative terminal of the bootstrap capacitor is connected to the output terminal of the transmission gate module and the negative terminal of the power supply of the transmission gate driver module. The driving circuit also includes a discharge tube driving module and a discharge tube; The first end of the discharge tube driving module is used to receive the pulse signal, and the second end of the discharge tube driving module is connected to the control end of the discharge tube; the discharge tube driving module is used to drive the discharge tube to be in a conducting state or a turning-off state according to the pulse signal. The input end of the discharge tube is connected to the output end of the transmission gate module; The output terminal of the discharge tube is used for grounding.
2. The power transistor drive circuit according to claim 1, characterized in that, The bootstrap module also includes a current-limiting resistor; The cathode of the bootstrap diode is connected to the control terminal of the power transistor and the positive terminal of the bootstrap capacitor through the current-limiting resistor.
3. The power transistor drive circuit according to claim 1, characterized in that, The transmission gate module includes a first switch and a second switch; The input terminals of the first and second switching transistors are connected and serve as the input terminals of the transmission gate module. The output terminals of the first and second switching transistors are connected and serve as the output terminals of the transmission gate module. The output terminal of the transmission gate driver module is connected to the control terminal of the first switch and the control terminal of the second switch.
4. The power transistor drive circuit according to claim 3, characterized in that, The first switching transistor is an N-type switching transistor, and the second switching transistor is a P-type switching transistor; Alternatively, the first switch is a P-type switch and the second switch is an N-type switch.
5. The power transistor drive circuit according to claim 1, characterized in that, The power transistor drive circuit also includes a level shifting module; The input terminal of the level shifting module is used to receive the pulse signal; The output of the level shifting module is connected to the first end of the transmission gate driver module.
6. The power transistor drive circuit according to claim 5, characterized in that, The voltage of the second power source is higher than the voltage of the first power source; The positive terminal of the low-voltage power supply of the level shifting module is used to connect to the first power supply; The positive terminal of the high-voltage power supply of the level transfer module is used to connect to the positive terminal of the bootstrap capacitor; The negative terminal of the power supply of the level shifting module is used to connect to the negative terminal of the bootstrap capacitor.
7. The power transistor drive circuit according to any one of claims 1 to 4, characterized in that, The driving circuit also includes an input stage module and a level shifting module; The input terminal of the input stage module is used to receive the pulse signal; The output of the input stage module is connected to the first end of the transmission gate driver module through the level shifting module.
8. A driver, characterized in that, The power transistor drive circuit includes any one of claims 1 to 7 above.
Citation Information
Patent Citations
Zero dead area grid driving circuit
CN102970015A
Level shifter and high-voltage half-bridge driver
CN118554940A