A method for improving surge capability between an RJ45 connector and a transformer

Abstract

This invention relates to the field of PCB layout and routing technology, and discloses a method and apparatus for improving the surge capability between an RJ45 connector and a transformer. The method includes: setting a non-metallic slot at the boundary between the primary and secondary sides of the transformer in the PCB area of ​​the transformer; placing the RJ45 connector in the PCB area of ​​an external interface socket away from the transformer; setting a preset straight-line distance between the RJ45 connector and the interface socket; and controlling the differential trace length from the RJ45 connector to the transformer within a preset differential trace length. The differential trace is thickened with a preset linewidth and kept continuous to reduce the accumulation of surge energy in the transmission path. This invention precisely aligns the slot with the inherent isolation axis of the transformer's primary and secondary windings, covering the central area where winding coupling is most concentrated, thus blocking the conduction path of surge energy through the parasitic capacitance between the windings.

Description

Technical Field

[0001] This invention relates to the field of PCB layout and routing technology, and in particular to a method and apparatus for improving the surge capability between an RJ45 connector and a transformer. Background Technology

[0002] In current PCB design, RJ45 interfaces are typically laid out based on available space. Near the RJ45 socket, a basic protection combination of a 1nF / 2kV capacitor and a 0Ω resistor is usually added—the 1nF / 2kV capacitor filters high-frequency interference, and the 0Ω resistor serves as a fault fuse or test point. To further enhance surge protection, additional ESD protection devices are added to the differential signal lines of network interfaces such as MDI-TN / MDI-TP and MDI-RP / MDI-RN. In practice, while using dedicated ESD devices like the AZ199-04S or placing ordinary ESD components near transformers and chips can effectively enhance ESD resistance, it increases PCB material costs and indirectly increases layout complexity. Summary of the Invention

[0003] This invention provides a method and apparatus for improving the surge capability between an RJ45 connector and a transformer, which can solve the technical problem that ordinary ESD components increase the material cost of the PCB and indirectly increase the layout difficulty.

[0004] To solve the above-mentioned technical problems, one technical solution adopted by the present invention is: to provide a method for improving the surge capability between an RJ45 connector and a transformer, the method comprising:

[0005] In the PCB area of ​​the transformer, a non-metallic slot is set at the boundary between the primary side and the secondary side of the transformer.

[0006] The RJ45 connector is placed in the PCB area of ​​the external interface socket away from the transformer. The preset straight-line distance between the RJ45 connector and the interface socket is set, and the differential trace length from the RJ45 connector to the transformer is controlled within the preset differential trace length. The differential trace is thickened with a preset line width and kept continuous to reduce the accumulation of surge energy in the transmission path.

[0007] Centered on the connection between the transformer and the RJ45 connector, a continuous isolation strip of a preset width extends to both sides, covering the entire differential trace area from the transformer to the RJ45 connector.

[0008] The Keepout area in all layers of the PCB area is cut out to prevent the placement of any copper foil, traces, vias or component pads.

[0009] The primary side of the transformer is connected to the protective ground in the corresponding PCB area, and the secondary side is connected to the signal ground. The two ground planes are physically separated by the Keepout area and are connected only by a single-point combination device to block the conduction path of surge energy on the ground plane.

[0010] Secondly, an apparatus for improving the surge capability between an RJ45 connector and a transformer is provided, comprising:

[0011] The module is configured to set non-metallic slots at the boundary between the primary and secondary sides of the transformer in the PCB area of ​​the transformer.

[0012] The distance setting module is used to set the RJ45 connector in the PCB area of ​​the external interface socket away from the transformer, set the preset straight-line distance between the RJ45 connector and the interface socket, and control the differential trace length from the RJ45 connector to the transformer within the preset differential trace length. The differential trace is thickened with a preset line width and kept continuous to reduce the accumulation of surge energy in the transmission path.

[0013] The isolation strip setting module is used to extend a continuous isolation strip of a preset width to both sides of the connection between the transformer and the RJ45 connector, covering the entire differential trace area from the transformer to the RJ45 connector.

[0014] The separator module is used to perform a cutout process in the Keepout area of ​​all layers in the PCB area, prohibiting the placement of any copper foil, traces, vias or component pads.

[0015] The module is used to connect the primary side of the transformer to the protective ground corresponding to the PCB area, and the secondary side to the signal ground. The two ground planes are physically separated by the Keepout area and are connected only by a single-point combination device to block the conduction path of surge energy on the ground plane.

[0016] The beneficial effects of this invention are as follows: By precisely aligning the slots with the inherent isolation axes of the transformer's primary and secondary windings, the central area where winding coupling is most concentrated is covered, blocking the conduction path of surge energy through the parasitic capacitance between windings. Simultaneously, the slots completely separate the PCB copper foil areas corresponding to the primary side (connected to PGND) and the secondary side (connected to DGND), preventing the copper foil from forming hidden conductive paths. This solves the isolation failure problem caused by "relying solely on winding isolation without effective PCB copper foil separation" in traditional designs, effectively cutting off the surge conduction path from both structural and electrical perspectives. The slot depth penetrates all PCB layers (signal layers, power layers, and ground layers), retaining only the substrate. This avoids the hidden conductive paths formed by traditional designs that "only slot the surface layer and do not hollow out the inner copper foil." Such hidden paths easily lead to residual surge energy that can be conducted to subsequent stages. The full-layer penetration design completely eliminates this risk, providing a fundamental and reliable isolation guarantee for the subsequent PHY chip. The slotted design, acting as a "basic isolation layer," forms a complete multi-layered protection loop with the front-end bidirectional TVS (ultra-fast response), primary-side TSS (surge discharge), and secondary-side common-mode inductor (interference suppression). The TVS diverts energy in the initial surge intrusion stage, the TSS discharges the remaining surge, the S1 slotted design blocks undischarged differential-mode surges, the Keepout isolation band weakens spatial coupling interference, and the common-mode inductor attenuates residual common-mode surges. Through the synergistic effect of these multiple components, the surge energy borne by the subsequent PHY chip is significantly reduced, decreasing the probability of chip damage due to surges. The slotted design works in conjunction with a single-point connection to the ground plane (0Ω resistor + high-frequency capacitor): the slotted design physically separates the protective ground (PGND) from the signal ground (DGND), and the single-point connection ensures consistent ground potential during normal operation while preventing "secondary interference" caused by surge energy coupling through the ground plane, thus guaranteeing the stability of network signal transmission. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating a method for improving the surge capability between an RJ45 connector and a transformer according to the first embodiment of the present invention.

[0018] Figure 2 This is a schematic diagram of the device for improving the surge capability between the RJ45 connector and the transformer according to the first embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0020] The terms “comprising” and “having”, and any variations thereof, used in this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but optionally includes steps or units not listed, or optionally includes other steps or units inherent to such process, method, product, or apparatus.

[0021] In this document, the term "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein are to be combined with other embodiments.

[0022] Figure 1 This is a flowchart illustrating a method for improving the surge capability between an RJ45 connector and a transformer according to the first embodiment of the present invention. Figure 1 As shown, the method includes:

[0023] Step S1: In the PCB area of ​​the transformer, a non-metallic slot is set at the boundary between the primary side and the secondary side of the transformer.

[0024] Step S2: Place the RJ45 connector in the PCB area of ​​the external interface socket away from the transformer, set the preset straight-line distance between the RJ45 and the interface socket, and control the differential trace length from the RJ45 connector to the transformer within the preset differential trace length. The differential trace is thickened with a preset line width and kept continuous to reduce the accumulation of surge energy in the transmission path.

[0025] Step S3: Using the connection between the transformer and the RJ45 connector as the center, extend a continuous isolation strip of a preset width to both sides to cover the entire differential trace area from the transformer to the RJ45 connector.

[0026] Step S4: Perform a cutout process in the Keepout area of ​​all layers in the PCB area to prohibit the placement of any copper foil, traces, vias or component pads.

[0027] Step S5: Connect the primary side of the transformer to the protective ground corresponding to the PCB area, and connect the secondary side to the signal ground. The two ground planes are physically separated by the Keepout area and are connected only by a single-point combination device to block the conduction path of surge energy on the ground plane.

[0028] By combining the design of "transformer isolation slotting + RJ45 connector layout optimization + full-layer keepout isolation + precise ground plane segmentation", the surge energy conduction path is blocked from both physical structure and electrical isolation aspects, reducing the interference of surges on the downstream PHY chip and main control module, and finally meeting the GB / T17626.5 (surge immunity) level 4 protection requirements, ensuring the stable operation of network interface circuits in complex scenarios such as lightning strikes and power grid fluctuations.

[0029] Step S1: By setting physical slots in the transformer PCB area, the creepage distance and electrical clearance between the primary side (RJ45 connection side) and the secondary side (PHY chip connection side) are significantly increased, structurally blocking the direct conduction of surge energy from the primary to the secondary side, and preventing surge breakdown of the isolation layer from affecting the subsequent circuit.

[0030] The slot location must be precisely positioned at the center axis within the transformer's silkscreen frame and aligned with the boundary between the primary and secondary windings inside the transformer. In practice, refer to the isolation lines marked on the transformer datasheet to determine the specific location to avoid isolation failure due to positioning deviation. The slot width must be ≥1mm (i.e., 40mil), which meets safety regulations regarding creepage distance and effectively prevents high-voltage surge breakdown. The slot depth must penetrate all copper foil layers of the PCB, including the top, bottom, and inner power and ground layers, retaining only the PCB substrate to ensure complete severing of conductive paths. The edges must be rounded with a radius ≥0.5mm to prevent surge energy from concentrating at sharp corners and causing point discharge, and also to prevent cracking due to stress concentration during PCB processing or use. The process requires that the slot be non-metallic, meaning there is no copper foil covering the slot, to prevent the formation of conductive paths that could lead to isolation failure.

[0031] First, switch to the Mechanical1 layer in the PCB design interface (or select a dedicated slotting layer according to company specifications). Use the "Rectangle Tool" to draw the slotting area, ensuring that the area completely covers the transformer primary-secondary boundary and leaves a gap of ≥0.2mm between the area and transformer pins and pads to avoid installation interference. After selecting the drawn rectangle, execute "Tools→Convert→Create Board Cutout from Selected Primitives" from the top menu. The system will automatically generate the board-level slotting. After completion, switch to the 3D view to visually check whether the slotting penetrates all copper foil layers and whether there are any interference issues with components. Finally, add the annotation "Non-plated Slot" to the "Drill Drawing" layer of the Gerber file to confirm the slotting process requirements to the manufacturer and avoid processing deviations.

[0032] If the slot location deviates from the primary-secondary boundary (e.g., biased towards the primary or secondary side), the isolation area on the non-biased side will be insufficient, and surges will still be conducted through the unisolated copper foil area, thus negating the isolation purpose of the slot. If the slot width is <1mm, it will result in insufficient creepage distance, and high-voltage surges will easily break through the isolation gap, leading to failure of safety tests. In actual design, the dimensions are repeatedly confirmed through software measurement tools.

[0033] Specifically, step S1 includes: slotting the isolation axis of the primary and secondary windings inside the transformer and covering the central area within the transformer silkscreen frame, with the slotted area completely separating the copper foil areas of the corresponding PCB areas on the primary and secondary sides. The slotting is non-metallic, without copper foil coverage, and the slotted area does not overlap with the transformer pins or pads to ensure the mechanical installation stability of the transformer; setting the slot width parameters, and according to the slot width parameters, the depth of the slot penetrates all layers (signal layer, power layer, ground layer) of the PCB area, with rounded corners at the slot edges to avoid tip discharge and stress concentration.

[0034] By creating non-metallic slots at the isolation axes of the primary and secondary windings inside the transformer, a dual effect of "physical structural isolation - PCB copper foil separation" is achieved: on the one hand, it aligns with the inherent isolation boundary of the windings, blocking surge energy from being conducted through coupling between the windings; on the other hand, it completely separates the corresponding PCB copper foil areas on the primary and secondary sides, preventing the copper foil from forming a conductive path. At the same time, through precise slot width and full-layer through-hole design, it meets the creepage distance requirements of safety regulations and ensures the mechanical installation stability of the transformer (no pin / pad interference).

[0035] First, obtain the "Winding Distribution Diagram" from the transformer datasheet to confirm the physical isolation axis (usually marked as "Isolation Line") between the primary (RJ45 side) and secondary (PHY side) windings. Use this axis as the slot centerline in the PCB design. If the datasheet does not mark this axis, measure the actual transformer winding pin distribution (the vertical line between the primary and secondary pins is the isolation axis). Ensure the deviation between the slot centerline and the winding isolation axis is ≤0.2mm (to avoid deviation leading to unisolated winding coupling areas). The slot area must simultaneously satisfy "covering the central area within the transformer silkscreen frame" and "completely separating the copper foil area": ​​the central area coverage should be 1 / 3 of the silkscreen frame width (e.g., if the silkscreen frame is 10mm wide, the slot should cover a 3-4mm wide central section), and the copper foil separation should ensure no overlap between the primary copper foil (connected to PGND) and the secondary copper foil (connected to DGND) on either side of the slot, with a spacing ≥ the slot width (to prevent copper foil edge creepage). The slot area should maintain a distance ≥0.2mm from all transformer pins and pads. The spacing (measured using the "Component Clearance" tool in PCB software) must not overlap to prevent solder from flowing into the slot during soldering and causing short circuits, or to prevent pin deformation due to stress during installation (affecting mechanical stability). For basic slot width selection, choose 1mm (40mil) for standard scenarios (operating voltage ≤30V), and 1.5-2mm (60-80mil) for industrial high-voltage scenarios (operating voltage 30-60V). The core principle is "slot width ≥ safety creepage distance requirement - pin spacing margin" (e.g., GB 4943.1 requires a creepage distance ≥0.7mm below 30V, therefore a 1mm slot width allows for a 0.3mm margin). Slot width and copper foil separation must match: slot width ≥ minimum spacing between the primary and secondary copper foil areas (e.g., if the copper foil edge spacing is 0.8mm, slot width ≥ 1mm) to ensure no "cross-slot connection" risk after slotting (avoiding copper foil residue causing isolation failure).

[0036] The slot depth must penetrate all layers of the PCB area, including the top layer, bottom layer, inner signal layers, power layers, and ground layers, retaining only the PCB substrate (checked using Altium Designer "3D View" to ensure no copper foil in any layer is removed). Slotting only on the surface layer is prohibited (as inner layer copper foil will form hidden conductive paths). Slot edges must be rounded with a radius R = 0.5-1mm (adjusted according to slot width: R = 0.5mm for 1mm slot width, R = 1mm for 2mm slot width) to avoid sharp corner discharge (surge energy easily concentrates at sharp corners and breaks down the air), and to reduce stress concentration on the PCB substrate (preventing cracking at the slot edges during high-temperature soldering or vibration). Marked "non-metallized," the inner wall of the slot must be free of any copper foil (the manufacturer must provide a "slot wall plating inspection report") to prevent the formation of primary-secondary conductive paths by the copper foil on the slot wall.

[0037] After importing the transformer package into the PCB design interface, execute the "Place→Line" command to draw the winding isolation axis on the "Mechanical1 layer" (based on the datasheet or actual measurement results) and label it "Isolation Axis". Switch to the "Top Layer", "Bottom Layer", and inner power / ground layers, and highlight the primary side copper foil area (connected to PGND) and the secondary side copper foil area (connected to DGND) with different colors to confirm the boundary between the two areas and ensure that the slots are completely separated (without intersection). Switch to the "Mechanical1 layer" and use the "RectangleTool" to draw the slot shape: with the isolation axis as the center line, draw a rectangle according to the determined slot width (e.g., 1mm) and coverage area (e.g., 3mm long), while adjusting the position so that the distance between the slot and the pin / pad is ≥0.2mm. Select the rectangle and execute "Tools→Convert→Create Board Cutout from SelectedPrimitives". In the pop-up dialog box, check "All". Layers (ensure full penetration), click "OK" to generate the slot; double-click the slot graphic, set "CornerRadius" to 0.5-1mm (rounded corner) in "Properties", and add the annotation "Non-plated Slot (Isolation AxiSAligned)"; switch to 3D view, rotate the view to check if the slot penetrates all layers, if it overlaps with pins / pads, and if the copper foil area is completely separated; execute "Tools→DesignRule Check", add "SlotTo Pad Clearance" rule (≥0.2mm) and "SlotTo Copper Clearance" rule (≥0.1mm) to ensure there are no violations.

[0038] Step S2: Keep the RJ45 connector away from the external interface socket (the most vulnerable entry point for surges) to reduce the interference of surges on the RJ45 through spatial radiation and electromagnetic coupling; at the same time, by controlling the trace length and width, reduce the accumulation of surge energy in the transmission path, thus balancing signal integrity and surge immunity.

[0039] The straight-line distance between the RJ45 and the external interface socket is ≥25.4mm (i.e., 1 inch). This distance keeps the RJ45 away from the direct surge area, reducing interference from spatial radiation coupling. The differential trace length from the RJ45 to the transformer is ≤25.4mm (1 inch), shortening the surge transmission path, reducing energy loss and attenuation on the conductor, and avoiding signal distortion caused by excessively long traces. The differential trace width is ≥0.3mm (12mil). Thicker traces reduce conductor impedance, decrease heat accumulation during surge current flow, and prevent conductor damage due to overheating. The length error of differential pairs in the same group is <5mil (0.127mm) to prevent signal distortion after surge impact due to time delay differences, thus affecting network data transmission. The trace routing uses 45° angles or rounded transitions to avoid sharp angles, as sharp angles easily cause signal reflection, and surge energy tends to concentrate at sharp corners, increasing the risk of breakdown.

[0040] Step S2 includes:

[0041] Determine the location of the external interface socket, place the RJ45 connector at the edge of the PCB area away from the socket, and use measuring tools to repeatedly confirm the preset straight-line distance between the RJ45 connector and the interface socket;

[0042] Routing begins from the differential pins of the RJ45 connector to the corresponding pins of the transformer. Routing parameters are set according to the preset trace width. After routing is complete, the interactive length adjustment tool is used to fine-tune the traces. By adding serpentine lines or other methods, the length of differential traces in the same group is ensured to be controlled within the preset differential trace length.

[0043] During the PCB layout phase, first determine the location of the external interface sockets, then place the RJ45 on the edge of the PCB away from the sockets. Use software "measurement tools" (such as Altium's "Measure Distance") to repeatedly confirm that the distance between them is ≥25.4mm. During the routing phase, select the "Differential Pair Routing Tool" and route from the differential pins (TX± / RX±) of the RJ45 to the corresponding pins of the transformer. Set the trace width to 0.3mm and the trace spacing to 0.6mm in the routing parameters (this parameter combination meets the 100Ω impedance requirement while ensuring signal integrity). After routing, use the "Interactive Length Tuning" tool to fine-tune the traces, ensuring that the length difference between differential pairs within the same group is <5mil by adding serpentine lines, etc.

[0044] Execute the top menu "Reports→Differential Pair Lengths" to generate a differential pair length report, and check whether the length error of each differential pair meets the requirements; at the same time, switch to the 2D view to check whether there are sharp angles, excessive vias, or other problems with the traces, and ensure that the traces are continuous without breaks to avoid surge energy not being properly discharged due to broken wires.

[0045] Step S3: Establish a dedicated isolation zone between the transformer and the RJ45 connector to further block the surge energy from spreading through space or wire coupling, and at the same time define the confirmation range for subsequent Keepout processing to ensure the thoroughness of isolation.

[0046] The isolation strip extends ≥50mil to both sides of the connection between the transformer and the RJ45 connector, forming a continuous area with a total width ≥100mil (2.54mm). This area completely covers all differential traces from the transformer to the RJ45 connector, ensuring that the entire trace is within the isolation protection range without any missing segments. A distance of ≥30mil is maintained between the isolation strip and other surrounding components (such as resistors and capacitors) to prevent surge interference coupling caused by components being too close to the isolation strip.

[0047] In the PCB design interface, switch to the "Keepout Layer" and use the "Rectangle Tool" to draw an isolation strip along the connection between the transformer and the RJ45. When drawing, first determine the midpoint of the connection, then extend it 50 mil to each side to ensure the total width meets the requirements. After drawing, use the "Select Connected Copper" tool to check if the isolation strip completely covers the differential traces. If there are any uncovered sections, adjust the isolation strip's range. Simultaneously, use the "Component Clearance" function to confirm that the spacing between the isolation strip and surrounding components is ≥30 mil. If there are conflicts, fine-tune the component positions.

[0048] Step S3 includes:

[0049] Switch to the Keepout area in the PCB design interface and draw an isolation strip along the line connecting the transformer and the RJ45 connector. When drawing, first determine the midpoint of the line, and then extend it to both sides to ensure that the total width meets the requirements.

[0050] After drawing, use tools to check whether the isolation band completely covers the differential traces. If there are uncovered sections, adjust the range of the isolation band. At the same time, check that the distance between the isolation band and the surrounding components is less than the preset distance (fine-tune the component positions if there is a conflict).

[0051] Step S4: Eliminate conductive paths within the isolation strip by hollowing out the entire layer, preventing surge energy from being conducted to other layers through copper foil, vias, etc., ensuring the electrical integrity of the isolation strip, and preventing signal interference from other layers from affecting the surge protection path.

[0052] The Keepout area completely overlaps with the isolation zone set in step S3 and covers all layers of the PCB, including the top layer, bottom layer, inner power layer, and inner ground layer, with no layers missing. After the cutout process, no copper foil (including power copper foil and ground copper foil), traces (signal traces and power traces), vias (metallized vias and non-metallized vias) and component pads may be placed within the isolation zone to ensure that there are no conductive structures within the isolation zone and to completely cut off the surge conduction path.

[0053] Step S4 includes:

[0054] In the Keepout area, draw the isolation strip graphic, and in the "Keepout Properties" dialog box of the graphic, select "All Layers" to ensure that the cutout area covers the entire layer;

[0055] Remove all conductive structures from the Keepout area. Conductive structures include at least: copper foil, traces, vias, or component pads.

[0056] After setup, check for any illegally placed conductive structures within the isolation zone. If any violations are found, delete or adjust them promptly.

[0057] In the "Keepout Layer" dialog box, select the isolation strip graphic drawn in step S3, double-click the graphic to open the "Keepout Properties" dialog box, and select "All Layers" in the "Layer" option to ensure that the cutout area covers the entire layer. In "Keepout Restrictions", check "Copper", "Traces", "Vias", and "Pads" to confirm that all conductive structures are prohibited. After setting, execute "Tools→DesignRule Check" (DRC check), check "Keepout Violations" in the check rules, and confirm that there are no illegally placed conductive structures within the isolation strip. If there are any violations, delete or adjust them in time.

[0058] Step S5: Physically isolate the protective ground from the signal ground by splitting the ground plane to prevent surge energy from being conducted to the signal system through the ground plane. At the same time, ensure consistent ground potential during normal operation by using a single-point connection, thus balancing surge resistance and signal stability.

[0059] The PCB area corresponding to the primary side of the transformer is connected to protective ground (PGND), which is used for rapid discharge of surge energy. The PCB area corresponding to the secondary side is connected to signal ground (DGND) to ensure the normal operation of signal devices such as the PHY chip. The two ground planes are physically separated by the Keepout area set in step S4, with the separation width consistent with the Keepout area width (≥100mil) to ensure no conductive path. The connection between the two ground planes is only allowed to be achieved through a single-point connection using a combination of a 0Ω resistor and a 100nF high-frequency capacitor. The 0Ω resistor ensures consistent ground potential during normal operation, while the 100nF high-frequency capacitor conducts rapidly during surge impact, assisting in the discharge of surge energy and preventing the formation of ground loops that could lead to surge energy diffusion.

[0060] Step S5 includes:

[0061] In the power / ground layer design, the ground plane is divided into PGND and DGND areas based on the primary and secondary boundaries of the transformer and the Keepout area, ensuring that the two areas do not overlap and are completely isolated through the Keepout area.

[0062] Reserve device pads at the edges of the two ground planes (near the Keepout area), connect the device to the ground plane through the device pads, check if there are any other conductive paths on the ground plane besides single-point connections, if so, delete the extra copper foil, and ensure that the connection is only made through the specified combination of devices.

[0063] In the power / ground plane design, first divide the ground plane into PGND and DGND areas based on the transformer primary / secondary boundary and the keepout area, ensuring that the two areas do not overlap and are completely isolated through the keepout area. Reserve component pads at the edges of the two ground planes (near the keepout area) and solder a "0Ω resistor + 100nF high-frequency capacitor" (choose a high-frequency MLCC type capacitor) to ensure the components are closely connected to the ground plane. After completion, execute "View→Connections→ShowNet Connections" to check if there are any conductive paths on the ground plane other than single-point connections. If so, delete the excess copper foil to ensure that connections are only made through the specified combination of components.

[0064] If the two ground planes are not isolated by the Keepout area, or if there are other conductive paths (such as extra copper foil or vias), surge energy will be conducted to the DGND area through the ground plane, interfering with signal devices. If the combination of "0Ω resistor + capacitor" is not used and only wires are used for direct connection, a ground loop will be formed, increasing the risk of surge coupling. In actual design, this is verified by both DRC checks and physical measurements.

[0065] Transformer slotting and full-layer keepout achieve physical isolation, blocking surge conduction paths; single-point ground plane connection and differential routing optimization provide electrical protection, reducing surge interference and energy accumulation. In actual design, strict control is exercised over the dimensional parameters of each step (such as slot width and isolation strip width) to avoid protection failure due to substandard parameters, ultimately ensuring that the network interface circuit meets industrial-grade surge protection requirements.

[0066] The method further includes:

[0067] A semiconductor discharge tube (TSS) is connected in series between the center tap on the primary side of the transformer and the protective ground (PGND) to achieve the initial discharge of lightning surge.

[0068] In the initial stage of a lightning surge (before energy dissipates), the rapid conduction characteristic of the TSS (Temperature Discharge Sequencer) directly discharges the surge energy to the protective ground (PGND), reducing the conduction of surge energy to the transformer secondary and subsequent circuits. The TSS selection should match the network interface's operating voltage and surge withstand requirements: 6-10V (compatible with the differential signal voltage of 100Base-TX / 1000Base-T network interfaces, avoiding false triggering during normal operation); surge withstand current: ≥10kA (8 / 20㎲ waveform, meeting the current requirements for level 4 lightning surges in GB / T17626.5); recovery time ≤1ms (rapidly recovering to a high-impedance state after the surge ends, avoiding interference with normal network signal transmission); surface mount packages such as SOD-123 and SOT-23 are preferred (saving PCB space and adapting to high-density layouts). The surge shield (TSS) is positioned close to the center tap pin on the primary side of the transformer, with a trace length ≤5mm between them (to shorten the surge transmission path and reduce energy loss); the trace width connecting the TSS to the center tap and PGND is ≥0.5mm (to meet the current carrying requirement of 10kA surge current and avoid overheating and melting of the wire); the PGND terminal of the TSS is directly connected to the PGND copper foil on the primary side, and the connection point is far away from the ground plane connection point of "0Ω resistor + capacitor" (to avoid surge energy coupling to DGND through the ground plane); the distance between the TSS and the transformer secondary side components (such as PHY chip and common mode inductor) is ≥50mil to prevent electromagnetic interference coupling during surge discharge.

[0069] Load the selected TSS package (e.g., SOD-123) into the PCB library and place it next to the center tap pin on the primary side of the transformer (distance ≤ 5mm). Use the "Rotation Tool" to connect one end of the TSS to the center tap pin on the primary side of the transformer and the other end to the PGND copper trace. Set the trace width to 0.5mm and avoid crossing other signal lines. Execute "Tools→DesignRule Check" and add a 50mil spacing limit between the TSS and secondary side components in the "Component Clearance" rule to check for any conflicts. Add the TSS identification and parameters (e.g., model, Vbo, surge current) to the schematic to ensure consistency between production and material selection.

[0070] The method further includes:

[0071] A TVS diode is connected between the differential signal pins of the RJ45 connector. The breakdown voltage matches the operating voltage of the network interface, and the diode quickly conducts and shunts the current when a surge pulse occurs.

[0072] To address the "ns-level rise" characteristic of surge voltage (the rise time of lightning surge voltage is typically 1-5ns), a TVS with a response time ≤1ns clamps the differential signal voltage at the moment of surge intrusion (within 1ns of the surge intrusion moment), preventing the downstream PHY chip (differential input withstand voltage is typically ≤20V) from being subjected to overvoltage impact. At the same time, by precisely matching the breakdown voltage with the operating voltage, it is ensured that the TVS is in a high-impedance state during normal operation, without affecting network signal transmission (the peak-to-peak value of the 100Base-TX / 1000Base-T differential signal is approximately 1.2-2V), achieving the dual goals of "rapid protection during surges and no interference during normal operation".

[0073] The breakdown voltage (Vbr) and operating voltage should be matched to meet the requirement that "TVS breakdown voltage > 1.5-2 times the maximum operating voltage of the network interface" to avoid false triggering of TVS conduction by normal signal fluctuations. For 100Base-TX / 1000Base-T network interfaces, the maximum operating voltage (peak-to-peak value) of the differential signal is about 2V, corresponding to an effective value of about 0.7V. Therefore, Vbr=5-8V should be selected (adjusted according to the "maximum differential input voltage" marked in the chip datasheet. For example, if the PHY chip is marked "maximum differential input voltage ±5V", then Vbr ≥ 7.5V, with a 2.5V margin). For industrial wide-temperature scenarios, the influence of temperature on Vbr should be considered (Vbr increases by about 0.5%-1% for every 10℃ increase in temperature). If the operating temperature range is -40℃ to 85℃, the lower limit of Vbr should be increased by 5%-8% when selecting a model (e.g., Vbr=6V at room temperature, Vbr=6.3-6.5V for wide-temperature scenarios). Do not select a model with Vbr < 5V (e.g., Vbr = 4.5V), as normal differential signal fluctuations (e.g., signal overshoot) can trigger TVS conduction, leading to a signal short circuit; do not select a model with Vbr > 8V (e.g., Vbr = 10V), as surge voltage can first exceed the PHY chip's withstand voltage (≤20V) before triggering TVS, rendering the protection meaningless.

[0074] The technical requirement for a response time ≤ 1ns is that the surge voltage rise time is typically 1-5ns. If the TVS response time is > 1ns (e.g., 2ns), the surge voltage will have already risen to over 20V before the TVS is turned on, and the PHY chip will have already been subjected to overvoltage impact, resulting in protection failure. Therefore, a TVS with a response time ≤ 1ns (typical value 0.5-0.8ns) must be selected to ensure that the clamping is completed before the surge voltage reaches the chip's withstand voltage.

[0075] According to the "Electrical Characteristics" section of the TVS datasheet, confirm that the "Response Time" parameter is marked as "≤1ns" (confirm whether it is a "typical value" or a "maximum value", and prioritize models with "maximum value ≤1ns", such as Littelfuse SMBJ6.5CA marked "Response Time: ≤1nS(max)"); exclude models with "no response time marked" or "marked as <5ns" (such as some domestic TVS only marked "fast response" without specific values, which may pose a risk of response delay).

[0076] In the datasheet, the "Response Time" under "Electrical Characteristics" is marked "Maximum value ≤ 1ns," ensuring immediate protection during transient interference. Models marked "Response Time: ≤1ns(max)," such as the Littelfuse SMBJ6.5CA, explicitly state this parameter in their datasheets and possess 600W peak pulse power, suitable for network interface surge protection scenarios. Models marked "Sub-nanosecond response" with a specific value ≤ 1ns, such as the Eaton SMBJ and SMCJ series, all indicate "Response time from 0V to minimum VBR is typically < 1.0ps," meaning the actual protection response speed meets the ≤ 1ns requirement. Low-capacitance compatible models, such as the ON Semiconductor NUP2105LT1G, have a response time < 1ns and a junction capacitance of only 3.5pF, suitable for high-speed signal line protection such as MDI differential lines, balancing surge resistance and signal integrity.

[0077] Models without a specific response time value, such as some domestically produced TVS devices that only indicate "fast response" or "fast transient suppression" without a clear time parameter, pose a risk of response delay and cannot guarantee the immediacy of surge protection. Models labeled "response time < 5ns" have an excessively large activation window for protection. When faced with high-speed transient interference such as lightning strikes or ESD, they cannot clamp the voltage in time, which can easily lead to damage to the downstream PHY chip.

[0078] The clamping voltage (Vc) should meet the requirement of "Vc≤80% of the maximum differential input voltage of the PHY chip". For example, if the chip withstands 20V, then Vc≤16V (it is recommended to choose Vc=12-15V, such as a TVS with Vbr=6.5V, where the typical value of Vc is 12V, which will clamp the voltage within a safe range during surges); the surge withstand power should meet the requirements of GB / T17626.5 Level 4, ≥400W (10 / 1000μS waveform) to ensure that it can withstand the energy impact of a single surge (to avoid the TVS being burned out); for packaging and parasitic parameters, SOD-323 and 0402 surface mount packages (parasitic inductance ≤0.5nH) should be preferred to avoid excessive parasitic inductance (such as TO-92 package parasitic inductance ≥5nH), which would delay the TVS conduction speed and offset the advantage of "response time ≤1ns".

[0079] The distance between the TVS and RJ45 pins must be ≤3mm (corresponding to a signal transmission time ≈0.01ns, much less than the TVS response time of 1ns). If the distance is >5mm (transmission time ≈0.017ns), although the transmission time is still short, the parasitic capacitance will increase (for every 1mm increase in trace, the parasitic capacitance increases by about 0.1pF), which can lead to a decrease in normal signal integrity. The trace width connecting the TVS and RJ45 pins should be ≥0.3mm (corresponding to a current carrying capacity ≥1A, with an instantaneous current exceeding 100A during surges, but the duration is only in the nS range, which a 0.3mm trace width can withstand), and the trace should be "straight-through without branches" to avoid the parasitic inductance generated by branches affecting the TVS conduction speed. If the TVS is bridged to ground (e.g., one end connected to TX+ and the other end connected to PGND), it will destroy the "balance characteristics" of the differential signal (normally, TX+ and TX- have opposite phases and equal amplitudes; bridging to ground will introduce common-mode noise), leading to an increase in the network transmission bit error rate (the measured bit error rate can be increased from...). Rise to Therefore, it must be strictly "connected between the ± pins of the same differential pair".

[0080] The method further includes:

[0081] A common-mode inductor (inductance value ≥ 100μH) is placed near the PHY chip connection side of the differential trace on the secondary side of the transformer to suppress common-mode interference caused by surges and avoid damage to downstream devices.

[0082] A common-mode inductor is placed near the PHY chip on the secondary side of the transformer. After the TVS shunt, TSS discharge, and physical isolation on the primary side, residual common-mode surge interference (such as common-mode voltage generated by lightning surge coupling) can still exist and be conducted to the PHY chip through the differential traces on the secondary side of the transformer. By placing a common-mode inductor with an inductance value ≥100μH near the PHY chip on the secondary side, its characteristics of "high impedance to common-mode signals and low impedance to differential-mode signals" can be utilized to attenuate the residual common-mode interference by ≥40dB (100MHz band), preventing damage to the differential input port of the PHY chip due to common-mode overvoltage, while not affecting the transmission of normal differential-mode network signals (100Base-TX / 1000Base-T).

[0083] The main frequencies of surge residual common-mode interference are concentrated in the 10kHz-100MHz range. When the inductance value is ≥100μH, the common-mode impedance in the 10kHz band is ≥62.8kΩ (impedance formula Z=2πfL), attenuating more than 90% of the low-frequency common-mode current. In the 100MHz band, although the impedance decreases due to core loss, the distributed capacitance of the inductor still achieves an attenuation of ≥20dB, meeting the common-mode interference tolerance requirements of the PHY chip (typically, the common-mode input voltage is ≤5V). The differential-mode frequencies of 100Base-TX / 1000Base-T network signals are concentrated below 10MHz. The differential-mode impedance of a 100μH inductor in the 10MHz band is only ≈6.28kΩ (far lower than the differential line characteristic impedance of 100Ω), which will not cause attenuation of normal signals or excessive delay (the measured delay increase is ≤1ns, far less than the standard allowable 5ns). The rated current (Ir) is ≥2 times the maximum operating current of the PHY chip. The differential input current of a 100Base-TX / 1000Base-T PHY chip is typically ≤100mA. Therefore, a common-mode inductor with Ir≥200mA is selected (to avoid inductor core saturation due to surge current or long-term operation, which would result in loss of common-mode rejection capability). The DC resistance (DCR) should be ≤5Ω (per winding). If DCR>10Ω, it will cause a differential signal voltage drop >100mV (calculated based on a 100mA current), which can trigger the signal amplitude detection threshold of the PHY chip, leading to link speed reduction. The parasitic capacitance (Cpar) should be ≤10pF (between windings). Excessive parasitic capacitance will create an "inductor-capacitor" resonance at high frequencies (e.g., 100MHz), causing a sharp drop in common-mode impedance and negating the inductor's suppression effect. Ferrite cores (e.g., Ni-Zn ferrite) are preferred for the core material, as they are effective in the 10kHz-100MHz range. The magnetic permeability stability in the frequency band is better than that of manganese-zinc magnetic cores, and the high-frequency loss is small, making it suitable for wide-band common-mode interference suppression.

[0084] The PCB layout and routing should be designed in a coordinated manner. The common-mode inductor should be installed close to the differential input pins of the PHY chip. The distance between the common-mode inductor and the differential input pins (such as TX±, RX±) of the PHY chip should be ≤5mm, and it should be located on the differential trace path of "transformer secondary-PHY chip", forming the order of "transformer secondary → common-mode inductor → PHY chip" (reverse arrangement is prohibited, i.e., the common-mode inductor should be close to the transformer secondary). If the common-mode inductor is far away from the PHY (e.g., the distance is >10mm), the trace between "common-mode inductor-PHY" will form an "antenna", recoupling spatial common-mode interference, resulting in a decrease in the interference suppression effect of more than 30%. The distance between the common-mode inductor and the PGND area on the primary side should be ≥50mil to avoid electromagnetic interference during primary-side surge discharge coupling to the common-mode inductor winding.

[0085] The TX± and RX± differential pairs of the transformer secondary winding pass through the two windings of the same core of the common-mode inductor, and the length difference between the two ends of the inductor is less than 3mm (to ensure the phase consistency of the differential signal and avoid introducing common-mode noise); the differential trace width from the common-mode inductor pin to the PHY chip is ≥0.3mm, and the spacing is 0.6mm (consistent with the trace parameters of the "transformer secondary-common-mode inductor" segment), maintaining a continuous 100Ω differential impedance to avoid signal reflection caused by impedance abrupt changes; vias are prohibited for the differential traces between the common-mode inductor and the PHY chip (vias will introduce common-mode parasitic inductance), and there should be no branches (branches will disrupt differential balance and generate common-mode signals); if the common-mode inductor has a metal casing grounding pin, connect it to DGND (signal ground) (do not connect it to PGND), and the grounding trace width is ≥0.3mm and the length is ≤3mm to avoid interference from casing coupling entering DGND through the grounding pin.

[0086] When a surge intrudes into the RJ45, a bidirectional TVS (≤1nS response) clamps the differential voltage, shunting 30%-50% of the surge energy; the remaining surge is conducted to the transformer primary, where a TSS (10kA withstand) discharges 60%-80% of the energy to PGND; transformer slotting and full-layer keepout block 10%-20% of undischarged differential-mode surges; a common-mode inductor with an inductance value ≥100μH attenuates more than 90% of residual common-mode surges, protecting the PHY chip; a single-point connection prevents surge energy from coupling through the ground plane, preventing secondary common-mode interference. Through layered protection, the interference of lightning surges (±8kV air discharge) on the PHY chip is reduced to a safe range, ensuring long-term stable operation of the network interface in complex industrial electromagnetic environments, while meeting the GB / T17626.5 Level 4 surge immunity requirements and 100Base-TX / 1000Base-T signal integrity standards.

[0087] This embodiment precisely aligns the inherent isolation axis of the transformer's primary and secondary windings through slotting, covering the central area where winding coupling is most concentrated, thus blocking the conduction path of surge energy through the parasitic capacitance between windings. Simultaneously, the slotting completely separates the PCB copper foil areas corresponding to the primary side (connected to PGND) and the secondary side (connected to DGND), preventing the copper foil from forming hidden conductive paths. This solves the isolation failure problem caused by "relying solely on winding isolation without effective PCB copper foil separation" in traditional designs, effectively cutting off the surge conduction path from both structural and electrical perspectives. The slotting depth penetrates all PCB layers (signal layers, power layers, and ground layers), retaining only the substrate, avoiding the hidden conductive paths formed by traditional "only surface slotting, inner copper foil not hollowed out"—such hidden paths easily lead to residual surge energy and conduction to subsequent stages. The full-layer penetration design completely eliminates this risk, providing a fundamental and reliable isolation guarantee for subsequent PHY chips. The slotted design, acting as a "basic isolation layer," forms a complete multi-layered protection loop with the front-end bidirectional TVS (ultra-fast response), primary-side TSS (surge discharge), and secondary-side common-mode inductor (interference suppression). The TVS diverts energy in the initial surge intrusion stage, the TSS discharges the remaining surge, the S1 slotted design blocks undischarged differential-mode surges, the Keepout isolation band weakens spatial coupling interference, and the common-mode inductor attenuates residual common-mode surges. Through the synergistic effect of these multiple components, the surge energy borne by the subsequent PHY chip is significantly reduced, decreasing the probability of chip damage due to surges. The slotted design works in conjunction with a single-point connection to the ground plane (0Ω resistor + high-frequency capacitor): the slotted design physically separates the protective ground (PGND) from the signal ground (DGND), and the single-point connection ensures consistent ground potential during normal operation while preventing "secondary interference" caused by surge energy coupling through the ground plane, thus guaranteeing the stability of network signal transmission.

[0088] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0089] In one embodiment, an apparatus for improving the surge capability between an RJ45 connector and a transformer is provided. This apparatus corresponds one-to-one with the method for improving the surge capability between an RJ45 connector and a transformer described in the above embodiments. Figure 2 As shown, the device for improving the surge capability between the RJ45 connector and the transformer includes a setting module 101, a distance setting module 102, an isolation strip setting module 103, a cutout processing module 104, and a separation module 105. Detailed descriptions of each functional module are as follows:

[0090] The module is configured to create a non-metallic slot at the boundary between the primary side (the side connected to the RJ45 connector) and the secondary side (the side connected to the PHY chip) of the transformer in the PCB area of ​​the transformer.

[0091] The distance setting module is used to set the RJ45 connector in the PCB area of ​​the external interface socket away from the transformer, set the preset straight-line distance between the RJ45 connector and the interface socket, and control the differential trace length from the RJ45 connector to the transformer within the preset differential trace length. The differential trace is thickened with a preset line width and kept continuous to reduce the accumulation of surge energy in the transmission path.

[0092] The isolation strip setting module is used to extend a continuous isolation strip of a preset width to both sides of the connection between the transformer and the RJ45 connector, covering the entire differential trace area from the transformer to the RJ45 connector.

[0093] The cutout module is used to perform cutout processing in the Keepout area of ​​all layers in the PCB area, prohibiting the placement of any copper foil, traces, vias or component pads.

[0094] The separation module is used to connect the primary side of the transformer to the protective ground corresponding to the PCB area, and the secondary side to the signal ground. The two ground planes are physically separated by the Keepout area and are connected only by a single-point combination device to block the conduction path of surge energy on the ground plane.

[0095] This embodiment precisely aligns the inherent isolation axis of the transformer's primary and secondary windings through slotting, covering the central area where winding coupling is most concentrated, thus blocking the conduction path of surge energy through the parasitic capacitance between windings. Simultaneously, the slotting completely separates the PCB copper foil areas corresponding to the primary side (connected to PGND) and the secondary side (connected to DGND), preventing the copper foil from forming hidden conductive paths. This solves the isolation failure problem caused by "relying solely on winding isolation without effective PCB copper foil separation" in traditional designs, effectively cutting off the surge conduction path from both structural and electrical perspectives. The slotting depth penetrates all PCB layers (signal layers, power layers, and ground layers), retaining only the substrate, avoiding the hidden conductive paths formed by traditional "only surface slotting, inner copper foil not hollowed out"—such hidden paths easily lead to residual surge energy and conduction to subsequent stages. The full-layer penetration design completely eliminates this risk, providing a fundamental and reliable isolation guarantee for subsequent PHY chips. The slotted design, acting as a "basic isolation layer," forms a complete multi-layered protection loop with the front-end bidirectional TVS (ultra-fast response), primary-side TSS (surge discharge), and secondary-side common-mode inductor (interference suppression). The TVS diverts energy in the initial surge intrusion stage, the TSS discharges the remaining surge, the S1 slotted design blocks undischarged differential-mode surges, the Keepout isolation band weakens spatial coupling interference, and the common-mode inductor attenuates residual common-mode surges. Through the synergistic effect of these multiple components, the surge energy borne by the subsequent PHY chip is significantly reduced, decreasing the probability of chip damage due to surges. The slotted design works in conjunction with a single-point connection to the ground plane (0Ω resistor + high-frequency capacitor): the slotted design physically separates the protective ground (PGND) from the signal ground (DGND), and the single-point connection ensures consistent ground potential during normal operation while preventing "secondary interference" caused by surge energy coupling through the ground plane, thus guaranteeing the stability of network signal transmission.

[0096] In the several embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as multiple units or components being combined or integrated into another system, or some features being ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interface, apparatus, or unit, and may be electrical, mechanical, or other forms.

[0097] Furthermore, in the various embodiments of the present invention, the functional units may be integrated into one processing unit, exist as separate physical units, or be integrated into one unit with two or more units. The integrated units described above may be implemented in hardware or as software functional units.

[0098] The above are merely embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for improving the surge capability between an RJ45 connector and a transformer, characterized in that, The method includes: In the PCB area of ​​the transformer, a non-metallic slot is set at the boundary between the primary side and the secondary side of the transformer. The RJ45 connector is placed in the PCB area of ​​the external interface socket away from the transformer. The preset straight-line distance between the RJ45 connector and the interface socket is set, and the differential trace length from the RJ45 connector to the transformer is controlled within the preset differential trace length. The differential trace is thickened with a preset line width and kept continuous to reduce the accumulation of surge energy in the transmission path. Centered on the connection between the transformer and the RJ45 connector, a continuous isolation strip of a preset width extends to both sides, covering the entire differential trace area from the transformer to the RJ45 connector. The Keepout area in all layers of the PCB area is cut out to prevent the placement of any copper foil, traces, vias or component pads. The primary side of the transformer is connected to the protective ground in the corresponding PCB area, and the secondary side is connected to the signal ground. The two ground planes are physically separated by the Keepout area and are connected only by a single-point combination device to block the conduction path of surge energy on the ground plane.

2. The method for improving the surge capability between an RJ45 connector and a transformer as described in claim 1, characterized in that, The method further includes the following steps after the primary side of the transformer, corresponding to the PCB area, is connected to protective ground, and the secondary side is connected to signal ground. The two ground planes are physically separated by a keepout area and connected only by a single-point combination device to block the conduction path of surge energy on the ground plane: A semiconductor discharge tube is connected in series between the center tap on the primary side of the transformer and the protective ground to complete the initial discharge of the lightning surge.

3. The method for improving the surge capability between an RJ45 connector and a transformer as described in claim 2, characterized in that, The method further includes the following steps after the primary side of the transformer, corresponding to the PCB area, is connected to protective ground, and the secondary side is connected to signal ground. The two ground planes are physically separated by a keepout area and connected only by a single-point combination device to block the conduction path of surge energy on the ground plane: A TVS diode is connected between the differential signal pins of the RJ45 connector. The breakdown voltage matches the operating voltage of the network interface, and the diode quickly conducts and shunts the current when a surge pulse occurs.

4. The method for improving the surge capability between an RJ45 connector and a transformer as described in claim 3, characterized in that, The method further includes the following steps after the primary side of the transformer, corresponding to the PCB area, is connected to protective ground, and the secondary side is connected to signal ground. The two ground planes are physically separated by a keepout area and connected only by a single-point combination device to block the conduction path of surge energy on the ground plane: A common-mode inductor is placed near the PHY chip connection side of the differential traces on the secondary side of the transformer to suppress common-mode interference caused by surges.

5. The method for improving the surge capability between an RJ45 connector and a transformer as described in claim 1, characterized in that, The step of setting a non-metallic slot at the boundary between the primary and secondary sides of the transformer in the PCB area of ​​the transformer includes: The isolation axis of the primary and secondary windings inside the transformer is slotted and the central area of ​​the transformer silkscreen frame is covered. The slotted area completely separates the copper foil area of ​​the corresponding PCB area of ​​the primary and secondary sides. The slotting is non-metallic and has no copper foil coverage. The slotted area does not overlap with the transformer pins and pads to ensure the mechanical installation stability of the transformer. Set the slot width parameter, and based on the slot width parameter, make the slot depth penetrate all layers of the PCB area. The slot edges adopt a rounded corner design.

6. The method for improving the surge capability between an RJ45 connector and a transformer as described in claim 1, characterized in that, The steps of placing the RJ45 connector in the PCB area of ​​the external interface socket away from the transformer, setting a preset straight-line distance between the RJ45 connector and the interface socket, and controlling the differential trace length from the RJ45 connector to the transformer within a preset differential trace length, wherein the differential trace is thickened with a preset line width and kept continuous to reduce the accumulation of surge energy in the transmission path, include: Determine the location of the external interface socket, place the RJ45 connector at the edge of the PCB area away from the socket, and use measuring tools to repeatedly confirm the preset straight-line distance between the RJ45 connector and the interface socket; Routing begins from the differential pins of the RJ45 connector to the corresponding pins of the transformer. Routing parameters are set according to the preset trace width. After routing is complete, the interactive length adjustment tool is used to fine-tune the routing. By adding serpentine lines, the length of differential traces in the same group is ensured to be controlled within the preset differential trace length.

7. The method for improving the surge capability between an RJ45 connector and a transformer as described in claim 1, characterized in that, The step of extending a continuous isolation strip of a predetermined width to both sides of the connection between the transformer and the RJ45 connector, covering the entire differential trace area from the transformer to the RJ45 connector, includes: Switch to the Keepout area in the PCB design interface and draw an isolation strip along the line connecting the transformer and the RJ45 connector. When drawing, first determine the midpoint of the line, and then extend it to both sides to ensure that the total width meets the requirements. After drawing, use tools to check whether the isolation band completely covers the differential traces. If there are uncovered sections, adjust the range of the isolation band. At the same time, check that the distance between the isolation band and the surrounding components is less than the preset distance.

8. The method for improving the surge capability between an RJ45 connector and a transformer as described in claim 1, characterized in that, The step of removing the keepout area in all layers of the PCB area to prevent the placement of any copper foil, traces, vias, or component pads includes: In the Keepout area, draw the isolation strip graphic, and in the "Keepout Properties" dialog box of the graphic, select "All Layers" to ensure that the cutout area covers the entire layer; All conductive structure arrangements, including at least one of copper foil, traces, vias, and component pads, are removed from the Keepout area. After setup, check for any illegally placed conductive structures within the isolation zone. If any violations are found, delete or adjust them promptly.

9. The method for improving the surge capability between an RJ45 connector and a transformer as described in claim 1, characterized in that, The primary side of the transformer is connected to the protective ground corresponding to the PCB area, and the secondary side is connected to the signal ground. The two ground planes are physically separated by a keepout area and connected only through a single-point combination device. The steps to block the conduction path of surge energy on the ground plane include: In the power / ground layer design, the ground plane is divided into PGND and DGND areas based on the primary and secondary boundaries of the transformer and the Keepout area, ensuring that the two areas do not overlap and are completely isolated through the Keepout area; Reserve device pads at the edges of the two ground planes, connect the devices to the ground planes through the device pads, check if there are any conductive paths on the ground planes other than single-point connections, if so, delete the excess copper foil, and ensure that the connection is only made through the specified combination of devices.

10. A device for improving the surge capability between an RJ45 connector and a transformer, characterized in that, The device includes: The module is configured to set non-metallic slots at the boundary between the primary and secondary sides of the transformer in the PCB area of ​​the transformer. The distance setting module is used to set the RJ45 connector in the PCB area of ​​the external interface socket away from the transformer, set the preset straight-line distance between the RJ45 connector and the interface socket, and control the differential trace length from the RJ45 connector to the transformer within the preset differential trace length. The differential trace is thickened with a preset line width and kept continuous to reduce the accumulation of surge energy in the transmission path. The isolation strip setting module is used to extend a continuous isolation strip of a preset width to both sides of the connection between the transformer and the RJ45 connector, covering the entire differential trace area from the transformer to the RJ45 connector. The cutout module is used to perform cutout processing in the Keepout area of ​​all layers in the PCB area, prohibiting the placement of any copper foil, traces, vias or component pads. The separation module is used to connect the primary side of the transformer to the protective ground corresponding to the PCB area, and the secondary side to the signal ground. The two ground planes are physically separated by the Keepout area and are connected only by a single-point combination device to block the conduction path of surge energy on the ground plane.

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