Synchronizer flip-flop circuit

Abstract

Embodiments disclosed herein relate to synchronizing signals across multiple independent clock domains. In an example, a synchronizer flip-flop circuit is provided. A synchronizer flip-flop circuit (100) includes: a first latch sub-circuit (112) coupled to receive input data (101); and a second latch sub-circuit (117) coupled to the first latch sub-circuit (112). The first latch sub-circuit (112) includes: a first inverter group; a first diode connected transistor (113) coupled in parallel to each of the inverters in the first group of inverters and configured to provide a first bias voltage to each of the inverters in the first group of inverters; and a second diode-connected transistor (114) coupled in parallel to each of the inverters in the first group of inverters and configured to provide a second bias voltage to each of the inverters in the first group of inverters.

Description

[0001] This article mainly deals with flip-flop circuits used to synchronize data across multiple clock domains. Background Technology

[0002] In electronic systems containing digital circuits and integrated circuits, clock signals generated by oscillators can be used to synchronize the functions of the circuit system. Essentially, clock signals help circuits operate or reset simultaneously, which can improve the performance of individual circuits and the electronic system as a whole. Clock signals are electronic logic signals that transition between logic low ("0") or "off" and logic high ("1") or "on" states based on a duty cycle. Edge-triggered circuitry can be triggered to become active during the transition cycles between 0 and 1 (or the rising edge) and between 1 and 0 (or the falling edge).

[0003] In digital logic circuits, flip-flops and latches can be included to store state information and ensure the proper ordering of logic within the electronic device. Furthermore, flip-flops can be used to synchronize logic across multiple clock domains. The output of a flip-flop can change at specific times determined by the state of a clock signal (e.g., switching the state from "0" to "1" and from "1" to "0"). Outside of these times, the flip-flop retains its current state. In this way, flip-flops store state data, such as "0" or "1," based on the state of the clock signal and the state of the data input.

[0004] An example of a flip-flop that can be used for clock domain synchronization is the D flip-flop. A D flip-flop can contain multiple stages of latches, each handling both clock and data signals. When the data signal changes state, the latch stores the latest state of the data signal. Some instances of D flip-flops further include a primary latch and a secondary latch, each of which may contain multiple inverters capable of storing state information. The primary latch controls the output value of the secondary latch, or in other words, controls which state is stored at a given time, because the secondary latch only changes its value in response to a change in the value of the primary latch.

[0005] However, the problem is that existing synchronizer flip-flops (including D flip-flops) have latency, which affects the speed at which the flip-flop can stabilize and store data when the state of the data input and clock signal changes. Some solutions to this problem involve introducing more inverter stages into the flip-flop to increase the mean time between failures, or the amount of time between expected failures of the flip-flop. However, this requires additional area and cost. Summary of the Invention

[0006] The various embodiments disclosed herein relate to flip-flop circuits for synchronizing data in circuits operating in different clock domains, and more particularly to inverters that provide a bias voltage to the flip-flop circuit to reduce the threshold voltage of the inverter's transistors and increase the data latching efficiency of the inverter. In an exemplary embodiment, a circuit arrangement is provided. The circuit arrangement includes a first latch sub-circuit coupled to receive an input; and a second latch sub-circuit coupled to the first latch sub-circuit. The first latch sub-circuit includes a first set of inverters comprising a first set of transistors of a first type and a second set of transistors of a second type; a first diode-connected transistor coupled to the body of each transistor in the first set of transistors; and a second diode-connected transistor coupled to the body of each transistor in the second set of transistors.

[0007] The present invention is provided to introduce, in a simplified form, a series of concepts further described in the detailed embodiments below. It is to be understood that the present invention is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Attached Figure Description

[0008] Figure 1 An exemplary synchronizer trigger circuit according to an embodiment is illustrated.

[0009] Figure 2 An exemplary synchronizer trigger circuit according to an embodiment is illustrated.

[0010] Figure 3 Exemplary aspects of the components of a synchronizer trigger circuit according to an embodiment are illustrated, along with a related graphical representation of voltage changes in those components.

[0011] Figure 4 An exemplary operating environment for performing logic with a synchronizer trigger circuit is illustrated according to an embodiment.

[0012] The drawings are not necessarily drawn to scale. In the drawings, similar reference numerals are used across several views to indicate corresponding parts. In some embodiments, components or operations may be divided into different blocks or combined into a single block.

[0013] Specific implementation aspects

[0014] Embodiments of this disclosure are described in specific contexts, such as in synchronizer trigger circuits, primary-secondary latch circuits, digital logic and inverter circuit systems, etc. Some embodiments may use other circuits, digital logic components, topologies, and applications that exhibit increased transistor efficiency, increased mean time between failures, and other characteristics based on reducing the threshold voltage of the transistor.

[0015] This paper discusses enhanced components, techniques, and systems relating to flip-flop circuits for synchronizing logic in circuits operating in different clock domains relative to each other, and more particularly to inverters that provide a bias voltage to the flip-flop circuit to reduce the threshold voltage of the inverter's transistors and increase the latch resolution efficiency of the inverter when operating to synchronize such logic. In electronic systems, clock generation systems can provide clock signals that can be used to synchronize the operation of digital circuit systems. Importantly, synchronizing digital circuit systems with clock signals allows digital circuit system components to perform sequential logic operations and other functions. For this purpose, flip-flops and latches can be implemented to store state data of the digital circuit system. In systems comprising multiple digital circuits, each operating in conjunction with different clock signals, or in other words, in different clock domains, synchronizer flip-flops can be used to synchronize data signals that can be provided by digital circuits in one clock domain to digital circuits in another clock domain (i.e., across clock domains).

[0016] Flip-flops and latches are examples of logic components within a digital circuit system that store state data (e.g., "0" or "1") based on inputs (e.g., input data signals) to the flip-flop at times specified by a clock signal. Some exemplary flip-flops include one or more inverters that can be triggered by a clock signal to store the state of the input data signal. After a change in state from 0 to 1 or from 1 to 0, the inverters may take some time to resolve or store the state data. For example, the flip-flop may currently be storing the value 1. When the data signal changes from 1 to 0, the flip-flop can be triggered to store the value 0. However, for a period of time, the output of the flip-flop may be in a metastable state with values ​​between 0 and 1. The time it takes for the flip-flop to resolve the metastable output and store the new value 0 is called the resolution time. If the inverters cannot resolve the data fast enough, the digital circuitry that performs logic based on the state data may fail. The amount of time between such failures is called the Mean Time Between Failures (MTBF). To increase the MTBF, exemplary flip-flops may use a large number of inverters to help ensure that the inverters resolve the data before a failure. However, the problem is that increasing the number of inverters in a flip-flop can increase latency in the overall digital circuit design, the cost of additional components, and the area overhead relative to the number of signals spanning the clock domain.

[0017] Alternatively, as disclosed herein, a synchronizer flip-flop may comprise two or more inverters coupled in series or in a multi-stage or hierarchical inverter configuration. Each inverter may comprise two transistors coupled together, and each transistor may be biased by a diode-connected transistor. The bias voltage reduces the threshold voltage of each transistor in the inverter, which effectively reduces the time required for the transistors to parse data when a data signal changes the state from 0 to 1 or from 1 to 0. Advantageously, such circuitry reduces latency within the flip-flop circuitry, latency throughout the entire digital circuitry implementing logic based on the data stored in the flip-flop circuitry, and design costs by avoiding a large number of inverters and by generating this bias voltage without using an external power supply.

[0018] In an exemplary embodiment, a circuit arrangement is provided. The circuit arrangement includes a first latch sub-circuit coupled to receive an input; and a second latch sub-circuit coupled to the first latch sub-circuit. The first latch sub-circuit includes a first set of inverters comprising a first set of transistors of a first type and a second set of transistors of a second type; a first diode-connected transistor coupled to the body of each transistor in the first set of transistors; and a second diode-connected transistor coupled to the body of each transistor in the second set of transistors.

[0019] In another exemplary embodiment, a synchronizer trigger circuit is provided. The synchronizer trigger circuit includes a first latch sub-circuit coupled to receive an input; and a second latch sub-circuit coupled to the first latch sub-circuit. The first latch sub-circuit includes a first inverter group; a first diode-connected transistor coupled in parallel to each inverter in the first inverter group and configured to provide a first bias voltage to each inverter in the first inverter group; and a second diode-connected transistor coupled in parallel to each inverter in the first inverter group and configured to provide a second bias voltage to each inverter in the first inverter group.

[0020] In yet another exemplary embodiment, a synchronizer trigger circuit is provided. The synchronizer trigger circuit includes a first latch sub-circuit coupled to receive an input; and a second latch sub-circuit coupled to the first latch sub-circuit. The first latch sub-circuit includes a first inverter group; a first diode-connected transistor coupled in parallel to each inverter in the first inverter group and configured to provide a first bias voltage to each inverter in the first inverter group; and a second diode-connected transistor coupled in parallel to each inverter in the first inverter group and configured to provide a second bias voltage to each inverter in the first inverter group. The second latch subcircuit includes a second inverter group; a third diode-connected transistor coupled in parallel to each inverter in the second inverter group and configured to provide a third bias voltage to each inverter in the second inverter group; and a fourth diode-connected transistor coupled in parallel to each inverter in the second inverter group and configured to provide a fourth bias voltage to each inverter in the second inverter group.

[0021] Figure 1 An exemplary synchronizer trigger circuit according to an embodiment is illustrated. Figure 1 The system includes a synchronizer trigger circuit 100, which includes a multiplexer 110, transmission gates 111, 115, 116 and 120, a main latch sub-circuit 112, diode-connected transistors 113 and 114, a secondary latch sub-circuit 117, diode-connected transistors 118 and 119, and a logic device 121.

[0022] Synchronizer flip-flop 100 represents a dual latch (i.e., master-slave latch) circuit capable of resolving a single bit-level signal (input data 101) provided by a digital circuit (not shown). Synchronizer flip-flop 100 can be used to store the state of input data 101 (e.g., "0", "1") and downstream provide the stored state data to different digital circuits (not shown) operating in different clock domains relative to the digital circuit providing input data 101 to synchronizer flip-flop 100. Therefore, synchronizer flip-flop 100 can be used to synchronize signals used by two or more digital circuits in different clock domains to a single clock cycle.

[0023] Synchronizer flip-flop 100 includes a multiplexer 110, which is coupled to receive input data 101 (from digital circuitry), test data 102 (e.g., scan input data), and a selection signal 103, and coupled to provide either input data 101 or test data 102 to elements of synchronizer flip-flop 100 based on the state of selection signal 103. Input data 101, test data 102, and selection signal 103 may each be a signal containing a value indicating a logic low state (i.e., "0") or a logic high state (i.e., "1"). When selection signal 103 is low, multiplexer 110 may provide input data 101 to transmission gate 111 for storage in synchronizer flip-flop 100. When selection signal 103 is high, multiplexer 110 may provide test data 102 to transmission gate 111 for storage in synchronizer flip-flop 100 for use during test routines (e.g., to ensure proper functioning of one or more elements of synchronizer flip-flop 100). The state of selection signal 103 can be controlled by a controller or other circuitry (not shown).

[0024] Input data 101 is an electronic logic signal with a state (e.g., logic high, logic low) that synchronizer flip-flop 100 will store for use by other digital circuits. In various instances, synchronizer flip-flop 100 can be triggered to store the last state value of input data 101 until the state of input data 101 changes. For example, initially, if input data 101 is in a logic low state, synchronizer flip-flop 100 may store a "0" in its elements. At a subsequent time, when input data 101 changes from a logic low state to a logic high state and select signal 103 is low, synchronizer flip-flop 100 may be configured to store a "1" in its elements.

[0025] When the selection signal 103 is in a high logic state, the transmission gate 111 can be coupled to receive input data 101 from the multiplexer 110. The transmission gate 111 contains two transistors coupled together. More specifically, the first transistor of the transmission gate 111 may contain an n-channel (or n-type) metal-oxide-semiconductor field-effect transistor (MOSFET) (also known as an NMOS), and the second transistor of the transmission gate 111 may contain a p-channel (or p-type) MOSFET (also known as a PMOS). Each transistor may contain a drain, a source, and a gate. The drain and source of the transistors may be coupled together. The gate of the PMOS transistor may be coupled to receive clock 104 (i.e., a clock signal) from a timing circuit (not shown). The gate of the NMOS transistor may be coupled to receive an inverted clock 105 (i.e., an inverted clock signal) that is substantially aligned with and opposite to clock 104 from the timing circuit. When clock 104 is in a low logic state ("0"), inverted clock 105 is in a high logic state ("1"), and transmission gate 111 is in conduction mode, transmission gate 111 can pass input data 101 to main latch subcircuit 112 and transmission gate 115. When clock 104 is in a high logic state and inverted clock 105 is in a low logic state, transmission gate 111 can be deactivated and prevent signals (e.g., input data 101 or test data 102) from flowing to main latch subcircuit 112 and transmission gate 115.

[0026] The primary latch subcircuit 112 represents a first or primary control flip-flop containing a first inverter group, which can control the operation of the secondary latch subcircuit 117 or a secondary inverter group following the first inverter group. In summary, the inverters of the primary latch subcircuit 112 can receive input data 101, store the state value of the input data 101 (e.g., "0" or "1"), and provide the state value to the transmission gate 116, and further downstream to another digital circuit (not shown) (e.g., output 106) and / or the secondary latch subcircuit 117. The primary latch subcircuit 112 can be configured to store subsequent state values ​​of the input data 101 when the state of the input data 101 changes to a state different from its stored state. After latching the new state of the input data 101, the primary latch subcircuit 112 can provide the new state value to the secondary latch subcircuit 117 for storage.

[0027] In this example, the main latch subcircuit 112 includes four inverters coupled in series. However, other numbers of inverters may be used in other embodiments. Each inverter includes an NMOS transistor and a PMOS transistor coupled together. More specifically, the gates of the NMOS and PMOS transistors of the first inverter in the main latch subcircuit 112 are coupled to receive input data 101 from the transmission gate 111, and the drains of the NMOS and PMOS transistors are coupled together to the gates of subsequent inverters in the main latch subcircuit 112. Each source of the PMOS transistor in the main latch subcircuit 112 is coupled to an internal power supply (e.g., V0). dd It receives power. Each source of the NMOS transistor in the main latch subcircuit 112 can be coupled to an individual ground node.

[0028] Deciphering the storage of a new state value via the master latch subcircuit 112 can be time-consuming. However, to avoid excessive time consumption (which could lead to malfunctions in the digital logic circuitry system outside the synchronizer flip-flop 100), diode-connected transistors 113 and 114 are included in the synchronizer flip-flop 100 and coupled to provide a body bias voltage to the inverter of the master latch subcircuit 112. Diode-connected transistor 113 may be a PMOS transistor, and diode-connected transistor 114 may be an NMOS transistor. Both the drain and gate of diode-connected transistor 113 may be coupled to the body of each PMOS transistor in the inverter of the master latch subcircuit 112. The source of diode-connected transistor 113 may be coupled to the internal power supply of the synchronizer flip-flop 100 (e.g., V0). dd Similarly, the drain and gate of diode-connected transistor 114 can be coupled to the body of each NMOS transistor in the inverter of the main latch subcircuit 112. The source of diode-connected transistor 114 can also be coupled to a ground node. Therefore, diode-connected transistors 113 and 114 can generate n-channel well bias voltage and p-channel well bias voltage respectively in real time during the operation of synchronizer flip-flop 100 (i.e., during the state switching of input data 101), which reduces the threshold voltage of the NMOS and PMOS transistors of the main latch subcircuit 112 and increases the latch resolution speed of the transistors. Advantageously, not only can this topology of the main latch subcircuit 112 be used to increase the mean time between failures (MTBF) of synchronizer flip-flop 100, but also the design stage area can be reduced because fewer flip-flop stages may be required and the bias voltages generated by diode-connected transistors 113 and 114 can be generated without the use of an external power supply.

[0029] After the state value of input data 101 is stored in the main latch subcircuit 112, the data input can be provided to transmission gate 116. Similar to transmission gates 111 and 115, transmission gate 116 contains NMOS and PMOS transistors coupled together to form a switch for the synchronizer flip-flop 100. When clock 104 is high, input data 101 can be provided to transmission gate 120 (which also contains NMOS and PMOS transistors coupled together) and secondary latch subcircuit 117. In various instances, secondary latch subcircuit 117 contains the same topology as the main latch subcircuit 112. Thus, in this example, secondary latch subcircuit 117 contains four inverters coupled in series, each inverter having two transistors coupled together (e.g., an NMOS transistor and a PMOS transistor). Similarly, the secondary latch subcircuit 117 is coupled to diode-connected transistors 118 and 119, which can provide p-channel and n-channel well bias voltages to the PMOS and NMOS transistors of the secondary latch subcircuit 117, respectively. In some cases, diode-connected transistors 118 and 119 can be the same devices as diode-connected transistors 113 and 114, respectively. In these cases, diode-connected transistors 113 and 114 can be coupled to provide bias voltages to both the primary latch subcircuit 112 and the secondary latch subcircuit 117, instead of including two additional devices (diode-connected transistors 118 and 119). Therefore, the secondary latch subcircuit 117 can perform latching of the state value of input data 101 controlled by the primary latch subcircuit 112 at an increasing rate based on the bias voltages provided by diode-connected transistors 118 and 119.

[0030] After latching the latest state value, the secondary latch subcircuit 117 can be coupled to provide the state value of the input data 101 to the logic device 121. The logic device 121 represents a digital logic device (NOT gate) that is invertible and coupled to provide the output 106 to one or more downstream digital circuits (not shown).

[0031] In other instances, the primary latch subcircuit 112 and the secondary latch subcircuit 117 may have different topologies individually and / or relative to each other. For example, each latch subcircuit may contain a different number of inverters, different types of transistors, etc. Furthermore, in some instances, the primary latch subcircuit 112 or the secondary latch subcircuit 117 may not be coupled to diode-connected transistors 113 and 114 or 118 and 119, respectively.

[0032] Figure 2 An exemplary synchronizer trigger circuit according to an embodiment is illustrated. Figure 2The system includes a synchronizer trigger circuit 200, which includes a multiplexer 210, transmission gates 211 and 221, a primary latch sub-circuit 212, a secondary latch sub-circuit 223, diode-connected transistors 213, 215, 224 and 226, an inverter 221, and logic devices 232 and 233.

[0033] Synchronizer flip-flop 200 represents a dual latch (i.e., master-slave latch) circuit capable of resolving a single bit-level signal (input data 201) provided by a digital circuit (not shown). Synchronizer flip-flop 200 can be used to store the state of input data 201 (e.g., "0", "1") and downstream provide the stored state data to different digital circuits (not shown) operating in different clock domains relative to the digital circuit providing input data 201 to synchronizer flip-flop 200. Therefore, synchronizer flip-flop 200 can be used to synchronize signals used by two or more digital circuits in different clock domains to a single clock cycle.

[0034] Synchronizer trigger 200 includes a multiplexer 210 coupled to receive input data 201 (from digital circuitry), test data 202, and a selector 203, and coupled to provide either the input data 201 or the test data 202 to elements of the synchronizer trigger 200 based on the state of the selector 203. The input data 201, test data 202, and selector 203 may each contain a signal indicating a logic low state (i.e., "0") or a logic high state (i.e., "1"). When selector 203 is low, multiplexer 210 can provide input data 201 to transmission gate 211 to implement the data latching function of the synchronizer trigger 200. When selector 203 is high, multiplexer 210 can provide test data 202 to transmission gate 211 to implement the testing function of the synchronizer trigger 200 and ensure the proper functioning of one or more elements of the synchronizer trigger 200. The state of selector 203 may be controlled by a controller or other circuitry (not shown).

[0035] Input data 201 indicates an electronic logic signal having a state that synchronizer flip-flop 200 will store for use by other digital circuits. In various instances, synchronizer flip-flop 200 can be triggered to store the last state value of input data 201 until the state of input data 201 changes. For example, initially, if input data 201 is in a logic low state, synchronizer flip-flop 200 may store a "0" in its element. At a subsequent time, when input data 201 changes from a logic low state to a logic high state, and selection 203 is low, synchronizer flip-flop 200 may be configured to store a "1" in its element.

[0036] When selector 203 is in a low logic state, transmission gate 211 can be coupled to receive input data 201 from multiplexer 210. Transmission gate 211 contains two transistors coupled together. More specifically, the first transistor of transmission gate 211 can contain an NMOS transistor, and the second transistor of transmission gate 211 can contain a PMOS transistor. Each transistor can contain a drain, a source, and a gate. The drain and source of the transistors can be coupled together. The gate of the PMOS transistor can be coupled to receive clock 204 (i.e., a clock signal) from a timing circuit (not shown). The gate of the NMOS transistor can be coupled to receive an inverted clock 205 (i.e., an inverted clock signal) from the timing circuit. When clock 204 is in a low logic state, inverted clock 205 is in a high logic state, and transmission gate 211 can operate in conduction mode, thereby allowing transmission gate 211 to pass input data 201 to main latch subcircuit 212 and inverter 221. When clock 204 is in a high logic state and inverted clock 205 is in a low logic state, transmission gate 211 can stop conducting and prevent signal flow to main latch sub-circuit 212 and inverter 221.

[0037] The primary latch subcircuit 212 represents a first control trigger comprising a first inverter group, which controls the operation of the secondary latch subcircuit 223, or a second inverter group following the first inverter group. In summary, the inverters of the primary latch subcircuit 212 can receive input data 201, store the state value of the input data 201 (e.g., "0" or "1"), and provide the state value to inverter 221, and further downstream to another digital circuit (not shown) (e.g., output 206) and / or transmission gate 222 and secondary latch subcircuit 223. The primary latch subcircuit 212 can be configured to store subsequent state values ​​of the input data 201 when the state of the input data 201 changes to a state different from its stored state. After latching the new state of the input data 201, the primary latch subcircuit 212 can provide the new state value to the secondary latch subcircuit 217 for storage.

[0038] In this example, the main latch subcircuit 212 includes two inverters coupled in a multi-stage inverter topology; however, other numbers of inverters may be used in other embodiments. The inverters are further coupled to diode-connected transistors 213 and 215, and further coupled to feed signals to transistors 217 and 218, and 219 and 220, respectively. Each inverter includes an NMOS transistor and a PMOS transistor coupled together. More specifically, with respect to the first inverter, the gate of each transistor is coupled to receive input data 201 from transmission gate 211, and the source of each transistor is coupled to the gate of transistor 217. The source of the PMOS transistor is coupled to receive input data 201 from an internal power supply (e.g., V0). ddThe NMOS transistor receives power, and its source can be coupled to a ground node. Similarly, relative to the second inverter, the gate of each transistor can be coupled to receive input data 201 from transmission gate 211, and the source of each transistor can be coupled to the gate of transistor 220. The source of the PMOS transistor can be coupled to an internal power supply (e.g., V0). dd The NMOS transistor receives power, and its source can be coupled to a ground node. The body of the PMOS transistor in each inverter can be coupled to receive a bias voltage 214 from diode-connected transistor 213. The body of the NMOS transistor in each inverter can be coupled to receive a bias voltage 216 from diode-connected transistor 215.

[0039] Transistors 217 and 218 are coupled to receive signals from the first inverter of the main latch subcircuit 212 and provide signals to inverter 221. In various embodiments, transistors 217 and 218 may be PMOS transistors. Transistors 217 and 218 may be coupled together at the source of transistor 217 and the drain of transistor 218. Furthermore, the bodies of transistors 217 and 218 may be coupled to receive bias voltage 214 from diode-connected transistor 213. Similarly, transistors 219 and 220 are coupled to receive signals from the second inverter of the main latch subcircuit 212 and provide signals to inverter 221. In various embodiments, transistors 219 and 220 may be NMOS transistors. Transistors 219 and 220 may be coupled together at the source of transistor 219 and the drain of transistor 220. The gates of transistors 218 and 219 may be coupled to receive inverted clock 205 and clock 204, respectively. The bodies of transistors 219 and 220 can be coupled to receive a bias voltage 216 from diode-connected transistor 215. Transistors 218 and 219 can be coupled together at the drains of transistor 218 and 219, forming a node between the two inverters of the main latch subcircuit 212, which allows the state value resolved and stored by the main latch subcircuit 212 to be provided to inverter 221.

[0040] Deciphering the storage of a new state value via the master latch subcircuit 212 can be time-consuming. However, to avoid excessive time consumption (which could lead to malfunctions in the digital logic circuitry system outside the synchronizer flip-flop 200), diode-connected transistors 213 and 215 are included in the synchronizer flip-flop 200 and coupled to provide a bias voltage to the inverter of the master latch subcircuit 212. Diode-connected transistor 213 may be a PMOS transistor, and diode-connected transistor 215 may be an NMOS transistor. Both the drain and gate of diode-connected transistor 213 may be coupled to the body of each PMOS transistor in the master latch subcircuit 212. The source of diode-connected transistor 213 may be coupled to the internal power supply of the synchronizer flip-flop 200 (e.g., V0). dd Therefore, no auxiliary power supply is required. Similarly, the drain and gate of diode-connected transistor 215 can be coupled to the body of each NMOS transistor in the main latch subcircuit 212. The source of diode-connected transistor 215 can also be coupled to the ground node of synchronizer flip-flop 200. Thus, diode-connected transistors 213 and 215 can generate n-channel well bias voltage and p-channel well bias voltage respectively in real time during the operation of synchronizer flip-flop 200 (i.e., during the state switching of input data 201), which reduces the threshold voltage of the NMOS and PMOS transistors in the main latch subcircuit 212 and increases the latch resolution speed of the transistors. Advantageously, not only can this topology of the main latch subcircuit 212 be used to increase the mean time between failures (MTBF) of synchronizer flip-flop 200, but also the design stage area can be reduced because fewer flip-flop stages may be required and the bias voltages generated by diode-connected transistors 213 and 215 can be generated without the use of an external power supply.

[0041] After the state value of input data 201 is stored in the main latch subcircuit 212, the input data 201 can be provided to the inverter 221. Similar to the inverter in the main latch subcircuit 212, the inverter 221 includes an NMOS transistor and a PMOS transistor coupled together. More specifically, the gates of the NMOS and PMOS transistors are coupled together and to the transmission gate 211 and the main latch subcircuit 212. The source of the PMOS transistor is coupled to receive power from an internal power supply. The source of the NMOS transistor is coupled to a ground node. The drains of the PMOS and NMOS transistors are coupled together and to the transmission gate 222. The inverter 221 can be configured to receive the input data 201 stored in the main latch subcircuit 212 and provide the state value to the transmission gate 222.

[0042] Similar to transmission gate 211, transmission gate 222 includes PMOS and NMOS transistors coupled together to form a switch for synchronizer flip-flop 200. When clock 204 is high, input data 201 is available to the secondary latch subcircuit 223 and logic device 232.

[0043] In various instances, the secondary latch subcircuit 223 comprises the same topology as the primary latch subcircuit 212. Thus, in this example, the secondary latch subcircuit 223 comprises two inverters coupled in a multi-stage inverter topology, each inverter having two transistors (e.g., an NMOS transistor and a PMOS transistor) coupled together. The first inverter may be further coupled to transistors 228 and 229, and the second inverter may be further coupled to transistors 230 and 231. However, unlike the primary latch subcircuit 212, the gates of transistors 229 and 230 are coupled to receive clock 204 and an inverted clock 205, respectively. Transistors 228 and 229 (which may be PMOS transistors) are coupled to receive a bias voltage 225 from a diode-connected transistor 224. The NMOS transistors (e.g., transistors 230 and 231) of the secondary latch subcircuit 223 may be coupled to receive a bias voltage 227 from a diode-connected transistor 226. Diode-connected transistors 224 and 226 may provide an n-channel well bias voltage (e.g., bias voltage 225) and a p-channel well bias voltage (e.g., bias voltage 227) to the transistors of the secondary latch subcircuit 223, respectively. In some cases, diode-connected transistors 224 and 226 may be the same devices as diode-connected transistors 213 and 215, respectively. In such cases, diode-connected transistors 213 and 215 may be coupled to provide bias voltages to both the primary latch subcircuit 212 and the secondary latch subcircuit 223, instead of including two additional devices (diode-connected transistors 224 and 226). Therefore, the secondary latch subcircuit 223 can perform latching of the state value of the input data 201 controlled by the primary latch subcircuit 212 at an increased speed based on bias voltages 225 and 227 provided by diode-connected transistors 224 and 226, respectively.

[0044] The secondary latch subcircuit 223 can be coupled to provide the state value of the input data 201 to logic device 232 (NOT gate). Logic device 232 can invert the state value and provide the inverted state value to logic device 233 (also a NOT gate). Logic device 233 can further invert the state value. Logic device 233 can be coupled to provide the output 206 to one or more downstream digital circuits (not shown).

[0045] In other instances, the primary latch subcircuit 212 and the secondary latch subcircuit 223 may have different topologies individually and / or relative to each other. For example, each latch subcircuit may contain a different number of inverters, different types of transistors, etc. Furthermore, in some instances, the primary latch subcircuit 212 or the secondary latch subcircuit 217 may not be coupled to diode-connected transistors 213 and 215 or 224 and 226, respectively.

[0046] Figure 3 Exemplary aspects of the components of a synchronizer trigger circuit according to an embodiment are illustrated, along with a related graphical representation of voltage changes in those components. Figure 3 The component 301 includes a diode-connected transistor 311 and a latch inverter 314. Figure 3 It also includes a graphical representation 302, which shows the voltage 303 of the body voltage (i.e., bias voltage 312) of the latch inverter 314 corresponding to aspect 301 as a function of time 304. The diode-connected transistor 311 and the latch inverter 314 can be a synchronizer trigger circuit (e.g., Figure 1 Synchronizer trigger 100, Figure 2 Exemplary components of the synchronizer trigger 200, respectively, for example Figure 1 diode-connected transistor 113 or Figure 2 Diode-connected transistor 213 and Figure 1 Main latch sub-circuit 112 or Figure 2 The inverter of the main latch sub-circuit 212.

[0047] Referring first to aspect 301, inverter 314 represents an inverter contained within a latch sub-circuit (e.g., primary latch sub-circuit 112, secondary latch sub-circuit 117). Inverter 314 includes a PMOS transistor 315 and an NMOS transistor 316 coupled to each other. More specifically, PMOS transistor 315 includes an inverter coupled to an internal power supply 310 (i.e., V0). dd The PMOS transistor 315 includes a source for receiving power, a gate coupled to the gate of the NMOS transistor 316 and further coupled to receive input data 317 from a logic circuit or another inverter in a latch sub-circuit, and a drain coupled to the NMOS transistor 316 and further coupled to provide input data 317 downstream to another inverter or a sub-latch sub-circuit. The PMOS transistor 315 also includes a body coupled to the gate and drain of the diode-connected transistor 311.

[0048] Diode-connected transistor 311 represents a PMOS transistor that generates a dynamic n-channel well bias voltage 312 to affect the operation of the PMOS transistor 315 of the inverter 314 in the synchronizer trigger circuit. While only diode-connected transistor 311 is shown in aspect 301, a second diode-connected transistor (e.g., a diode-connected NMOS transistor) may be included in various embodiments and coupled to provide a p-channel well bias voltage to affect the operation of the NMOS transistor 316 of the inverter 314. For brevity, the second diode-connected transistor is not shown or discussed in aspect 301.

[0049] The diode-connected transistor 311 includes components coupled to a power source 310 (i.e., V). dd The source of the PMOS transistor 311 receives power, and the gate and drain of the PMOS transistor 315 are coupled together to provide a bias voltage 312 to the body of the PMOS transistor 315. Based on the power supply 310, the diode-connected transistor 311 generates a body current 313 (which may be a reverse bias drain current), and a voltage is generated between the gate and drain of the diode-connected transistor 311. Therefore, the bias voltage 312 measured at the node where the gate and drain of the diode-connected transistor 311 are coupled can be a value less than the voltage provided by the power supply 310, as defined by the following equation, where the bias voltage is defined as V. b And V SG The voltage across the source and gate of diode-connected transistor 311:

[0050] V b = V dd - V SG .

[0051] When the body current 313 flows to the PMOS transistor 315, a non-zero voltage (V) is generated between the source and body of the PMOS transistor 315. sb This voltage can be defined using the following equation:

[0052] V sb = V dd - V b ,

[0053] Where V sb The cut-in voltage is less than that of the source-body diode (not shown) of the PMOS transistor 315. Therefore, because V sb The value is also less than V dd Therefore, when bias voltage 312 is applied to PMOS transistor 315, the threshold voltage (V) of PMOS transistor 315 is... thThis can be reduced. This may increase the data parsing and latching speed of the PMOS transistor 315. In various instances, the bias voltage 312 and therefore the V of the PMOS transistor 315 are reduced. sb It can be determined based on the characteristics of PMOS transistor 315 and diode-connected transistor 311.

[0054] Next reference Figure 3 The graphical representation 302 illustrates the effect of the bias voltage 312 changing with time 304 (voltage 303) and the state change of input data 317 on the bias voltage 312. During the static time period when input data 317 is currently in a logic low state (i.e., "0") and does not change its state within the time interval 304, the bias voltage 312 can have a constant voltage, a distance from V. dd It has a voltage drop of 155 mV. In this static state, the bias voltage 312 can generate a small leakage current or body current 313 in the PMOS transistor 315. However, at time 304 when the input data 317 changes the state from logic low to logic high or from "0" to "1", the bias voltage 312 can decrease in voltage 303, which increases the voltage drop of the bias voltage 312 to 230 mV. During this transition between the states of the input data 317, the voltage 303 of the bias voltage 312 increases, which can increase the body current 313 and V. sb And reduce the V of PMOS transistor 315 th After the transition, at subsequent time 304, the bias voltage 312 can return to 155 mV, which prevents excessive leakage from the PMOS transistor 315 during non-transition or static times.

[0055] Although only the low-to-high transition is shown in the graphical representation 302, a similar voltage drop increase in the bias voltage 312 may occur when the input data 317 transitions from a logic high state to a logic low state. Therefore, the V of the PMOS transistor 315... th The voltage drop can be dynamically changed only during the transition of the logic state of input data 317 to improve the efficiency of inverter 314 during such transitions. Furthermore, such a voltage drop can occur by using an internal power supply (power supply 310) and in the absence of an external power supply that can provide a fixed bias voltage. Advantageously, not only is design area and cost reduced by using power supply 310, but leakage of transistors 315 and 316 of inverter 314 is also reduced and dynamically changed only when inverter 314 is assigned the task of latching the changing state value of input data 317.

[0056] Figure 4 An exemplary operating environment for performing logic with a synchronizer trigger circuit is illustrated according to an embodiment. Figure 4The demonstration operating environment 400 includes a clock generator circuit 405, logic circuit 410, flip-flops 415, and logic circuit 425. The flip-flops include a primary latch sub-circuit 416 and a secondary latch sub-circuit 417. Flip-flop 415 may represent a synchronizer flip-flop circuit that includes multiple latches and other circuitry that synchronizes data signals in the clock domain, for example... Figure 1 Synchronizer flip-flop 100. For example, flip-flop 415 includes a master latch subcircuit 416 and a secondary latch subcircuit 417. In various instances, the master latch subcircuit 416 may include various elements, such as those related to... Figure 1 The main latch sub-circuit 112 and Figure 2 The main latch subcircuit 212 shows and describes those components. Similarly, the secondary latch subcircuit 417 may contain various components, such as those related to... Figure 1 The secondary latch sub-circuit 117 and Figure 2 The components shown and described in the secondary latch sub-circuit 223.

[0057] Logic circuit 410 represents a digital circuit, digital logic device, or combination or variation of electronic and logic elements capable of performing logical steps according to a first clock signal. The first clock signal may or may not be the same clock signal as the second clock signal generated by clock generator circuit 405 (e.g., Figure 1 (clock 104). The logic circuit 410 can generate a data signal by executing logic and provide a data signal synchronized with the first clock signal to the flip-flop 415.

[0058] Flip-flop 415 represents a synchronizer flip-flop circuit, which includes a primary latch sub-circuit 416 and a secondary latch sub-circuit 417 capable of synchronizing the data signal of logic circuit 410 with a second clock signal of clock generator circuit 405. Clock generator circuit 405 represents a clock generation circuit that may include an oscillator. Clock generator circuit 405 can provide the second clock signal to both primary latch sub-circuit 416 and secondary latch sub-circuit 417, which allow their components to store the state of the data signal.

[0059] The master latch subcircuit 416 represents a first, master-controlled latch containing a first group of inverters, which can control the operation of the secondary latch subcircuit 417 based on the state of a data signal provided by logic circuit 410 and a second clock signal provided by clock generator circuit 405. In summary, the inverters of the master latch subcircuit 416 can receive a data signal from logic circuit 410, store the state value of the data signal (e.g., "0" or "1"), and provide the state value to the secondary latch subcircuit 417. The master latch subcircuit 416 can be configured to store subsequent state values ​​of the data signal when the state of the data signal changes to a state different from its stored state. In various instances, to resolve the data signal as the state changes, the master latch subcircuit 416 may include diode-connected transistors (e.g., ...). Figure 1 The diode-connected transistors 113 and 114 can provide a bias voltage to the inverter of the main latch subcircuit 416 to improve the inverter's speed. After a new state of the latched data signal, the main latch subcircuit 416 can provide the new state value to the secondary latch subcircuit 417 for storage.

[0060] The secondary latch subcircuit 417 includes a second inverter group and a diode-connected transistor (e.g., ...). Figure 1 The secondary latch subcircuit 417 uses diode-connected transistors 118 and 119 and can simulate the function of the main latch subcircuit 416, except that it stores the state value of the data signal from the logic circuit 410 according to the main latch subcircuit 416. After parsing and storing the state data of the data signal, the secondary latch subcircuit 417 can be coupled to provide the data signal or its currently stored state value to the logic circuit 425.

[0061] Logic circuit 425 also represents a digital circuit, digital logic device, or combination or variation of electronic and logic elements capable of performing logical steps according to a third clock signal. In various instances, logic circuit 425 operates according to a clock signal different from the first clock signal used by logic circuit 410. Therefore, logic circuit 425 operates in a second clock domain relative to logic circuit 410. For example, logic circuit 425 may operate according to a second clock signal generated by clock generator circuit 405 (i.e., the second clock signal may be the same as the third clock signal). Importantly, flip-flop 415 may be included in operating environment 401 to synchronize data signals from logic circuit 410 to the clock domain of logic circuit 425 before providing data signals from logic circuit 410 to logic circuit 425. Logic circuit 425 can use the synchronized data signals to perform various operations and downstream output a second data signal to another logic circuit (not shown) or another flip-flop (not shown).

[0062] While some of the examples provided herein are described in the context of synchronizer trigger circuits, subcircuits, systems, subsystems, components, devices, architectures, or environments, it should be understood that the latches, triggers, logic elements, and other circuits, systems, and methods described herein are not limited to such embodiments and are applicable in a variety of other processes, systems, applications, devices, etc., such as other circuits, logic devices, latches, transistors, etc., in the context of, for example, increased transistor resolution and other benefits. Therefore, aspects of the invention can be embodied in other systems, methods, and other configurable systems.

[0063] Unless the context clearly requires otherwise, throughout the specification and claims, the terms “comprise,” “comprising,” etc., shall be interpreted in an inclusive sense, not an exclusive or exhaustive sense; that is, in the sense of “including but not limited to.” As used herein, the terms “connection,” “coupling,” or any variation thereof mean any direct or indirect connection or coupling between two or more elements; the coupling or connection between elements may be physical, logical, or a combination thereof. Furthermore, when used in this application, the terms “in this document,” “above,” “below,” and similar terms refer to the entire application and not any particular part of it. Where the context permits, singular or plural terms used in the specific embodiments above may also include either the plural or the singular, respectively. The term “or” relating to a list of two or more items covers all of the following interpretations of the term: any one of the items in the list, all the items in the list, and any combination of the items in the list.

[0064] The phrases “in some embodiments,” “according to some embodiments,” “in the illustrated embodiments,” “in other embodiments,” etc., generally mean that the specific feature, structure, or characteristic following the phrase is included in at least one embodiment of the invention, and may be included in more than one embodiment. Furthermore, such phrases do not necessarily refer to the same embodiment or different embodiments.

[0065] The specific implementations of the techniques described above are not intended to be exhaustive or to limit the techniques to the exact forms disclosed above. While specific examples of the techniques are described above for illustrative purposes, those skilled in the art will recognize that various equivalent modifications can be made within the scope of the techniques. For example, although processes or blocks are presented in a given order, alternative implementations may execute routines with steps or employ systems with blocks in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and / or modified to provide alternatives or sub-combinations. Each of these processes or blocks can be implemented in various different ways. Furthermore, although processes or blocks are sometimes shown as being executed sequentially, these processes or blocks may be changed to be executed or implemented in parallel, or may be executed at different times. Moreover, any specific numbers mentioned herein are merely examples; alternative implementations may employ different values ​​or ranges.

[0066] The teachings of the techniques provided herein can be applied to other systems, not necessarily those described above. The elements and actions of the various examples described above can be combined to provide alternative implementations of the techniques. Some alternative implementations of the techniques may include not only the additional elements of those implementations mentioned above, but also fewer elements.

[0067] Given the specific implementations described above, these and other changes may be made to the technology. While the foregoing descriptions depict certain instances of the technology and describe the best modes considered, the technology can be practiced in many ways, however detailed the foregoing may be. The details of the system may vary significantly in its particular implementations, while still being covered by the technology disclosed herein. As mentioned above, the specific terms used when describing certain features or aspects of the technology should not be construed as implying that the terms are redefined herein to limit to any particular characteristic, feature, or aspect of the technology associated with the term. In general, unless such terms are explicitly defined in the specific implementations section above, the terms used in the appended claims should not be construed as limiting the technology to the specific instances disclosed in the specification. Therefore, the actual scope of the technology covers not only the disclosed instances but also all equivalent ways of practicing or implementing the technology under the claims.

[0068] To reduce the number of claims, certain aspects of the technology are presented hereinafter in certain claim forms, but the applicant may consider aspects of the technology in any number of claim forms. For example, although only one aspect of the technology is described as a computer-readable medium, other aspects may also be embodied as a computer-readable medium, or in other forms, such as in a means-plus-function technical solution. Any technical solution intended to be treated under 35 USC § 112(f) will begin with the phrase “for a component,” but the use of the term “for” in any other context is not intended to invoke treatment under 35 USC § 112(f). Therefore, the applicant reserves the right to seek additional technical solutions after the filing of this application, in the form of such additional technical solutions, in this application or a continuing application.

Claims

1. A circuit device, comprising: a first latch sub-circuit coupled to receive an input; and a second latch sub-circuit coupled to the first latch sub-circuit; wherein the first latch sub-circuit comprises: a first group of inverters including a first group of transistors of a first type and a second group of transistors of a second type; a first diode-connected transistor coupled to a body of each transistor of the first group of transistors; and a second diode-connected transistor coupled to a body of each transistor of the second group of transistors.

2. The circuit device of claim 1, wherein the second latch sub-circuit comprises: a second group of inverters including a third group of transistors of the first type and a fourth group of transistors of the second type; a third diode-connected transistor coupled to a body of each transistor of the third group of transistors; and a fourth diode-connected transistor coupled to a body of each transistor of the fourth group of transistors.

3. The circuit device of claim 2, wherein the first type is N-type, and wherein the second type is P-type.

4. The circuit device of claim 2, wherein the first group of inverters are coupled in series, and wherein the second group of inverters are coupled in series.

5. The circuit device of claim 2, wherein the first group of inverters are coupled in parallel, and wherein the second group of inverters are coupled in parallel.

6. The circuit device of claim 2, wherein the first diode-connected transistor provides a first bias voltage to the body of each transistor of the first group of transistors, wherein the second diode-connected transistor provides a second bias voltage to the body of each transistor of the second group of transistors, wherein the third diode-connected transistor provides a third bias voltage to the body of each transistor of the third group of transistors, and wherein the fourth diode-connected transistor provides a fourth bias voltage to the body of each transistor of the first group of transistors.

7. The circuit device of claim 6, wherein each of the first diode-connected transistor, the second diode-connected transistor, the third diode-connected transistor, and the fourth diode-connected transistor are coupled to receive power from an internal power supply.

8. The circuit device of claim 7, wherein the first bias voltage, the second bias voltage, the third bias voltage, and the fourth bias voltage are each based on the power from the internal power supply and a body voltage of each respective transistor, wherein the first bias voltage is equal to the third bias voltage, and wherein the second bias voltage is equal to the fourth bias voltage.

9. A synchronizer flip-flop circuit, comprising: a first latch sub-circuit coupled to receive an input; and a second latch sub-circuit coupled to the first latch sub-circuit; wherein the first latch sub-circuit comprises: a first group of inverters; a first diode-connected transistor coupled to each inverter in the first inverter group and configured to provide a first bias voltage to each inverter in the first inverter group; and a second diode-connected transistor coupled to each inverter in the first inverter group and configured to provide a second bias voltage to each inverter in the first inverter group.

10. The synchronizer flip-flop circuit of claim 9, wherein the second latch subcircuit comprises: a second inverter group; a third diode-connected transistor coupled in parallel to each inverter in the second inverter group and configured to provide a third bias voltage to each inverter in the second inverter group; and a fourth diode-connected transistor coupled in parallel to each inverter in the second inverter group and configured to provide a fourth bias voltage to each inverter in the second inverter group.

11. The synchronizer flip-flop circuit of claim 10, wherein the first inverter group is coupled in series, and wherein the second inverter group is coupled in series.

12. The synchronizer flip-flop circuit of claim 10, wherein the first inverter group is coupled in parallel, and wherein the second inverter group is coupled in parallel.

13. The synchronizer flip-flop circuit of claim 10, wherein each inverter in the first inverter group comprises two transistors, wherein each inverter in the second inverter group comprises two transistors, and wherein each of the transistors comprises a source, a gate, a drain, and a body.

14. The synchronizer flip-flop circuit of claim 13, wherein one of the two transistors of each inverter is an N-type transistor, and wherein a different one of the two transistors of each inverter is a P-type transistor.

15. The synchronizer flip-flop circuit of claim 13, wherein an output of the first diode-connected transistor is coupled to the body of each first transistor of the two transistors of the first inverter group, and wherein an output of the second diode-connected transistor is coupled to the body of each second transistor of the two transistors of the first inverter group.

16. The synchronizer flip-flop circuit of claim 13, wherein each of the first diode-connected transistor, the second diode-connected transistor, the third diode-connected transistor, and the fourth diode-connected transistor is coupled to receive power from an internal power supply.

17. The synchronizer flip-flop circuit of claim 16, wherein the first bias voltage, the second bias voltage, the third bias voltage, and the fourth bias voltage are each based on the power from the internal power supply and a body voltage of each respective transistor of the two transistors, wherein the first bias voltage is equal to the third bias voltage, and wherein the second bias voltage is equal to the fourth bias voltage.

18. A synchronizer flip-flop circuit, comprising: a first latch subcircuit coupled to receive an input; and a second latch subcircuit coupled to the first latch subcircuit; wherein the first latch subcircuit comprises: a first inverter group; a first diode-connected transistor coupled to each inverter in the first inverter group and configured to provide a first bias voltage to each inverter in the first inverter group; and a second diode-connected transistor coupled to each inverter in the first inverter group and configured to provide a second bias voltage to each inverter in the first inverter group; and wherein the second latch subcircuit comprises: a second inverter group; a third diode-connected transistor coupled to each inverter in the second inverter group and configured to provide a third bias voltage to each inverter in the second inverter group; and a fourth diode-connected transistor coupled to each inverter in the second inverter group and configured to provide a fourth bias voltage to each inverter in the second inverter group.

19. The synchronizer flip-flop circuit of claim 18, wherein the first inverter group comprises a first set of transistors of a first type and a second set of transistors of a second type, wherein the second inverter group comprises a third set of transistors of the first type and a fourth set of transistors of the second type, and wherein each of the transistors comprises a source, a gate, a drain, and a body.

20. The synchronizer flip-flop circuit of claim 19, wherein the second latch subcircuit is coupled to provide the input to one or more downstream circuits.

Images