Inertia CMOS-MEMS structure capable of reducing stress sensitivity and manufacturing method

Abstract

The invention discloses an inertial CMOS-MEMS structure capable of reducing stress sensitivity and a manufacturing method thereof, the top surface of an MEMS structure layer is arranged on the bottom surface of an MEMS substrate, and the bottom surface of the MEMS structure layer is arranged on the top surface of an ASIC lower cover so as to form a structure with the MEMS substrate above and the ASIC lower cover below; the MEMS structure layer is provided with N sensitive structures, n sensitive structures are arranged outside the bonding ring, N-n sensitive structures are arranged in the bonding ring, the ASIC lower cover is provided with a cavity, the N-n sensitive structures are suspended, and the n sensitive structures are connected with the ASIC lower cover and used for leading out electric signals. By blocking a stress direct transmission path, zero drift caused by thermal stress is effectively reduced, the MEMS-ASIC structure has remarkable advantages in the aspect of zero-bias stability indexes, meanwhile, the MEMS and the ASIC are directly interconnected, routing is reduced, and parasitic parameters can be effectively reduced; the mismatching degree between the sensitive differential capacitor pairs is reduced, so that the absolute zero offset is reduced, and the zero offset stability is improved; and the MEMS and the ASIC are integrated, so that obvious advantages are achieved in the aspects of chip miniaturization and low cost.

Description

Technical Field

[0001] This invention relates to MEMS sensors, specifically an inertial CMOS-MEMS structure and fabrication method for reducing stress sensitivity. Background Technology

[0002] MEMS inertial sensors are one of the most widely used and industrialized core categories in MEMS technology. They are mainly used to detect and measure various motion parameters, including linear acceleration, angular velocity, tilt angle, impact, vibration, and multiple degrees of freedom (DoF). As an important component of inertial measurement units (IMUs) or micro-inertial systems, these sensors sense the motion state of a carrier in space, providing key signal inputs for navigation and positioning, attitude stabilization, trajectory tracking, and motion control. They are widely used in consumer electronics, automotive electronics, aerospace, industrial automation, and the Internet of Things (IoT).

[0003] MEMS inertial sensors have two main problems: 1. MEMS stress sensitivity issue: In MEMS inertial sensors, zero-bias temperature drift is a key indicator affecting their performance reliability in high-precision navigation, positioning, and motion control applications. The root of this problem lies in the mismatch of coefficients of thermal expansion (CTE) among various materials within the sensor module. During temperature changes, the inconsistent expansion and contraction of these materials leads to internal thermal stress, causing unexpected deformation of the sensitive structure. This ultimately results in zero-point signal shift and its nonlinear drift with temperature, significantly reducing the sensor's accuracy and stability. This is a critical technical bottleneck restricting its application in high-precision fields such as inertial navigation and precision industrial control.

[0004] Currently, the mainstream solution for compensating for temperature drift in MEMS accelerometers is software compensation. This method relies on the premise that "temperature drift has good repeatability," assuming that the accelerometer's temperature drift characteristics remain constant after the initial calibration. However, the temperature drift characteristics of MEMS accelerometers slowly drift and change over time, due to factors such as the number of thermal cycles, mechanical stress relaxation, parasitic capacitance, and the asymmetry of the encapsulating colloid. This results in the unsatisfactory performance of existing mainstream compensation techniques.

[0005] Therefore, the present invention aims to create an inherently stable mechanical environment from the source—that is, the design and manufacturing process of the chip—to obtain inherently low and stable zero-drift temperature characteristics.

[0006] Currently, the process cross-section of most MEMS inertial devices Figure 1As shown, the structure, from bottom to top, mainly consists of a MEMS substrate, a structural layer, and a MEMS top cover. Other thin film layers serve as intermediate dielectric layers and metal interconnect layers to achieve structural bonding, electrical lead-out, and insulation isolation. In this architecture, the MEMS substrate acts as a mechanical support carrier; the MEMS structural layer is fixed to the substrate through bonding processes and contains movable sensing elements formed by micromachining processes, such as suspended mass blocks, elastic beams, and comb-like structures; the MEMS top cover is bonded to the MEMS structural layer, forming an airtight cavity, thereby providing the necessary vacuum-sealed environment and external mechanical protection for the sensing structure.

[0007] However, in applications requiring high precision and stability, the aforementioned structure is susceptible to thermal stress caused by temperature changes. Specifically, for example... Figure 1 As shown by the red arrow, stress is generated from the packaging substrate, transmitted vertically to the MEMS substrate via a short path, and further transmitted to the structural anchor point, causing additional stress-induced strain (displacement) in the sensitive mass block. This causes the zero point of the MEMS sensor to drift with temperature, making it difficult to meet the performance requirements of long-term stability and temperature reliability for this type of application.

[0008] 2. MEMS and ASIC integration issues: In MEMS inertial sensor chips, such as Figure 2 As shown, it typically includes a MEMS chip and an ASIC chip. The MEMS chip pad and the ASIC chip pad are connected via wire bonds, establishing an electrical connection between the MEMS and ASIC chips. The inertial physical quantities sensed by the MEMS chip are transmitted to the ASIC chip for modulation / amplification / demodulation / noise filtering / digitalization, etc., before being output. The ASIC is also connected to the substrate via wire bonds, enabling power supply / IO connectivity / sensor signal output.

[0009] The problem with this design is that in order to bring the MEMS signal out to the MEMS chip pad, a long trace needs to be designed, which will result in large parasitic parameters, such as parasitic capacitance and parasitic resistance. In addition, the wire bond between MEMS and ASIC is also long and has poor consistency. This will result in large parasitic parameters and the inconsistency of the wire bond will affect the consistency of the sensing differential capacitor pairs. Summary of the Invention

[0010] To address the shortcomings of the prior art, this invention provides an inertial CMOS-MEMS structure and fabrication method with reduced stress sensitivity. This solves the problem of existing MEMS structures being susceptible to temperature-induced stress. By blocking the direct stress transmission path, this invention effectively reduces zero-point drift caused by thermal stress, exhibiting significant advantages in zero-bias stability. Furthermore, the direct interconnection between the MEMS and ASIC reduces wiring and effectively lowers parasitic parameters; it also reduces the mismatch between sensitive differential capacitor pairs, thereby reducing absolute zero bias and improving zero-bias stability. The integration of MEMS and ASIC also offers significant advantages in chip miniaturization and cost reduction.

[0011] To achieve the above-mentioned technical objectives, the present invention adopts the following technical solution: including, It includes a MEMS substrate, a MEMS structure layer, and an ASIC lower cover. The top surface of the MEMS structure layer is disposed on the bottom surface of the MEMS substrate, and the bottom surface of the MEMS structure layer is disposed on the top surface of the ASIC lower cover, so as to form a structure in which the MEMS substrate is on top and the ASIC lower cover is on the bottom. The MEMS structure layer has N sensitive structures, of which n sensitive structures are placed outside the bonding ring and Nn sensitive structures are placed inside the bonding ring. The ASIC lower cover has a cavity located below the Nn sensitive structures, so that the Nn sensitive structures are suspended. The n sensitive structures are connected to the ASIC lower cover to lead out electrical signals.

[0012] The cavity is also provided with Nn stop blocks, each of which corresponds one-to-one with one of the Nn sensitive structures. The stop blocks are located below the sensitive structures, and a gap is formed between the stop blocks and the sensitive structures so that the Nn sensitive structures are suspended.

[0013] A method for fabricating an inertial CMOS-MEMS structure with reduced stress sensitivity, comprising, Step 100: Fabrication of MEMS substrate; Step 200: Fabricate a MEMS structure layer, bond the MEMS structure layer to the bottom surface of the MEMS substrate, and etch the MEMS structure layer to form N sensitive structures; Step 300: Fabricate the ASIC lower cover. The ASIC lower cover has cavities in the regions corresponding to the Nn sensitive structures. The ASIC lower cover is bonded to the bottom surface of the MEMS structure layer, so that the cavities are located below the Nn sensitive structures, thereby suspending the Nn sensitive structures and connecting the n sensitive structures to the ASIC lower cover.

[0014] Step 100, fabricating the MEMS substrate, specifically includes: Step 101: Prepare the MEMS substrate; Step 102: Perform multilayer Oxide / Metal deposition and etching on the MEMS substrate; Step 103: Perform Top oxide via etching based on step 102.

[0015] Step 200, fabricating the MEMS structure layer, specifically includes: Step 201: Prepare MEMS structure layers; Step 202: Perform shallow trench etching on the surface of the MEMS structure layer.

[0016] The steps for setting N sensitive structures in the MEMS structure layer are as follows: Step 203: Thinning the MEMS structure layer; Step 204: Perform TSV etching on the thinned MEMS structure layer; Step 205: Fill the MEMS structure layer with TSV; Step 206: Deposit and etch bonding metals into the MEMS structure layer; Step 207: Perform DRIE etching on the MEMS structure layer to form the sensitive structure, wherein n of the sensitive structures are located outside the bonding ring.

[0017] Step 300, fabricating the ASIC bottom cover, includes: Step 301: Prepare the ASIC bottom cover; Step 302: Perform CMOS process flow on the ASIC lower cover; Step 303: Perform cavity etching on the ASIC bottom cover; It also includes, Step 304: Bond the ASIC bottom cover to the MEMS structure layer; Step 305: Thin the MEMS substrate; Step 306: Create pad windows at n of the aforementioned sensitive structures.

[0018] In summary, the present invention has achieved the following technical effects: This invention significantly improves the stress transmission path by attaching a MEMS structure layer to a suspended MEMS substrate. Stress from the packaging substrate must travel a significantly longer path to reach the sensitive structural region; this extended path effectively attenuates the stress value, thereby greatly reducing its impact on the sensitive area. Thanks to this structural optimization, the device maintains excellent zero-position stability within its operating range. The key technical aspect of this patent is the optimized process flow, which places the MEMS substrate on top of the chip (top surface) and attaches the MEMS structure layer to the lower surface of the substrate, thus suspending the MEMS sensing structure within the cavity package. This structure effectively blocks the direct transmission of external stress to the sensitive area, significantly reducing the impact of thermomechanical stress on device performance, thereby improving the sensor's zero-bias stability and temperature reliability. The MEMS chip and the ASIC chip are directly bonded together via a bonding ring.

[0019] This invention relates to a MEMS inertial sensor structure that achieves stress isolation through structural inversion and suspension design. The substrate supporting the movable MEMS structure is placed on the top surface of the chip. In the package, the substrate is in a suspended position, which avoids the direct transmission of stress to the MEMS structure and reduces the stress sensitivity of the MEMS structure.

[0020] In this invention, the suspended MEMS structure is directly bonded to the ASIC chip, reducing the parasitic parameters of the MEMS sensitive structure on the ASIC. This invention can be applied to MEMS accelerometers, MEMS gyroscopes, MEMS IMUs, MEMS vibration sensors, optical MEMS, RF MEMS, etc. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a traditional MEMS inertial device and its stress path. Figure 2 This is a schematic diagram of the leads of a traditional MEMS inertial device; Figure 3 This is a schematic diagram of the MEMS inertial device in this application; Figure 4 This is a schematic diagram of the stress path in this application; Figure 5 This is a schematic diagram of the process for fabricating MEMS substrates; Figure 6 This is a schematic diagram of the process for fabricating MEMS structural layers; Figure 7 This is a schematic diagram of the process of bonding the MEMS structure layer to the MEMS substrate; Figure 8 This is a flowchart illustrating the process of manufacturing the MEMS lower cover; Figure 9 This is a schematic diagram showing the integration of the MEMS lower cover and the MEMS structural layer; Figure 10 This is a schematic diagram of the product packaging in this application; Figure 11 It is the signal transmission path from MEMS to ASIC. Detailed Implementation

[0022] The present invention will be further described in detail below with reference to the accompanying drawings.

[0023] This specific embodiment is merely an explanation of the present invention and is not intended to limit the invention. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but such modifications are protected by patent law as long as they are within the scope of the claims of the present invention.

[0024] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0025] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0026] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0027] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0028] Example: Figure 3 It is an inertial CMOS-MEMS structure that reduces stress sensitivity, including It includes a MEMS substrate, a MEMS structure layer, and an ASIC lower cover. The top surface of the MEMS structure layer is disposed on the bottom surface of the MEMS substrate, and the bottom surface of the MEMS structure layer is disposed on the top surface of the ASIC lower cover, so as to form a structure in which the MEMS substrate is on top and the ASIC lower cover is on the bottom. The MEMS structure layer has N sensitive structures, of which n sensitive structures are placed outside the bonding ring and Nn sensitive structures are placed inside the bonding ring. The ASIC lower cover has a cavity located below the Nn sensitive structures, so that the Nn sensitive structures are suspended. The n sensitive structures are connected to the ASIC lower cover to lead out electrical signals.

[0029] This invention integrates the MEMS sensing component and the ASIC interface circuitry together via wafer-level bonding. A MEMS substrate is disposed on the top layer, and the MEMS structure layer is fixed beneath the MEMS substrate using a bonding process. An ASIC acts as a bottom cover, bonded beneath the MEMS structure layer, providing physical protection and forming a sealed cavity.

[0030] The present invention provides a mechanical load-bearing structure attached to a suspended MEMS substrate. Meanwhile, the MEMS lower cover serves as a carrier for the entire MEMS chip during the packaging process, thus preventing the stress of the packaging substrate / module PCB from being directly transferred to the MEMS structure layer.

[0031] like Figure 3 As shown, a SiO2 layer 1 and a MEMS metal layer 2 are formed between the MEMS substrate and the MEMS structure layer. The MEMS structure layer is etched to obtain the sensitive structure, including a mass block 5, an elastic beam / comb tooth 6, an anchor point 7, and a via-filled metal 9. The MEMS structure layer is connected to the ASIC bottom cover via a bonding ring 8. Figure 3 As shown, three sensitive structures are located inside the bonding ring 8, and one sensitive structure is located outside the bonding ring 8, for a total of four sensitive structures. Placing three sensitive structures inside reduces the impact of stress, and placing one sensitive structure outside is used to extract signals. An ASIC metal layer 3, a SiO2 / SiNx layer 4, and a bonding metal layer 12 are formed between the MEMS structure layer and the ASIC bottom cover. A cavity 13 is provided in the ASIC bottom cover, and a stop block 10 is provided inside the cavity 13. The number of stop blocks 10 is the same as the number of sensitive structures located in the bonding ring 8, which is three here. A chip pad 11 is provided at the end of the ASIC bottom cover.

[0032] In this design, SiO2 layer 1 is used to isolate the non-grounded metal from the MEMS substrate and to isolate different metal layers. MEMS metal layer 2 is used to lead MEMS signals from the anchor point and guide them to the chip pad output; it is generally made of materials such as aluminum, copper, or titanium. ASIC Metal layer 3 serves as the lead metal for the ASIC chip, providing signal guidance and shielding; it is typically made of aluminum / copper. SiO2 / SiNx layer 4 is silicon dioxide / silicon nitride, isolating different metal layers. Mass block 5 senses inertial signals (acceleration / angular velocity). With inertial force input, it generates displacement, causing deformation of the connected elastic beam and displacement of the attached comb teeth, resulting in capacitance changes and converting the inertial signal into an electrical signal. Elastic beam / comb teeth 6, equivalent to a spring, is the intermediary structure between the mass block and anchor point 7. The comb teeth are attached to the mass block, forming capacitance between them, serving as the sensing unit for the inertial signal. Anchor point 7 fixes the mass block (comb teeth) and elastic beam to the MEMS substrate. Bonding ring 8 is a crucial component forming the closed cavity, bearing the bonding pressure. Through-hole filling metal 9, also known as TSV (through silicon via) metal, is typically made of tungsten and guides the MEMS signal to the MEMS metal output. Stop block / Stopper 10: Limit the displacement of the mass block in the Z direction to prevent the elastic beam from breaking due to excessive displacement; Chip Pad 11: Lead the CMOS-MEMS signal to the package node; Bonding metal layer 12 is two metal layers that form an alloy in the bonding process to ensure the vacuum degree of the cavity; Cavity 13 is a stable vacuum gas-tight atmosphere environment, a closed space formed by MEMS substrate / ASIC / bonding ring / bonding metal layer.

[0033] Figure 4 This is a schematic diagram of the stress path of the structure in this application. The red path represents the stress path. It can be seen that the stress from the packaging substrate needs to be transmitted to the MEMS substrate after passing through the bonding position, and then from the MEMS substrate to the sensitive structure. Since the sensitive structure of this application only contacts the MEMS substrate at the top, the stress of the sensitive structure only comes from the substrate and only reaches the sensitive structure after a significant deflection. This application extends the stress transmission path and effectively attenuates the stress value, thereby significantly reducing the impact of stress on the sensitive area.

[0034] The cavity is also provided with Nn stop blocks, each of which corresponds one-to-one with one of the Nn sensitive structures. The stop blocks are located below the sensitive structures, and a gap is formed between the stop blocks and the sensitive structures so that the Nn sensitive structures are suspended.

[0035] The stop block in this application can limit the displacement of the mass block in the Z direction, and prevent the elastic beam from breaking due to excessive displacement.

[0036] This application is highly compatible with existing MEMS process platforms and can be implemented by only local optimization and parameter adjustment based on the existing process. It does not require the introduction of complex or additional process modules and has high feasibility and industrialization capability.

[0037] Structurally, compared to conventional structures, this application replaces the MEMS bottom cover with an ASIC wafer. Therefore, based on the completed ASIC wafer, a metal thin film that facilitates bonding with the MEMS structure layer needs to be added before bonding to the MEMS structure to complete the entire process. From a supply chain perspective, this application requires the MEMS fab and ASIC to work together, which differs from the conventional approach where the MEMS wafer and ASIC wafer can be completed separately on the fab.

[0038] A method for fabricating an inertial CMOS-MEMS structure with reduced stress sensitivity, comprising, Step 100: Fabrication of MEMS substrate; Step 200: Fabricate a MEMS structure layer, bond the MEMS structure layer to the bottom surface of the MEMS substrate, and etch the MEMS structure layer to form N sensitive structures; Step 300: Fabricate the ASIC lower cover. The ASIC lower cover has cavities in the regions corresponding to the Nn sensitive structures. The ASIC lower cover is bonded to the bottom surface of the MEMS structure layer, so that the cavities are located below the Nn sensitive structures, thereby suspending the Nn sensitive structures and connecting the n sensitive structures to the ASIC lower cover.

[0039] Step 100, fabricating the MEMS substrate, specifically includes, for example... Figure 5 As shown, Step 101: Prepare the MEMS substrate; Step 102: Perform multilayer Oxide / Metal deposition and etching on the MEMS substrate; Step 103: Perform Top oxide via etching based on step 102.

[0040] Step 200, fabricating the MEMS structure layer, specifically includes, for example... Figure 6 As shown, Step 201: Prepare MEMS structure layers; Step 202: Perform shallow trench etching on the surface of the MEMS structure layer.

[0041] The steps for setting N sensitive structures in the MEMS structure layer are as follows: Figure 7 As shown, Step 203: Thinning the MEMS structure layer; Step 204: Perform TSV etching on the thinned MEMS structure layer; Step 205: Fill the MEMS structure layer with TSV; Step 206: Deposit and etch bonding metals into the MEMS structure layer; Step 207: Perform DRIE etching on the MEMS structure layer to form the sensitive structure, wherein n of the sensitive structures are located outside the bonding ring.

[0042] Step 300, fabricating the ASIC bottom cover, includes, for example... Figure 8 As shown, Step 301: Prepare the ASIC bottom cover; Step 302: Perform CMOS process flow on the ASIC lower cover; Step 303: Perform cavity etching on the ASIC bottom cover; It also includes, such as Figure 9 As shown, Step 304: Bond the ASIC bottom cover to the MEMS structure layer; Step 305: Thin the MEMS substrate; Step 306: Create pad windows at n of the aforementioned sensitive structures.

[0043] This application integrates MEMS and ASIC on the same chip: such as Figure 10 As shown, the MEMS signal is led out from the MEMS sensitive structure via label 101, and then connected to the ASIC signal processing module via short lead 103+ vertical bonding point, or connected to the ASIC signal processing module via the nearest vertical bonding point. Using ASIC-packaged wire bonding for power supply and digital output, both signals are not easily affected by parasitics.

[0044] Figure 11 This is the signal transmission path from MEMS to ASIC. The analog signal transmission path in this application is short and has small parasitic capacitance / resistance, which is beneficial to improving output accuracy and is less susceptible to external electromagnetic interference.

[0045] The product packaged in this application has a small size and a significant cost advantage.

[0046] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention shall fall within the scope of the technical solution of the present invention.

Claims

1. An inertial CMOS-MEMS structure with reduced stress sensitivity, characterized in that: It includes a MEMS substrate, a MEMS structure layer, and an ASIC lower cover. The top surface of the MEMS structure layer is disposed on the bottom surface of the MEMS substrate, and the bottom surface of the MEMS structure layer is disposed on the top surface of the ASIC lower cover, so as to form a structure in which the MEMS substrate is on top and the ASIC lower cover is on the bottom. The MEMS structure layer has N sensitive structures, of which n sensitive structures are placed outside the bonding ring and Nn sensitive structures are placed inside the bonding ring. The ASIC lower cover has a cavity located below the Nn sensitive structures, so that the Nn sensitive structures are suspended. The n sensitive structures are connected to the ASIC lower cover to lead out electrical signals.

2. The inertial CMOS-MEMS structure for reducing stress sensitivity according to claim 1, characterized in that: The cavity is also provided with Nn stop blocks, each of which corresponds one-to-one with one of the Nn sensitive structures. The stop blocks are located below the sensitive structures, and a gap is formed between the stop blocks and the sensitive structures so that the Nn sensitive structures are suspended.

3. A method for fabricating an inertial CMOS-MEMS structure with reduced stress sensitivity, characterized in that: include, Step 100: Fabrication of MEMS substrate; Step 200: Fabricate a MEMS structure layer, bond the MEMS structure layer to the bottom surface of the MEMS substrate, and etch the MEMS structure layer to form N sensitive structures; Step 300: Fabricate the ASIC lower cover. The ASIC lower cover has cavities in the regions corresponding to the Nn sensitive structures. The ASIC lower cover is bonded to the bottom surface of the MEMS structure layer, so that the cavities are located below the Nn sensitive structures, thereby suspending the Nn sensitive structures and connecting the n sensitive structures to the ASIC lower cover.

4. The method for fabricating an inertial CMOS-MEMS structure with reduced stress sensitivity according to claim 3, characterized in that: Step 100, fabricating the MEMS substrate, specifically includes: Step 101: Prepare the MEMS substrate; Step 102: Perform multilayer Oxide / Metal deposition and etching on the MEMS substrate; Step 103: Perform Top oxide via etching based on step 102.

5. The method for fabricating an inertial CMOS-MEMS structure with reduced stress sensitivity according to claim 3, characterized in that: Step 200, fabricating the MEMS structure layer, specifically includes: Step 201: Prepare MEMS structure layers; Step 202: Perform shallow trench etching on the surface of the MEMS structure layer.

6. The method for fabricating an inertial CMOS-MEMS structure with reduced stress sensitivity according to claim 5, characterized in that: The steps for setting N sensitive structures in the MEMS structure layer are as follows: Step 203: Thinning the MEMS structure layer; Step 204: Perform TSV etching on the thinned MEMS structure layer; Step 205: Fill the MEMS structure layer with TSV; Step 206: Deposit and etch bonding metals into the MEMS structure layer; Step 207: Perform DRIE etching on the MEMS structure layer to form the sensitive structure, wherein n of the sensitive structures are located outside the bonding ring.

7. The method for fabricating an inertial CMOS-MEMS structure with reduced stress sensitivity according to claim 3, characterized in that: Step 300, fabricating the ASIC bottom cover, includes: Step 301: Prepare the ASIC bottom cover; Step 302: Perform CMOS process flow on the ASIC lower cover; Step 303: Perform cavity etching on the ASIC bottom cover.

8. The method for fabricating an inertial CMOS-MEMS structure with reduced stress sensitivity according to claim 7, characterized in that: It also includes, Step 304: Bond the ASIC bottom cover to the MEMS structure layer; Step 305: Thin the MEMS substrate; Step 306: Create pad windows at n of the aforementioned sensitive structures.

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