A system and method for improving the testing efficiency of a logic analyzer on a memory chip

Abstract

The application relates to the technical field of data storage, and discloses a system for improving the test efficiency of a logic analyzer on a storage chip and a test efficiency method thereof, which comprises: an SOC chip connected with a test circuit board on one side and connected with the lower surface of a conversion board on the other side; wherein the first connecting area of the lower surface of the conversion board is used for connecting the SOC chip, and the second connecting area of the upper surface of the conversion board is used for connecting a to-be-tested storage chip; the first connecting area of the lower surface of the conversion board is provided with a first pin structure corresponding to the pin arrangement of the SOC chip, and the first pin structure comprises a plurality of first pins; the second connecting area of the upper surface of the conversion board is provided with a second pin structure corresponding to the pin arrangement of the to-be-tested storage chip, and each second pin structure comprises a plurality of second pins; and the conversion board comprises a plurality of metal layers stacked between the upper surface and the lower surface. The application improves the response speed of storage chip testing.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data storage, in particular to a system for improving the test efficiency of a logic analyzer on a storage chip and a test efficiency method thereof. BACKGROUND

[0002] When testing key performance indicators such as timing parameters, protocol consistency, signal integrity, and data transmission performance of a storage chip, a logic analyzer is one of the core test equipment, which can realize the synchronous acquisition and analysis of multi-channel signals and provide data support for performance evaluation.

[0003] Currently, when a logic analyzer is used to test a storage chip, the test function is relatively single, and it is not possible to simultaneously measure other associated signals (such as power ripple and control signal timing) while carrying out core performance testing of the storage chip. Therefore, multiple tests are required in stages, which significantly prolongs the overall test cycle and is not conducive to improving test efficiency. SUMMARY

[0004] The present application provides a system for improving the test efficiency of a logic analyzer on a storage chip and a test efficiency method thereof, which can solve the technical problem of single test function, inability to simultaneously measure other associated signals (such as power ripple and control signal timing) while carrying out core performance testing of the storage chip, and the need for multiple tests in stages, which significantly prolongs the overall test cycle and is not conducive to improving test efficiency.

[0005] To solve the above technical problems, one technical solution adopted by the present application is to provide a system for improving the test efficiency of a logic analyzer on a storage chip, which comprises:

[0006] One side of the SOC chip is connected to the test circuit board, and the other side is connected to the lower surface of the adapter board;

[0007] The first connection area of the lower surface of the adapter board is used to connect the SOC chip, and the second connection area of the upper surface of the adapter board is used to connect the storage chip to be tested. The first connection area of the lower surface of the adapter board is provided with a first pin structure corresponding to the pin arrangement of the SOC chip, and the first pin structure comprises a plurality of first pins. The second connection area of the upper surface of the adapter board is provided with a second pin structure corresponding to the pin arrangement of the storage chip to be tested, and each second pin structure comprises a plurality of second pins. The adapter board comprises a plurality of metal layers stacked between the upper surface and the lower surface. Each second pin is connected to the corresponding first pin through the wiring and metal via in at least one metal layer, realizing the connection of the SOC chip to the storage chip.

[0008] The upper surface of the adapter plate is further provided with a plurality of test pads located on both sides of the second connection area along a first direction, a plurality of resistors located on both sides of the second connection area along a second direction, and a connector located at the edges of the adapter plate along the first direction, the connector being connected with a connection line of a logic analyzer, so that the test signal or test data of the storage chip to be tested is output to the logic analyzer, the first direction and the second direction are perpendicular, the connector includes a plurality of output pins, a second pin in the second connection area is connected with one end of a corresponding resistor through a wire, and the other end of the resistor is connected with an output pin of the corresponding connector through a wire; the test pad is connected with at least one second pin through a wire in the metal layer, and the test pad is connected with an oscilloscope to display a test waveform.

[0009] In a second aspect, a test method for testing a storage chip based on the above test efficiency system is provided, and the method comprises:

[0010] The adapter plate is arranged according to the layout of the LPDDR5 chip, the first connection area of the lower surface of the adapter plate is used for connecting the SOC chip, the second connection area of the upper surface of the adapter plate is used for connecting the storage chip to be tested, the first connection area of the lower surface of the adapter plate is provided with a first pin structure corresponding to the pin arrangement of the SOC chip, the first pin structure includes a plurality of first pins, the second connection area of the upper surface of the adapter plate is provided with a second pin structure corresponding to the pin arrangement of the storage chip to be tested, each second pin structure includes a plurality of second pins, the adapter plate includes a plurality of metal layers stacked between the upper surface and the lower surface, each second pin is connected with a corresponding first pin through a wire and a metal via in at least one metal layer, the upper surface of the adapter plate is further provided with a plurality of test pads located on both sides of the second connection area along a first direction, a plurality of resistors located on both sides of the second connection area along a second direction, and a connector located at the edges of the adapter plate along the first direction, the first direction and the second direction are perpendicular, the connector includes a plurality of output pins, a second pin in the second connection area is connected with one end of a corresponding resistor through a wire, and the other end of the resistor is connected with a corresponding output pin through a wire, and the test pad is connected with at least one second pin through a wire in the metal layer;

[0011] After the LPDDR5 chip is welded on the upper surface of the adapter plate, a test circuit board is formed, wherein the test circuit board is provided with a mounting area;

[0012] The lower surface of the adapter plate is welded on the mounting area, and the SOC chip is welded to the mounting area of the test circuit board, so that the LPDDR5 chip is connected with the SOC chip through the adapter plate;

[0013] The connector is connected with the logic analyzer, and the test pad is connected with the oscilloscope, the LPDDR5 chip is tested by the test circuit board, the test signal or test data of the to-be-tested storage chip is output to the logic analyzer through the connector, the logic analyzer analyzes the test signal or test data and obtains a test result, and the test result is displayed through the oscilloscope.

[0014] The application has the advantages that the multi-dimensional practical value is exhibited in the storage chip test scene, the pain points of the traditional test scheme are solved, efficient and reliable support is provided for storage chip performance verification, the test precision is significantly improved, the storage chip performance verification reliability is ensured, the authenticity and accuracy of the test data are ensured through multi-dimensional design, and accurate basis is provided for storage chip performance evaluation. The differential wiring, impedance matching resistance and ground shielding structure of the adapter plate effectively suppress the crosstalk, reflection and noise interference of high-speed signals (such as 5500MT / s signals of LPDDR5), ensure that the test signal is highly consistent with the actual interaction function signal of the SOC and the storage chip, avoid test misjudgment caused by signal distortion, for example, the waveform captured by the oscilloscope can truly reflect the timing jitter of the data pin of the storage chip, and the read and write data collected by the logic analyzer can accurately judge the data transmission correctness. The waveform visualization of the oscilloscope and the batch data collection of the logic analyzer are complementary, which not only realizes accurate measurement of microscopic parameters such as signal amplitude and period, but also completes verification of macroscopic performance such as data transmission stability and timing consistency, covers the full-dimensional test scene of the storage chip from “signal quality” to “function reliability”, and compared with a single test device, can more comprehensively find potential problems (such as implicit timing deviation and occasional data errors) of the storage chip. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a schematic view of the upper surface of the adapter plate.

[0016] Figure 2 is a schematic view of the lower surface of the adapter plate.

[0017] Figure 3 is a flowchart of a test method for testing a storage chip based on a system for improving the test efficiency of a logic analyzer on a storage chip. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the application.

[0019] The terms "comprising" and "having," and any variations thereof, used in this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0020] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0021] Figure 1 This is a schematic diagram of the system for improving the testing efficiency of a logic analyzer for memory chips, according to the first embodiment of the present invention. Figure 1 As shown, the system includes:

[0022] One side of the SOC chip is connected to the test circuit board, and the other side is connected to the lower surface of the adapter board;

[0023] The adapter board has a first connection area on its lower surface for connecting a SOC chip, and a second connection area on its upper surface for connecting a memory chip under test. The first connection area on the lower surface of the adapter board has a first pin structure corresponding to the pin arrangement of the SOC chip, and the first pin structure includes multiple first pins. The second connection area on the upper surface of the adapter board has a second pin structure corresponding to the pin arrangement of the memory chip under test, and each second pin structure includes multiple second pins. The adapter board includes multiple metal layers stacked between the upper and lower surfaces. Each second pin is connected to the corresponding first pin through a trace and a metal via in at least one metal layer, thus enabling the SOC chip to connect to the memory chip.

[0024] The adapter board's upper surface is also provided with several test pads located on both sides of the second connection area along the first direction, several resistors located on both sides of the second connection area along the second direction, and connectors located at the edges of the adapter board along the first direction. The connectors are connected to the connection lines of the logic analyzer to output the test signals or test data of the memory chip under test to the logic analyzer. The first and second directions are perpendicular. The connectors include several output pins. The second pins in the second connection area are connected to one end of the corresponding resistors through traces, and the other end of the resistors are connected to the output pins of the corresponding connectors through traces. The test pads are connected to at least one second pin through traces in the metal layer. The test pads are connected to an oscilloscope to display the test waveforms.

[0025] like Figures 1-3 As shown, a customized adapter board achieves precise compatibility between the SOC chip and the memory chip under test, while integrating test interfaces for an oscilloscope and logic analyzer, balancing functional communication and test analysis needs. The hardware system consists of the SOC chip, adapter board, test circuit board, memory chip under test, and external test equipment (logic analyzer, oscilloscope). The structural parameters and functional positioning of each component are precisely designed around the memory chip testing scenario.

[0026] The SOC chip (System on Chip) serves as the control core of the entire test efficiency system. It adopts a double-sided pin layout design. One side of the pins is used to connect to the test board to obtain stable power supply, system clock, and test commands issued by the host computer. The other side of the pins are dedicated to the storage interface, including data pins, address pins, control pins, etc. The number of pins, the spacing between them, and the signal definitions all follow industry standards and are fully matched with the first pin structure of the adapter board to ensure seamless transmission of functional signals.

[0027] The test circuit board primarily handles power distribution and command forwarding functions, integrating a power management module, a clock module, and a control module. The power management module provides stable power to the SOC chip at different voltage levels, adapting to the core voltage and I / O voltage requirements of the SOC chip; the clock module outputs a standard clock signal to ensure the normal operation of the SOC chip; and the control module receives commands from the external host computer and transmits them to the SOC chip, triggering the memory chip's testing process.

[0028] The adapter board is the core component of the solution, employing a multi-layer PCB design. The thickness and number of layers are customized according to signal transmission requirements (typically 8-16 layers), with clear division of functions between the upper and lower surfaces and internal metal layers. The first connection area on the lower surface is the SOC adaptation area. The pin spacing, number, and arrangement of the first pin structure correspond one-to-one with the SOC chip's memory interface pins. The pins are made of highly conductive copper alloy with gold plating to reduce contact resistance. The second connection area on the upper surface is the memory chip adaptation area. The second pin structure can be flexibly designed according to the model of the memory chip under test, adapting to memory chips with different pin arrangements such as LPDDR5 and DDR5. The internal metal layer serves as the signal trace layer, employing a microstrip or stripline design. The metal vias utilize blind-buried via technology to reduce signal crosstalk. The test pads on the upper surface feature a circular or square design, with a pad diameter larger than the oscilloscope probe diameter for precise probe contact, and are gold-plated to prevent oxidation. The resistors on both sides in the second direction are surface-mount precision resistors, with resistance values ​​customized according to the amplitude and frequency of the test signal. The edge connectors are high-speed differential connectors, with the number of output pins matching the number of test signal channels, supporting stable transmission of high-frequency signals.

[0029] Taking the LPDDR5 chip as an example, the memory chip under test is connected to the second pin structure of the adapter board by soldering or socketing. It receives test commands from the SOC chip, completes data read and write operations, and feeds back test signals.

[0030] The logic analyzer is used to acquire test data in batches. By connecting to the connector on the adapter board via a connecting cable, it can simultaneously capture multiple data signals and control signals to analyze the correctness and timing consistency of data transmission. The oscilloscope is used to capture the dynamic waveforms of key signals. After the probe contacts the test pad, it can intuitively display parameters such as the amplitude, period, and jitter of the signal, making it easier to troubleshoot signal integrity issues.

[0031] Pin mapping principle: The adapter board achieves a precise one-to-one mapping between the first and second pins through internal metal layer traces and metal vias. This mapping relationship strictly follows the signal definitions of the SOC chip and the memory chip. For example, the pins of the SOC correspond to the pins of the memory chip through the internal traces of the adapter board, avoiding functional abnormalities caused by signal mismatch. At the same time, the mapping path adopts the shortest path design to shorten the signal transmission distance and reduce signal attenuation.

[0032] Test signal splitting principle: To avoid interference from the test circuit to the functional signals, the solution adopts a "main functional path + test branch path" design. Functional signals are transmitted only along the main path from the first pin to the internal trace and then to the second pin; test signals are split from the second pin, with one path being conditioned by a resistor before connecting to the connector, and the other directly connected to the test pad. A reasonable distance is maintained between the branch path and the main path, and a grounding isolation strip is provided to prevent signal crosstalk.

[0033] Signal conditioning principle: The resistors on both sides of the second direction are the core components of signal conditioning, mainly serving the functions of current limiting, damping, and impedance matching. Current limiting prevents test signal overload from damaging the connector and logic analyzer interface; damping suppresses signal reflection and reduces signal jitter; impedance matching ensures that the source impedance and load impedance remain consistent during test signal transmission, guaranteeing stable signal amplitude and improving the accuracy of test data.

[0034] Memory chip testing has extremely high requirements for signal integrity, especially for high-speed memory chips (such as LPDDR5 with speeds exceeding 5500MT / s). The solution has been comprehensively optimized from three dimensions: wiring, shielding, and protection.

[0035] The internal metal layer of the adapter board uses differential routing, with the data signal and the corresponding strobe signal having strictly consistent trace lengths and the phase difference controlled within a very small range. Grounding copper foil is placed around the traces of critical signals to form a "signal line-ground line" shielding structure, reducing crosstalk between adjacent signals. Sharp angle bends are avoided during the routing process, and 45-degree angles or rounded transitions are used to reduce signal reflection.

[0036] Except for the pin area and test pads, the upper and lower surfaces of the adapter board are covered with a grounding copper layer to enhance the overall shielding effect and resist external electromagnetic interference. Grounding pins are set in the connector and test pad areas, which are connected to the grounding copper layer to form a grounding loop, further improving the anti-interference capability.

[0037] The adapter board has separate power and ground layers. The power layer provides stable power to the first and second pins, while the ground layer is connected to the grounding copper foil and grounding pins of each metal layer to form a low-impedance grounding network, reducing the impact of power supply noise on the signal.

[0038] The solution addresses the testing needs of different memory chip models by providing ample compatibility in the adapter board design, thereby reducing the cost and time required for testing multiple models.

[0039] The second pin structure is customizable: The second connection area on the upper surface of the adapter board adopts a modular design, allowing for customization of different second pin structures based on the number of pins, pin spacing, and pin definitions of the memory chip under test. For example, when testing an LPDDR5 chip, the second pin is designed according to its pin specifications; when testing a DDR5 chip, it is replaced with a second pin module adapted for DDR5, without the need to redesign the overall structure of the adapter board.

[0040] The resistor parameters are replaceable. The precision resistors on both sides of the second direction adopt a pluggable or surface-mount design. According to the signal characteristics of different memory chips, resistors with different resistance values ​​can be quickly replaced to adapt to the conditioning requirements of test signals.

[0041] The connectors are compatible with multiple devices. The edge connectors adopt industry-standard interfaces, making them compatible with logic analyzers of different brands and channel numbers. No additional custom cables are required, which improves the versatility of the solution.

[0042] The application process in memory chip testing scenarios is clear and convenient, enabling rapid completion of test preparation, signal acquisition, and analysis. One side of the SOC chip is soldered or socketed to the test circuit board, while the other side is precisely aligned with the first connection area on the lower surface of the adapter board. The memory chip under test (DUT) is mounted on the second connection area on the upper surface of the adapter board. The logic analyzer's connection cable is connected to the connector on the edge of the adapter board, and the oscilloscope probes are placed on the designated test pads. The test circuit board is powered on; the power management module supplies power to the SOC chip, and the clock module outputs a standard clock. After initialization, the SOC chip receives test commands from the host computer. The SOC chip sends read / write commands to the DUT via the adapter board, and the DUT executes the commands and sends back test signals. The test signals are transmitted in two paths: one path, after resistor conditioning, is transmitted to the logic analyzer via the connector for batch data acquisition; the other path is captured by the oscilloscope through the test pads for real-time waveform display. Testers use a logic analyzer to analyze the accuracy of data transmission and determine whether there are data errors in the memory chip; they use an oscilloscope to observe the timing, amplitude and other parameters of the waveform to check for signal jitter, noise and other problems, and finally complete the performance evaluation of the memory chip.

[0043] It demonstrates multi-dimensional practical value in memory chip testing scenarios, solving the pain points of traditional testing solutions and providing efficient and reliable support for memory chip performance verification. It significantly improves testing accuracy, ensures the reliability of memory chip performance verification, and guarantees the authenticity and accuracy of test data through multi-dimensional design, providing accurate basis for memory chip performance evaluation.

[0044] The differential routing, impedance matching resistors, and grounding shielding structure of the adapter board effectively suppress crosstalk, reflection, and noise interference from high-speed signals (such as the 5500MT / s signal of LPDDR5), ensuring that the test signals are highly consistent with the functional signals of the actual interaction between the SOC and the memory chip, avoiding test misjudgments caused by signal distortion. For example, the waveform captured by the oscilloscope can accurately reflect the timing jitter of the data pins of the memory chip, and the read and write data collected by the logic analyzer can accurately determine the correctness of data transmission.

[0045] The waveform visualization of the oscilloscope and the batch data acquisition of the logic analyzer complement each other, realizing both precise measurement of micro parameters such as signal amplitude and period, and verification of macro performance such as data transmission stability and timing consistency. It covers all dimensions of testing scenarios for memory chips, from "signal quality" to "functional reliability". Compared with a single test device, it can more comprehensively discover potential problems of memory chips (such as hidden timing deviations and occasional data errors).

[0046] The modular design of the adapter board's second pin structure allows for quick matching of pin requirements for different memory chip models such as LPDDR5 and DDR5 by replacing the adapter module, eliminating the need to redesign the entire adapter board or test efficiency system. Replaceable precision resistors and universal interface connectors further reduce hardware replacement costs due to device compatibility or signal characteristic differences. Compared to traditional solutions, hardware development costs for multi-model testing can be reduced by 40%-60%. For testing new memory chip models, only the second pin module of the adapter board needs to be customized and resistor parameters matched; there is no need to rebuild the connection system between the SOC and the test circuit board. The test preparation cycle is shortened from 2-4 weeks in traditional solutions to 1-3 days, significantly improving the response speed of memory chip testing, especially adapting to the rapid iteration testing needs of the chip development stage.

[0047] While ensuring functional communication, the integrated test interface design simplifies the testing process and reduces the complexity of manual operation: traditional solutions require switching hardware between "functional connection" and "test verification" (such as disconnecting the SOC from the memory chip and then connecting to the test equipment), while this solution, through the parallel design of "functional main path + test branch path", can realize normal interaction between the SOC and the memory chip and test signal acquisition simultaneously without disassembling or reassembling the hardware. For example, testers can observe the signal waveform in real time through an oscilloscope without interrupting the SOC's read and write commands to the memory chip, improving test efficiency by more than 30%.

[0048] The adapter board integrates test pads, resistor conditioning circuitry, and connectors. Oscilloscope probes can directly contact the pads, and logic analyzer cables can be inserted into the edge connectors to start testing, eliminating the need for building complex test wiring circuits. Meanwhile, the gold-plated test pads and their larger diameter design reduce probe contact deviation, and the universal interface design of the connectors avoids equipment adaptation and debugging. Even non-experienced testers can quickly complete test preparation, reducing human training costs.

[0049] During the R&D process of memory chips, this solution can capture signal waveforms in real time using an oscilloscope, helping engineers locate chip design defects (such as amplitude attenuation caused by insufficient pin drive capability). It can also collect abnormal data in batches using a logic analyzer to analyze timing optimization directions, providing data support for chip iteration. In the mass production stage of memory chips, the solution's rapid test preparation features and accurate data acquisition capabilities enable efficient quality inspection of batch chips. For example, by simultaneously testing the read / write speed and data accuracy of 10-20 memory chips using a logic analyzer, the mass production quality inspection efficiency is improved by 5-8 times compared to traditional single-chip testing. Furthermore, the test results can be directly integrated into the production management system to generate digital quality inspection reports. The solution's high-temperature resistance and anti-interference design are suitable for extreme environment testing of memory chips in fields such as automotive electronics and industrial control (such as high-temperature and high electromagnetic interference scenarios). Through stable signal transmission and test acquisition, the reliability of memory chips under harsh conditions is verified, expanding the application scope of the solution in specialized industries.

[0050] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0051] In one embodiment, a testing method for memory chip testing based on a system for improving the testing efficiency of a logic analyzer for memory chips is provided. This personalized insurance product recommendation device based on LSTM technology corresponds one-to-one with the system for improving the testing efficiency of a logic analyzer for memory chips described in the above embodiment. For example... Figures 1-3 As shown,

[0052] Step 1: Set up the adapter board according to the layout of the LPDDR5 chip. The first connection area on the lower surface of the adapter board is used to connect the SOC chip, and the second connection area on the upper surface of the adapter board is used to connect the memory chip under test. The first connection area on the lower surface of the adapter board has a first pin structure corresponding to the pin arrangement of the SOC chip, and the first pin structure includes multiple first pins. The second connection area on the upper surface of the adapter board has a second pin structure corresponding to the pin arrangement of the memory chip under test, and each second pin structure includes multiple second pins. The adapter board includes multiple gold... The adapter board has a metal layer, and each second pin is connected to the corresponding first pin through at least one trace and metal via in the metal layer. The upper surface of the adapter board is also provided with a plurality of test pads located on both sides of the second connection area along the first direction, a plurality of resistors located on both sides of the second connection area along the second direction, and connectors located at the edges of the adapter board along the first direction. The first direction and the second direction are perpendicular. The connectors include a plurality of output pins. The second pins in the second connection area are connected to one end of the corresponding resistor through traces, and the other end of the resistor is connected to the corresponding output pin through traces. The test pads are connected to at least one second pin through traces in the metal layer.

[0053] Step 2: After soldering the LPDDR5 chip onto the upper surface of the adapter board, a test circuit board is assembled. The test circuit board has a mounting area.

[0054] Step 3: Solder the lower surface of the adapter board to the mounting area, and solder the SOC chip to the mounting area of ​​the test circuit board so that the LPDDR5 chip is connected to the SOC chip through the adapter board.

[0055] Step 4: Connect the connector to the logic analyzer and the test pads to the oscilloscope. The test circuit board will test the LPDDR5 chip. The test signal or test data of the memory chip under test will be output to the logic analyzer through the connector. The logic analyzer will analyze the test signal or test data and obtain the test results. The test results will be displayed on the oscilloscope.

[0056] This embodiment focuses on the pin characteristics and signal requirements of LPDDR5 chips. Through customized adapter board design, precise hardware assembly, and professional test connections, it achieves functional interoperability and performance testing between LPDDR5 chips and SOC chips. The adapter board strictly matches the pin definitions, signal characteristics, and package specifications of the LPDDR5 chip, and integrates test interfaces to ensure functional compatibility and test feasibility.

[0057] The adapter board features a dual-layer pin structure design (matching LPDDR5 and SOC): The first pin structure on the lower surface (interfacing with the SOC chip) is designed based on the pin definitions of the SOC chip's LPDDR5 controller, covering all types of pins required for LPDDR5 communication. The first pin structure includes at least: Data pins: 16 in total, corresponding to the 16-bit data bus of LPDDR5. The pin spacing must match the pin spacing of the SOC chip (usually 0.5mm or 0.65mm, depending on the SOC package model); Data strobe pins: 1 set of differential data strobe pins for every 8 data pins (2 sets in total). The spacing between the data strobe pins and adjacent data pins must meet impedance matching requirements; Address / control pins: Arranged according to the address and control pin sequence of the SOC chip to ensure consistent instruction signal transmission timing; Power / ground pins: Evenly distributed around the signal pins, with one ground pin configured for every 4-6 signal pins to reduce power supply noise interference to the signal. The first pin structure is made of copper alloy substrate with gold plating (thickness ≥3um) to reduce contact resistance (e.g., contact resistance ≤50log) and avoid poor contact caused by oxidation, adapting to the transmission requirements of LPDDR5 high-speed signals (5500MT / s and above).

[0058] The upper surface has a second pin structure (interfacing with the LPDDR5 chip). The pin arrangement follows the LPDDR5 chip's package pin specifications (taking common FBGA packages as an example, such as 110-ball or 132-ball packages). The key pin correspondences are as follows: The data pins of the second pin structure correspond one-to-one with the pins of the LPDDR5 chip. The pin spacing is consistent with the ball spacing of the LPDDR5 package (usually 0.8mm), and ensures that the pad area of ​​each data pin of the second pin structure (e.g., pad area ≥ 0.2mm²) meets the reflow soldering process requirements; the differential signal pins must ensure that the center-to-center spacing of the differential pair pins is 0.8mm (meeting the FBGA package standard), and the trace length difference is ≤ 500um to avoid timing offset; the power pins correspond to the power input pins of the LPDDR5 chip, and the pads must have pre-reserved heat dissipation holes to prevent local overheating and chip damage during soldering; the ground pins correspond completely to the pins of the LPDDR5 chip, and the number of ground pins is ≥ 1.5 times the number of power pins to enhance the grounding effect. The pin identification design marks the pin number next to the second pin structure, which facilitates pin alignment during LPDDR5 chip soldering and avoids incorrect soldering.

[0059] The adapter board features an internal metal layer and signal connection design. The metal layer configuration (adapted to LPDDR5 high-speed signals) utilizes an 8-layer PCB design, with the layer stack-up order as follows: "Top surface - First signal trace layer - Ground layer - Second signal trace layer - Third signal trace layer - Power layer - Fourth signal trace layer - Bottom surface." The ground and power layers are complete, covering the entire adapter board area, providing stable power and ground references for LPDDR5 high-speed signals. The signal trace layers are used for connecting the first and second pins, as well as routing test pads, resistors, and connectors. The metal layer material is high-purity electrolytic copper (purity ≥99.9%). Trace widths are customized according to signal type: Data / address signals: 0.15mm width, impedance control of 50Ω±10%; Differential signals: 0.12mm width, 0.18mm spacing, differential impedance control of 100Ω±10%; Power / ground traces: 0.3mm width to reduce current loss.

[0060] For signal connection paths, each second pin (interfacing with LPDDR5) is connected to its unique first pin (interfacing with the SOC) via a "signal trace layer + metal via". For example: LPDDR5 data pin (second pin) → first signal trace layer → metal via (e.g., blind via, from the top surface layer to the first signal trace layer) → third signal trace layer → metal via (e.g., buried via, from the third signal trace layer to the bottom surface layer) → SOC data pin (first pin). All signal path lengths are controlled within the range of 5mm-8mm, and the path length difference between signals in the same group is ≤300um (micrometers) to ensure timing synchronization. The metal vias are designed using laser drilling technology, with a via diameter of 0.1mm and a copper plating thickness ≥20um. A grounding ring (0.05mm wide) is placed around the via to reduce crosstalk between the vias and adjacent signals.

[0061] The adapter board features an auxiliary test structure (e.g., to accommodate LPDDR5 testing requirements). Test pads (connected to the oscilloscope) are distributed along a first direction (e.g., the X-axis) on both sides of the second connection area (corresponding to the LPDDR5 soldering area), with 8-10 pads on each side, totaling 16-20. Priority is given to connecting critical LPDDR5 pins: mandatory connections: 4 sets of differential strobe signals and clock signals; optional connections: data signals. The pads are circular with a diameter of 0.5mm, gold-plated (thickness ≥2um), and a 1mm center-to-center spacing to facilitate precise contact by oscilloscope probes (e.g., commonly 0.3mm diameter). The spacing between the pads and adjacent traces is ≥0.2mm to prevent short circuits.

[0062] Resistors (signal conditioning) are distributed along the second direction (e.g., the Y-axis, perpendicular to the X-axis) on both sides of the second connection area, with 12-16 resistors on each side, corresponding one-to-one with the LPDDR5 signal pins. The resistor parameters must be adapted to the LPDDR5 signal characteristics: 50Ω±5% precision surface-mount resistors are used to match the signal source impedance with the load impedance and suppress signal reflection; 1 / 16W power resistors are used to meet the power consumption requirements of the LPDDR5 signal (e.g., single-channel signal current ≤10mA). One end of each resistor is connected to the corresponding second pin (e.g., the LPDDR5 signal pin) via a Signal1 layer trace, and the other end is connected to the connector's output pin via a Signal2 layer trace. The trace length is ≤3mm, and the distance between the resistor and the second pin is ≥0.3mm to avoid heat effects during soldering.

[0063] Connectors (for docking logic analyzers) are distributed along the first direction (e.g., the X-axis) on both sides of the adapter board. Each side has one high-speed differential connector (e.g., TE Connectivity 1784894-2, or an industrial-grade connector of the same specification). Each connector contains 24 output pins, covering all signal channels of LPDDR5: output pin allocation: 16 data signals, 4 data strobe signals (2 differential groups), 2 clock signals (1 differential group), and 2 control signals; the interface supports a maximum signal transmission rate of 8000MT / s, meeting the high-speed testing requirements of LPDDR5. The connectors are soldered to the adapter board using a reflow soldering process, with the soldering temperature controlled at 240℃±5℃.

[0064] The test circuit board needs to have reserved mounting area for the adapter board. Precise soldering is required to achieve hardware integration of LPDDR5, the adapter board, and the SOC. The specific steps are as follows:

[0065] The dimensions of the mounting area are consistent with the dimensions of the lower surface of the adapter board (e.g., if the adapter board is 50mm × 40mm, the mounting area is 50mm × 40mm). A soldering pad is provided within the area that perfectly corresponds to the structure of the first pin on the adapter board (e.g., material, spacing, and quantity are identical to the first pin). A 0.5mm positioning mark is reserved around the soldering pad to facilitate adapter board alignment. Four positioning holes (e.g., 1mm in diameter) are provided at the edge of the mounting area, corresponding to the positioning holes on the adapter board. Precise fixing of the adapter board is achieved through positioning pins, with a positioning error ≤0.1mm, preventing pin misalignment during soldering.

[0066] Solder the adapter board to the test circuit board. Clean the lower surface of the adapter board and the mounting area of ​​the test circuit board, wiping away oil and dust with isopropyl alcohol to ensure the soldering surface is free of impurities. Apply flux (e.g., no-clean flux, viscosity 100-150 cP) to the soldering pads in the mounting area of ​​the test circuit board, with a thickness ≤0.1mm. Precisely align the first pin structure on the lower surface of the adapter board with the soldering pads in the mounting area of ​​the test circuit board and secure it with locating pins. Use reflow soldering, with the soldering curve set as follows: preheating stage (e.g., 150℃, 60s) → heating stage (e.g., 150℃-220℃, 30s) → peak stage (e.g., 245℃±5℃, 10s) → cooling stage (e.g., 220℃-100℃, 40s). Post-soldering inspection: Use a magnifying glass (e.g., 20x magnification) to observe the soldering condition of all pins, ensuring no cold solder joints (e.g., solder fill rate ≥90%) or short circuits (e.g., no solder bridges between pins).

[0067] Apply solder paste (with a particle size ≤25um, suitable for FBGA package soldering) to the second connection area on the upper surface of the adapter board, with a thickness of 0.1mm-0.15mm; according to the markings next to the second pin structure, precisely align the pins of the LPDDR5 chip with the second pin to ensure that the critical pins are not misaligned.

[0068] Hot air gun soldering is used (e.g., hot air gun temperature 300℃±10℃, air speed level 3). Heat evenly from the center of the chip to the edge for 15s-20s until the flux completely melts and forms a solder joint. Post-soldering inspection: Check the internal quality of the BGA solder joint with X-ray inspection (e.g., resolution ≤5um) to ensure there are no voids (e.g., void rate ≤5%). At the same time, use a multimeter to measure the resistance between the power pin and the ground pin (e.g., resistance ≥100kΩ) to rule out short circuit faults.

[0069] The pins of the SOC chip must match the reserved pins in the mounting area of ​​the test circuit board (excluding the area covered by the adapter board). The SOC chip is soldered using a reflow soldering process, and the soldering curve is consistent with that of the adapter board. However, the peak temperature needs to be adjusted according to the heat resistance rating of the SOC chip (e.g., if the SOC is a 12nm process, the peak temperature should be ≤235℃). Power on the test circuit board (e.g., the initial voltage is 80% of the SOC core voltage), and measure the clock pin output of the SOC using an oscilloscope (e.g., the frequency must meet the clock requirements of the LPDDR5 controller, such as 1600MHz) to confirm that the SOC chip starts up normally.

[0070] After completing the hardware assembly, the performance of the LPDDR5 chip is verified by connecting the test equipment and executing the test procedure. The specific steps are as follows:

[0071] Select a logic analyzer that supports high-speed parallel signal acquisition (such as the Tektronix MSO58 or equivalent), with a sampling rate ≥10GS / s and ≥32 channels to meet the acquisition requirements of all LPDDR5 signal channels. Use impedance matching cables (e.g., 50Ω characteristic impedance, 1m length) to connect the logic analyzer's channel interfaces to the connectors on both sides of the adapter board one by one. For example: Logic analyzer channel 1 → connector output pin 1, channel 2 → output pin 2... channel 24 → output pin 24; after connection, use the logic analyzer's self-test function to confirm the signal integrity of all channels (e.g., amplitude deviation ≤5%) to rule out poor connection issues.

[0072] Select a dual-channel or quad-channel oscilloscope (such as the Keysight DSOX1204G or equivalent), with a bandwidth ≥2GHz, a sampling rate ≥10GS / s, and support for differential signal measurement. Use an active differential probe (e.g., 1MΩ / 50Ω input impedance, 2GHz bandwidth). Contact the positive probe terminal to the test pad and the negative terminal to the adjacent ground pad, ensuring uniform contact pressure between the probe and the pads (to avoid damaging the pads). Oscilloscope parameter settings: select "Data Strobe Signal" as the trigger source, set the trigger level to 0.5V (midpoint level of the LPDDR5 signal), set the time base to 100ps / div, and set the voltage range to 1V / div for easy observation of signal timing and amplitude.

[0073] Power on the test circuit board, and the power management module outputs the voltage required by LPDDR5, as well as the core voltage (e.g., 0.8V) and IO voltage (e.g., 1.8V) required by the SOC. The host computer sends an initialization command to the SOC chip, and the SOC's LPDDR5 controller completes the configuration of the LPDDR5 chip (including timing parameters, burst length, prefetch mechanism, etc., which must comply with the JEDEC LPDDR5 standard). After the configuration is completed, the SOC sends a "read / write test start signal" to the LPDDR5.

[0074] The logic analyzer collects all LPDDR5 signals at a sampling rate of 10GS / s, with a sampling duration of 10ms, covering more than 1000 read / write cycles. The analysis and test data are then performed: the logic analyzer automatically compares the consistency between "sent data" and "received data," and calculates the statistical error rate (required to be ≤). At the same time, it analyzes the timing relationship between address signals and control signals to determine whether there are problems such as address latching errors or command execution delays, and finally generates a "data integrity test report".

[0075] The oscilloscope captures the waveforms of key signals (such as synchronization waveforms and clock waveforms) in real time, displaying the signal amplitude (VIH ≥ 0.8V, VIL ≤ 0.2V), rise time (e.g., rise time ≤ 50ps), and jitter (e.g., jitter ≤ 10ps). It performs quantitative analysis of the waveforms: using the oscilloscope's "jitter measurement" function, it calculates the signal's periodic jitter and time interval error to determine if it conforms to the LPDDR5 timing specifications. Simultaneously, it observes whether the waveform has overshoot (≤ 10%) or undershoot (≥ -10%), identifies signal integrity issues, and generates a "waveform quality analysis report."

[0076] Test data from the logic analyzer and oscilloscope are uploaded to the host computer via USB interface. The host computer integrates the two reports and generates an "LPDDR5 Chip Comprehensive Test Report," marking it as "Pass" or "Fail" (Pass standard: data error rate ≤ (Signal jitter ≤10ps, amplitude conforms to specifications);

[0077] If the test fails, locate the problem point according to the report (e.g., data error corresponds to poor soldering of data pins, excessive jitter corresponds to impedance mismatch), re-check the hardware soldering or adjust the adapter board traces until the test passes.

[0078] This embodiment, by leveraging the high-speed characteristics and testing requirements of LPDDR5 chips, demonstrates multi-dimensional practical value in LPDDR5 chip functional verification and performance testing scenarios through customized adapter board design, standardized assembly processes, and professional testing configuration. Through multi-stage design optimization, it ensures that test data accurately reflects the performance of the LPDDR5 chip, providing a reliable basis for chip quality assessment.

[0079] For LPDDR5 high-speed signals of 5500MT / s and above, the adapter board adopts an 8-layer PCB structure, differential traces (e.g., impedance 100Ω±10%), 50Ω precision matching resistors, and full-area grounding shielding to effectively suppress signal crosstalk, reflection, and electromagnetic interference. For example, the difference in trace length between the selected data signal and the data signal is ≤300μm to ensure timing synchronization. The waveform jitter captured by the oscilloscope is ≤10ps, which is highly consistent with the actual operating state of LPDDR5 and avoids test misjudgments caused by signal distortion.

[0080] The logic analyzer (sampling rate ≥ 10GS / s) enables batch data acquisition from all signal channels, including 16 data signals and 4 data strobe signals, and can accurately calculate the statistical error rate (required ≤). The test assesses data transmission integrity using a macroscopic method; an oscilloscope (bandwidth ≥ 2GHz) focuses on key signal amplitudes (e.g., VIH ≥ 0.8V, VIL ≤ 0.2V), rise time (≤ 50ps), and other microscopic parameters to investigate signal quality issues. This combined approach covers both "macroscopic data reliability" and "microscopic signal quality," providing a more comprehensive detection of hidden defects in LPDDR5 (such as occasional timing deviations) compared to single-device testing.

[0081] By precisely controlling the reflow soldering profile (peak temperature 245℃±5℃), X-ray inspection (void rate ≤5%), and multimeter resistance verification (power supply and ground resistance ≥100kΩ), we ensure that the soldering of LPDDR5, adapter boards, and SOCs is free of cold solder joints and short circuits, avoiding test anomalies caused by hardware connection problems and further improving the reliability of test results.

[0082] The second pin structure on the upper surface of the adapter board can be flexibly adjusted according to different LPDDR5 packages (such as 110-ball / 132-ball FBGA). Only the pin module needs to be replaced to adapt to different LPDDR5 models. The connector uses an industrial-grade standard interface, compatible with mainstream logic analyzers, eliminating the need for customized dedicated interfaces. Compared to traditional solutions, this reduces hardware development costs and shortens the development cycle for testing multiple LPDDR5 models.

[0083] The test circuit board mounting area has reserved positioning holes (error ≤ 0.1mm) and marking lines. The soldering of the adapter board, LPDDR5, and SOC all have clear parameters (such as hot air gun temperature 300℃±10℃, flux thickness 0.1-0.15mm). Even non-senior engineers can operate according to the process, reducing human training costs by 40%. At the same time, functional connection and testing can be achieved simultaneously without disassembling the hardware, shortening test preparation time by more than 60%.

[0084] The adapter board integrates test pads (e.g., 0.5mm in diameter, 1mm spacing) and edge connectors on its upper surface. Oscilloscope probes simply contact the pads, and logic analyzer cables are inserted into the connectors to complete the test connection, eliminating the need for complex additional wiring circuitry. Compared to the traditional method of "soldering test leads point by point," this reduces wiring time and avoids equipment damage caused by wiring errors.

[0085] The host computer can automatically issue LPDDR5 initialization commands (timing parameters, prefetching mechanisms, etc., comply with JEDEC standards). The logic analyzer and oscilloscope automatically collect data and generate "data integrity reports" and "waveform quality reports," which are ultimately integrated into a comprehensive test report (marked as pass / fail). Testers no longer need to manually analyze massive amounts of data, improving analysis efficiency. The reports are highly standardized, facilitating the archiving and comparison of batch test data.

[0086] In the embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0087] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0088] The above are merely embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A system for improving the testing efficiency of a logic analyzer for memory chips, characterized in that, The system includes: a SOC chip, an adapter board, a test circuit board, a memory chip under test, a logic analyzer, and an oscilloscope. The test circuit board is used for power distribution and command forwarding. One side of the SOC chip is connected to the test circuit board, and the other side is connected to the lower surface of the adapter board; The adapter board has a first connection area on its lower surface for connecting a SOC chip, and a second connection area on its upper surface for connecting a memory chip under test. The first connection area on the lower surface of the adapter board has a first pin structure corresponding to the pin arrangement of the SOC chip, and the first pin structure includes multiple first pins. The second connection area on the upper surface of the adapter board has a second pin structure corresponding to the pin arrangement of the memory chip under test, and each second pin structure includes multiple second pins. The adapter board includes multiple metal layers stacked between the upper and lower surfaces. Each second pin is connected to the corresponding first pin through a trace and a metal via in at least one metal layer, thus enabling the SOC chip to connect to the memory chip. The adapter board's upper surface is further provided with several test pads located on both sides of the second connection area along the first direction, several resistors located on both sides of the second connection area along the second direction, and connectors located at the edges of the adapter board along the first direction. The connectors are connected to the connection lines of a logic analyzer, outputting the test signals or test data of the memory chip under test to the logic analyzer. The first and second directions are perpendicular. The connectors include several output pins. The second pins in the second connection area are connected to one end of the corresponding resistors through traces, and the other end of the resistors are connected to the output pins of the corresponding connectors through traces. The test pads are connected to at least one second pin through traces in the metal layer, and the test pads are connected to an oscilloscope to display the test waveforms. The system employs a test signal splitting mechanism. Functional signals are transmitted only along the main path from the first pin to the internal trace and then to the second pin. Test signals, on the other hand, branch off from the second pin, with one path being conditioned by a resistor and connected to the connector, and the other path being directly connected to the test pad.

2. A method for testing the efficiency of a memory chip based on the testing efficiency system described in claim 1, characterized in that, The method includes the following steps: The adapter board is configured according to the layout of the LPDDR5 chip. The first connection area on the lower surface of the adapter board is used to connect the SOC chip, and the second connection area on the upper surface of the adapter board is used to connect the memory chip under test. The first connection area on the lower surface of the adapter board is provided with a first pin structure corresponding to the pin arrangement of the SOC chip. The first pin structure includes multiple first pins. The second connection area on the upper surface of the adapter board is provided with a second pin structure corresponding to the pin arrangement of the memory chip under test. Each second pin structure includes multiple second pins. The adapter board includes multiple metal layers stacked between the upper and lower surfaces. Each second pin is connected to the corresponding first pin through a trace and a metal via in at least one metal layer. The upper surface of the adapter board is also provided with a number of test pads located on both sides of the second connection area along the first direction, a number of resistors located on both sides of the second connection area along the second direction, and connectors located at the edges of both sides of the adapter board along the first direction. The first direction and the second direction are perpendicular. The connectors include a number of output pins. The second pins in the second connection area are connected to one end of the corresponding resistor through a trace, and the other end of the resistor is connected to the corresponding output pin through a trace. The test pads are connected to at least one second pin through traces in the metal layers. After the LPDDR5 chip is soldered onto the upper surface of the adapter board, a test circuit board is formed, which has a mounting area. The lower surface of the adapter board is soldered to the mounting area, and the SOC chip is soldered to the mounting area of ​​the test circuit board, so that the LPDDR5 chip is connected to the SOC chip through the adapter board. Connect the connector to the logic analyzer and the test pads to the oscilloscope. The test circuit board tests the LPDDR5 chip. The test signal or test data of the memory chip under test is output to the logic analyzer through the connector. The logic analyzer analyzes the test signal or test data and obtains the test results. The test results are displayed on the oscilloscope.

Images