DDR reference voltage parameter adjustment method, system, device and storage medium

Abstract

The application discloses a DDR reference voltage parameter adjustment method, system, device and storage medium, the method comprises the following steps: obtaining a digital eye diagram of a read direction of a DDR memory and a corresponding eye height amplitude distribution; excluding invalid sampling points caused by register range limitation from sampling points of the digital eye diagram to obtain a set of valid sampling points; determining a target optimization region according to the eye height amplitude distribution of the set of valid sampling points; optimizing a read direction Vref value of the target optimization region, and synchronously adjusting a write direction Vref value and a terminal resistance parameter; compiling the read direction Vref value, the write direction Vref value and the terminal resistance parameter after adjustment into configuration code to write into a test program of a DDR memory controller; running the test program and obtaining an optimized digital eye diagram until the eye height of the optimized digital eye diagram meets a preset tolerance; and the application can avoid interference of invalid sampling points caused by register range limitation, and realize accurate determination of an optimal Vref parameter combination.

Description

Technical Field

[0001] This application belongs to the field of DDR technology, specifically relating to a method, system, device and storage medium for adjusting DDR reference voltage parameters. Background Technology

[0002] With the development of DDR4 (Double Data Rate 4 Synchronous Dynamic Random-Access Memory), LPDDR4 (Low Power Double Data Rate 4 Synchronous Dynamic Random-Access Memory), and LPDDR5 (Low Power Double Data Rate 5 Synchronous Dynamic Random-Access Memory) memory technologies, data transmission rates and bandwidths have significantly improved. Ensuring system signal integrity has become particularly critical. The eye width and eye height of the signal eye diagram are key indicators for measuring the quality of high-speed signals, and their stability directly affects the reliability and performance of the system.

[0003] The factors affecting eye diagram quality are numerous. To maintain sufficient timing margin and noise tolerance under high-speed operating conditions, existing DDR memory systems have introduced a Vref (reference voltage) calibration mechanism to improve stability in the eye height direction while ensuring sufficient eye width. Among common adjustment methods, to facilitate signal quality evaluation, the actual analog eye diagram is usually converted into a digital two-dimensional eye diagram composed of several sampling points for analysis.

[0004] However, this type of digital eye diagram is not intuitive enough in characterizing signal quality. It requires repeated comparison of eye diagram differences at different frequencies for evaluation. Furthermore, it is difficult to identify and eliminate invalid sampling points, which makes it impossible to accurately restore the optimal voltage position when using the eye diagram for reference voltage calibration, thus affecting the final signal margin and system stability. Summary of the Invention

[0005] This application provides a method, system, device, and storage medium for adjusting DDR reference voltage parameters, which can avoid interference from invalid sampling points caused by register range limitations and achieve accurate determination of the optimal Vref parameter combination.

[0006] To address the aforementioned technical problems, in a first aspect, this application provides a method for adjusting DDR reference voltage parameters, comprising the following steps:

[0007] Obtain the digital eye diagram of the DDR memory read direction and the corresponding eye height amplitude distribution;

[0008] From the sampling points of the digital eye diagram, invalid sampling points due to register range limitations are excluded to obtain a set of valid sampling points;

[0009] The target optimization region is determined based on the eye height amplitude distribution of the effective sampling point set;

[0010] The read direction Vref value of the target optimization region is optimized, and the write direction Vref value and the termination resistance parameter are adjusted simultaneously.

[0011] The adjusted and determined read direction Vref value, write direction Vref value, and termination resistor parameters are compiled into configuration code and written into a test program for the DDR memory controller.

[0012] Run the test program and obtain the optimized digital eye diagram until the eye height of the optimized digital eye diagram meets the preset tolerance. Then lock the current corresponding read direction Vref value, write direction Vref value and termination resistor parameter as the optimal Vref parameter combination.

[0013] As a further improvement to this application, the exclusion of invalid sampling points due to register range limitations includes:

[0014] For each sampling point in the digital eye diagram, obtain the equalization control register value corresponding to its sampling time;

[0015] When the value of the equalization control register exceeds the preset valid value range, the current sampling point is determined to be invalid and is discarded.

[0016] As a further improvement to this application, the step of determining the target optimization region based on the eye height amplitude distribution of the effective sampling point set includes:

[0017] The digital eye diagram is divided into several grids, and the number of valid sampling points falling into each grid is counted to determine the sampling point density of each grid.

[0018] Connect adjacent grids with sampling point density higher than the first density threshold to form one or more candidate optimization regions;

[0019] Calculate the average eye height amplitude of all valid sampling points within each candidate optimization region;

[0020] The candidate optimization region with the highest average eye height amplitude exceeding the first amplitude threshold is determined as the target optimization region.

[0021] As a further improvement to this application, the optimization of the read direction Vref value of the target optimization region includes:

[0022] Obtain the voltage values ​​of all valid sampling points within the target optimization area;

[0023] The median or average value of the voltage is determined as the read direction Vref value of the target optimization region for optimization.

[0024] As a further improvement to this application, the synchronous adjustment of the write direction Vref value and the termination resistor parameter includes:

[0025] The write direction Vref value is determined based on the optimized read direction Vref value and the preset matching relationship between the write direction Vref value and the read direction Vref value.

[0026] Obtain the overshoot and undershoot amplitudes of the signal waveform at the logic level transition of the digital eye diagram;

[0027] Compare the overshoot amplitude with the undershoot amplitude. If the overshoot amplitude is greater than the undershoot amplitude, increase the terminating resistor parameter; if the overshoot amplitude is less than the undershoot amplitude, decrease the terminating resistor parameter.

[0028] The terminating resistor parameter is the negative feedback parameter of the on-chip terminating resistor.

[0029] As a further improvement to this application, the step of ensuring that the eye height of the optimized digital eye diagram meets a preset tolerance includes:

[0030] Determine whether the eye height of the optimized digital eye diagram meets the preset tolerance;

[0031] If satisfied, the Vref value for the read direction, the Vref value for the write direction, and the terminal resistance parameter corresponding to the current digital eye diagram will be locked as the optimal combination of Vref parameters.

[0032] If the conditions are not met, the Vref value for the read direction, the Vref value for the write direction, and the terminal resistance parameters corresponding to the current digital eye diagram will be iteratively optimized.

[0033] As a further improvement to this application, the iterative optimization of the read direction Vref value, write direction Vref value, and termination resistance parameters corresponding to the current digital eye diagram includes:

[0034] Based on the optimized digital eye diagram and the corresponding eye height amplitude distribution, the set of effective sampling points is updated.

[0035] Repeat the steps of determining the target optimization region, optimizing the read direction Vref value, adjusting the write direction Vref value and the terminal resistor parameter, compiling and running the test program, obtaining the optimized digital eye diagram, and determining whether the eye height meets the preset tolerance, until the eye height of the optimized digital eye diagram meets the preset tolerance.

[0036] The read direction Vref value, write direction Vref value, and termination resistor parameter corresponding to the current digital eye diagram are locked as the optimal Vref parameter combination.

[0037] Secondly, this application provides a DDR reference voltage parameter adjustment system, comprising:

[0038] The acquisition unit is used to acquire the digital eye diagram of the DDR memory read direction and the corresponding eye height amplitude distribution;

[0039] The exclusion unit is used to exclude invalid sampling points from the sampling points of the digital eye diagram due to register range limitations, thereby obtaining a set of valid sampling points;

[0040] The determining unit is used to determine the target optimization region based on the eye height amplitude distribution of the effective sampling point set;

[0041] The adjustment unit is used to optimize the read direction Vref value of the target optimization region, and simultaneously adjust the write direction Vref value and the terminal resistance parameter.

[0042] The compilation unit is used to compile the adjusted and determined read direction Vref value, write direction Vref value, and termination resistor parameters into a test program that writes configuration code to the DDR memory controller.

[0043] The optimization unit is used to run the test program and obtain the optimized digital eye diagram until the eye height of the optimized digital eye diagram meets the preset tolerance, and lock the current corresponding read direction Vref value, write direction Vref value and termination resistor parameter as the optimal Vref parameter combination.

[0044] Thirdly, this application provides a computer device, the computer device including a processor and a memory coupled to the processor, the memory storing a calculation program, the computer program being executed by the processor causing the processor to perform the steps of the above-described DDR reference voltage parameter adjustment method.

[0045] Fourthly, this application provides a computer-readable storage medium storing a computer program that is executed by a processor to implement the above-described DDR reference voltage parameter adjustment method.

[0046] The DDR reference voltage parameter adjustment method, system, device, and storage medium provided in this application have the following beneficial effects:

[0047] This application first obtains the digital eye diagram of the DDR memory read direction and the corresponding eye height amplitude distribution. The analog read direction signal is converted into quantifiable discrete data. Invalid sampling points due to register range limitations are excluded from the sampling points of the digital eye diagram, eliminating distorted data caused by register saturation. This ensures that the effective sampling point set accurately reflects the actual transmission characteristics of the read direction signal, eliminating interference from invalid sampling points. Based on the eye height amplitude distribution of this effective sampling point set, a target optimization region is determined, allowing the optimization of the read direction Vref value to focus on this target optimization region. Simultaneously, the write direction Vref value and termination resistor parameters are adjusted, taking into account... The collaborative characteristics of the shared transmission link for DDR memory read and write signals and the impedance matching requirements of the transmission link are considered. Then, the adjusted parameters are compiled into configuration code and written into the test program of the DDR memory controller. By running the test program, the optimized digital eye diagram is obtained iteratively until the optimized eye height meets the preset tolerance and the optimal parameter combination is locked. This ensures that the final parameter combination can stably adapt to the DDR memory hardware state, avoids interference from invalid sampling points caused by register range limitations, achieves accurate determination of the optimal Vref parameter combination, effectively improves the eye height margin and noise tolerance of the read direction signal, and enhances the reliability of DDR memory data reading and the overall signal integrity. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only a part of the embodiments of this application, and not all of the embodiments. For those skilled in the art, other drawings obtained from these drawings without creative effort are all within the scope of protection of this application.

[0049] Figure 1 This is a flowchart of the DDR reference voltage parameter adjustment method provided in the embodiments of this application.

[0050] Figure 2 This is a flowchart illustrating the process of excluding invalid sampling points in the DDR reference voltage parameter adjustment method provided in this application embodiment.

[0051] Figure 3 This is a flowchart illustrating the determination of the target optimization region in the DDR reference voltage parameter adjustment method provided in this application embodiment.

[0052] Figure 4 This is a flowchart illustrating the optimization of the read direction Vref value in the DDR reference voltage parameter adjustment method provided in this application embodiment.

[0053] Figure 5 This is a flowchart illustrating the adjustment of the write direction Vref value and the termination resistor parameter in the DDR reference voltage parameter adjustment method provided in this application embodiment.

[0054] Figure 6 This is a flowchart illustrating the process of determining whether the eye height of the digital eye diagram meets the preset tolerance in the DDR reference voltage parameter adjustment method provided in this application embodiment.

[0055] Figure 7 This is a flowchart illustrating the determination of the optimal Vref parameter combination in the DDR reference voltage parameter adjustment method provided in this application embodiment.

[0056] Figure 8 This is an embodiment diagram of the grid in the DDR reference voltage parameter adjustment method provided in this application.

[0057] Figure 9 This is a block diagram of the DDR reference voltage parameter adjustment system provided in the embodiments of this application.

[0058] Figure 10 A schematic diagram of the structure of a computer device provided in an embodiment of this application.

[0059] Figure 11 This is a schematic diagram of the structure of the storage medium provided in the embodiments of this application. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0061] To make the description of this disclosure more detailed and complete, illustrative descriptions of the implementation methods and specific embodiments of this application are provided below; however, this is not the only form of implementing or utilizing the specific embodiments of this application. The implementation methods cover the features of multiple specific embodiments and the method steps and their order for constructing and operating these specific embodiments. However, other specific embodiments can also be used to achieve the same or equivalent functions and step sequences. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0062] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0063] In the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The word "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more. Other quantifiers should be understood similarly. The preferred embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. Furthermore, the embodiments of this application and the features in the embodiments can be combined with each other without conflict.

[0064] With the development of DDR4, LPDDR4 and LPDDR5 memory technologies, data transmission rates and bandwidth have been significantly improved, making the guarantee of system signal integrity particularly critical. The eye width and eye height of the signal eye diagram are key indicators for measuring the quality of high-speed signals, and their stability is directly related to the reliability and performance of the system.

[0065] The factors affecting eye diagram quality are numerous. To maintain sufficient timing margin and noise tolerance under high-speed operating conditions, existing DDR memory systems have introduced a Vref (reference voltage) calibration mechanism to improve stability in the eye height direction while ensuring sufficient eye width. Among common adjustment methods, to facilitate signal quality evaluation, the actual analog eye diagram is usually converted into a digital two-dimensional eye diagram composed of several sampling points for analysis.

[0066] However, this type of digital eye diagram is not intuitive enough in characterizing signal quality. It requires repeated comparison of eye diagram differences at different frequencies for evaluation. Furthermore, it is difficult to identify and eliminate invalid sampling points, which makes it impossible to accurately restore the optimal voltage position when using the eye diagram for reference voltage calibration, thus affecting the final signal margin and system stability.

[0067] In view of this, please refer to Figures 1-11 This application proposes a method, system, device, and storage medium for adjusting DDR reference voltage parameters, which can avoid interference from invalid sampling points caused by register range limitations and achieve accurate determination of the optimal Vref parameter combination.

[0068] Please refer to Figure 1The flowchart below shows the DDR reference voltage parameter adjustment method provided in this application. The method includes the following steps:

[0069] Step S1: Obtain the digital eye diagram of the DDR memory read direction and the corresponding eye height amplitude distribution;

[0070] DDR (Double Data Rate) is a memory data transfer technology standard. In the signal transmission link of DDR memory, the read direction refers to the direction of data transmission. The signal quality in this direction directly determines the accuracy of data reading. If there are problems such as distortion or noise interference in the read direction signal, it will cause the controller to misjudge the data, thereby affecting the stability of the system.

[0071] In view of this, the embodiments of this application obtain a digital eye diagram of the DDR memory read direction and simultaneously obtain the eye height amplitude distribution. Here, the eye height amplitude distribution refers to the distribution of eye height (i.e. voltage amplitude) corresponding to all sampling points in the digital eye diagram, which can provide a basis for subsequent elimination of invalid sampling points and determination of target optimization areas.

[0072] Specifically, a digital eye diagram is a two-dimensional graph composed of discrete sampling points, which is generated by sampling and quantizing the analog signal transmitted by the DDR memory system. The horizontal axis is the time unit UI (Unit Interval), and the vertical axis is the signal voltage amplitude.

[0073] Step S2: From the sampling points of the digitized eye diagram, exclude invalid sampling points due to register range limitations to obtain a set of valid sampling points;

[0074] In step S2, based on the digital eye diagram obtained in step S1, invalid data caused by register range limitations needs to be removed to ensure that subsequent parameter adjustments are based on real and reliable signal characteristics.

[0075] As an optional implementation method, please refer to Figure 2 This is a flowchart illustrating the process of excluding invalid sampling points in the DDR reference voltage parameter adjustment method provided in this application embodiment. The exclusion of invalid sampling points due to register range limitations includes:

[0076] Step S20: For each sampling point in the digital eye diagram, obtain the equalization control register value corresponding to its sampling time;

[0077] Understandably, the Equalization Control Register (ECR) is a key component in DDR memory systems, capable of compensating for signal distortion and improving signal integrity. However, the configuration values ​​of this type of register have a preset effective range. When the degree of signal distortion exceeds the register's adjustment capability, the register value will reach the upper or lower limit of the range, entering an output saturation state. At this time, the signal voltage reflected by the corresponding sampling point is not the actual transmitted signal level, but distorted data affected by register saturation. If such sampling points are retained, it will lead to deviations in subsequent eye height amplitude distribution analysis, thereby affecting the determination of the optimal Vref parameter.

[0078] In this embodiment, the sampling points are associated with the equalization control registers at the corresponding times, and the sampling points collected when the registers are working within the effective range are selected. Therefore, for each sampling point in the digital eye diagram, the value of the equalization control register corresponding to its sampling time needs to be obtained.

[0079] Step S21: When the value of the equalization control register exceeds the preset valid value range, the current sampling point is determined to be invalid and is discarded.

[0080] It should be noted that the preset effective value range of the equalization control register is the working range in which it can normally achieve signal equalization adjustment. If the value exceeds this range, the register will output saturation. This effective value range is determined by its hardware design specifications and is directly determined at the factory.

[0081] In an optional embodiment, the equalization control register typically includes a decision feedback equalization register for compensating for inter-symbol interference in the forward transmission link, and a read-write equalization register for adjusting the signal equalization intensity in the read-write direction. Since the read-direction Vref parameter needs to be optimized later, and the read-write equalization register is directly responsible for the read-direction signal equalization adjustment, it is sufficient to determine the effective value range of the read-write equalization register.

[0082] In this embodiment of the application, for each sampling point in the digital eye diagram, the value of the equalization control register corresponding to its sampling time is obtained. If the value of the read / write equalization register corresponding to the sampling time of the sampling point exceeds the preset effective value range, it indicates that the currently collected signal voltage cannot reflect the true read direction signal quality and is an invalid sampling point. All sampling points determined to be invalid are removed from the sampling point set of the digital eye diagram to obtain an effective sampling point set that can truly reflect the read direction signal characteristics.

[0083] Step S3: Determine the target optimization region based on the eye height amplitude distribution of the effective sampling point set;

[0084] In this embodiment of the application, based on the effective sampling point set obtained in step S2, it is necessary to accurately locate the target optimization region to provide a clear adjustment region for subsequent reading direction Vref value optimization.

[0085] As an optional implementation method, please refer to Figure 3 This is a flowchart illustrating the process of determining the target optimization region in the DDR reference voltage parameter adjustment method provided in this application embodiment. The step of determining the target optimization region based on the eye height amplitude distribution of the effective sampling point set includes:

[0086] Step S30: Divide the digital eye diagram into several grids, count the number of valid sampling points falling into each grid, and determine the sampling point density of each grid;

[0087] In an optional embodiment, the horizontal axis of the digital eye diagram is time and the vertical axis is eye height amplitude. The continuous digital eye diagram can be discretized first, dividing the digital eye diagram into several rectangular grids of uniform size to avoid density statistical deviations caused by differences in grid size.

[0088] Furthermore, the number of valid sampling points falling into each grid is counted, and the sampling point density is determined by the ratio of the number of valid sampling points to the grid area.

[0089] Specifically, a higher sampling point density indicates a more concentrated data set of the reading direction signal within that interval, and a more significant impact of the signal characteristics of that interval on the overall signal quality.

[0090] Step S31: Connect adjacent grids with sampling point density higher than the first density threshold to form one or more candidate optimization regions;

[0091] In this embodiment, a first density threshold is set according to signal transmission requirements, which can filter out grids with relatively sparse sampling points and retain only high-density grids with concentrated signals. At the same time, adjacent grids with sampling point densities higher than the first density threshold are connected to form one or more candidate optimization regions.

[0092] For example, the aforementioned adjacent grids can be understood as grids that share edges in space, ensuring that the connected region is a continuous region, rather than multiple scattered grids.

[0093] In an optional embodiment, please refer to Figure 8 This is an embodiment diagram of the grid in the DDR reference voltage parameter adjustment method provided in this application. In this embodiment, the grids with sampling point density higher than the first density threshold include grid A, grid B, grid C, grid D, and grid E.

[0094] In this context, grid A is an independent grid, grids B and C are adjacent grids, and grids D and E are adjacent grids. Therefore, grids B and C can be connected to form a candidate optimization region, grids D and E can be connected to form a candidate optimization region, and grid A can be a separate candidate optimization region.

[0095] Step S32: Calculate the average eye height amplitude of all valid sampling points in each candidate optimization region;

[0096] In an optional embodiment, after one or more candidate optimization regions are formed, it is necessary to calculate the average eye height amplitude of all valid sampling points within the candidate optimization region and quantize the signal strength of each candidate optimization region.

[0097] Since the eye height of a single sampling point may fluctuate due to instantaneous noise and accidental interference, it cannot accurately reflect the true signal quality of the area. The average eye height amplitude is the arithmetic mean of the eye height values ​​of all valid sampling points in the area, which can offset the random fluctuations caused by a single sampling point.

[0098] Step S33: The candidate optimization region with the highest average eye height amplitude that is higher than the first amplitude threshold is determined as the target optimization region.

[0099] Furthermore, a first amplitude threshold is set to exclude candidate regions with excessively low average eye height amplitude and poor basic signal quality. After the average eye height amplitude is higher than the first amplitude threshold, the candidate optimization region with the highest average eye height amplitude is selected as the target optimization region.

[0100] It is understandable that the selected target optimization region has concentrated and sufficient signal strength. After VREF optimization, it can further improve eye height amplitude, maximize signal margin, and thus significantly improve the stability and anti-interference ability of the overall reading direction signal. At the same time, the target optimization region is the core distribution range of the signal. Compared with optimizing other regions with poor foundation, its optimization effect can achieve better adjustment effect at a lower adjustment cost.

[0101] Step S4: Optimize the read direction Vref value of the target optimization region, and simultaneously adjust the write direction Vref value and the termination resistance parameter;

[0102] It is understandable that the target optimization region is the core region where the read direction signal is concentrated. Optimizing the read direction Vref value in this region can maximize the noise tolerance and signal recognition accuracy of this region.

[0103] Meanwhile, the read and write signals of DDR memory systems usually share the transmission bus. The setting of the write direction Vref value will affect the bus level reference environment. If only the read direction is optimized and the write direction is ignored, the read and write signals may interfere with each other on the bus.

[0104] Furthermore, the terminating resistor parameter directly determines the impedance matching state of the transmission link. Impedance mismatch will cause signal reflection, resulting in distortions such as overshoot and undershoot, which will affect the transmission quality of the read direction signal. Therefore, while adjusting the read direction Vref value, it is necessary to adjust the write direction Vref value and the terminating resistor parameter in a coordinated manner to avoid adjustment imbalance caused by optimizing a single parameter and ensure the stability of the overall signal transmission link of the DDR memory system.

[0105] As an optional implementation method, please refer to Figure 4 This is a flowchart illustrating the optimization of the read direction Vref value in the DDR reference voltage parameter adjustment method provided in this application embodiment. The optimization of the read direction Vref value in the target optimization region includes:

[0106] Step S40: Obtain the voltage values ​​of all valid sampling points within the target optimization area;

[0107] In this embodiment, it is necessary to obtain the voltage values ​​of all valid sampling points within the target optimization area, rather than only a portion of the sampling points, to avoid inaccurate subsequent parameter settings due to sampling bias.

[0108] Step S41: Optimize the target optimization region by determining the median or average value of the voltage values ​​as the reading direction Vref value.

[0109] Furthermore, the median or average voltage value of all valid sampling points within the target optimization area, i.e., the median or average eye height amplitude of all valid sampling points within the target optimization area, is determined as the read direction Vref value of the target optimization area for optimization. This ensures that the Vref value can accurately match the center level of the signal in the target area, thereby achieving optimal optimization of the read direction Vref.

[0110] In one optional embodiment, the average value is the arithmetic mean of all voltage values, which can reflect the overall average voltage level and is suitable for scenarios where the voltage distribution is relatively uniform and there are no extreme values; the median is the value in the middle position after sorting all voltage values, which has a stronger anti-interference ability against extreme values ​​and is suitable for scenarios where there are a small amount of fluctuation in voltage distribution. All of the above settings are feasible, and this application does not impose too many limitations on them.

[0111] As an optional implementation method, please refer to Figure 5This is a flowchart illustrating the adjustment of the write direction Vref value and termination resistance parameter in the DDR reference voltage parameter adjustment method provided in this application embodiment. The simultaneous adjustment of the write direction Vref value and termination resistance parameter includes:

[0112] Step S42: Determine the write direction Vref value based on the optimized read direction Vref value and the preset matching relationship between the write direction Vref value and the read direction Vref value;

[0113] In this embodiment, after the optimized read direction Vref value is determined, the write direction Vref value is determined by a preset matching relationship between the write direction Vref value and the read direction Vref value, so as to avoid level conflicts between read and write signals in the shared transmission link and affect the stability of data transmission.

[0114] It should be noted that the preset matching relationship is a coordination rule pre-set according to the transmission link characteristics of the DDR memory system. Its essence is to ensure that the write direction Vref and the read direction Vref are in a reasonable coordination range. It usually includes a fixed ratio relationship or a fixed difference relationship, such as the read direction Vref being 1.2 times the write direction Vref, or the difference between the write direction Vref and the read direction Vref being a fixed value. This relationship can be determined through historical test data or based on empirical values, and this application does not limit it.

[0115] Thus, this application determines the write direction Vref value based on the optimized read direction Vref and the preset matching relationship, ensuring that the optimized write direction Vref and read direction Vref are coordinated and adapted, so that the level reference of the read and write signals remains stable when transmitted in the bus, and avoids mutual interference.

[0116] Step S43: Obtain the overshoot and undershoot amplitudes of the signal waveform at the logic level transition of the digitized eye diagram;

[0117] In this embodiment, the terminal resistor parameters also need to be optimized. When the signal is transmitted in the DDR memory system transmission link, if the link impedance is mismatched, the signal will be reflected at the node of the transmission path. The reflected signal is superimposed on the original signal, which will generate overshoot and undershoot at the logic level transition: overshoot is the peak value of the signal exceeding the target high level, and undershoot is the valley value of the signal below the target low level. The magnitude of the two directly reflects the severity of the impedance mismatch.

[0118] The larger the overshoot and undershoot amplitudes, the stronger the reflection and the worse the impedance matching, resulting in more severe damage to the eye diagram.

[0119] The digital eye diagram contains complete time and voltage information of the signal waveform. By extracting the voltage peak and voltage valley at the logic level transition and calculating the difference with the target level, the overshoot and undershoot amplitudes can be obtained.

[0120] It should be noted that when optimizing the terminal resistor parameters, it is not limited to the target optimization area determined above, but is determined based on the complete digital eye diagram. If adjustments are made only based on the target optimization area, impedance mismatch issues in other intervals may be ignored, thereby causing new signal distortion. Those skilled in the art should be aware of this.

[0121] Step S44: Compare the overshoot amplitude with the undershoot amplitude. If the overshoot amplitude is greater than the undershoot amplitude, increase the terminating resistor parameter; if the overshoot amplitude is less than the undershoot amplitude, decrease the terminating resistor parameter.

[0122] The terminating resistor parameter is the negative feedback parameter of the on-chip terminating resistor.

[0123] In an optional embodiment, this application specifically involves adjusting the negative feedback parameter of the on-chip terminating resistor. Since the on-chip terminating resistor can match the characteristic impedance of the transmission link, its negative feedback parameter directly determines the actual impedance of the terminating resistor. When the negative feedback parameter increases, the equivalent impedance value of the terminating resistor increases; when the negative feedback parameter decreases, the equivalent impedance value decreases. By adjusting the negative feedback parameter of the on-chip terminating resistor, the impedance of the terminating resistor is made to be consistent with the characteristic impedance of the transmission link.

[0124] Specifically, when the overshoot amplitude is greater than the undershoot amplitude, it indicates that the equivalent impedance of the transmission link is lower than the impedance of the terminating resistor. The positive reflection generated after the signal is reflected at the terminating resistor is more severe. At this time, increasing the negative feedback parameter of the terminating resistor can improve the equivalent impedance of the terminating resistor, so that it can suppress the positive reflection in a state closer to the characteristic impedance of the link, thereby reducing the overshoot amplitude.

[0125] When the overshoot amplitude is less than the undershoot amplitude, it indicates that the equivalent impedance of the transmission link is higher than the impedance of the terminating resistor, and the reverse reflection is more severe. At this time, reducing the negative feedback parameter of the terminating resistor can reduce the equivalent impedance of the terminating resistor, thus achieving a near match with the characteristic impedance of the link, suppressing the reverse reflection, and reducing the undershoot amplitude. By adjusting the negative feedback parameter of the on-chip terminating resistor, a stable link environment can be provided for the signal transmission after Vref optimization in the read and write directions.

[0126] Step S5: Compile the adjusted and determined read direction Vref value, write direction Vref value, and termination resistor parameters into configuration code and write it into the test program of the DDR memory controller;

[0127] In an optional embodiment, the DDR memory controller, as the hardware control core, cannot directly recognize and load decimal or hexadecimal parameter values. Therefore, it is necessary to convert these optimized parameters into configuration code that conforms to the controller instruction set specification.

[0128] It is understandable that different models of DDR memory controllers have preset parameter configuration formats. As long as the adjusted and determined read direction Vref value, write direction Vref value and termination resistor parameters can be mapped into machine instructions that the controller can parse, and the parameters can be correctly identified and loaded, this application will not elaborate on this further.

[0129] It should be clarified that the "DDR memory controller test program" involved in this application is a general program that is already widely available in the prior art. This application does not impose any restrictions on the specific programming language, execution logic, storage path, etc. of the test program, which should be known to those skilled in the art.

[0130] Step S6: Run the test program and obtain the optimized digital eye diagram until the eye height of the optimized digital eye diagram meets the preset tolerance. Then, lock the current corresponding read direction Vref value, write direction Vref value and termination resistor parameter as the optimal Vref parameter combination.

[0131] In this embodiment, the optimized read direction Vref value, write direction Vref value and termination resistor parameters need to be actually loaded into the DDR memory system to ensure that the DDR memory system operates according to the optimized parameters. Then, the optimized digital eye diagram is obtained, and the actual signal quality after parameter adjustment is verified by comparing it with the preset tolerance.

[0132] If the current optimization adjustment does not meet the standard, continue to repeat the above steps S1-S5 until the eye height of the optimized digital eye diagram meets the preset tolerance, and lock the current corresponding read direction Vref value, write direction Vref value and terminal resistor parameter as the optimal Vref parameter combination.

[0133] As an optional implementation method, please refer to Figure 6 This is a flowchart illustrating the process of determining whether the eye height of a digital eye diagram meets a preset tolerance in the DDR reference voltage parameter adjustment method provided in this application embodiment. The step of determining whether the eye height of the optimized digital eye diagram meets the preset tolerance includes:

[0134] Step S60: Determine whether the eye height of the optimized digital eye diagram meets the preset tolerance;

[0135] Specifically, the preset tolerance is a minimum eye height that is pre-set based on the actual application scenario, operating frequency, and data transmission error rate requirements of the DDR memory system. If the optimized eye height meets this tolerance, it means that the noise tolerance and level recognition accuracy of the signal meet the application requirements, and the reliability of data reading can be guaranteed.

[0136] In this embodiment of the application, the actual eye height after parameter adjustment is quantitatively compared with the preset tolerance to determine whether the optimized eye height meets the preset tolerance.

[0137] In an optional embodiment, when the optimized eye height is greater than or equal to the preset tolerance, it indicates that the signal quality after the current parameter adjustment meets the standard; when the optimized eye height is less than the preset tolerance, it indicates that the current parameters still cannot meet the application requirements and further iterative optimization is needed.

[0138] Step S61: If satisfied, lock the read direction Vref value, write direction Vref value and termination resistor parameter corresponding to the current digital eye diagram as the optimal Vref parameter combination;

[0139] In this embodiment, if the optimized eye height is greater than or equal to the preset tolerance, it means that the previous parameter combination can enable the signal quality of the DDR memory system to meet the application requirements. The read direction Vref value, write direction Vref value and termination resistor parameter corresponding to the current digital eye diagram can be directly locked as the optimal Vref parameter combination.

[0140] If the conditions are not met, the Vref value for the read direction, the Vref value for the write direction, and the terminal resistance parameters corresponding to the current digital eye diagram will be iteratively optimized.

[0141] If the optimized eye height is less than the preset tolerance, it means that the current parameter adjustment has not completely solved the problems of signal distortion and impedance mismatch. Therefore, it is necessary to repeat the above steps S1-S5 to iteratively optimize the read direction Vref value, write direction Vref value and terminal resistor parameters corresponding to the current digital eye diagram until the optimized digital eye diagram's eye height meets the preset tolerance.

[0142] As an optional implementation method, please refer to Figure 7 This is a flowchart illustrating the process of determining the optimal Vref parameter combination in the DDR reference voltage parameter adjustment method provided in this application embodiment. The iterative optimization of the read-direction Vref value, write-direction Vref value, and termination resistor parameters corresponding to the current digitized eye diagram includes:

[0143] Step S62: Update the set of effective sampling points based on the optimized digital eye diagram and the corresponding eye height amplitude distribution;

[0144] In this embodiment, when the original set of valid sampling points can no longer reflect the signal characteristics of the current state after the parameters are adjusted, valid sampling points are re-selected based on the newly acquired digital eye diagram to avoid optimization deviations caused by using old data for iteration.

[0145] Step S63: Repeat the steps of determining the target optimization region, optimizing the read direction Vref value, adjusting the write direction Vref value and the terminal resistor parameter, compiling and running the test program, obtaining the optimized digital eye diagram, and determining whether the eye height meets the preset tolerance, until the eye height of the optimized digital eye diagram meets the preset tolerance.

[0146] Furthermore, repeat the steps described above: determining the target optimization region, optimizing the read direction Vref value, adjusting the write direction Vref value and the termination resistor parameters, compiling and running the test program, and correcting the deviations in the previous optimization.

[0147] For example, a more precise target optimization area can be redefined, or the Vref value of the read / write direction can be fine-tuned to ensure that each iteration of optimization is based on the previous test results, until the eye height of the optimized digital eye diagram meets the preset tolerance and the iteration stops.

[0148] Step S64: Lock the read direction Vref value, write direction Vref value and termination resistor parameter corresponding to the current digital eye diagram to the optimal Vref parameter combination.

[0149] In this embodiment, when the eye height meets the preset tolerance during iteration, it indicates that the current read direction Vref value, write direction Vref value, and termination resistor parameters can accurately adapt to the signal quality requirements of the current DDR memory system. Therefore, it is necessary to lock the read direction Vref value, write direction Vref value, and termination resistor parameters corresponding to the current digital eye diagram as the optimal Vref parameter combination.

[0150] In an optional embodiment, the optimal Vref parameter combination can be directly stored in the non-volatile register of the DDR memory controller to ensure that the parameter can still be loaded after the device restarts, and to ensure that the optimal Vref parameter combination can work stably for a long time on the current DDR memory system.

[0151] The DDR reference voltage parameter adjustment method provided in this application first obtains the digital eye diagram of the DDR memory read direction and the corresponding eye height amplitude distribution. It then converts the read direction analog signal into quantifiable discrete data. Invalid sampling points due to register range limitations are excluded from the sampling points of the digital eye diagram, eliminating distorted data caused by register saturation. This ensures that the effective sampling point set truly reflects the actual transmission characteristics of the read direction signal, eliminating interference from invalid sampling points. Based on the eye height amplitude distribution of this effective sampling point set, a target optimization region is determined, allowing the optimization of the read direction Vref value to focus on this target optimization region. Simultaneously, the write direction Vref value and termination resistor parameters are adjusted synchronously. The parameters were adjusted to balance the collaborative characteristics of the shared transmission link for DDR memory read / write signals with the impedance matching requirements of the transmission link. The adjusted parameters were then compiled into configuration code and written into the test program of the DDR memory controller. The optimized digital eye diagram was obtained iteratively by running the test program until the optimized eye height met the preset tolerance and the optimal parameter combination was locked. This ensured that the final parameter combination could stably adapt to the DDR memory hardware state, avoiding interference from invalid sampling points caused by register range limitations. This achieved accurate determination of the optimal Vref parameter combination, effectively improving the eye height margin and noise tolerance of the read direction signal, and enhancing the reliability and overall signal integrity of DDR memory data reading.

[0152] Based on the above-described DDR reference voltage parameter adjustment method, this application also provides a DDR reference voltage parameter adjustment system, please refer to... Figure 9 The present application provides a block diagram of a DDR reference voltage parameter adjustment system, which includes:

[0153] The acquisition unit is used to acquire the digital eye diagram of the DDR memory read direction and the corresponding eye height amplitude distribution;

[0154] The exclusion unit is used to exclude invalid sampling points from the sampling points of the digital eye diagram due to register range limitations, thereby obtaining a set of valid sampling points;

[0155] The determining unit is used to determine the target optimization region based on the eye height amplitude distribution of the effective sampling point set;

[0156] The adjustment unit is used to optimize the read direction Vref value of the target optimization region, and simultaneously adjust the write direction Vref value and the terminal resistance parameter.

[0157] The compilation unit is used to compile the adjusted and determined read direction Vref value, write direction Vref value, and termination resistor parameters into a test program that writes configuration code to the DDR memory controller.

[0158] The optimization unit is used to run the test program and obtain the optimized digital eye diagram until the eye height of the optimized digital eye diagram meets the preset tolerance, and lock the current corresponding read direction Vref value, write direction Vref value and termination resistor parameter as the optimal Vref parameter combination.

[0159] As a further improvement to this application, the exclusion of invalid sampling points due to register range limitations includes:

[0160] For each sampling point in the digital eye diagram, obtain the equalization control register value corresponding to its sampling time;

[0161] When the value of the equalization control register exceeds the preset valid value range, the current sampling point is determined to be invalid and is discarded.

[0162] As a further improvement to this application, the step of determining the target optimization region based on the eye height amplitude distribution of the effective sampling point set includes:

[0163] The digital eye diagram is divided into several grids, and the number of valid sampling points falling into each grid is counted to determine the sampling point density of each grid.

[0164] Connect adjacent grids with sampling point density higher than the first density threshold to form one or more candidate optimization regions;

[0165] Calculate the average eye height amplitude of all valid sampling points within each candidate optimization region;

[0166] The candidate optimization region with the highest average eye height amplitude exceeding the first amplitude threshold is determined as the target optimization region.

[0167] As a further improvement to this application, the optimization of the read direction Vref value of the target optimization region includes:

[0168] Obtain the voltage values ​​of all valid sampling points within the target optimization area;

[0169] The median or average value of the voltage is determined as the read direction Vref value of the target optimization region for optimization.

[0170] As a further improvement to this application, the synchronous adjustment of the write direction Vref value and the termination resistor parameter includes:

[0171] The write direction Vref value is determined based on the optimized read direction Vref value and the preset matching relationship between the write direction Vref value and the read direction Vref value.

[0172] Obtain the overshoot and undershoot amplitudes of the signal waveform at the logic level transition of the digital eye diagram;

[0173] Compare the overshoot amplitude with the undershoot amplitude. If the overshoot amplitude is greater than the undershoot amplitude, increase the terminating resistor parameter; if the overshoot amplitude is less than the undershoot amplitude, decrease the terminating resistor parameter.

[0174] The terminating resistor parameter is the negative feedback parameter of the on-chip terminating resistor.

[0175] As a further improvement to this application, the step of ensuring that the eye height of the optimized digital eye diagram meets a preset tolerance includes:

[0176] Determine whether the eye height of the optimized digital eye diagram meets the preset tolerance;

[0177] If satisfied, the Vref value for the read direction, the Vref value for the write direction, and the terminal resistance parameter corresponding to the current digital eye diagram will be locked as the optimal combination of Vref parameters.

[0178] If the conditions are not met, the Vref value for the read direction, the Vref value for the write direction, and the terminal resistance parameters corresponding to the current digital eye diagram will be iteratively optimized.

[0179] As a further improvement to this application, the iterative optimization of the read direction Vref value, write direction Vref value, and termination resistance parameters corresponding to the current digital eye diagram includes:

[0180] Based on the optimized digital eye diagram and the corresponding eye height amplitude distribution, the set of effective sampling points is updated.

[0181] Repeat the steps of determining the target optimization region, optimizing the read direction Vref value, adjusting the write direction Vref value and the terminal resistor parameter, compiling and running the test program, obtaining the optimized digital eye diagram, and determining whether the eye height meets the preset tolerance, until the eye height of the optimized digital eye diagram meets the preset tolerance.

[0182] The read direction Vref value, write direction Vref value, and termination resistor parameter corresponding to the current digital eye diagram are locked as the optimal Vref parameter combination.

[0183] For other details regarding the implementation techniques of each unit in the DDR reference voltage parameter adjustment system provided in the above embodiments, please refer to the description in the DDR reference voltage parameter adjustment method in the above embodiments, which will not be repeated here.

[0184] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For system-type embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0185] Please refer to Figure 10 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. The computer device 40 includes a processor 41 and a memory 42 coupled to the processor 41.

[0186] The memory 42 stores a calculation program. When the computer program is executed by the processor 41, the processor 41 performs the steps of the comprehensive testing method for the SSD system disk in the above embodiment.

[0187] The processor 41 can also be referred to as a CPU (Central Processing Unit). The processor 41 may be an integrated circuit chip with signal processing capabilities. The processor 41 can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. A general-purpose processor can be a microprocessor or any conventional processor.

[0188] Please refer to Figure 11This is a schematic diagram of the structure of the storage medium provided in the embodiments of this application. The computer-readable storage medium of this application embodiment stores a computer program 50. The computer program 50 is executed by a processor to implement the artificial intelligence-based actuarial analysis method in the above embodiments. The computer program 50 can be stored in the storage medium in the form of a software product, including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media that can store program code, such as USB flash drives, mobile hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks, or computer devices such as computers, servers, mobile phones, and tablets. The server can be an independent server or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDN), and big data and artificial intelligence platforms.

[0189] It should be noted that, in the several embodiments provided in this application, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed between each other can be through some interfaces, or indirect coupling or communication connection between devices or units, and can be electrical, mechanical, or other forms.

[0190] In specific implementation, the modules / units included in the various devices and products described in the above embodiments can be software modules / units, hardware modules / units, or a combination of both.

[0191] For example, for various devices and products applied to or integrated into chips, each module / unit can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into chip modules, each module / unit can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The unit can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, all of their modules / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0192] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0193] The above embodiments are merely exemplary implementations used to illustrate the principles of the embodiments of this application; however, the embodiments of this application are not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of this application, and these modifications and improvements are also considered to be within the protection scope of the embodiments of this application.

Claims

1. A method for adjusting DDR reference voltage parameters, characterized in that, Includes the following steps: Obtain the digital eye diagram of the DDR memory read direction and the corresponding eye height amplitude distribution; From the sampling points of the digital eye diagram, invalid sampling points due to register range limitations are excluded to obtain a set of valid sampling points; The target optimization region is determined based on the eye height amplitude distribution of the effective sampling point set; The read direction Vref value of the target optimization region is optimized, and the write direction Vref value and the termination resistance parameter are adjusted simultaneously. The adjusted and determined read direction Vref value, write direction Vref value, and termination resistor parameters are compiled into configuration code and written into a test program for the DDR memory controller. Run the test program and obtain the optimized digital eye diagram until the eye height of the optimized digital eye diagram meets the preset tolerance. Then lock the current corresponding read direction Vref value, write direction Vref value and termination resistor parameter as the optimal Vref parameter combination.

2. The DDR reference voltage parameter adjustment method as described in claim 1, characterized in that, The exclusion of sampling points that are invalid due to register range limitations includes: For each sampling point in the digital eye diagram, obtain the equalization control register value corresponding to its sampling time; When the value of the equalization control register exceeds the preset valid value range, the current sampling point is determined to be invalid and is discarded.

3. The DDR reference voltage parameter adjustment method as described in claim 1, characterized in that, The step of determining the target optimization region based on the eye height amplitude distribution of the effective sampling point set includes: The digital eye diagram is divided into several grids, and the number of valid sampling points falling into each grid is counted to determine the sampling point density of each grid. Connect adjacent grids with sampling point density higher than the first density threshold to form one or more candidate optimization regions; Calculate the average eye height amplitude of all valid sampling points within each candidate optimization region; The candidate optimization region with the highest average eye height amplitude exceeding the first amplitude threshold is determined as the target optimization region.

4. The DDR reference voltage parameter adjustment method as described in claim 1, characterized in that, The optimization of the read direction Vref value of the target optimization region includes: Obtain the voltage values ​​of all valid sampling points within the target optimization area; The median or average value of the voltage is determined as the read direction Vref value of the target optimization region for optimization.

5. The DDR reference voltage parameter adjustment method as described in claim 1, characterized in that, The synchronization involves adjusting the write direction Vref value and the termination resistance parameter, including: The write direction Vref value is determined based on the optimized read direction Vref value and the preset matching relationship between the write direction Vref value and the read direction Vref value. Obtain the overshoot and undershoot amplitudes of the signal waveform at the logic level transition of the digital eye diagram; Compare the overshoot amplitude with the undershoot amplitude. If the overshoot amplitude is greater than the undershoot amplitude, increase the terminating resistor parameter; if the overshoot amplitude is less than the undershoot amplitude, decrease the terminating resistor parameter. The terminating resistor parameter is the negative feedback parameter of the on-chip terminating resistor.

6. The DDR reference voltage parameter adjustment method as described in claim 1, characterized in that, The process of ensuring that the eye height of the optimized digital eye diagram meets a preset tolerance includes: Determine whether the eye height of the optimized digital eye diagram meets the preset tolerance; If satisfied, the Vref value for the read direction, the Vref value for the write direction, and the terminal resistance parameter corresponding to the current digital eye diagram will be locked as the optimal combination of Vref parameters. If the conditions are not met, the Vref value for the read direction, the Vref value for the write direction, and the terminal resistance parameters corresponding to the current digital eye diagram will be iteratively optimized.

7. The DDR reference voltage parameter adjustment method as described in claim 6, characterized in that, The iterative optimization of the read direction Vref value, write direction Vref value, and termination resistance parameters corresponding to the current digital eye diagram includes: Based on the optimized digital eye diagram and the corresponding eye height amplitude distribution, the set of effective sampling points is updated. Repeat the steps of determining the target optimization region, optimizing the read direction Vref value, adjusting the write direction Vref value and the terminal resistor parameter, compiling and running the test program, obtaining the optimized digital eye diagram, and determining whether the eye height meets the preset tolerance, until the eye height of the optimized digital eye diagram meets the preset tolerance. The read direction Vref value, write direction Vref value, and termination resistor parameter corresponding to the current digital eye diagram are locked as the optimal Vref parameter combination.

8. A DDR reference voltage parameter adjustment system, characterized in that, include: The acquisition unit is used to acquire the digital eye diagram of the DDR memory read direction and the corresponding eye height amplitude distribution; The exclusion unit is used to exclude invalid sampling points from the sampling points of the digital eye diagram due to register range limitations, thereby obtaining a set of valid sampling points; The determining unit is used to determine the target optimization region based on the eye height amplitude distribution of the effective sampling point set; The adjustment unit is used to optimize the read direction Vref value of the target optimization region, and simultaneously adjust the write direction Vref value and the terminal resistance parameter. The compilation unit is used to compile the adjusted and determined read direction Vref value, write direction Vref value, and termination resistor parameters into a test program that writes configuration code to the DDR memory controller. The optimization unit is used to run the test program and obtain the optimized digital eye diagram until the eye height of the optimized digital eye diagram meets the preset tolerance, and lock the current corresponding read direction Vref value, write direction Vref value and termination resistor parameter as the optimal Vref parameter combination.

9. A computer device, characterized in that, The computer device includes a processor and a memory coupled to the processor, the memory storing a computer program that, when executed by the processor, causes the processor to perform the steps of the DDR reference voltage parameter adjustment method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that is executed by a processor to implement the DDR reference voltage parameter adjustment method as described in any one of claims 1-7.

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