Debugging method of optical module for PCIe interface, PCIe optical module and PCIe device

Abstract

The present application relates to a kind of optical module debugging method for PCIe interface, PCIe optical module and PCIe equipment, belong to optical communication technical field, method includes: the optical module to be debugged is connected into first test system and starts link training process;If training fails, then execute optical module optimization process;If training succeeds, then the optical module to be debugged is connected into second test system;Equalization parameter is adjusted to the optical module to be debugged;The optical module to be debugged is connected into first test system, to send test information, if bit error rate is less than 1e-12, then debugging is successful, save optical module equalization parameter and optical module optimization result, end debugging, obtain PICe optical module, the present application realizes that PCIe data is carried out high-speed lossless transmission by optical fiber, compatible with existing PCIe equipment, applied to the optical interconnection of calculation unit in AI data center high-performance server, with high bandwidth, low latency, low power consumption, easy maintenance and the like.

Description

Technical Field

[0001] This invention belongs to the field of optical communication technology. Specifically, this invention relates to a method for debugging an optical module for a PCIe interface, a PCIe optical module, and a PCIe device. Background Technology

[0002] In recent years, AI computing power has exploded, and the interconnection speed of intelligent computing center networks has continued to evolve. For example, IB network speeds have increased from HDR and NDR to GDR, Ethernet speeds from 400G and 800G to 1.6T, and NVLink and NVSwitch speeds have increased by one level every two years. This has in turn driven the improvement of PCIe bus speeds in the computing field. In recent years, the PCIe bus transmission speed has continued to double, gradually increasing from 2.5GT / s in PCIe 1.0 to 64GT / s in PCIe 6.0, and PCIe 7.0 is moving towards 128GT / s. The intervals between speed level improvements are getting smaller and smaller, and PCIe 8.0 technology is already in the works.

[0003] In existing technologies, PCIe bus communication uses electrical signals to transmit data. PCIe electrical signals utilize traditional copper cables and PCB copper traces as the information transmission link, such as... Figure 1 As shown, due to the "skin effect" of high-speed signal transmission, the limitations of electrical interconnects become increasingly prominent as the speed increases. On the one hand, the transmission distance is drastically shortened. For example, the transmission distance of PCIe 1.0 copper cable can reach 10 meters, but it is shortened to 3-4 meters in PCIe 4.0. The transmission distance of PCIe 5.0 and 6.0 copper cables can hardly meet the interconnection needs between data center racks, and the transmission distance of PCIe 7.0 using copper cables is only a few tens of centimeters. On the other hand, high-speed electrical signals in copper cables also face serious problems such as high-frequency signal attenuation, crosstalk between channels, and electromagnetic interference. In order to ensure signal integrity, additional complex auxiliary mechanisms are required. This not only increases the design difficulty but also leads to a significant increase in power consumption, becoming the core obstacle to further upgrades of PCIe technology.

[0004] With the widespread adoption of AI large-scale model training, large-scale data analysis, and real-time rendering, the demand for computing power has exploded, making high-performance computing clusters with tens of thousands of GPUs a standard feature. In these clusters, massive amounts of data need to be exchanged at high speed between GPUs and between servers. Traditional PCIe, using electrical interconnect technology, can only meet short-distance connections within a single machine and cannot support long-distance, efficient data exchange across racks or clusters. For example, during large-scale machine learning model training, the data synchronization efficiency between multiple GPUs directly determines the training time, and the distance and bandwidth limitations of PCIe electrical interconnects can severely slow down the training process. This urgently requires an interconnect method that can balance long distances, high bandwidth, and low latency, and necessitates an optical transmission technology for PCIe scenarios to overcome the shortcomings of existing electrical transmission technologies. However, replacing electrical transmission with optical transmission is not a simple matter; a series of technical obstacles need to be overcome in PCIe scenarios to achieve this. Summary of the Invention

[0005] This invention proposes a technical solution for high-speed transmission of PCIe data via optical fiber, in order to solve the problems of short electrical transmission distance and insufficient bandwidth in the existing PCIe technology.

[0006] A first aspect of the present invention provides a method for debugging an optical module with a PCIe interface, comprising the following steps:

[0007] S1, connect the fiber optic interfaces of the first optical module to be debugged and the second optical module to be debugged with a multimode fiber of length W meters, and connect them to the PCIe optical module test link of the first test system; power on and initialize the first test system; where W is the target transmission distance of the optical module to be debugged;

[0008] S2, the first test system starts the link training process; if the training is successful, proceed to step S3; if the training fails, proceed to the PCIe optical module hardware optimization process and then return to step S1.

[0009] S3, connect the first and second optical modules to be debugged into the second test system respectively, and connect the output and input ends of the optical signal interface of the optical module to be debugged with W-meter optical fiber to form an optical fiber loop;

[0010] S4, adjust the equalization parameters of the input and output terminals of the first and second optical modules to be debugged respectively, and keep the equalization parameters of the first and second optical modules to be debugged consistent after adjustment;

[0011] S5, connect the first and second optical modules to be debugged into the first test system. The first debugging computer sends test information to the second debugging computer through the PCIe optical module test link. If the bit error rate (BER) of the signal received by the second debugging computer is greater than 1e-12, and if it is necessary to adjust the equalization parameters of the optical module input and output ends, return to step S4. If it is necessary to optimize the optical module hardware, execute the PCIe optical module hardware optimization process and return to step S1.

[0012] S6. If the bit error rate (BER) of the signal received by the second debugging computer is less than 1e-12, the debugging is successful. Save the optical module equalization parameters and optical module optimization results, end the debugging, and obtain the PICe optical module.

[0013] The first testing computer is the source server, and the second testing computer is the destination server.

[0014] Furthermore, the link training process specifically includes:

[0015] L1. Check if the PCIe optical module at the other end of the link is online. If it is not online, prompt "No test device connected" and end the debugging. If it is online, establish a communication protocol.

[0016] L2, swap training sequences TS1 and TS2 to complete bit locking and symbol locking. If used for PCIe 3.0 applications, it also includes block locking, negotiates link rate, and corrects channel polarity reversal.

[0017] L3. Continue to exchange training TS1 and TS2 sequences, complete link width and topology negotiation, and complete deskew adjustment between channels;

[0018] L4. If all link training is completed, the first test system enters full-function working state and reports "training successful"; otherwise, it reports "training failed".

[0019] L5. When a link error occurs, parameters need to be adjusted, or the rate changes, it automatically enters Recovery state and returns to L1 for retraining to restore stable communication.

[0020] Furthermore, the PCIe optical module hardware optimization process specifically includes:

[0021] Y1 optimizes high-speed electrical connectors, including reducing insertion loss, reducing reflection coefficient, and reducing crosstalk.

[0022] Y2 optimizes the PCB board material of the optical module, including: using high-frequency PCB board material with lower insertion loss, shortening the wiring length of the high-speed transmission link on the PCB board, reducing the insertion loss of the PCB board link, reducing the difference in wiring length of the high-speed transmission line in the PCB board transceiver channel, and reducing input and output crosstalk.

[0023] Y3 optimizes the number of data channels in the optical module, including: comparing the number of data channels with the number of PCIe signal channels; if they are not equal or the data channels are not in one-to-one correspondence, then optimizing the correspondence between the data channels in the optical module.

[0024] Y4 optimizes the power supply module of the optical module, including reducing power ripple;

[0025] Y5 improves the optical and electrical chips inside the optical module, including: enhancing the linearity parameters of the optical and electrical chips, increasing the bandwidth of the optical and electrical chips to meet PCIe signal requirements, improving the adjustable function of equalization parameters, and reducing signal damage during photoelectric conversion.

[0026] Furthermore, the optimization of the optical module PCB board includes: optical module PCB board electrical link insertion loss <3dB@16GHz, and PCB board high-speed transmission link wiring length <10mm;

[0027] The optimization of the optical module power supply module includes: optical module power supply ripple <30mVpp

[0028] Furthermore, the first test system specifically includes:

[0029] The first testing computer is connected to the electrical signal port of the first optical module to be tested via its PCIe electrical signal interface; the second testing computer is connected to the electrical signal port of the second optical module to be tested via its PCIe electrical signal interface.

[0030] Furthermore, the second testing system specifically includes:

[0031] The first debugging computer is connected to the electrical signal port of the optical module to be debugged through its PCIe electrical signal interface; the third debugging computer is connected to the I2C interface converter through its serial bus interface, and the I2C interface converter is electrically connected to the electrical control interface of the optical module to be debugged; the third debugging computer is the optical module debugging computer.

[0032] Furthermore, adjusting the equalization parameters at the input and output terminals of the first and second optical modules to be debugged also includes:

[0033] The optical module transmitter performs pre-emphasis parameter adjustment, optical module receiver performs CTLE adjustment, and optical module bandwidth, gain adjustment, and output signal amplitude adjustment.

[0034] Furthermore, in step S6, after the bit error rate (BER) of the second test computer is less than 1e-12, a two-way verification process is also included.

[0035] In a second aspect, the present invention provides a PCIe optical module, which is an optical module successfully debugged by the debugging method described in the first aspect of the present invention, for connecting PCIe devices and realizing optical transmission connection between PCIe devices.

[0036] In a third aspect, the present invention provides a PCIe device with a PCIe optical module interface, wherein the PCIe device integrates Pe PCIe optical modules as described in the second aspect of the present invention, each PCIe optical module providing a bidirectional transceiver optical fiber interface; the value of Pe ranges from 1 to 32.

[0037] The advantages of this invention compared to the prior art are:

[0038] The PICe optical module successfully obtained by the method described in this invention has the following advantages:

[0039] 1. The PCIe 5.0 transmission protocol requires BER < 1e-12, which is consistent with the debugging specifications of this invention. Therefore, the PICe optical module of this invention can meet the PCIe 5.0 signal transmission requirements and realize high-speed transmission of PCIe 5.0 data through optical fiber.

[0040] 2. No secondary encoding or decoding processing is performed on the existing PCIe data. The original PCIe protocol is used, resulting in low latency. This achieves compatibility with existing PCIe devices and completely "transparent transmission" of signals from existing PCIe devices.

[0041] 3. The cost of PCIe signal optical transmission is "converted" to the cost of PCIe signal electrical link transmission, or equivalent to the cost of a single electrical link transmission. That is, if the system transmission cost can still meet the requirements of PCIe electrical signal transmission after the PCIe signal has passed through an "electrical link + optical link," then successful optical transmission of the PCIe signal can be achieved. This invention minimizes the damage during photoelectric conversion and optical transmission, i.e., reduces the optical transmission cost, ultimately ensuring that the PCIe signal meets the received SNR requirements and the received bit error rate meets the PCIe protocol standard after passing through the electrical link + optical transmission link, thus realizing optical interconnection transmission of existing PCIe devices.

[0042] 4. PCIe fiber optic transmission replaces traditional PCIe electrical transmission, overcoming its shortcomings. Optical transmission features high bandwidth, low latency, low power consumption, and ease of maintenance. Furthermore, fiber optic transmission is unaffected by electromagnetic interference, enabling long-distance lossless transmission over kilometers—dozens of times faster than traditional copper interconnects—and easily adapts to PCIe 7.0 and future higher-speed transmission requirements. In addition, the maturity of supporting technologies such as photoelectric conversion and linear optical engines provides technical support for the photoelectric conversion and stable transmission of PCIe signals. Attached Figure Description

[0043] Figure 1 A schematic diagram of the electrical transmission link of a conventional PCIe device provided for an embodiment of the present invention.

[0044] Figure 2 This is a schematic flowchart of a method for debugging an optical module with a PCIe interface, provided in an embodiment of the present invention.

[0045] Figure 3 This is a schematic diagram of the first test system structure provided in an embodiment of the present invention.

[0046] Figure 4 This is a schematic diagram of the second test system structure provided in an embodiment of the present invention.

[0047] Figure 5 This is a schematic diagram of a PICe device provided in an embodiment of the present invention. Detailed Implementation

[0048] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0049] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0050] Method Implementation Examples

[0051] This invention enables high-speed transmission of PCIe data through optical fiber by optimizing and training the optical module. It is also compatible with existing PCIe devices and features high bandwidth, low latency, low power consumption, and easy maintenance.

[0052] In a first aspect, the present invention provides a method for debugging an optical module with a PCIe interface, the flowchart of which is shown below. Figure 2 As shown, it includes the following steps:

[0053] S1, connect the fiber optic interfaces of the first optical module to be debugged and the second optical module to be debugged with a multimode fiber of length W meters, and connect them into the PCIe optical module test link of the first test system; power on and initialize the first test system.

[0054] Wherein, the first test system, such as Figure 3 As shown, it includes: a first debugging computer, which is connected to the electrical signal port of the first optical module to be debugged through its PCIe electrical signal interface; and a second debugging computer, which is connected to the electrical signal port of the second optical module to be debugged through its PCIe electrical signal interface.

[0055] Where W represents the target transmission distance of the optical module to be debugged.

[0056] For example, W is a 10-meter-long OM3 multimode optical fiber.

[0057] The first testing computer is the source server, and the second testing computer is the destination server.

[0058] S2, the first test system starts the link training process; if the training is successful, proceed to step S3; if the training fails, proceed to the PCIe optical module hardware optimization process and then return to step S1.

[0059] S3, connect the first and second optical modules to be debugged into the second test system respectively, and connect the output and input ends of the optical signal interface of the optical module to be debugged with W-meter optical fiber to form an optical fiber loop.

[0060] The second test system, such as Figure 4 As shown, it includes: a first debugging computer, which is connected to the electrical signal port of the optical module to be debugged through its PCIe electrical signal interface; and a third debugging computer, which is connected to an I2C interface converter through its serial bus interface, and the I2C interface converter is electrically connected to the electrical control interface of the optical module to be debugged.

[0061] The third testing computer is an optical module testing computer.

[0062] S4, adjust the equalization parameters of the input and output terminals of the first and second optical modules to be debugged respectively, and keep the equalization parameters of the first and second optical modules to be debugged consistent after adjustment.

[0063] The adjustment of the equalization parameters at the input and output terminals of the first and second optical modules to be debugged also includes:

[0064] This includes pre-emphasis adjustment at the optical module transmitter, CTLE adjustment (equalization parameter) at the optical module receiver, and adjustment of the optical module bandwidth, gain, and output signal amplitude.

[0065] The equalization parameters at the input and output ends of an optical module refer to the technology of compensating for transmission loss by adjusting the intensity of different frequency components in the signal, thereby ensuring signal transmission quality. Adjusting the equalization parameters at the input and output ends is mainly used to solve the inter-symbol interference (ISI) problem caused by medium loss during high-speed signal transmission, in order to reduce the bit error rate.

[0066] Output equalization (Tx Eq): Before signal transmission, high-frequency components are enhanced or low-frequency components are attenuated through pre-emphasis or de-emphasis techniques to ensure signal integrity.

[0067] Input equalization (Rx Eq): At the signal receiving end, equalization measures such as CTLE (Continuous Time Linear Equalization) and FFE are used to weight the received signal and correct and compensate for signal impairment caused by the transmission link.

[0068] The equalization parameters of the optical module to be debugged will automatically retain the last adjusted value after adjustment, regardless of whether the power is off.

[0069] S5, connect the first and second optical modules to be debugged into the first test system. The first debugging computer sends test information to the second debugging computer through the PCIe optical module test link. If the bit error rate (BER) of the signal received by the second debugging computer is greater than 1e-12, and if it is necessary to adjust the equalization parameters of the optical module input and output ends, return to step S4. If it is necessary to optimize the optical module hardware, execute the PCIe optical module hardware optimization process and return to step S1.

[0070] S6. If the bit error rate (BER) of the signal received by the second debugging computer is less than 1e-12, the debugging is successful. Save the optical module equalization parameters and optical module optimization results, end the debugging, and obtain the PICe optical module.

[0071] Furthermore, in step S6, after the bit error rate (BER) of the second test computer is less than 1e-12, a two-way verification process is also included, specifically:

[0072] S6.1 Power on and initialize the first test system; start the link training process of the first test system; if the training is successful, execute step S8; if the training fails, execute the PCIe optical module hardware optimization process and return to step S1.

[0073] S6.2, the bidirectional transmission bit error rate (BER) test procedure includes:

[0074] S6.2.1, the first testing computer sends test information to the second testing computer through the PCIe optical module test link. If the bit error rate (BER) of the second testing computer is not less than 1e-12, and the optical module equalization parameters need to be adjusted, then return to step S4. If the optical module hardware needs to be improved, then execute the PCIe optical module hardware optimization process and return to step S1.

[0075] S6.2.2, the second testing computer sends test information to the first testing computer through the PCIe optical module test link. If the bit error rate (BER) of the first testing computer is not less than 1e-12, and the optical module equalization parameters need to be adjusted, then return to step S4. If the optical module hardware needs to be improved, then execute the PCIe optical module hardware optimization process and return to step S1.

[0076] S6.3 If the bit error rate (BER) of the first and second debugging computers is less than 1e-12, the debugging is successful. Save the optical module equalization parameters and optical module hardware optimization results, end the debugging, and obtain the PICe optical module.

[0077] The link training process specifically includes:

[0078] L1. Check if the PCIe optical module at the other end of the link is online. If it is not online, prompt "No test device connected" and end the debugging. If it is online, establish a communication protocol.

[0079] L2, swap training sequences TS1 and TS2 to complete bit locking and symbol locking. If used for PCIe 3.0 applications, it also includes block locking and negotiates link rate, correcting channel polarity reversal if necessary.

[0080] TS1 and TS2 are special data packets used for initialization and synchronization during PCIe link training. The TS1 sequence consists of 8 characters and is mainly used for initialization and synchronization at the start of link training, detecting the PCIe link configuration information. The TS2 sequence consists of 32 characters and is used for further training and adjusting link parameters, confirming the detection results of the TS1 sequence to improve the reliability and performance of data transmission. These two sequences are sent continuously during link training.

[0081] L3. Continue to exchange training TS1 and TS2 sequences, complete link width and topology negotiation, and complete deskew adjustment between channels.

[0082] Deskip adjustment involves sending specific training sequences at the output, detecting the arrival time difference of these sequences at the input, and dynamically adjusting the delay of each channel to ensure data synchronization before entering the data link layer. Deskip adjustment compensates for inconsistent signal transmission delays caused by differences in physical trace lengths between different channels within the same link, ensuring precise alignment of data at the input of all channels for correct data reassembly.

[0083] L4. If all link training is completed, the first test system enters full-function working state and reports "training successful"; otherwise, it reports "training failed".

[0084] When training is successful, the link is fully optimized and can reliably transmit Transaction Layer Packets (TLP) and Data Link Layer Packets (DLLP).

[0085] L5. When a link error occurs, parameters need to be adjusted, or the rate changes, it automatically enters Recovery state and returns to L1 for retraining to restore stable communication.

[0086] The link training process ensures that PCIe signals can self-update their configuration during startup, recovery, or when errors occur. This establishes a stable, reliable communication link that meets transmission performance requirements in an unknown physical link environment, effectively determining the usability of the physical link. Link training is a hardware-driven, self-negotiation process requiring no user intervention. Once training is successful, the source and destination ends of the PCIe signal connected to the optical module under test can send and receive data signals on the existing data link.

[0087] The PCIe optical module hardware optimization process specifically includes:

[0088] Y1 optimizes high-speed electrical connectors, including reducing insertion loss, reducing reflection coefficient, and reducing crosstalk.

[0089] Y2 optimizes the PCB material of the optical module, including: using PCB material with lower insertion loss, shortening the wiring length of the high-speed transmission link on the PCB, reducing the insertion loss of the PCB link, reducing the difference in wiring length of the high-speed transmission line in the PCB transceiver channel, and reducing input and output crosstalk.

[0090] Preferably, the insertion loss of the optical module PCB board is <3dB@16GHz, and the wiring length of the high-speed transmission link on the PCB board is <10mm.

[0091] Y3 optimizes the number of data channels in the optical module, including comparing the number of data channels with the number of PCIe signal channels. If they are not equal or the data channels are not in one-to-one correspondence, the correspondence between the optical module data channels is optimized.

[0092] Ideally, the number of optical transmission channels meets the PCIe link width requirements, such as PCIex4, PCIex8, or PCIex16 matching the actual number of transmission link channels.

[0093] Y4 optimizes the power supply module of the optical module, including reducing power ripple.

[0094] Ideally, the power ripple of the optical module is <30mVpp.

[0095] Y5 improves the optical and electrical chips inside the optical module, including: enhancing the linearity parameters of the optical and electrical chips, increasing the bandwidth of the optical and electrical chips to meet PCIe signal requirements, improving the adjustable function of equalization parameters, and reducing signal damage during photoelectric conversion.

[0096] After the above-mentioned optical module optimization measures, the eye height, eye width and jitter tests of PCIe 5.0 modulated optical signals can meet the requirements of the 32Gb / s optical eye diagram template, and the PCIe 5.0 transmission requirement BER<1e-12. Therefore, the optical module successfully debugged by the method described in this invention can meet the PCIe 5.0 signal transmission requirements.

[0097] In a second aspect, the present invention provides a PCIe optical module, the structural schematic diagram of which is shown below. Figure 4 The structure of the optical module to be debugged is shown in the figure, specifically including:

[0098] The transmitter (TOSA) is responsible for electro-optical conversion. The linear laser driver receives the input electrical signal from the electrical interface, amplifies and equalizes the electrical signal, drives the laser LD to generate a modulated optical signal, and outputs the modulated optical signal through the optical signal interface for transmission via optical fiber.

[0099] The receiver (ROSA) is responsible for optical-to-electrical conversion. After the optical signal enters the optical module through the optical signal interface input, it is received by the detector (PD) and converted into a weak current signal. The linear transimpedance amplifier (TIA) converts the current signal into a voltage signal and amplifies and equalizes it, providing a stable input for subsequent circuits.

[0100] The electrical control interface provides power to the module and transmits control signals (such as I2C) to the MCU, enabling management functions such as temperature compensation and power monitoring. The electrical signal interface (such as a QSFP-DD connector) is responsible for connecting to devices such as switches to complete signal input and output.

[0101] The core structure of the PCIe optical module revolves around the photoelectric conversion function. Its internal components are connected through precision circuits and optical paths to collaboratively complete the mutual conversion between electrical and optical signals. The PCIe optical module is an optical module successfully debugged using the debugging method described in the first aspect of this invention. It can be used to connect PCIe devices to achieve optical transmission connections between PCIe devices. The PCIe device is a computer device, GPU device, or interface conversion device that uses the PCIe communication protocol.

[0102] A third aspect of the present invention provides a PCIe device having a PCIe optical module interface, such as... Figure 5As shown, the PCIe device integrates PE PCIe optical modules as described in the second aspect of the present invention, and each PCIe optical module provides a bidirectional transceiver fiber interface.

[0103] Furthermore, the value of Pe ranges from 1 to 32. Preferably, Pe is 2, 4, 6, or 8.

[0104] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A method for debugging a PCIe optical module with a PCIe interface, characterized in that, Includes the following steps: S1, connect the fiber optic interfaces of the first PCIe optical module to be debugged and the second PCIe optical module to be debugged with a multimode fiber of length W meters, and connect them into the PCIe optical module test link of the first test system; The first test system is powered on and initialized; where W is the target transmission distance of the PCIe optical module to be debugged; S2, the first test system starts the PCIe optical module test link training process; if the training is successful, proceed to step S3; if the training fails, return to step S1 after the PCIe optical module hardware optimization process is executed. S3, connect the first and second PCIe optical modules to be debugged into the second test system respectively, and connect the output and input ends of the optical signal interfaces of the first or second PCIe optical modules to be debugged into the second test system with W meters of optical fiber to form an optical fiber loop. S4, adjust the equalization parameters of the input and output terminals of the first and second PCIe optical modules to be debugged respectively, and keep the equalization parameters of the first and second PCIe optical modules to be debugged consistent after adjustment; S5, connect the fiber optic interfaces of the first and second PCIe optical modules to be debugged using a multimode fiber of length W meters, and connect it to the first test system. The first debugging computer sends test information to the second debugging computer through the PCIe optical module test link. If the bit error rate (BER) of the signal received by the second debugging computer is greater than 1e... -12 If it is necessary to adjust the equalization parameters of the input and output ends of the PCIe optical module to be debugged, return to step S4; if it is necessary to optimize the hardware of the PCIe optical module to be debugged, execute the PCIe optical module hardware optimization process and return to step S1. S6, if the bit error rate (BER) of the signal received by the second adjustment computer is less than 1e -12 If the debugging is successful, save the optical module equalization parameters and optical module hardware optimization results, end the debugging, and obtain a successfully debugged PCIe optical module; The first testing computer is the source server, and the second testing computer is the destination server; The first test system specifically includes: The first testing computer is connected to the electrical signal port of the first PCIe optical module to be tested via its PCIe electrical signal interface; the second testing computer is connected to the electrical signal port of the second PCIe optical module to be tested via its PCIe electrical signal interface. The second testing system specifically includes: The first debugging computer is connected to the electrical signal port of the first or second PCIe optical module to be debugged, which is connected to the second test system, through its PCIe electrical signal interface; the third debugging computer is connected to an I2C interface converter through its serial bus, and the I2C interface converter is electrically connected to the electrical control interface of the first or second PCIe optical module to be debugged, which is connected to the second test system. The third testing computer is an optical module testing computer. The PCIe optical module hardware optimization process includes: optimizing the high-speed electrical connector, optimizing the PCIe optical module PCB board, optimizing the number of data channels in the PCIe optical module, optimizing the PCIe optical module power module, and improving the optical and electrical chips inside the PCIe optical module.

2. The PCIe optical module debugging method for PCIe interface according to claim 1, characterized in that, The link training process specifically includes: L1. Check if the PCIe optical module at the other end of the link is online. If it is not online, prompt "No test device connected" and end the debugging. If it is online, establish a communication protocol. L2, swap training sequences TS1 and TS2 to complete bit locking and symbol locking. If used for PCIe 3.0 applications, it also includes block locking, negotiates link rate, and corrects channel polarity reversal. L3. Continue to exchange training sequences TS1 and TS2, complete the negotiation of link width and topology, and complete the deskew adjustment between channels; L4. If all link training is completed, the first test system enters full-function working state and reports "training successful"; otherwise, it reports "training failed". L5. When a link error occurs, parameters need to be adjusted, or the rate changes, it automatically enters Recovery state and returns to L1 for retraining.

3. The PCIe optical module debugging method for PCIe interface according to claim 1, characterized in that, The PCIe optical module hardware optimization process specifically includes: Y1 optimizes high-speed electrical connectors, including reducing insertion loss, reducing reflection coefficient, and reducing crosstalk. Y2 optimizes the PCB material of the PCIe optical module, including: using PCB material with lower insertion loss, shortening the wiring length of the high-speed transmission link on the PCB board, reducing the insertion loss of the PCB board link, reducing the difference in wiring length of the high-speed transmission line in the PCB board transceiver channel, and reducing input and output crosstalk. Y3 optimizes the number of data channels in the PCIe optical module, including comparing the number of data channels with the number of PCIe signal channels. If they are not equal, the correspondence between the PCIe optical module data channels is optimized. Y4 optimizes the power supply module of the PCIe optical module, including reducing power ripple; Y5 improves the optical and electrical chips inside the PCIe optical module, including: improving the linearity parameters of the optical and electrical chips, increasing the bandwidth of the optical and electrical chips to meet the PCIe signal requirements, improving the adjustable function of the equalization parameters, and reducing signal damage during the photoelectric conversion process.

4. A PCIe optical module debugging method for a PCIe interface according to claim 3, characterized in that: The optimization of the PCIe optical module PCB board includes: PCIe optical module PCB board electrical link insertion loss <3dB@16GHz, and PCB board high-speed transmission link wiring length <10mm. The optimization of the PCIe optical module power supply module includes: PCIe optical module power supply ripple <30mVpp.

5. A method for debugging a PCIe optical module with a PCIe interface according to claim 1, characterized in that, The adjustment of the equalization parameters at the input and output terminals of the first and second PCIe optical modules to be debugged includes: Adjust the pre-emphasis parameters at the PCIe optical module transmitter, adjust the CTLE at the PCIe optical module receiver, and adjust the bandwidth, gain, and output signal amplitude of the PCIe optical module.

6. A method for debugging a PCIe optical module with a PCIe interface according to claim 1, characterized in that, In step S6, the bit error rate (BER) of the second testing computer is less than 1e. -12 Then, a two-way verification process is also included.

7. A PCIe optical module, characterized in that, The PCIe optical module is a PCIe optical module that has been successfully debugged by the debugging method described in any one of claims 1 to 6, and is used to connect PCIe devices to realize optical transmission connection between PCIe devices. The PCIe optical module includes a transmitter, a receiver, an electronic control interface, and an electronic signal interface, wherein: The transmitting end is responsible for electro-optical conversion, including: a linear laser driver that receives the input electrical signal from the electrical signal interface, amplifies and equalizes the electrical signal, and then drives the laser LD to generate a modulated optical signal. The modulated optical signal is then output to the optical fiber for transmission through the optical signal interface. The receiving end is responsible for optical-to-electric conversion, including: after the optical signal enters the PCIe optical module through the optical signal interface input terminal, it is received by the detector PD and converted into a weak current signal. Then, the current signal is converted into a voltage signal by the linear transimpedance amplifier TIA and amplified and equalized. The electrical control interface provides power to the module and transmits control signals to the MCU; The electrical signal interface is responsible for connecting to the switch and completing the input and output of signals.

8. A PCIe device with a PCIe optical module interface, characterized in that, The PCIe device integrates Pe as described in claim 7, and each PCIe optical module provides a bidirectional transceiver fiber optic interface; the value of Pe ranges from 1 to 32.

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