Memory device and method of manufacturing the same

Abstract

A memory device and a method of manufacturing the same are provided herein. The memory device includes: a stacked structure including a plurality of conductive layers and a plurality of interlayer insulating layers alternately stacked in a cell array region and a contact region; a plurality of cell plugs formed within the stack structure in the cell array region; a plurality of select line contacts coupled to conductive layers allocated as select lines among the plurality of conductive layers; and a separation pattern penetrating the conductive layer assigned as a drain selection line in the cell array region, the separation pattern extending from the cell array region to the contact region. The separation pattern separates the plurality of selection line contact portions from each other.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0102480, filed on August 1, 2024, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. TECHNICAL FIELD

[0003] Various embodiments of the present disclosure generally relate to a memory device and a method of manufacturing the same, and more particularly, to a memory device including a separation pattern and a method of manufacturing the same. BACKGROUND

[0004] A memory device can include a non-volatile memory device in which stored data is retained even when power is cut off. Depending on a structure in which memory cells are arranged, a non-volatile memory device can be classified into a two-dimensional (2D) structure and a three-dimensional (3D) structure. Memory cells of a non-volatile memory device having a 2D structure can be arranged in a single layer on a substrate. Memory cells of a non-volatile memory device having a 3D structure can be stacked in a vertical direction on a substrate. Because the degree of integration of a non-volatile memory device having a 3D structure is higher than that of a non-volatile memory device having a 2D structure, electronic devices using a non-volatile memory device having a 3D structure are recently increasing. SUMMARY

[0005] Embodiments of the present disclosure can provide a memory device. The memory device can include a stack structure including a plurality of conductive layers and a plurality of interlayer insulating layers alternately stacked in a cell array region and a contact region. A plurality of cell plugs can be formed in the stack structure on the cell array region. A plurality of selection line contacts are coupled to conductive layers among the plurality of conductive layers that are assigned as selection lines. A separation pattern penetrates the conductive layers assigned as drain selection lines in the cell array region, the separation pattern extending from the cell array region to the contact region. The separation pattern can separate the plurality of selection line contacts from each other.

[0006] Embodiments of the present disclosure can provide a memory device. The memory device can include a stack structure including a plurality of conductive layers and a plurality of interlayer insulating layers alternately stacked in a cell array region and a contact region, the cell array region including a first cell region, a second cell region, a third cell region, and a fourth cell region. A plurality of cell plugs is formed within the stack structure in the cell array region. A plurality of selection line contacts is coupled to conductive layers among the plurality of conductive layers that are assigned as selection lines. A first separation pattern is disposed between the first cell region and the second cell region and penetrates the conductive layers that are assigned as drain selection lines in the cell array region, the first separation pattern extending from the cell array region to the contact region. A second separation pattern is disposed between the second cell region and the third cell region and penetrates the conductive layers that are assigned as drain selection lines in the cell array region, the second separation pattern extending from the cell array region to the contact region. A third separation pattern is disposed between the third cell region and the fourth cell region and penetrates the conductive layers that are assigned as drain selection lines in the cell array region, the third separation pattern extending from the cell array region to the contact region. The first separation pattern and the third separation pattern can separate the plurality of selection line contacts from each other.

[0007] Embodiments of the present disclosure can provide a method of manufacturing a memory device. The method can include forming a stack structure by alternately stacking a plurality of conductive layers and a plurality of interlayer insulating layers on a cell array region and a contact region; forming a plurality of cell plugs in the stack structure on the cell array region; forming a pre-selection line contact coupled to a conductive layer among the plurality of conductive layers that is assigned as a selection line; forming a trench that penetrates the conductive layer that is assigned as a drain selection line, the trench extending from the cell array region to the contact region; and filling the trench with an insulating layer to form a separation pattern. The trench can penetrate the pre-selection line contact to separate the pre-selection line contact into a plurality of selection line contacts.

[0008] Embodiments of the present disclosure can provide a method of manufacturing a memory device. The method can include forming a stack structure by alternately stacking a plurality of conductive layers and a plurality of interlayer insulating layers in a cell array region and a contact region, the cell array region including a first cell region and a second cell region; forming a plurality of cell plugs within the stack structure in the cell array region; forming a first selection line contact and a second selection line contact coupled to conductive layers that are assigned as selection lines; forming a trench that penetrates the conductive layers that are assigned as drain selection lines between the first cell region and the second cell region, the trench extending from the cell array region to the contact region; and filling the trench with an insulating layer to form a separation pattern. The trench can separate the first selection line contact and the second selection line contact from each other. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1FIG. 1 is a diagram illustrating a memory device according to one embodiment of the present disclosure.

[0010] Figure 2 FIG. 2 is a diagram illustrating a structure of a memory cell array according to one embodiment of the present disclosure.

[0011] Figure 3A Figure 3B Figure 3C FIGS. 3A to 3D are views for explaining a structure of a memory device according to one embodiment of the present disclosure.

[0012] Figure 4A Figure 4B Figure 5A Figure 5B Figure 5C Figure 6 Figure 7A Figure 7B Figure 7C Figure 8A Figure 8B Figure 8C Figure 9A Figure 9B FIGS. 4A to 4D are views for explaining a method of manufacturing a memory device according to one embodiment of the present disclosure.

[0013] Figure 10A Figure 10B Figure 11A Figure 11B FIGS. 5A to 5D are views for explaining a method of manufacturing a memory device according to one embodiment of the present disclosure.

[0014] Figure 12 FIG. 6 is a block diagram illustrating a configuration of a memory system according to one embodiment of the present disclosure.

[0015] Figure 13 FIG. 7 is a block diagram illustrating a configuration of a memory system according to one embodiment of the present disclosure.

[0016] Figure 14 FIG. 8 is a block diagram illustrating a configuration of a computing system according to one embodiment of the present disclosure.

[0017] Figure 15 FIG. 9 is a block diagram illustrating a computing system according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] The specific configurations or functional descriptions in the embodiments of the present disclosure introduced in the present specification or the present application are provided as examples to describe the embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure can be practiced in various forms, and should not be interpreted as being limited to the embodiments described in the specification or the application.

[0019] ​​​​​​​​​​​​​​​​​​It will be understood that when an element or layer is referred to as being "on" or "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element or layer is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers present. Like reference numerals refer to like elements throughout.

[0020] Various embodiments of the present disclosure relate to a memory device and a method of manufacturing the memory device, which can reduce difficulty of a process and reduce defects in the process.

[0021] Figure 1 is a diagram illustrating a memory device according to one embodiment of the present disclosure.

[0022] Referring to Figure 1 The memory device 100 can include a memory cell array 110, a peripheral circuit 170, and a control circuit 180.

[0023] The memory cell array 110 can include first to i-th memory blocks BLK1 to BLKi. Each of the first to i-th memory blocks BLK1 to BLKi can include a plurality of memory cells capable of storing data. A drain select line DSL, a word line WL, a source select line SSL, and a source line SL can be connected to each of the first to i-th memory blocks BLK1 to BLKi, and a bit line BL can be commonly connected to the first to i-th memory blocks BLK1 to BLKi.

[0024] Each of the first to i-th memory blocks BLK1 to BLKi can be formed to have a three-dimensional (3D) structure. Each memory block having the 3D structure can include memory cells stacked in a direction perpendicular to a substrate.

[0025] Each memory cell can store 1-bit data or 2-bit or more data according to a program scheme. For example, a scheme for storing 1-bit data in one memory cell is referred to as a single-level cell (SLC) scheme, and a scheme for storing 2-bit data in one memory cell is referred to as a multi-level cell (MLC) scheme. A scheme for storing 3-bit data in one memory cell is referred to as a triple-level cell (TLC) scheme, and a scheme for storing 4-bit data in one memory cell is referred to as a quad-level cell (QLC) scheme. In addition, 5-bit or more data can be stored in one memory cell.

[0026] The peripheral circuit 170 can perform a program operation to store data in the memory cell array 110, a read operation to output data stored in the memory cell array 110, and an erase operation to erase data stored in the memory cell array 110. For example, the peripheral circuit 170 can include the voltage generator 120, the row decoder 130, the page buffer set 140, the column decoder 150, and the input / output circuit 160.

[0027] The voltage generator 120 can generate various operation voltages Vop required for a program operation, a read operation, or an erase operation in response to the operation code OP CD. For example, the voltage generator 120 can generate a program voltage, a turn-on voltage, a turn-off voltage, a negative voltage, a pre-charge voltage, a verify voltage, a read voltage, a pass voltage, or an erase voltage in response to the operation code OP CD. The operation voltages Vop generated by the voltage generator 120 can be applied to the drain select lines DSL, the word lines WL, the source select lines SSL, and the source lines SL of the selected memory block through the row decoder 130.

[0028] The program voltage can be a voltage applied to a selected word line among the word lines WL during a program operation, and can be used to increase a threshold voltage of a memory cell connected to the selected word line. The turn-on voltage can be applied to the drain select lines DSL or the source select lines SSL, and can be used to turn on a drain select transistor or a source select transistor. The turn-off voltage can be applied to the drain select lines DSL or the source select lines SSL, and can be used to turn off a drain select transistor or a source select transistor. For example, the turn-off voltage can be set to 0 V. The pre-charge voltage is a voltage higher than 0 V, and can be applied to a bit line during a read operation. The verify voltage can be used for a verify operation to determine whether a threshold voltage of a selected memory cell has been increased up to a target level. The verify voltage can be set to various levels depending on the target level, and can be applied to the selected word line.

[0029] The read voltage can be applied to the selected word line during a read operation on the selected memory cell. For example, the read voltage can be set to various levels according to a program scheme of the selected memory cell. The pass voltage can be a voltage applied to an unselected word line among the word lines WL during a program operation or a read operation, and can be used to turn on a memory cell connected to the unselected word line. The erase voltage can be used for an erase operation to erase memory cells included in a selected memory block, and can be applied to the source lines SL.

[0030] The row decoder 130 can transfer the operating voltage Vop to the drain select line DSL, the word line WL, the source select line SSL, and the source line SL connected to the memory block selected in response to the row address RADD. For example, the row decoder 130 can be connected to the voltage generator 120 through the global line, and can be connected to the first memory block BLK1 to the i-th memory block BLKi through the drain select line DSL, the word line WL, the source select line SSL, and the source line SL.

[0031] The page buffer group 140 can include page buffers (not shown) connected to the first memory block BLK1 to the i-th memory block BLKi, respectively. For example, the respective page buffers (not shown) can be connected to the first memory block BLK1 to the i-th memory block BLKi through the bit line BL. During a read operation, the page buffers (not shown) can sense a current or a voltage of the bit line (which varies depending on a threshold voltage of a selected memory cell) in response to a page buffer control signal PBSIG, and can store the sensed data.

[0032] The column decoder 150 can be configured to transfer data between the page buffer group 140 and the input / output circuit 160 in response to the column address CADD. For example, the column decoder 150 can be connected to the page buffer group 140 through the column line CL, and can transmit an enable signal through the column line CL. The page buffers (not shown) included in the page buffer group 140 can receive or output data through the data line DL in response to the enable signal.

[0033] The input / output circuit 160 can receive or output a command CMD, an address ADD, or data through the input / output line I / O. For example, the input / output circuit 160 can transmit the command CMD and the address ADD received from the external controller through the input / output line I / O to the control circuit 180, and can transmit data received from the external controller through the input / output line I / O to the page buffer group 140. Alternatively, the input / output circuit 160 can output data received from the page buffer group 140 through the input / output line I / O to the external controller.

[0034] The control circuit 180 can output at least one of the operation code OPCD, the row address RADD, the page buffer control signal PBSIG, or the column address CADD in response to the command CMD and the address ADD. For example, when the command CMD input to the control circuit 180 is a command corresponding to a program operation, the control circuit 180 can control the peripheral circuit 170 so that the program operation is performed on the memory block selected by the address ADD. When the command CMD input to the control circuit 180 is a command corresponding to a read operation, the control circuit 180 can control the peripheral circuit 170 so that the read operation is performed on the memory block selected by the address, and output the data read. When the command CMD input to the control circuit 180 is a command corresponding to an erase operation, the control circuit 180 can control the peripheral circuit 170 so that the erase operation is performed on the memory block selected.

[0035] Figure 2 is a diagram illustrating a structure of a memory cell array according to an embodiment of the disclosure.

[0036] Referring to Figure 2 , the memory cell array 110 can include first to i-th memory blocks BLK1 to BLKi. The first to i-th memory blocks BLK1 to BLKi can be arranged to be spaced apart from each other along a Y axis. The first to i-th memory blocks BLK1 to BLKi can extend along an X axis.

[0037] The first to i-th memory blocks BLK1 to BLKi can be commonly connected to first to j-th bit lines BL1 to BLj. For example, the first to j-th bit lines BL1 to BLj can extend along the Y axis, and can be arranged to be spaced apart from each other along the X axis. The first to j-th bit lines BL1 to BLj can be respectively connected to the first to i-th memory blocks BLK1 to BLKi on the first to i-th memory blocks BLK1 to BLKi.

[0038] Figure 3A 、 Figure 3B and Figure 3C is a view for explaining a structure of a memory device according to an embodiment of the disclosure.

[0039] Figure 3A may be a layout view of the i-th memory block BLKi. Figure 3B may be a cross-sectional view taken along a line A-A' of Figure 3A . Figure 3C may be a cross-sectional view taken along a line B-B' of Figure 3A .

[0040] Referring to Figure 3A 、 Figure 3B and Figure 3CThe i-th memory block BLKi can be distinguished from an adjacent memory block by a slit SI. For example, the slit SI can be positioned in each of +Y and -Y directions of the i-th memory block BLKi, and can extend along the X axis. The i-th memory block BLKi can be adjacent to other memory blocks with the slit SI interposed therebetween.

[0041] The i-th memory block BLKi can include a cell array region CA and a contact region CTA. For example, the contact region CTA can be positioned in the +X direction of the cell array region CA. Although the contact region CTA is shown to be positioned on only one side of the cell array region CA in Figure 3A The contact region CTA can be positioned on both sides of the cell array region CA. For example, a first contact region can be positioned in the -X direction of the cell array region CA, and a second contact region can be positioned in the +X direction of the cell array region CA.

[0042] The cell array region CA can include a plurality of cell plugs CP. The cell plugs CP can be formed in a direction perpendicular to the substrate SUB (e.g., the +Z direction). The cell plugs CP can be arranged in a plurality of rows. Each row can include cell plugs CP spaced apart from each other along the X axis. The plurality of rows can be spaced apart from each other along the Y axis. Centers of the cell plugs CP included in odd-numbered rows can be offset from centers of the cell plugs CP included in even-numbered rows. For example, cell plugs CP adjacent to each other in the +Y direction can be arranged in a zigzag manner. Although Figure 3A Although an embodiment in which the plurality of cell plugs CP are arranged in eight rows in the cell array region CA is illustrated, the present disclosure is not limited thereto. For example, the i-th memory block BLKi can include cell plugs CP consisting of eight rows or less or eight rows or more in the cell array region CA.

[0043] The cell plugs CP each can include a pillar-shaped blocking layer BOX, a charge trapping layer CT formed along an inner wall of the blocking layer BOX, a tunnel isolation layer TOX formed along an inner wall of the charge trapping layer CT, a channel layer CH formed along an inner wall of the tunnel isolation layer TOX, and a core pillar CO formed in a pillar shape in a region surrounded by the channel layer CH. The blocking layer BOX and the tunnel isolation layer TOX each can be formed of an oxide layer (e.g., a silicon oxide layer). The charge trapping layer CT can be formed of a nitride layer. The channel layer CH can be formed of a doped silicon layer. The core pillar CO can be formed of an insulating layer or a conductive layer. The blocking layer BOX, the charge trapping layer CT, the tunnel isolation layer TOX, the channel layer CH, and the core pillar CO formed in the cell plug CP can extend in the vertical direction Z.

[0044] A bit line can be positioned on the cell array region CA of the i-th memory block BLKi. For example, a first bit line BL1 to a j-th bit line BLj can be positioned on the cell array region CA. The first bit line BL1 to the j-th bit line BLj can be arranged to be spaced apart from each other along the X axis. Further, each of the first bit line BL1 to the j-th bit line BLj can extend along the Y axis. Each of the first bit line BL1 to the j-th bit line BLj can be coupled to at least one cell plug CP.

[0045] The contact region CTA can include a stepped structure. A contact portion can be formed in the contact region CTA. For example, a plurality of select line contact portions SCT1 to SCT8 and a plurality of word line contact portions WCT can be formed in the contact region CTA. Each of the word line contact portions WCT can be coupled to each of the word lines WL of the i-th memory block BLKi. Further, each of the select line contact portions SCT1 to SCT8 can be coupled to each of the drain select lines DSL of the i-th memory block BLKi. Figure 1 Figure 1

[0046] The i-th memory block BLKi can include at least one separation pattern. In one embodiment of the disclosure, a structure including first to third separation patterns SP1, SP2, and SP3 will be described as one example. The first to third separation patterns SP1, SP2, and SP3 can be spaced apart from each other in the Y axis direction. Each of the first to third separation patterns SP1, SP2, and SP3 can extend along the X axis. For example, each of the first to third separation patterns SP1, SP2, and SP3 can extend in the -X direction (or the +X direction). A cross section of each of the first to third separation patterns SP1, SP2, and SP3 can have a long axis in the +X direction and a short axis in the +Y direction. The first to third separation patterns SP1, SP2, and SP3 can be arranged to be parallel to each other.

[0047] The cell array region CA can be divided into a plurality of cell regions by the first to third separation patterns SP1, SP2, and SP3. For example, the first separation pattern SP1 can be positioned between a first cell region CA1 and a second cell region CA2. The second cell region CA2 can be positioned in the -Y direction of the first cell region CA1. The second separation pattern SP2 can be positioned between the second cell region CA2 and a third cell region CA3. The third cell region CA3 can be positioned in the -Y direction of the second cell region CA2. The third separation pattern SP3 can be positioned between the third cell region CA3 and a fourth cell region CA4. The fourth cell region CA4 can be positioned in the -Y direction of the third cell region CA3. As described above, the first to fourth cell regions CA1, CA2, CA3, and CA4 can be arranged to be spaced apart from each other in the Y axis direction. Figure 3A ​​As illustrated in the middle, when three separate patterns SP1, SP2, and SP3 are included in the i-th memory block BLKi, the cell array region CA can be divided into four cell regions (e.g., CA1, CA2, CA3, and CA4). When the i-th memory block BLKi includes N separate patterns, the cell array region CA can be divided into N+1 cell regions.

[0048] The i-th memory block BLKi can include conductive layers CL stacked along the Z-axis, and interlayer insulating layers ILD formed between the conductive layers CL. An upper insulating layer UIL can be formed on the stacked structure including the conductive layers CL and the interlayer insulating layers ILD. The conductive layers CL can include at least one drain select line DSL, a plurality of word lines WL, and at least one source select line SSL. It can be understood that, in Figure 3B and Figure 3C Only a portion of the stacked conductive layers CL is depicted in the middle and the right. In one embodiment of the disclosure, a structure in which two drain select lines DSL are stacked will be described as one example.

[0049] A cell plug CP penetrating the conductive layers CL and the interlayer insulating layers ILD in the Z-axis direction can be formed in the cell array region CA. A cell contact CCT can be formed on the cell plug CP. The cell plug CP can be coupled to the bit lines BL1 to BLj through the cell contact CCT.

[0050] A first separate pattern SP1 can be formed between a first cell region CA1 and a second cell region CA2. The first separate pattern SP1 can be formed to a depth of separating the drain select lines DSL. For example, the drain select line DSL corresponding to the first cell region CA1 and the drain select line DSL corresponding to the second cell region CA2 can be separated from each other by the first separate pattern SP1. In addition, the first separate pattern SP1 can extend to the contact region CTA, and can separate the first select line contact SCT1 and the second select line contact SCT2 formed on the contact region CTA from each other. The first select line contact SCT1 and the second select line contact SCT2 can be positioned adjacent to each other, and each of the first select line contact SCT1 and the second select line contact SCT2 can be coupled to the drain select line DSL located at the uppermost position among the stacked conductive layers CL. In some embodiments, the drain select line DSL located at the uppermost position is the conductive layer CL directly coupled to the select line contact without any intermediate conductive layer(s) between the drain select line DSL located at the uppermost position and the select line contact. For example, as illustrated in the middle, the drain select line DSL located at the uppermost position is the conductive layer CL directly coupled to the select line contact without any intermediate conductive layer(s) between the drain select line DSL located at the uppermost position and the select line contact. Figure 3CAs shown in FIG. 1, the drain select line DSL located in the uppermost position is a conductive layer CL directly coupled to the first select line contact SCT1 and the second select line contact SCT2, and in this example, by way of reference, is the conductive layer CL located furthest from the substrate SUB. For example, as shown in FIG. 1, the first select line contact SCT1 and the second select line contact SCT2 can extend to the same depth. Figure 3C As shown in FIG. 2, the drain select line DSL located in the uppermost position is a conductive layer CL directly coupled to the seventh select line contact SCT7 and the eighth select line contact SCT8, and in this example, by way of reference, is the conductive layer CL located second furthest from the substrate SUB. The first select line contact SCT1 and the second select line contact SCT2 can extend to the same depth.

[0051] Further, the first separation pattern SP1 can separate the fifth select line contact SCT5 and the sixth select line contact SCT6 formed on the contact area CTA from each other. The fifth select line contact SCT5 and the sixth select line contact SCT6 can be located adjacent to each other, and each of the fifth select line contact SCT5 and the sixth select line contact SCT6 can be coupled to a drain select line DSL located below and adjacent to a drain select line DSL disposed in the uppermost portion among the stacked conductive layers CL. The fifth select line contact SCT5 and the sixth select line contact SCT6 can extend to the same depth.

[0052] As described above, the first separation pattern SP1 can separate the drain select line DSL corresponding to the first cell area CA1 and the drain select line DSL corresponding to the second cell area CA2 from each other, and can separate the first select line contact SCT1 and the fifth select line contact SCT5 coupled to the drain select line DSL corresponding to the first cell area CA1 and the second select line contact SCT2 and the sixth select line contact SCT6 coupled to the drain select line DSL corresponding to the second cell area CA2.

[0053] The second separation pattern SP2 can be formed between the second cell area CA2 and the third cell area CA3. The second separation pattern SP2 can be formed to a depth that separates the drain select lines DSL. For example, the drain select line DSL corresponding to the second cell area CA2 and the drain select line DSL corresponding to the third cell area CA3 can be separated from each other by the second separation pattern SP2. Further, the second separation pattern SP2 can extend to the contact area CTA.

[0054] A third separation pattern SP3 can be formed between the third cell region CA3 and the fourth cell region CA4. The third separation pattern SP3 can be formed to a depth of the drain select lines DSL. For example, the drain select lines DSL corresponding to the third cell region CA3 and the drain select lines DSL corresponding to the fourth cell region CA4 can be separated from each other by the third separation pattern SP3. Also, the third separation pattern SP3 can extend to the contact region CTA and can separate the third select line contact SCT3 and the fourth select line contact SCT4 formed on the contact region CTA from each other. The third select line contact SCT3 and the fourth select line contact SCT4 can be positioned adjacent to each other, and each of the third select line contact SCT3 and the fourth select line contact SCT4 can be coupled to the drain select lines DSL disposed at the uppermost portion among the stacked conductive layers CL. The third select line contact SCT3 and the fourth select line contact SCT4 can extend to the same depth.

[0055] Also, the third separation pattern SP3 can separate the seventh select line contact SCT7 and the eighth select line contact SCT8 formed on the contact region CTA from each other. The seventh select line contact SCT7 and the eighth select line contact SCT8 can be positioned adjacent to each other, and each of the seventh select line contact SCT7 and the eighth select line contact SCT8 can be coupled to the drain select lines DSL positioned below and adjacent to the drain select lines DSL disposed at the uppermost portion among the stacked conductive layers CL. The seventh select line contact SCT7 and the eighth select line contact SCT8 can extend to the same depth.

[0056] As described above, the third separation pattern SP3 can separate the drain select lines DSL corresponding to the third cell region CA3 and the drain select lines DSL corresponding to the fourth cell region CA4 from each other, and can separate the third select line contact SCT3 and the seventh select line contact SCT7 coupled to the drain select lines DSL corresponding to the third cell region CA3 and the fourth select line contact SCT4 and the eighth select line contact SCT8 coupled to the drain select lines DSL corresponding to the fourth cell region CA4.

[0057] The contact region CTA can include a stepped structure formed on a side of the cell array region CA. For example, the contact region CTA can include a stepped structure extending in the +X direction from the cell array region CA. For example, the contact region CTA can include a pad through which the drain select lines DSL, the word lines WL, and the source select lines SSL are exposed.

[0058] The select line contacts SCT1 to SCT8 can be formed in the contact area CTA. The select line contacts SCT1, SCT2, SCT3, and SCT4 can be coupled to the drain select lines DSL positioned in the uppermost portion among the plurality of conductive layers CL, and the select line contacts SCT5, SCT6, SCT7, and SCT8 can be coupled to the drain select lines DSL positioned below the drain select lines DSL in the uppermost portion to be adjacent thereto. The word line contacts WCT can be coupled to the word lines WL, respectively. The drain select lines DSL can receive an operating voltage Vop through the select line contacts SCT1 to SCT8. Also, the word lines WL can receive the operating voltage Vop through the word line contacts WCT.

[0059] Figure 4A 、 Figure 4B 、 Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 6 、 Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 9A and Figure 9B are views for explaining a method of manufacturing a memory device according to one embodiment of the disclosure.

[0060] Referring to Figure 4A and Figure 4B , a source line layer 101 is formed on a cell array area CA and a contact area CTA of the memory device. The source line layer 101 can be a doped semiconductor layer, for example, a semiconductor layer doped with n-type impurities. In one embodiment, the source line layer 101 can be formed by implanting impurities into a surface of a substrate SUB illustrated in Figure 3B and Figure 3C , or by depositing at least one doped silicon layer on the substrate SUB.

[0061] Subsequently, a stack structure 103 and 105 is formed by alternately stacking first material layers 103 and second material layers 105 in the cell array area CA and the contact area CTA. The second material layers 105 can be layers for forming conductive layers such as word lines, select lines, or pads, and the first material layers 103 can be interlayer insulating layers for insulating the stacked conductive layers from each other.

[0062] The first material layers 103 are formed of a material having a high etching selectivity with respect to the second material layers 105. For example, the first material layers 103 can include an insulating material such as an oxide, and the second material layers 105 can include a sacrificial material such as a nitride.

[0063] Subsequently, a stepped structure can be formed by partially etching the stack structures 103 and 105 in the contact area CTA. For example, a portion of the first material layer 103 and the second material layer 105 can be etched such that each of the first material layer 103 and the second material layer 105 is exposed.

[0064] Referring to Figure 5A , Figure 5B and Figure 5C , a first upper insulating layer 107 is formed on the entire structure of the cell array area CA and the contact area CTA. The steps of the stepped structure of the contact area CTA can be eliminated by the first upper insulating layer 107. For example, the first upper insulating layer 107 can be formed of an oxide layer.

[0065] Subsequently, a mask pattern 109 is formed on the first upper insulating layer 107. The mask pattern 109 is formed such that a portion in which each of the cell plugs is to be formed in the cell array area CA has an opening OP.

[0066] Referring to Figure 6 , a hole H is formed through the stack structures 103 and 105 by etching the stack structures 103 and 105 using the mask pattern 109 (see Figure 5B ) as a barrier. At this time, the contact area CTA (see Figure 5A and Figure 5C ) is prevented from being etched by the mask pattern, such that the hole is not formed.

[0067] Thereafter, the mask pattern is removed.

[0068] Subsequently, a cell plug CP including a channel layer 112 and a memory layer surrounding the channel layer 112 is formed in the hole H. For example, the memory layer 111 is formed on the sidewall of each hole H. The memory layer 111 can include at least one of a blocking layer, a charge trapping layer, and a tunnel isolation layer, and the charge trapping layer can include a floating gate such as silicon, a charge trapping material such as nitride, a phase change material, a nanodot, etc. Thereafter, each hole H is completely filled with the channel layer 112 up to a central area of the hole to form the cell plug CP. In one embodiment, the channel layer 112 can be formed to have a hollow structure of the open central area of each hole H, and a core pillar can be formed in the open central area.

[0069] Referring to Figure 7A , Figure 7B and Figure 7CIn the cell array region CA, the stack structures 103 and 105 are etched at both ends of the Y axis of the region in which the cell plugs CP are arranged, thereby forming trenches T extending in the X axis direction. The sidewalls of the first material layers 103 and the second material layers 105 (see Figure 6 ) of the stack structures 103 and 105 can be exposed by the trenches T. The trenches T can extend from the cell array region CA to the contact region CTA in a linear shape.

[0070] Subsequently, the second material layers exposed by the trenches T are removed, and conductive layers 115 are formed in spaces in which the second material layers are removed. Among the conductive layers 115, at least one conductive layer 115 positioned at the lowermost portion can be a source select line, at least one conductive layer 115 positioned at the uppermost portion can be a drain select line, and the remaining conductive layers 115 can be word lines. The conductive layers 115 formed on the contact region CTA extend in the X axis direction to have different lengths, and the conductive layers disposed at the lower portion extend longer in the X axis direction. Accordingly, each of the conductive layers 115 formed on the contact region CTA can include a region that does not overlap with the conductive layers disposed at the upper portion, and the region that does not overlap with the conductive layers disposed at the upper portion can be defined as a pad.

[0071] Subsequently, the trenches T are filled with an insulating layer to form slits 113. The slits 113 can be formed of an oxide layer.

[0072] Referring to Figure 8A , Figure 8B and Figure 8C , a second upper insulating layer 117 is formed over the entire structure of the cell array region CA and the contact region CTA. The second upper insulating layer 117 can be formed of an oxide layer.

[0073] Subsequently, a portion of the pads of the conductive layers 115 can be exposed by an etching process of the second upper insulating layer 117 and the first upper insulating layer 107 formed on the contact region CTA. As the etching process, an anisotropic dry etching process can be performed. In addition, pre-select line contacts 119 and word line contacts 121 that come into contact with the pads of the exposed conductive layers 115 can be formed. For example, each pre-select line contact 119 can be circular, elliptical, or rectangular in cross-section in the horizontal direction.

[0074] In one embodiment, as illustrated in Figure 3A , when the cell array region CA is divided into four cell regions CA1, CA2, CA3, and CA4, one pre-select line contact 119 can be formed for two adjacent cell regions.

[0075] Referring to Figure 9A and Figure 9BThe etching process is performed to form trench TCs that penetrate the second upper insulating layer 117, the first upper insulating layer 107, at least two first material layers 103 among the plurality of first material layers 103 disposed at the upper portion, and at least one conductive layer 115 among the plurality of conductive layers 115 disposed at the upper portion. As the etching process for forming the trench TCs, an anisotropic dry etching process can be performed.

[0076] The trench TCs can respectively correspond to the first to third separation patterns SP1 to SP3 illustrated in FIGS. 1A to 1C. Figure 3A , Figure 3B and Figure 3C . For example, any one of the trench TCs can extend in a linear shape along the X-axis between the first cell region CA1 (see Figure 3A ) and the second cell region CA2 (see Figure 3A ). Also, any one of the trench TCs can extend in a linear shape along the X-axis between the second cell region CA2 (see Figure 3A ) and the third cell region CA3 (see Figure 3A ). Also, any one of the trench TCs can extend in a linear shape along the X-axis between the third cell region CA3 (see Figure 3A ) and the fourth cell region CA4 (see Figure 3A ). The trench TCs can be formed to penetrate the upper conductive layer 115 serving as a drain select line among the plurality of conductive layers 115. Accordingly, the conductive layers 115 disposed at the upper portion and serving as drain select lines corresponding to the first cell region CA1 (see Figure 3A ), the second cell region CA2 (see Figure 3A ), the third cell region CA3 (see Figure 3A ), and the fourth cell region CA4 (see Figure 3A ) are separated from each other by the trench TCs.

[0077] In one embodiment, although it is illustrated that the trench TCs are formed between the cell plugs CP, some of the trench TCs can be formed to overlap some of the cell plugs CP. In this case, the cell plugs CP overlapping some of the trench TCs can be referred to as dummy cell plugs.

[0078] The trench TCs can extend to the contact region CTA, and some of the trench TCs can penetrate the pre-select line contact 119 (see Figure 8A ), so that each of the pre-select line contacts 119 (see Figure 8A ) can be separated into two select line contacts 119A and 119B by some of the trench TCs. Accordingly, two pre-select line contacts 119 (seeFigure 8A ) can be separated into four select line contacts 119A and 119B respectively corresponding to the first, second, third, and fourth cell regions. The horizontal cross-section of each of the select line contacts 119A and 119B can be semi-circular or rectangular. In some embodiments, the conductive layer 115 at the uppermost position is directly coupled to a select line contact (i.e., 119A or 119B) or a pre-select line contact 119 without any intermediate conductive layer(s) between the conductive layer 115 at the uppermost position and the select line contact or the pre-select line contact. For some embodiments, the conductive layer 115 at the uppermost position can be assigned as a drain select line. For example, as shown in Figure 9B , the conductive layer 115 at the uppermost position is the conductive layer 115 directly coupled to the select line contact 119A and the select line contact 119B, and in this example, by way of reference, is the conductive layer 115 positioned furthest from the source line layer 101. For example, as shown in Figure 9B , the conductive layer 115 at the uppermost position is the conductive layer 115 directly coupled to the select line contact 119A and the select line contact 119B, and in this example, by way of reference, is the conductive layer 115 positioned second furthest from the source line layer 101.

[0079] As described above, according to one embodiment of the disclosure, one pre-select line contact is formed for two cell regions to form select line contacts corresponding to multiple cell regions. In a trench formation process for separating drain select lines, the pre-select line contact is separated into two by a trench, and a process is performed so that select line contacts corresponding to each cell region are formed. Thus, in one embodiment, a process of forming select line contacts can be more easily performed, and process defects in which select line contacts corresponding to adjacent cell regions contact each other can be reduced.

[0080] Subsequently, the inside of each trench TC is filled with an insulating layer to form a separation pattern 123. The separation pattern 123 can be formed of an oxide layer.

[0081] Figure 10A 、 Figure 10B 、 Figure 11A and Figure 11B are views for explaining a method of manufacturing a memory device according to one embodiment of the disclosure.

[0082] The method of manufacturing a memory device according to one embodiment of the disclosure can perform the same as the method of manufacturing a memory device described with reference to Figure 4A 、 Figure 4B 、 Figure 5A 、 Figure 5B 、 Figure 5C ,Figure 6 , Figure 7A , Figure 7B and Figure 7C the same process steps as described above, and then process steps corresponding to the process steps of Figure 10A , Figure 10B , Figure 11A and Figure 11B are performed.

[0083] With reference to Figure 10A and Figure 10B , a second upper insulating layer 117 is formed over the entire structure of the cell array region CA and the contact region CTA. The second upper insulating layer 117 can be formed of an oxide layer.

[0084] Subsequently, a portion of the pads of the conductive layer 115 can be exposed by an etching process of the second upper insulating layer 117 and the first upper insulating layer 107 formed on the contact region CTA. As the etching process, an anisotropic dry etching process can be performed.

[0085] For example, when the cell array region CA is divided into four cell regions CA1, CA2, CA3 and CA4 as illustrated in Figure 3A , four contact holes CTH1, CTH2, CTH3 and CTH4 corresponding to the four cell regions CA1, CA2, CA3 and CA4, respectively, can be formed, and the four contact holes CTH1, CTH2, CTH3 and CTH4 can expose the pads of the conductive layers 115 among the conductive layers 115 disposed in the uppermost portion and serving as drain select lines. In addition, four contact holes CTH5, CTH6, CTH7 and CTH8 corresponding to the four cell regions CA1, CA2, CA3 and CA4, respectively, can be formed, and the four contact holes CTH5, CTH6, CTH7 and CTH8 can expose the pads of the conductive layers 115 among the conductive layers 115 serving as drain select lines, which are disposed below the conductive layers 115 disposed in the uppermost portion to be adjacent thereto.

[0086] In the process of forming the above-described contact holes CTH1, CTH2, CTH3, CTH4, CTH5, CTH6, CTH7 and CTH8, adjacent contact holes CTH1 and CTH2 or CTH3 and CTH4 or CTH5 and CTH6 or CTH7 and CTH8 can be formed so that the distance between the contact holes becomes shorter during the etching process, and thus the contact holes contact each other as illustrated in the drawing.

[0087] Subsequently, the interiors of the contact holes CTH1, CTH2, CTH3, CTH4, CTH5, CTH6, CTH7, and CTH8 can be filled with a conductive material to form the selection line contacts 119A and 119B. At this time, when the distance between the contact holes is so close that the contact holes contact each other, the adjacent selection line contacts 119A and 119B can be physically coupled to each other.

[0088] During the process of forming the above-described contact holes CTH1, CTH2, CTH3, CTH4, CTH5, CTH6, CTH7, and CTH8 and the selection line contacts 119A and 119B, the process of forming the contact hole through which the pad of the remaining conductive layer 115 is exposed and the process of forming the word line contact 121 in the contact hole can be performed together.

[0089] Referring to Figure 11A and Figure 11B , an etching process is performed to form the trench TC that penetrates the second upper insulating layer 117, the first upper insulating layer 107, at least two first material layers 103 disposed at the upper portion among the plurality of first material layers 103, and at least one conductive layer 115 disposed at the upper portion among the plurality of conductive layers 115. As the etching process for forming the trench TC, an anisotropic dry etching process can be performed.

[0090] The trench TC can correspond to the first to third separation patterns SP1 to SP3 illustrated in Figure 3A , Figure 3B and Figure 3C , respectively. For example, any one of the trenches TC can extend along the X-axis between the first cell region CA1 (see Figure 3A ) and the second cell region CA2 (see Figure 3A ). Also, any one of the trenches TC can extend along the X-axis between the second cell region CA2 (see Figure 3A ) and the third cell region CA3 (see Figure 3A ). In addition, any one of the trenches TC can extend along the X-axis between the third cell region CA3 (see Figure 3A ) and the fourth cell region CA4 (see Figure 3A ). The trench TC can be formed to penetrate the upper conductive layer 115 serving as a drain selection line among the plurality of conductive layers 115. Accordingly, the upper portion disposed and serving as the first cell region CA1 (see Figure 3A ), the second cell region CA2 (see Figure 3A ), the third cell region CA3 (see Figure 3A ), and the fourth cell region CA4 (see Figure 3AThe conductive layers 115 of the drain select lines are separated from each other by the trenches TC.

[0091] In one embodiment, although it is shown that the trenches TC are formed between the cell plugs CP, some of the trenches TC can be formed to overlap some of the cell plugs CP. In this case, the cell plugs CP overlapping some of the trenches TC can be referred to as dummy cell plugs.

[0092] The trenches TC can extend to the contact region CTA, and some of the trenches TC can penetrate between adjacent select line contacts 119A and 119B, such that the adjacent select line contacts 119A and 119B can be physically separated from each other by the trenches TC. Thus, the four select line contacts 119A and 119B in contact with the conductive layers 115 of the drain select lines disposed in the same layer can correspond to the first, second, third, and fourth cell regions, respectively, and can be physically and electrically separated from each other.

[0093] Subsequently, the inside of each of the trenches TC is filled with an insulating layer to form a separation pattern 123. The separation pattern 123 can be formed of an oxide layer.

[0094] Figure 12 is a block diagram illustrating a configuration of a memory system according to one embodiment of the disclosure.

[0095] Referring to Figure 12 , a memory system 1000 according to an embodiment of the disclosure includes a memory device 1200 and a controller 1100.

[0096] The memory device 1200 can be used to store data information having various data formats such as text, graphics, and software code. The memory device 1200 can be a memory device described with reference to Figure 1 , Figure 2 , Figure 3A , Figure 3B and Figure 3C described with reference to Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 5C , Figure 6 , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 8C , Figure 9A and Figure 9B or Figure 10A , Figure 10B , Figure 11A and Figure 11BThe memory device 1200 is manufactured by the described manufacturing method. The structure of the memory device 1200 and its manufacturing method are the same as those described above, and thus a detailed description thereof will be omitted.

[0097] The controller 1100 can be connected to a host and the memory device 1200, and can access the memory device 1200 in response to a request from the host. For example, the controller 1100 can control reading, writing, erasing, and background operations of the memory device 1200.

[0098] The controller 1100 includes a random access memory (RAM) 1110, a central processing unit (CPU) 1120, a host interface 1130, an error correction code (ECC) circuit 1140, a memory interface 1150, and the like.

[0099] Here, the RAM 1110 can be used as a working memory of the CPU 1120, a cache memory between the memory device 1200 and the host, a buffer memory between the memory device 1200 and the host, and the like. For reference, the RAM 1110 can be replaced with a static random access memory (SRAM), a read only memory (ROM), or the like.

[0100] The CPU 1120 can control the overall operation of the controller 1100. For example, the CPU 1120 can operate firmware such as a flash translation layer (FTL) stored in the RAM 1110.

[0101] The host interface 1130 can perform interface connection with a host. In one embodiment, the controller 1100 can communicate with the host through at least one of various interface protocols such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and a proprietary protocol.

[0102] The ECC circuit 1140 can detect and correct errors in data read from the memory device 1200 using an error correction code (ECC).

[0103] The memory interface 1150 can perform interface connection with the memory device 1200. For example, the memory interface 1150 includes a NAND interface or a NOR interface.

[0104] For reference, the controller 1100 can further include a buffer memory (not illustrated) for temporarily storing data. Here, the buffer memory can be used to store data transferred to an external device through the host interface 1130 or data transferred from the memory device 1200 through the memory interface 1150. The controller 1100 can further include a ROM storing code data for connection with the host interface.

[0105] Because the memory system 1000 according to one embodiment of the disclosure includes the memory device 1200 having improved integration and enhanced characteristics, integration and characteristics of the memory system 1000 can also be improved.

[0106] Figure 13 is a block diagram illustrating a configuration of a memory system according to one embodiment of the disclosure. Hereinafter, a repeated description of the configuration identical to that described above will be omitted.

[0107] Referring to Figure 13 , the memory system 1000’ according to one embodiment of the disclosure can include a memory device 1200’ and a controller 1100. Also, the controller 1100 can include a RAM 1110, a CPU 1120, a host interface 1130, an ECC circuit 1140, a memory interface 1150, etc.

[0108] The memory device 1200’ can be a volatile memory, and the memory device 1200’ can be a memory device described with reference to Figure 1 , Figure 2 , Figure 3A , Figure 3B and Figure 3C , and can be manufactured according to the manufacturing method described with reference to Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 5C , Figure 6 , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 8C , Figure 9A and Figure 9B or Figure 10A , Figure 10B , Figure 11A and Figure 11B . The structure of the memory device 1200’ and the manufacturing method thereof are identical to those described above, and thus a detailed description thereof will be omitted.

[0109] Further, the memory device 1200' can be a multi-chip package including a plurality of memory chips. The plurality of memory chips can be divided into a plurality of groups. The plurality of groups can communicate with the controller 1100 through the first channel CH1 to the kth channel CHk. Also, the memory chips of each group can communicate with the controller 1100 through a common channel. For reference, the memory system 1000' can be modified such that each single memory chip is connected to a corresponding single channel.

[0110] As described above, because the memory system 1000' according to one embodiment of the disclosure includes the memory device 1200' having improved integration and enhanced characteristics, the integration and characteristics of the memory system 1000' can also be improved. In particular, in one embodiment, the memory device 1200' can be formed of a multi-chip package, whereby the data storage capacity of the memory system 1000' can be increased, and its operating speed can be enhanced.

[0111] Figure 14 is a block diagram illustrating a configuration of a computing system according to one embodiment of the disclosure. Hereinafter, a repetitive description of the configuration identical to that described above will be omitted.

[0112] Referring to Figure 14 , the computing system 2000 according to one embodiment of the disclosure can include a memory device 2100, a CPU 2200, a RAM 2300, a user interface 2400, a power supply 2500, a system bus 2600, etc.

[0113] The memory device 2100 stores data provided through the user interface 2400, data processed by the CPU 2200, etc. Further, the memory device 2100 can be electrically connected to the CPU 2200, the RAM 2300, the user interface 2400, the power supply 2500, etc. through the system bus 2600. For example, the memory device 2100 can be connected to the system bus 2600 through a controller (not illustrated), or alternatively, the memory device 2100 can be directly connected to the system bus 2600. In the case where the memory device 2100 is directly connected to the system bus 2600, the functions of the controller can be performed by the CPU 2200, the RAM 2300, etc.

[0114] Here, the memory device 2100 can be a volatile memory, and the memory device 2100 can be the memory device described with reference to Figure 1 , Figure 2 , Figure 3A , Figure 3B and Figure 3C described with reference to Figure 4A , Figure 4B , Figure 5A ,Figure 5B 、 Figure 5C 、 Figure 6 、 Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 9A and Figure 9B or Figure 10A 、 Figure 10B 、 Figure 11A and Figure 11B The memory device 2100 can be manufactured by the manufacturing method described above. The structure of the memory device 2100 and the manufacturing method thereof are the same as those described above, and thus a detailed description thereof will be omitted.

[0115] Further, as described above with reference to Figure 13 , the memory device 2100 can be a multi-chip package including a plurality of memory chips.

[0116] The computing system 2000 having the above-described configuration can be a computer, an ultra-mobile personal computer (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smartphone, an e-book, a portable multimedia player (PMP), a game console, a navigation device, a black box, a digital camera, a 3-dimensional (3D) television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting / receiving information in a wireless environment, one of various devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a remote information processing network, an RFID device, etc.

[0117] As described above, because the computing system 2000 according to one embodiment of the disclosure includes the memory device 2100 having improved integration and enhanced characteristics, the characteristics of the computing system 2000 can also be improved.

[0118] Figure 15 is a block diagram illustrating a computing system according to one embodiment of the disclosure.

[0119] Referring to Figure 15 , the computing system 3000 according to one embodiment of the disclosure can include a software layer including an operating system 3200, an application program 3100, a file system 3300, a conversion layer 3400, etc. Further, the computing system 3000 can include a hardware layer such as a memory device 3500.

[0120] The operating system 3200 can manage software resources, hardware resources, etc. of the computing system 3000, and can control program execution of the CPU. The application program 3100 can be any of various application programs to be executed in the computing system 3000, and can be a utility program executed by the operating system 3200.

[0121] The file system 3300 can refer to a logical structure for controlling data, files, etc. existing in the computing system 3000, and can organize files or data to be stored in the memory device 3500, etc. based on certain rules. The file system 3300 can be determined depending on the operating system 3200 used in the computing system 3000. For example, when the operating system 3200 is a Windows series of Microsoft, the file system 3300 can be a file allocation table (FAT), an NT file system (NTFS), etc. Also, when the operating system 3200 is a Unix / Linux family, the file system 3300 can be an extended file system (EXT), a Unix file system (UFS), a journaling file system (JFS), etc.

[0122] Although the operating system 3200, the application program 3100, and the file system 3300 are illustrated as separate blocks in the drawing, the application program 3100 and the file system 3300 can be included in the operating system 3200.

[0123] The translation layer 3400 translates an address into a form suitable for the memory device 3500 in response to a request from the file system 3300. For example, the translation layer 3400 can translate a logical address generated by the file system 3300 into a physical address of the memory device 3500. Here, mapping information of the logical address and the physical address can be stored in the form of an address translation table. For example, the translation layer 3400 can be a flash translation layer (FTL), a universal flash storage link layer (ULL), etc.

[0124] The memory device 3500 can be a volatile memory, and the memory device 3500 can be a memory device described with reference to Figure 1 、 Figure 2 、 Figure 3A 、 Figure 3B and Figure 3C described with reference to Figure 4A 、 Figure 4B 、 Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 6 、 Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 8A 、 Figure 8B 、 Figure 8C ,Figure 9A and Figure 9B or Figure 10A , Figure 10B , Figure 11A and Figure 11B The memory device 3500 can be manufactured by the manufacturing method described above. The structure of the memory device 3500 and the manufacturing method thereof are the same as those described above, and thus a detailed description thereof will be omitted.

[0125] The computing system 3000 having the configuration mentioned above can be divided into an operating system layer implemented in a higher level area and a controller layer implemented in a lower level area. The application program 3100, the operating system 3200, and the file system 3300 can be included in the operating system layer and can be driven by a working memory of the computing system 3000. Also, the translation layer 3400 can be included in the operating system layer or the controller layer.

[0126] As described above, because the computing system 3000 according to one embodiment of the disclosure includes the memory device 3500 having improved integration and enhanced characteristics, the characteristics of the computing system 3000 can also be improved.

[0127] According to one embodiment of the disclosure, by securing a margin on the contact area for forming a contact plug coupled to the selection line, the difficulty of the process can be reduced and defects in the process can be reduced.

Claims

1. A memory device, comprising: a stack structure including a plurality of conductive layers and a plurality of interlayer insulating layers alternately stacked in a cell array region and a contact region; a plurality of cell plugs formed within the stack structure in the cell array region; a plurality of select line contacts coupled to the conductive layers among the plurality of conductive layers that are assigned as select lines; and a separation pattern that penetrates the conductive layers assigned as the select lines in the cell array region, the separation pattern extending from the cell array region to the contact region, wherein the separation pattern separates the plurality of select line contacts from each other.

2. The memory device of claim 1, wherein the separation pattern penetrates the conductive layers for the select lines in the contact region and is positioned between the plurality of select line contacts.

3. The memory device of claim 1, wherein a horizontal cross-section of each of the plurality of select line contacts is substantially semi-circular or substantially rectangular.

4. The memory device of claim 1, wherein the conductive layers among the plurality of conductive layers in the contact region other than the conductive layers assigned as the select lines are conductive layers assigned as word lines, and wherein the memory device further comprises: word line contacts respectively coupled to the conductive layers assigned as the word lines.

5. The memory device of claim 1, wherein the separation pattern is disposed between the cell plugs and overlaps a portion of the cell plugs.

6. The memory device of claim 1, further comprising: an upper insulating layer formed on an upper portion of the stack structure, wherein the separation pattern penetrates the upper insulating layer.

7. The memory device of claim 1, wherein the cell array region includes a first cell region and a second cell region, and wherein the separation pattern is disposed at a boundary between the first cell region and the second cell region to physically separate the conductive layers assigned as the select lines in the first cell region from the conductive layers assigned as the select lines in the second cell region.

8. The memory device of claim 7, wherein each of the plurality of select line contacts is coupled to the conductive layers assigned as the select lines in the first cell region or the conductive layers assigned as the select lines in the second cell region.

9. A memory device, comprising: a stack structure including a plurality of conductive layers and a plurality of interlayer insulating layers alternately stacked in a cell array region and a contact region, the cell array region including a first cell region, a second cell region, a third cell region, and a fourth cell region; a plurality of cell plugs formed within the stack structure in the cell array region; a plurality of select line contacts coupled to the conductive layers among the plurality of conductive layers that are assigned as select lines; and a separation pattern that penetrates the conductive layers assigned as the select lines in the cell array region, the separation pattern extending from the cell array region to the contact region, wherein the separation pattern separates the plurality of select line contacts from each other. a first separation pattern disposed between the first cell region and the second cell region and penetrating the conductive layers in the cell array region that are assigned as the selection lines, the first separation pattern extending from the cell array region to the contact region; a second separation pattern disposed between the second cell region and the third cell region and penetrating the conductive layers in the cell array region that are assigned as the selection lines, the second separation pattern extending from the cell array region to the contact region; and a third separation pattern disposed between the third cell region and the fourth cell region and penetrating the conductive layers in the cell array region that are assigned as the selection lines, the third separation pattern extending from the cell array region to the contact region, wherein the first separation pattern and the third separation pattern separate the plurality of selection line contacts from each other.

10. The memory device of claim 9, wherein each of the first separation pattern, the second separation pattern, and the third separation pattern penetrates the conductive layers in the contact region that are assigned as the selection lines, and wherein the first separation pattern and the third separation pattern directly contact each of the plurality of selection line contacts and are positioned between the plurality of selection line contacts.

11. The memory device of claim 9, wherein a horizontal cross-section of each of the plurality of selection line contacts is substantially semi-circular or substantially rectangular.

12. The memory device of claim 9, wherein the plurality of conductive layers in the contact region other than the conductive layers assigned as the selection lines are conductive layers assigned as word lines, and the memory device further comprises: word line contacts respectively coupled to the conductive layers assigned as the word lines.

13. The memory device of claim 9, wherein each of the first separation pattern, the second separation pattern, and the third separation pattern is disposed between the cell plugs and overlaps a portion of the cell plugs.

14. The memory device of claim 9, further comprising: an upper insulating layer formed on an upper portion of the stack structure, wherein each of the first separation pattern, the second separation pattern, and the third separation pattern penetrates the upper insulating layer.

15. A method of manufacturing a memory device, comprising: forming a stack structure by alternately stacking a plurality of conductive layers and a plurality of interlayer insulating layers in a cell array region and a contact region; forming a plurality of cell plugs in the stack structure in the cell array region; forming pre-selection line contacts coupled to the conductive layers among the plurality of conductive layers that are assigned as selection lines; forming a trench that penetrates the conductive layers assigned as the selection lines, the trench extending from the cell array region to the contact region; and filling the trench with an insulating layer to form a separation pattern, ​ ​ wherein the trench penetrates the pre-selection line contact to separate the pre-selection line contact into a plurality of selection line contacts.

16. The method of claim 15, further comprising: forming an upper insulating layer on an upper portion of the stack structure prior to forming the pre-selection line contact, wherein the pre-selection line contact penetrates the upper insulating layer to couple to the conductive layer assigned as the selection line.

17. The method of claim 16, wherein the trench penetrates the upper insulating layer, the pre-selection line contact, and the conductive layer assigned as the selection line in a substantially linear shape.

18. The method of claim 15, wherein the pre-selection line contact is formed such that a horizontal cross-section thereof has a substantially elliptical, circular, or rectangular shape.

19. The method of claim 18, wherein each selection line contact of the plurality of selection line contacts is formed such that a horizontal cross-section thereof has a substantially semi-circular or rectangular shape.

20. The method of claim 15, wherein forming the pre-selection line contact comprises forming a word line contact coupled to each of the conductive layers assigned as word lines among the plurality of conductive layers except for the conductive layer assigned as the selection line.

21. A method of manufacturing a memory device, comprising: forming a stack structure by alternately stacking a plurality of conductive layers and a plurality of interlayer insulating layers in a cell array region and a contact region, the cell array region including a first cell region and a second cell region; forming a plurality of cell plugs within the stack structure in the cell array region; forming a first selection line contact and a second selection line contact coupled to the conductive layer assigned as a selection line among the plurality of conductive layers; forming a trench penetrating the conductive layer assigned as the selection line between the first cell region and the second cell region, the trench extending from the cell array region to the contact region; and filling the trench with an insulating layer to form a separation pattern, wherein the trench separates the first selection line contact and the second selection line contact from each other. ​

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