Storage device

Abstract

The present invention minimizes the size of a chip while suppressing the deterioration of an interface speed. According to one embodiment, a memory device includes a substrate (W1), a first circuit layer (100), a second circuit layer (200), and a wiring layer (300). The substrate has a first region (AA) and a second region (DA). The first circuit layer includes a CMOS circuit. The wiring layer is provided above the second circuit layer, and includes a pad electrically connected to the CMOS circuit via the second circuit layer. The second circuit layer includes a stacked body and a plurality of first pillars (MP). The laminated body includes first insulator layers (32) and first conductor layers (22) that are alternately laminated in a first region, and includes first insulator layers and first members (SM) that are alternately laminated in a second region. The plurality of first pillars pass through the stacked body in the first region, and are electrically connected to the source line (21) above the stacked body. The pad has a portion that overlaps the laminate and does not have a portion that overlaps the source line.

Description

Technical Field

[0001] The implementation relates to a storage device. Background Technology

[0002] NAND flash memory, which is capable of non-volatile data storage, is known. Summary of the Invention

[0003] This invention suppresses interface speed degradation and reduces chip size. The memory device of the embodiment has a bonding surface. The memory device includes a substrate, a first circuit layer, a second circuit layer, and a wiring layer. The substrate has a first region and a second region arranged in a first direction. The first circuit layer is disposed between the substrate and the bonding surface and includes CMOS circuitry. The second circuit layer is disposed above the bonding surface. The wiring layer is disposed above the second circuit layer and includes pads electrically connected to the CMOS circuitry via the second circuit layer. The second circuit layer includes a stack body, a plurality of first pillars, and source lines. In the first region, the stack body includes alternating layers of a first insulating layer and a first conductive layer in a second direction intersecting the first direction; and in the second region, it includes alternating layers of a first insulating layer and a first conductive layer in the second direction, or alternating layers of a first insulating layer and a first component in the second direction, wherein the material of the first component is different from both the first insulating layer and the first conductive layer. Multiple first pillars extend through the laminate in a second direction within a first region and are electrically connected to the source line above the laminate. The pads have portions overlapping the laminate in the second direction but not portions overlapping the source line in the second direction. Attached Figure Description

[0004] Figure 1 This is a block diagram illustrating an example of the overall configuration of a storage system equipped with the storage device of the first embodiment.

[0005] Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array included in the memory device of the first embodiment.

[0006] Figure 3 This is a perspective view showing an example of the appearance of the storage device according to the first embodiment.

[0007] Figure 4 This is a top view showing an example of the planar layout of the storage device according to the first embodiment.

[0008] Figure 5 This is a top view showing an example of the planar layout within the core area of ​​the storage cell array of the storage device of the first embodiment.

[0009] Figure 6 It is along Figure 5The cross-sectional view along line VI-VI shows an example of the cross-sectional structure within the storage area of ​​the storage cell array included in the storage device of the first embodiment.

[0010] Figure 7 It is along Figure 6 The cross-sectional view along line VII-VII shows an example of the cross-sectional structure of the storage column of the storage device of the first embodiment.

[0011] Figure 8 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device according to the first embodiment.

[0012] Figure 9 This is a top view showing an example of the planar layout of the wiring layer in the storage device of the first embodiment.

[0013] Figure 10 This is a top view showing an example of the planar layout near the solder pad portion in the storage device of the first embodiment.

[0014] Figure 11 It is along Figure 10 The XI-XI line cross-sectional view shows an example of the cross-sectional structure near the solder pad in the storage device of the first embodiment.

[0015] Figure 12 This is a flowchart illustrating an example of a method for manufacturing a storage device according to the first embodiment.

[0016] Figure 13 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the storage device according to the first embodiment.

[0017] Figure 14 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the storage device according to the first embodiment.

[0018] Figure 15 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the storage device according to the first embodiment.

[0019] Figure 16 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the storage device according to the first embodiment.

[0020] Figure 17 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the storage device according to the first embodiment.

[0021] Figure 18 This is a top view showing an example of the planar layout near the solder pads in the storage device of the first comparative example.

[0022] Figure 19 It is along Figure 18 The cross-sectional view along line XIX-XIX shows an example of the cross-sectional structure near the solder pad in the storage device of the first comparative example.

[0023] Figure 20 This is a top view showing an example of the planar layout near the solder pads in the storage device of the second comparative example.

[0024] Figure 21 It is along Figure 20 The cross-sectional view along line XXI-XXI shows an example of the cross-sectional structure near the solder pad in the storage device of the second comparative example.

[0025] Figure 22 This is a top view showing an example of the planar layout near the solder pad portion in the storage device of the second embodiment.

[0026] Figure 23 It is along Figure 22 The cross-sectional view along lines XXIII-XXIII shows an example of the cross-sectional structure near the solder pad in the storage device of the second embodiment.

[0027] Figure 24 This is a flowchart illustrating an example of a method for manufacturing a storage device according to the second embodiment.

[0028] Figure 25 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the storage device according to the second embodiment.

[0029] Figure 26 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the storage device according to the second embodiment.

[0030] Figure 27 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the storage device according to the second embodiment.

[0031] Figure 28 This is a top view showing an example of the planar layout near the solder pad portion in the storage device of the third embodiment.

[0032] Figure 29 It is along Figure 28 The cross-sectional view along line XXIX-XXIX shows an example of the cross-sectional structure near the solder pad in the storage device of the third embodiment.

[0033] Figure 30 This is a flowchart illustrating an example of a method for manufacturing a storage device according to the third embodiment.

[0034] Figure 31 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the storage device according to the third embodiment.

[0035] Figure 32 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the storage device according to the third embodiment.

[0036] Figure 33 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the storage device according to the third embodiment.

[0037] Figure 34 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the storage device according to the third embodiment.

[0038] Figure 35 This is a top view showing an example of the planar layout near the solder pad portion in the storage device of the fourth embodiment.

[0039] Figure 36 It is along Figure 35 The cross-sectional view along line XXXVI-XXXVI shows an example of the cross-sectional structure near the solder pad in the storage device of the fourth embodiment.

[0040] Figure 37 This is a top view showing an example of the planar layout near the solder pad portion in the storage device of the fifth embodiment.

[0041] Figure 38 It is along Figure 37 The cross-sectional view along lines XXXVIII-XXXVIII shows an example of the cross-sectional structure near the solder pad in the storage device of the fifth embodiment.

[0042] Figure 39 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device of the sixth embodiment.

[0043] Figure 40 This is a top view showing an example of the planar layout near the solder pad portion in the storage device of the sixth embodiment.

[0044] Figure 41 It is along Figure 40 The cross-sectional view along the XLI-XLI line shows an example of the cross-sectional structure near the solder pad in the storage device of the sixth embodiment.

[0045] Figure 42 This is a flowchart illustrating an example of a method for manufacturing a storage device according to the sixth embodiment.

[0046] Figure 43This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the storage device according to the sixth embodiment.

[0047] Figure 44 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the storage device according to the sixth embodiment.

[0048] Figure 45 This is a top view showing an example of the planar layout near the solder pad portion in the storage device of the seventh embodiment.

[0049] Figure 46 It is along Figure 45 The XLVI-XLVI line cross-sectional view shows an example of the cross-sectional structure near the solder pad in the storage device of the seventh embodiment.

[0050] Figure 47 This is a top view showing an example of the planar layout near the solder pad portion in the storage device of the eighth embodiment.

[0051] Figure 48 It is along Figure 47 The cross-sectional view along the XLVIII-XLVIII line shows an example of the cross-sectional structure near the solder pad in the storage device of the eighth embodiment.

[0052] Figure 49 This is a top view showing an example of the planar layout near the solder pad portion in the storage device of the ninth embodiment.

[0053] Figure 50 It is along Figure 49 The LL-line cross-sectional view shows an example of the cross-sectional structure near the solder pad in the storage device of the 9th embodiment.

[0054] Figure 51 This is a top view showing an example of the planar layout near the solder pad portion in the storage device of the 10th embodiment.

[0055] Figure 52 It is along Figure 51 The cross-sectional view along line LII-LII shows an example of the cross-sectional structure near the solder pad in the storage device of the 10th embodiment.

[0056] Figure 53 This is a top view showing an example of the planar layout near the solder pad portion in the storage device of the 11th embodiment.

[0057] Figure 54 It is along Figure 53 The LIV-LIV line cross-sectional view shows an example of the cross-sectional structure near the solder pad in the storage device of the 11th embodiment.

[0058] Figure 55 This is a cross-sectional view showing an example of the detailed cross-sectional structure near two opposing bonding pads in the storage device of the first embodiment. Detailed Implementation

[0059] Hereinafter, various embodiments will be described with reference to the accompanying drawings. Each embodiment illustrates an apparatus and method for embodying the technical concept of the invention. The drawings are schematic diagrams or conceptual diagrams. The dimensions, scales, etc., of each drawing may not be the same as the actual situation. The structural illustrations have been appropriately omitted. The shading added to the top view may not be related to the raw materials and characteristics of the constituent elements. In this specification, constituent elements having substantially the same function and structure are labeled with the same symbols. Numbers, characters, etc., added to the reference symbols are used to distinguish similar elements represented by the same reference symbols from one another.

[0060] <1> First Embodiment

[0061] The first embodiment relates to a storage device having a structure in which the source lines in the region where the ends of the storage cell array overlap with the solder pads exposed on the surface of the storage device are removed, and an insulating film is embedded in this region. Hereinafter, the storage device 1 of the first embodiment will be described.

[0062] <1-1> Composition

[0063] First, the configuration of the storage device 1 in the first embodiment will be described.

[0064] <1-1-1> Overall Structure of Storage Device 1

[0065] Figure 1 This is a block diagram illustrating an example of the overall configuration of a storage system equipped with the storage device 1 of the first embodiment. For example... Figure 1 As shown, the storage device 1 is controlled by an external memory controller 2. The storage device 1 is, for example, a NAND flash memory capable of non-volatile data storage. The storage device 1 includes, for example, a memory cell array 10, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15, a line decoder module 16, and a sense amplifier module 17.

[0066] The storage cell array 10 contains multiple blocks BLK0 to BLKn (where "n" is an integer greater than or equal to 1). A block BLK is a collection of multiple storage cells. A block BLK corresponds, for example, to a unit for erasing data. A block BLK contains multiple pages. A page corresponds to a unit for reading and writing data. The storage cell array 10 is provided with multiple bit lines BL0 to BLm (where "m" is an integer greater than or equal to 1) and multiple word lines WL, but these are not shown in the diagram. Each storage cell is associated, for example, with one bit line BL and one word line WL.

[0067] Input / output circuit 11 is the interface circuit responsible for sending and receiving input / output signals with memory controller 2. Input / output signals include, for example, data (DAT), status information, address information, and instructions. Input / output circuit 11 can input and output data (DAT) with both the sense amplifier module 17 and memory controller 2. Input / output circuit 11 can output status information transmitted from register circuit 13 to memory controller 2. Input / output circuit 11 can output address information and instructions transmitted from memory controller 2 to register circuit 13 respectively.

[0068] The logic controller 12 controls the input / output circuit 11 and the sequencer 14 based on the control signals input from the memory controller 2. For example, the logic controller 12 controls the sequencer 14 to start the memory device 1. The logic controller 12 notifies the input / output circuit 11 that the input / output signals received from the input / output circuit 11 are instructions or address information, etc. The logic controller 12 commands the input / output circuit 11 to input or output the input / output signals.

[0069] Register circuit 13 temporarily stores status information, address information, and instructions. The status information is updated based on the control of sequencer 14 and transmitted to input / output circuit 11. Address information includes block address, page address, column address, etc. Instructions include commands related to various operations of storage device 1.

[0070] The sequencer 14 controls the overall operation of the storage device 1. Based on the instructions and address information stored in the register circuit 13, the sequencer 14 performs read operations, write operations, erase operations, etc.

[0071] The driver circuit 15 generates the voltage used in read, write, and erase operations. Furthermore, the driver circuit 15 supplies the generated voltage to the line decoder module 16, the sense amplifier module 17, and the like.

[0072] The row decoder module 16 is a circuit used to select the block BLK to be operated on, or to transmit voltage to wiring such as word lines WL. The row decoder module 16 includes multiple row decoders RD0 to RDn. The row decoders RD0 to RDn are associated with blocks BLK0 to BLKn respectively, and are used to select the block BLK. Each row decoder RD transmits the voltage generated by the driver circuit 15 to various wirings disposed in the memory cell array 10.

[0073] The sensing amplifier module 17 is a circuit used to transmit voltage to each bit line BL or to read data. The sensing amplifier module 17 includes multiple sensing amplifier units SAU0 to SAUm. Each sensing amplifier unit SAU0 to SAUm is associated with multiple bit lines BL0 to BLm. Each sensing amplifier unit SAU includes a sensing amplifier capable of determining data based on the voltage of the associated bit line BL, and a latching circuit for temporarily storing the data.

[0074] Furthermore, the combination of storage device 1 and memory controller 2 can also constitute a semiconductor device. An example of such a semiconductor device is an SD card. TM Memory cards such as memory cards, or SSDs (solid state drives), etc.

[0075] <1-1-2> Circuit configuration of memory cell array 10

[0076] Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array 10 included in the memory device 1 of the first embodiment. Figure 2 The diagram shows two blocks, BLK0 and BLK1, within a plurality of blocks BLK contained in the storage cell array 10. (Example...) Figure 2 As shown, in the memory cell array 10, each block BLK is provided with select gate lines SGD and SGS, and word lines WL0 to WL(N-1) (N is an integer greater than or equal to 2). Bit lines BL0 to BLm and source line SL are shared by multiple blocks BLK, for example.

[0077] Each BLK block contains multiple NAND strings NS. Each NAND string NS is associated with bit lines BL0 to BLm. In other words, each bit line BL is shared by NAND strings NS that are assigned the same column address among multiple BLK blocks. Each NAND string NS is connected between its associated bit line BL and source line SL. Each NAND string NS contains, for example, N memory cell transistors MT0 to MT(N-1), and select transistors ST1 and ST2. Each memory cell transistor MT is a memory cell with a control gate and charge storage layer, non-volatilely storing data. Select transistors ST1 and ST2 are used to select the BLK block.

[0078] In each NAND string NS, select transistor ST1, memory cell transistors MT(N-1) to MT0, and select transistor ST2 are connected in series. Specifically, the drain and source terminals of select transistor ST1 are connected to the associated bit line BL and the drain terminal of memory cell transistor MT(N-1), respectively. The drain and source terminals of select transistor ST2 are connected to the source terminal and source line SL of memory cell transistor MT0, respectively. Memory cell transistors MT0 to MT(N-1) are connected in series between select transistors ST1 and ST2.

[0079] Each select gate line SGD is connected to the gate terminal of each select transistor ST1 within the associated block BLK. The select gate line SGS is connected to the gate terminal of each select transistor ST2 within the associated block BLK. Word lines WL0 to WL(N-1) are connected to the control gate terminals of each memory cell transistor MT0 to MT(N-1) within the associated block BLK. A "page" corresponds to the set of multiple memory cell transistors MT connected to the common word line WL within the same BLK. Depending on the number of bits stored by the memory cell transistor MT, the set of multiple memory cell transistors MT connected to the common word line WL within the same BLK may have a storage capacity of more than two pages of data.

[0080] Furthermore, the circuit configuration of the memory cell array 10 can also be other circuit configurations. For example, multiple select gate lines (SGDs) that can be independently controlled can be provided in each BLK. In this case, each BLK is configured to be selectable in units of multiple cells corresponding to the multiple select gate lines (SGDs).

[0081] Hereinafter, the storage device 1 of the first embodiment will be described as an example in which each NAND string NS has eight storage cell transistors MT0 to MT7 that are respectively connected to word lines WL0 to WL7 (i.e., N=8).

[0082] <1-1-3> Structure of storage device 1

[0083] The structure of the storage device 1 according to the first embodiment will be described below.

[0084] Furthermore, a three-dimensional orthogonal coordinate system is used in the accompanying figures. The X direction corresponds to the extension direction of the word line WL. The Y direction corresponds to the extension direction of the bit line BL. The Z direction corresponds to the vertical direction relative to the front surface of the reference semiconductor substrate. "Up and down" is defined based on the direction along the Z direction. The positive direction (above) corresponds to the direction away from the reference semiconductor substrate. The XY plane (section) corresponds to the plane (section) parallel to the X and Y directions, respectively. The YZ section corresponds to the section parallel to the Y and Z directions, respectively. The XZ section corresponds to the section parallel to the X and Z directions, respectively.

[0085] (1: Appearance of storage device 1)

[0086] First, the appearance of the memory device 1 according to the first embodiment will be described. The memory device 1 of the first embodiment is formed by bonding two semiconductor circuit substrates on which semiconductor circuits are respectively formed, and then separating the bonded semiconductor circuit substrates chip by chip. That is, the memory device 1 of the first embodiment has a bonding surface formed by bonding semiconductor substrates W1 and W2. Semiconductor substrates W1 and W2 are silicon substrates. Hereinafter, the case where semiconductor substrate W2 is removed during the manufacturing process of memory device 1 will be described. Depending on the structure of the memory cell array 10, a portion of semiconductor substrate W2 may also be retained after semiconductor substrates W1 and W2 are bonded together.

[0087] Figure 3 This is a perspective view showing an example of the appearance of the storage device 1 according to the first embodiment. Figure 3 As shown, the storage device 1 includes, for example, a semiconductor substrate W1, a CMOS layer 100, a bonding layer B1, a bonding layer B2, a storage layer 200, and a wiring layer 300.

[0088] A CMOS layer 100 is disposed on a semiconductor substrate W1. The CMOS layer 100 contains CMOS circuitry (control circuitry) formed using the semiconductor substrate W1. The semiconductor substrate W1 has impurity diffusion regions, etc., consistent with the design of the CMOS circuitry. The CMOS layer 100 includes, for example, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15, a line decoder module 16, and a sense amplifier module 17. The CMOS layer 100 can also be referred to as a circuit layer.

[0089] A bonding layer B1 is disposed on the CMOS layer 100. The bonding layer B1 is formed using a semiconductor substrate W1. The bonding layer B1 includes a plurality of bonding pads that are electrically connected to the CMOS circuit disposed on the CMOS layer 100 to form part of the semiconductor circuit.

[0090] Bonding layer B2 is disposed on bonding layer B1. Bonding layer B2 is formed using semiconductor substrate W2 (not shown). Bonding layer B2 includes a plurality of bonding pads that are electrically connected to the memory cell array 10 disposed on memory layer 200 to form part of a semiconductor circuit. The plurality of bonding pads included in bonding layer B2 are respectively connected to the plurality of bonding pads included in bonding layer B1. The junction between bonding layers B1 and B2 corresponds to the boundary between the layer formed using semiconductor substrate W1 and the layer formed using semiconductor substrate W2, i.e., the bonding surface.

[0091] The memory layer 200 is disposed on the bonding layer B2. The memory layer 200 includes a memory cell array 10 formed using a semiconductor substrate W2. The memory layer 200 may also be referred to as a circuit layer.

[0092] A wiring layer 300 is disposed on the memory layer 200. The wiring layer 300 is formed after the semiconductor substrates W1 and W2 are bonded together. The wiring layer 300 includes wiring connected to the semiconductor circuitry disposed on the memory layer 200, and a plurality of pad portions PD. The plurality of pad portions PD include conductive portions (pads) exposed on the surface of the memory device 1. The plurality of pad portions PD are used to connect the memory device 1 to the memory controller 2, etc., or to supply power, etc.

[0093] (2: Planar layout of storage device 1)

[0094] Figure 4 This is a top view showing an example of the planar layout of the storage device 1 according to the first embodiment. (e.g.) Figure 4 As shown, the storage device 1 includes, for example, a core region CR, a peripheral region PR, a wall region WR, and a slot region KR.

[0095] The core region CR is, for example, a rectangular region located near the center of the semiconductor substrate W1. Within the core region CR, for example, a memory cell array 10, a register circuit 13, a sequencer 14, a driver circuit 15, a line decoder module 16, and a sense amplifier module 17 are configured.

[0096] The peripheral region PR is a square annular region that surrounds the core region CR. Within the peripheral region PR, for example, input / output circuits 11 and a logic controller 12 are configured. Additionally, within the peripheral region PR, for example, contacts are configured to connect wiring on the wiring layer 300 to circuitry on the CMOS layer 100 or the memory layer 200.

[0097] The wall region WR is a square annular region that surrounds the outer perimeter of the outer region PR. Within the wall region WR, at least one sealing part ES (not shown) is disposed, also surrounding the outer perimeter of the outer region PR. Details regarding the sealing part ES will be described below.

[0098] The trench region KR is a square annular region that surrounds the outer periphery of the wall region WR. The trench region KR is connected to the outermost periphery of the memory device 1. Within the trench region KR, for example, alignment marks used during the manufacture of the memory device 1 are disposed. The structure of the trench region KR can also be removed during the dicing step of cutting the semiconductor circuit substrate chip by chip (memory device 1).

[0099] (3: Planar layout of storage cell array 10)

[0100] Figure 5 This is a top view showing an example of the planar layout within the core region CR of the storage cell array 10 included in the storage device 1 of the first embodiment. (See attached image.) Figure 5 As shown, the memory cell array 10 includes multiple slots (SLTs), multiple memory columns (MPs), and multiple contacts (CVs and CCs). Additionally, the memory cell array 10 includes, for example, memory regions (SAs) and contact regions (CAs) arranged in the X direction.

[0101] Each slit SLT is a plate-shaped component extending along the X direction. Each slit SLT has a portion extending along the X direction, transversely cutting the storage region SA and the contact region CA along the X direction. Multiple slit SLTs are arranged in the Y direction. Each slit SLT separates adjacent wirings (e.g., word lines WL0 to WL7, and select gate lines SGD and SGS) separated by that slit SLT. In each slit SLT, conductors with insulating spacers on their sidewalls can be configured to insulate them from their wirings, or insulating materials can be embedded. In the memory cell array 10, the regions divided by the slit SLTs along the Y direction correspond to one block BLK.

[0102] Storage region SA contains multiple storage columns (MPs). Each storage column (MP) functions as a columnar component, for example, a NAND string (NS). The multiple storage columns (MPs) are arranged in a grid pattern within each block BLK. At least one bit line (BL) is arranged overlapping each storage column (MP). Each bit line (BL) has a portion extending in the Y direction and arranged in the X direction. In this example, two bit lines (BLs) are arranged overlapping one storage column (MP). The associated storage columns (MPs) and bit lines (BLs) are electrically connected via contacts (CVs).

[0103] The contact area CA is used to connect the stacked wiring (e.g., word lines WL, select gate lines SGD and SGS) of the memory cell array 10 to the row decoder module 16. Within the contact area CA, each block BLK is configured with multiple contacts CC. In each block BLK, the multiple contacts CC are electrically connected to one corresponding wiring in the stacked wiring. In each BLK, at least one contact CC is electrically connected to the select gate line SGS, word lines WL0 to WL7, and select gate line SGD.

[0104] Furthermore, within the contact area CA, the multiple contacts CC in each BLK are not limited to, for example... Figure 5 The configuration shown, arranged in a row along the X direction, can also be arranged in a grid pattern within each block BLK. Alternatively, two node regions CA can be configured within the core region CR, sandwiching the storage region SA along the X direction. Another option is to configure the node regions CA by dividing the storage region SA along the X direction.

[0105] Furthermore, the core region CR includes a valid region AA and a dummy region DA arranged in the Y direction. The valid region AA and the dummy region DA each overlap with the storage region SA and the contact region CA, respectively. Within the overlapping area of ​​the storage region SA and the valid region AA, multiple storage columns MP are configured for storing data. Within the overlapping area of ​​the contact region CA and the valid region AA, multiple contacts CC are configured for controlling valid blocks BLK.

[0106] A dummy region DA is configured at the Y-direction end of the core region CR. Within the core region CR, two dummy regions DA can be configured, sandwiching the effective region AA in the Y-direction. A dummy block DBLK corresponds to the region within the dummy region DA that is divided along the Y-direction by the slit SLT. Each dummy region DA contains at least one dummy block DBLK. Figure 5 The diagram shows two dummy blocks, DBLK0 and DBLK1, arranged in the Y direction. Multiple dummy columns (DMPs) can be configured within the area of ​​the dummy block DBLK that overlaps with the storage area SA. The dummy column DMP is a pattern used to compensate for the shape of the storage column MP and has the same structure as the storage column MP. The dummy column DMP is not connected to the contact CV or the bit line BL. Therefore, the dummy column DMP is not used for storing data.

[0107] The dummy region DA, in the portion corresponding to the outer edge of the core region CR, also includes a dummy step portion DS. The dummy step portion DS includes the ends of the stacked wiring arranged in a stepped manner. A sacrificial component SM remains in the portion of the dummy step portion DS corresponding to the stacked wiring. The sacrificial component SM is a component used in the replacement process of forming the stacked wiring. In the replacement process, the sacrificial components SM in alternating stacks and in the insulating layer are replaced with conductors, thereby forming the stacked wiring. More specifically, in the replacement process, the sacrificial component SM is removed via a slit SLT, and then a conductor is embedded in the space left after the sacrificial component SM is removed. Therefore, sacrificial components SM located away from the slit SLT may not be replaced with conductors and remain in the replacement process. Thus, the ends of the stacked sacrificial components SM are arranged in a stepped manner. An example of the structure of the dummy step portion DS is shown in the following description. Figure 11 middle.

[0108] (4: Cross-sectional structure within the storage region SA of the storage cell array 10)

[0109] Figure 6 It is along Figure 5 The cross-sectional view along line VI-VI shows an example of the cross-sectional structure within the storage region SA of the storage cell array 10 included in the storage device 1 of the first embodiment. Figure 6 An example of the structure of a memory cell array 10 formed on a semiconductor substrate W2 before bonding with a semiconductor substrate W1, and the bonding layer B2 above it, is shown, with coordinate axes labeled with the semiconductor substrate W2 as a reference. Figure 6 As shown, the storage cell array 10 includes, for example, conductive layers 21-24, insulating layers 31-34, insulating components 36, and contacts CV, V1, and V2 within the storage region SA.

[0110] A conductive layer 21 is disposed on a semiconductor substrate W2. An insulating layer 31 is disposed on the conductive layer 21. Conductive layers 22 and insulating layers 32 are alternately disposed on the insulating layer 31 in the Z direction. That is, a plurality of conductive layers 22 are arranged in the Z direction. Thus, the stacked layer corresponding to the memory cell array 10 includes conductive layers 22 and insulating layers 32 alternately disposed in the Z direction. The number of conductive layers 22 corresponds, for example, to the number of stacked wiring layers (select gate line SGS, word line WL, and select gate line SGD).

[0111] An insulating layer 33, a conductive layer 23, and an insulating layer 34 are sequentially disposed on the uppermost conductive layer 22. Conductive layers 21 and 22 are, for example, formed as plates extending along the XY plane. Conductive layer 23, for example, has a linear portion extending in the Y direction. Conductive layer 21 is used as the source line SL. In this example, the 10 conductive layers 22 arranged in the Z direction are used sequentially from the source line SL side as the select gate line SGS, word lines WL0 to WL7, and select gate line SGD. Conductive layer 23 is used as the bit line BL. Conductive layer 21, for example, contains polysilicon (Si). Conductive layer 22, for example, contains tungsten (W). Conductive layer 23, for example, contains copper (Cu).

[0112] A conductive layer 24 is disposed above conductive layer 23. Conductive layer 24 is the wiring connecting the relay bit line BL to the sense amplifier module 17. Conductive layer 23 and conductive layer 24 are connected via contact V1. A conductive layer 25 is disposed above conductive layer 24. Conductive layer 25 corresponds to bonding pads. Conductive layer 24 and conductive layer 25 are connected via contact V2. The sides of conductive layer 24, and contacts V1 and V2 are covered by insulating layer 34. Insulating layer 34 may be composed of multiple insulating films. The sides of conductive layer 25 are covered by insulating layer 35. Insulating layer 35 and conductive layer 25 are contained in bonding layer B2. Memory cell array 10 may contain multiple conductive layers 24. Bonding layer B2 may contain multiple conductive layers 25. Conductive layer 25 may contain, for example, copper.

[0113] The insulating member 36 has a plate-like portion formed extending along the XZ plane. The insulating member 36 separates the insulating layer 31 from the alternately arranged conductive layer 22 and insulating layer 32. In this example, the insulating member 36 is embedded in the slit SLT. Alternatively, a conductor with insulating spacers on its sidewalls can be arranged in the slit SLT and insulated from the conductive layers 21 and 22 respectively.

[0114] Each memory pillar MP extends along the Z-direction, penetrating and connecting the insulating layer 31 with alternating conductive layers 22 and insulating layers 32 to the conductive layer 21. Each memory pillar MP includes, for example, a core component 40, a semiconductor layer 41, and a stacked film 42. The core component 40 is an insulator extending along the Z-direction. The semiconductor layer 41 covers the core component 40. A portion of the side surface of the semiconductor layer 41 is in contact with the conductive layer 21. That is, the semiconductor layer 41 and the conductive layer 21 (source line SL) within the memory pillar MP are electrically connected via the side surface of the memory pillar MP. The stacked film 42 covers the side surface and bottom surface of the semiconductor layer 41, except for the contact portion between the semiconductor layer 41 and the conductive layer 21. A connection is established between the corresponding semiconductor layer 41 (memory pillar MP) and the conductive layer 23 (bit line BL) via a contact CV.

[0115] The portion of the conductive layer 22 used as the select gate line SGS that intersects with the memory pillar MP functions as the select transistor ST2. The portion of the conductive layer 22 used as the word line WL that intersects with the memory pillar MP functions as the memory cell transistor MT. The portion of the conductive layer 22 used as the select gate line SGD that intersects with the memory pillar MP functions as the select transistor ST1. In each memory pillar MP, the semiconductor layer 41 serves as the channel (current path) for the memory cell transistors MT0 to MT7 contained in the NAND string NS, as well as the select transistors ST1 and ST2.

[0116] (5: Cross-sectional structure of storage column MP)

[0117] Figure 7 It is along Figure 6 The cross-sectional view along line VII-VII shows an example of the cross-sectional structure of the storage column MP included in the storage device 1 of the first embodiment. Figure 6 A cross-section containing the storage pillar MP and the conductive layer 22, parallel to the front side of the semiconductor substrate W2, is shown. Figure 6 As shown, the multilayer film 42 includes, for example, a tunnel insulating film 43, an insulating film 44, and a bulk insulating film 45. The tunnel insulating film 43 surrounds the sides of the semiconductor layer 41. The insulating film 44 surrounds the sides of the tunnel insulating film 43. The bulk insulating film 45 surrounds the sides of the insulating film 44. The conductive layer 22 surrounds the sides of the bulk insulating film 45. The tunnel insulating film 43 and the bulk insulating film 45 each comprise, for example, silicon oxide films (SiO2). The insulating film 44 is used as a charge storage layer for a memory cell transistor MT. The insulating film 44 comprises, for example, silicon nitride (SiN).

[0118] (6: Cross-sectional structure of storage device 1)

[0119] Figure 8 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device 1 according to the first embodiment. Figure 8 The diagram shows a portion of the core region CR, peripheral region PR, and wall region WR after semiconductor substrates W1 and W2 are bonded, with coordinate axes based on semiconductor substrate W1. Furthermore, in this example, semiconductor substrate W2 is removed after the bonding process of semiconductor substrates W1 and W2. The memory layer 200 and bonding layer B2 are located within the core region CR, and have [missing information - likely related to structural details]. Figure 6 The storage cell array 10 shown is configured with its structure reversed vertically. For example... Figure 8As shown, CMOS layer 100 includes insulating layer 110. Bonding layer B1 includes insulating layer 111. Storage layer 200 includes insulating layer 210, conductive layer 211, sacrificial component 212, and conductive layer 213. Wiring layer 300 includes insulating layer 301, insulating component 302, conductive layer 303, insulating layer 304, insulating layer 305, and insulating layer 306.

[0120] An insulating layer 110 is disposed on a semiconductor substrate W1. The insulating layer 110 covers at least a portion of wiring, contacts, components, etc., disposed on the CMOS layer 100. The insulating layer 110 can be composed of various insulating films. An insulating layer 111 is disposed on the insulating layer 110. The insulating layer 111 covers the side surface of the bonding pads of the bonding layer B1. An insulating layer 35 of the bonding layer B2 is disposed on the insulating layer 111.

[0121] An insulating layer 210 is disposed on an insulating layer 35. The insulating layer 210 covers at least a portion of the wiring, contacts, components, etc. disposed in the storage layer 200. The insulating layer 210 may be composed of various insulating films and may include insulating layers 33 and 34. A conductor layer 211, a sacrificial member 212, and a conductor layer 213 are sequentially deposited on the insulating layer 210. The group of conductor layers 211, sacrificial member 212, and conductor layer 213 is disposed at the height of the conductor layer 21. Specifically, the height of the lower surface of the conductor layer 211 is aligned with the height of the lower surface of the conductor layer 21 (source line SL). The height of the upper surface of the conductor layer 213 is aligned with the height of the upper surface of the conductor layer 21 (source line SL). The conductor layer 21 in the core region CR corresponds to the structure obtained by replacing the sacrificial member 212 with a conductor after depositing the conductor layer 211, sacrificial member 212, and conductor layer 213. That is, the height of the sacrificial component 212 is the same as the height after the conductor layer 21 and the semiconductor layer 41 in each memory pillar MP are connected. The conductor layers 211 and 213, for example, each contain polysilicon (Si). The sacrificial component 212, for example, contains silicon nitride (SiN).

[0122] An insulating layer 301 is disposed on conductive layers 213 and 21. An insulating member 302 is disposed within a portion of the peripheral region PR and a portion of the wall region WR, respectively, penetrating the insulating layer 301, conductive layer 213, sacrificial member 212, and conductive layer 211. The upper surface of the insulating member 302 can be aligned with the upper surface of the insulating layer 301, or a step difference can be formed between the insulating member 302 and the insulating layer 301. The lower surface of the insulating member 302 can be aligned with the lower surface of the conductive layer 211, or it can be located at the height between the lower surface of the conductive layer 211 and the conductive layer 26 described below.

[0123] A conductive layer 303 is disposed on an insulating layer 301. Additionally, the conductive layer 303 may have portions disposed on insulating members 302 within the peripheral region PR and the wall region WR. The conductive layer 303 is interrupted (insulated) at least between the peripheral region PR and the wall region WR. The conductive layer 303 may also have portions that are continuously disposed between the core region CR and the peripheral region PR.

[0124] The wiring layer 300 includes a through-hole VA in the core region CR, a through-hole VB in the peripheral region PR, and a through-hole VC in the wall region WR. Through-hole VA penetrates the insulating layer 301. The conductive layer 303 in the core region CR is disposed along the through-hole VA and may have a portion connected to the conductive layer 21 via the through-hole VA. Through-hole VB penetrates the insulating component 302. The conductive layer 303 in the peripheral region PR is disposed along the through-hole VB and may have a portion connected to the contact C3 via the through-hole VB. The portion of the conductive layer 303 disposed in the through-hole VB is insulated from the conductive layers 211 and 213 by the insulating component 302. Through-hole VC penetrates the insulating component 302. The conductive layer 303 in the wall region WR is disposed along the through-hole VC and may have a portion connected to the sealing portions ES1 and ES2 via the through-hole VC. The portion of the conductive layer 303 disposed in the through-hole VC is insulated from the conductive layers 211 and 213 by the insulating component 302.

[0125] Insulating layers 304, 305, and 306 are sequentially disposed on insulating layer 301 or conductive layer 303. Each of insulating layers 304, 305, and 306 has portions disposed along vias VA, VB, and VC, respectively. Insulating layer 301, insulating component 302, and insulating layer 304, for example, each comprise a silicon oxide film (SiO2). Insulating layer 305, for example, comprises silicon nitride (SiN). Insulating layer 306, for example, comprises polyimide.

[0126] Within the core region CR, the CMOS layer 100 includes a gate insulating film 101, a gate electrode 102, conductive layers 103 and 104, and contacts C0 to C2. The bonding layer B1 includes a conductive layer 105. The gate insulating film 101 is disposed on the semiconductor substrate W1. The gate electrode 102 of the core region CR is disposed on the gate insulating film 101 and is used as the gate electrode of transistor TR1. Transistor TR1 is included, for example, in a sense amplifier module 17. The conductive layer 103 is a wiring layer above the gate electrode 102. Contact C0 connects the gate electrode 102 and the conductive layer 103. Contact C1 connects the impurity diffusion region of transistor TR1 disposed on the semiconductor substrate W1 to the conductive layer 103. The conductive layer 104 is a wiring layer disposed at a height between the conductive layer 103 and the bonding layer B1. Contact C2 is disposed at a height between the conductive layer 103 and the bonding layer B1. At least one conductive layer 103 is connected to conductive layer 105 via at least one contact C2 and at least one conductive layer 104. Conductive layer 105 corresponds to a bonding pad disposed in bonding layer B1. Conductive layer 105 is connected to conductive layer 25 disposed opposite to conductive layer 105 in bonding layer B2. Thus, semiconductor layer 41 in core region CR is electrically connected to transistor TR1 via contact CV, conductive layers 23-25 ​​and 103-105, and contacts CV, V1, V2, C1 and C2.

[0127] Similar to the core region CR, within the peripheral region PR, the CMOS layer 100 includes a gate insulating film 101, a gate electrode 102, conductor layers 103 and 104, and contacts C0 to C2. The bonding layer B1 includes a conductor layer 105. The gate electrode 102 of the peripheral region PR is used as the gate electrode of transistor TR2. Transistor TR2 can be, for example, a transistor connected to a power line, or a transistor included in the input / output circuit 11. Within the peripheral region PR, the bonding layer B2 includes a conductor layer 25, and the memory layer 200 includes conductor layers 24 and 26, and contacts V1, V2, and C3. Conductor layer 26 is a wiring disposed on the same layer as conductor layer 23. At least one contact C3 is provided on conductor layer 26. The upper part of each contact C3 reaches at least the height of conductor layer 211. Moreover, the upper part of each contact C3 is covered by conductor layer 303 and electrically connected to conductor layer 303. Thus, the conductor layer 303 in the peripheral region PR is electrically connected to the transistor TR2 via at least one contact C3, conductor layers 24-26 and 103-105, and contacts V1, V2, C1 and C2.

[0128] Within the wall region WR, the storage device 1 includes contacts C1W, C2W, C3W, V1W, and V2W, and conductive layers 103W, 104W, 105W, 24W, 25W, and 26W in each of the sealing portions ES1 and ES2. Contacts C1W, C2W, C3W, V1W, and V2W are disposed on the same layer as contacts C1, C2, C3, V1, and V2, respectively. Conductive layers 103W, 104W, 105W, 24W, 25W, and 26W are disposed on the same layer as conductive layers 103, 104, 105, 24, 25, and 26, respectively. The group of contacts C1W, C2W, C3W, V1W, and V2W with conductive layers 103W, 104W, 105W, 24W, 25W, and 26W is arranged in a ring shape in top view, but the relevant figures are omitted. That is, sealing parts ES1 and ES2 are each arranged in a square ring shape within the wall region WR, surrounding the outer periphery of the core region CR, and also surrounding the outer periphery PR. Compared with sealing part ES1, sealing part ES2 is located on the outer side.

[0129] Within the wall region WR, the semiconductor substrate W1 includes a P-type well region PW and an N-type well region NW. The P-type well region PW is a diffusion region of P-type impurities located near the upper surface of the semiconductor substrate W1. + The N-type well region NW is the diffusion region of N-type impurities located near the upper surface of the semiconductor substrate W1. + The P-type well region PW and the N-type well region NW are respectively connected to the sealing parts ES1 and ES2. Furthermore, the conductive layer 303 in the wall region WR is connected to the P-type well region PW via the contacts C1W, C2W, C3W, V1W, and V2W corresponding to the sealing part ES1, and the conductive layers 103W, 104W, 105W, 24W, 25W, and 26W. Similarly, the conductive layer 303 in the wall region WR is connected to the N-type well region NW via the contacts C1W, C2W, C3W, V1W, and V2W corresponding to the sealing part ES2, and the conductive layers 103W, 104W, 105W, 24W, 25W, and 26W.

[0130] The sealing portions ES1 and ES2 described above are structures that allow positive and negative charges generated inside and outside the wall region WR to dissipate to the semiconductor substrate W1. Furthermore, both sealing portions ES1 and ES2 can suppress the penetration of moisture and other substances from the outside of the wall region WR into the core region CR. Both sealing portions ES1 and ES2 can suppress stress generated on the interlayer insulating film (e.g., tetraethoxysilane (TEOS)) of the storage device 1. Additionally, both sealing portions ES1 and ES2 can be used as crack arresters.

[0131] (7: Plan layout of wiring layer 300)

[0132] Figure 9 This is a top view showing an example of the planar layout of the wiring layer 300 in the storage device 1 of the first embodiment. Figure 9 This involves extracting the core area (CR), the peripheral area (PR), the wall area (WR), and a portion of the wiring and solder pads (PD) and illustrating them. For example... Figure 9 As shown, within the wall region WR, the sealing part ES1 is arranged to surround the outer periphery of the core region CR and the outer periphery of the peripheral region PR. The sealing part ES2 is arranged to surround the outer periphery of the sealing part ES1.

[0133] Inside the wall region WR, a plurality of conductive layers 303 are disposed. Each of the plurality of conductive layers 303 has a portion extending in the Y direction. The plurality of conductive layers 303 are arranged in the X direction. The plurality of conductive layers 303 may include, for example, a conductive layer 303A used as part of a source line SL, and a conductive layer 303B used as part of a power line PL. Conductor layers 303A and 303B may be arranged alternately. Conductor layer 303A may be located in… Figure 8 Within the core region CR shown, there is a portion of conductive layer 303 that is connected to conductive layer 21 via via VA. On the other hand, conductive layer 303B does not have a portion that is connected to conductive layer 21 via via VA.

[0134] Multiple pads (PDs) are disposed inside the wall region WR. One pad (PD) is connected to each conductive layer 303B. Power supply voltage, ground voltage, etc., are applied to the pads (PDs) connected to the conductive layers 303B. On the other hand, pads (PDs) that do not overlap with conductive layers 303A and 303B are connected, for example, to interface circuits such as input / output circuit 11 and logic controller 12. At least the pads (PDs) that do not overlap with conductive layers 303A and 303B are disposed overlapping with the core region CR and the peripheral region PR, respectively.

[0135] (8: Planar layout of the solder pad portion PD)

[0136] Figure 10 This is a top view showing an example of the planar layout near the pad portion PD in the storage device 1 of the first embodiment. Figure 10 The diagram shows a portion of the pad PD for connection to the input / output circuit 11 and the logic controller 12, as well as a portion of the core region CR and the peripheral region PR in the storage device 1.

[0137] like Figure 10 As shown, the pad portion PD overlaps with both the core region CR and the peripheral region PR. Furthermore, the pad portion PD overlaps with the dummy region DA within the core region CR, but not with the active region AA. The pad portion PD includes a conductive portion MA, an insulating portion BA, a through-hole TV, and a through-hole VB.

[0138] The conductive portion MA, for example, includes a conductive layer 303. The conductive portion MA is rectangular in shape, for example, when viewed from above. The outer edge of the conductive portion MA corresponds to the outer edge of the solder pad portion PA. The insulating portion BA, for example, includes an insulating member 302. The insulating portion BA is rectangular in shape, for example, when viewed from above, and overlaps with the conductive portion MA. Compared to the outer edge of the conductive portion MA, the outer edge of the insulating portion BA is located further inward.

[0139] Through-holes TV and VB are rectangular in shape when viewed from above and overlap with the conductive portion MA. Through-holes TV and VB are arranged in the Y direction. Compared to the outer edge of the insulating portion BA, the outer edges of each through-hole TV and VB are located further inward. Through-hole TV is contained within both the dummy region DA and the peripheral region PR. Therefore, the boundary between the dummy region DA and the peripheral region PR overlaps with the through-hole TV when viewed from above. A portion of the conductive portion MA is exposed through the through-hole TV. The portion of the conductive portion MA exposed through the through-hole TV corresponds to the pad used to connect the storage device 1 to the memory controller 2. Through-hole VB is contained within the peripheral region PR and extends through a portion of the insulating portion BA. The conductive portion MA is electrically connected via the through-hole VB to a plurality of contacts C3 arranged in a manner overlapping with the through-hole VB.

[0140] (9: Cross-sectional structure of the pad portion PD)

[0141] Figure 11 It is along Figure 10 The cross-sectional view along line XI-XI shows an example of the cross-sectional structure near the solder pad portion PD in the storage device 1 of the first embodiment. For example... Figure 11 As shown, in the storage device 1, the stacked body corresponding to the storage cell array 10, within the dummy region DA, includes either an insulating layer 32 and a conductive layer 22 alternately stacked in the Z direction, or an insulating layer 32 and a sacrificial member SM alternately stacked in the Z direction. The material of the sacrificial member SM is different from that of the insulating layer 32 and the conductive layer 22. The dummy step portion DS, for example, includes an insulating layer 32 and a sacrificial member SM alternately stacked in the Z direction. In other words, the stacked body corresponding to the storage cell array 10, within the dummy region DA, has a stacked body portion formed by the alternating stacking of the insulating layer 32 and the sacrificial member SM in the Z direction. Moreover, in this stacked body portion, the ends of the stacked sacrificial members SM are arranged in a stepped shape. A plurality of dummy pillars DMP penetrate the stacked body corresponding to the storage cell array 10 in the Z direction within the dummy region DA.

[0142] The through-hole TV penetrates the insulating layers 304, 305, and 306. At the bottom of the through-hole TV, a portion of the conductive layer 303 corresponding to the conductive portion MA is exposed. Furthermore, the insulating member 302 corresponding to the insulating portion BA is provided at the same height as the source line SL and is provided in the region overlapping with the through-hole TV in the Z direction. Therefore, conductive layers 21, 211, and 213 are not provided in the region overlapping with the through-hole TV in the Z direction. In other words, the portion of the conductive layer 303 corresponding to the conductive portion MA that is exposed through the through-hole TV does not have a portion overlapping with conductive layers 21, 211, and 213 in the Z direction. In the storage device 1 of the first embodiment, at least the source line SL between the dummy step portion DS and the conductive layer 303 is removed.

[0143] The conductive layer 303 corresponding to the conductive portion MA has a portion disposed along the via VB and connected to a plurality of contacts C3 via the via VB. Furthermore, the conductive layer 303 corresponding to the conductive portion MA is electrically connected to the transistor TR2 on the semiconductor substrate W1 via the plurality of contacts C3. In other words, the pad corresponding to the conductive portion MA is electrically connected via the storage layer 200 to the interface circuitry (e.g., input / output circuitry 11 and logic controller 12) included in the CMOS circuitry disposed on the CMOS layer 100.

[0144] Furthermore, when a step difference is formed between the insulating layer 301 and the insulating member 302, the conductive layer 303 may have a portion disposed along the step difference formed between the insulating layer 301 and the insulating member 302. The through-hole TV may have a portion facing at least the dummy step portion DS in the Z direction, and a portion facing the dummy pillar DMP in the Z direction. The insulating portion BA may be disposed by removing a portion of the dummy pillar DMP, or by removing a portion of the dummy step portion DS.

[0145] In the storage device 1 described above, the storage layer 200 is located within the peripheral region PR and is disposed on the same layer as the source line SL. It has a first sublayer (e.g., conductor layer 211) containing at least a portion of the same material as the source line SL as its main component, and a second sublayer (e.g., conductor layer 213) disposed above the first sublayer by a spacer member (e.g., sacrificial member 212). Furthermore, the via TV does not have any portion overlapping the first sublayer and the second sublayer in the Z direction.

[0146] Additionally, a conductive layer 303 is disposed above the source line SL in the Z direction, includes a portion corresponding to the pad (via TV), and is electrically connected to the CMOS circuit on the semiconductor substrate W1. The conductive layer 303 has a portion overlapping the dummy pillar DMP in the Z direction. This portion of the conductive layer 303 is not separated from the source line SL, but is separated from the insulating member 302 disposed at the same height as the source line SL, and faces the dummy pillar DMP in the Z direction. The pad (via TV) has a portion overlapping the dummy pillar DMP in the Z direction, but does not have a portion overlapping the source line SL in the Z direction. An insulating layer 304 is disposed to cover the upper part of the conductive layer 303. A via TV is disposed in the insulating layer 304 such that the surface of the portion of the conductive layer 303 corresponding to the pad is exposed. The storage layer 200 further includes: an insulating layer 210, disposed around the stack corresponding to the storage cell array 10 in top view; and at least one contact C3, a portion of which is disposed at the same height as the stack and extends in the Z direction within the insulating layer 210 and is electrically connected to the CMOS circuit. The conductive layer 303 also has a portion electrically connected to the at least one contact C3.

[0147] <1-2> Manufacturing Method

[0148] Secondly, regarding the manufacturing method of the storage device 1 in the first embodiment, please refer appropriately. Figure 12 The method for forming the pad portion PD after the semiconductor substrate W1 and semiconductor substrate W2 are described. Figure 12 This is a flowchart illustrating an example of a method for manufacturing the storage device 1 according to the first embodiment. Figures 13-17 These are cross-sectional views illustrating an example of the cross-sectional structure during the manufacturing process of the storage device 1 according to the first embodiment, showing a cross-section including the area near the solder pad portion PD.

[0149] First, semiconductor substrate W2 is removed from the bonded semiconductor substrates W1 and W2 (step ST11). For example, CMP (Chemical Mechanical Polishing) is used to remove semiconductor substrate W2. After removing semiconductor substrate W2, as... Figure 13 As shown, an insulating layer 301 is formed. Alternatively, the insulating layer 301 may be pre-formed between the semiconductor substrate W2 and the conductive layer 21. In this case, the surface of the insulating layer 301 will be exposed through the process of step ST11.

[0150] Next, as Figure 14As shown, the opening BAH is formed (step ST12). Specifically, firstly, a mask is formed to partially open the insulating portion BA as seen from above. Then, through anisotropic etching, the insulating layer 301, conductive layers 21, 211, and 213, and the sacrificial member 202 are removed from the opening of the mask to form the opening BAH. At the opening BAH, the upper parts of multiple dummy pillars DMP and multiple contacts C3 are exposed. The upper parts of each of the multiple dummy pillars DMP and multiple contacts C3 may remain in the opening BAH in a protruding shape.

[0151] Next, as Figure 15 As shown, an insulating member 302 is formed in the opening BAH (step ST13). Specifically, firstly, the insulating member 302 is formed by filling the opening BAH. Then, for example, the insulating member 302 formed outside the opening BAH is removed by CMP treatment. Thus, the insulating member 302 remaining in the opening BAH corresponds to the insulating portion BA. Furthermore, the CMP treatment in step ST13 can also maintain a step difference between the insulating layer 301 and the insulating member 302.

[0152] Next, as Figure 16 As shown, a through-hole VB is formed (step ST14). Specifically, first, a mask is formed to partially open the through-hole VB as seen from above. Then, through anisotropic etching, the insulating component 302 is removed from the opening of the mask to form the through-hole VB. At the through-hole VB, the upper parts of multiple contacts C3 are exposed.

[0153] Next, as Figure 17 As shown, a conductive layer 303 is formed (step ST15). Specifically, for example, firstly, the conductive layer 303 is formed by CVD (Chemical Vapor Deposition) or the like, and a mask covering the portion of the conductive part MA is formed. Then, an anisotropic etching process is performed, thereby processing the conductive layer 303 into the shape of the conductive part MA.

[0154] Next, insulating layers 304, 305, and 306 are formed (step ST16), and a through-hole TV is formed (step ST17). At this point, with... Figure 11 The structure corresponding to the pad PD shown is now complete.

[0155] <1-3> Effects of the first embodiment

[0156] The storage device 1 according to the first embodiment described above can both suppress the degradation of interface speed and reduce chip size. Hereinafter, the effects of the storage device 1 of the first embodiment will be explained using a first comparative example and a second comparative example.

[0157] Figure 18 This is a top view showing an example of the planar layout near the solder pad portion PDy in the storage device 1Y of the first comparative example. (See attached image.) Figure 18 As shown, in the storage device 1Y of the first comparative example, the pad portion PDy is contained in the peripheral region PR and is far from the core region CR. Moreover, unlike the pad portion PD, the pad portion PDy does not have an insulating portion BA.

[0158] Figure 19 It is along Figure 18 The cross-sectional view along line XIX-XIX shows an example of the cross-sectional structure near the solder pad portion PDy in the storage device 1Y of the first comparative example. (See image below.) Figure 19 As shown, in the memory device 1Y, the insulating component 302 is replaced by an insulating layer 307. The insulating layer 307 is disposed on the insulating layer 301 and has a portion disposed along the opening BAH and the via VB. A conductive layer 303 corresponding to the conductive portion MA is disposed along the insulating layer 307 and connected to multiple contacts C3 via the via VB. In the memory device 1Y, the structure corresponding to the source line SL is removed below the via TV. This suppresses parasitic capacitance between the conductive portion MA and the source line SL. On the other hand, depending on the layout of the pad portion PDy, the chip size of the memory device 1Y may increase.

[0159] Figure 20 This is a top view showing an example of the planar layout near the solder pad portion PDz in the storage device 1Z of the second comparative example. (See attached image.) Figure 20 As shown, the pad portion PDz in the storage device 1Z of the second comparative example, like that in the first embodiment, has a portion that overlaps with the dummy region DA. On the other hand, the insulating portion BA in the pad portion PDz is provided in a manner that does not overlap with the through hole TV when viewed from above.

[0160] Figure 21 It is along Figure 20 The cross-sectional view along line XXI-XXI shows an example of the cross-sectional structure near the solder pad portion PDz in the storage device 1Z of the second comparative example. (See image below.) Figure 21 As shown, in the storage device 1Z, the via TV is arranged to overlap with the dummy region DA (e.g., the dummy step portion DS). On the other hand, unlike the first embodiment, the storage device 1Z has a conductive layer 21, or conductive layers 211 and 213, disposed in the portion facing the via TV in the Z direction. Therefore, in the storage device 1Z, compared to the first comparative example, the chip size can be reduced, but the parasitic capacitance between the conductive portion MA and the source line SL may increase. Therefore, in the second comparative example, compared to the first comparative example, there is a risk of interface speed degradation.

[0161] In contrast, the storage device 1 of the first embodiment has a structure in which the source line SL in the region where the end of the storage cell array 10 (dummy region DA) overlaps with the pad portion PD is removed, and an insulating member 302 is embedded in this region. Specifically, in the storage device 1 of the first embodiment, the storage layer 200 includes: a stacked body, in the effective region AA, comprising an insulating layer 32 and a conductive layer 22 alternately stacked in the Z direction, and in the dummy region DA, comprising a sacrificial member SM disposed on the same layer as the conductive layer 22; a plurality of storage pillars MP and a plurality of dummy pillars DMP penetrating the stacked body; and a source line SL (conductive layer 21) connected to the plurality of storage pillars MP above the stacked body. Moreover, the pad (through-hole TV) corresponding to a portion of the conductive portion MA exposed at the via TV has a portion overlapping the sacrificial member SM in the Z direction, but does not have a portion overlapping the source line SL in the Z direction.

[0162] Therefore, in the memory device 1 of the first embodiment, the parasitic capacitance between the conductive portion MA and the source line SL, i.e., the parasitic capacitance of the solder pad, can be reduced. Furthermore, regarding the chip size of the memory device 1 of the first embodiment, since the solder pad portion PD and the dummy region DA overlap in the Z direction, it can be reduced in size, similar to the second comparative example. Thus, the memory device 1 of the first embodiment can both suppress interface speed degradation and reduce chip size.

[0163] <2> Second Implementation Method

[0164] The storage device 1A of the second embodiment has a structure in which, instead of forming a through hole VB as described in the first embodiment, a contact VBP is formed through the insulating member 302, and the conductive layer 303 and the contact C3 are electrically connected via the contact VBP. The details of the storage device 1A of the second embodiment will be described below.

[0165] <2-1> Composition

[0166] The storage device 1A of the second embodiment has the same configuration as the storage device 1 of the first embodiment, except for the structure of the solder pad portion PD. Hereinafter, the planar layout and cross-sectional structure of the solder pad portion PTa in the storage device 1A of the second embodiment will be described.

[0167] <2-1-1> Planar layout of the pad portion PDA

[0168] Figure 22 This is a top view showing an example of the planar layout near the pad portion PDa in the storage device 1A of the second embodiment. Figure 22The diagram shows a portion of the pad PDa for connection to the input / output circuit 11 and the logic controller 12, as well as a portion of the core region CR and the peripheral region PR in the storage device 1A.

[0169] like Figure 22 As shown, the pad portion PDa overlaps with both the core region CR and the peripheral region PR. Furthermore, the pad portion PDa overlaps with the dummy region DA within the core region CR, but not with the active region AA. The pad portion PDa includes a conductive portion MA, an insulating portion BA, a through-hole TV, and multiple contacts VBP.

[0170] The conductive portion MA, insulating portion BA, and through-hole TV in the pad portion PDA are each configured the same as in the pad portion PD of the first embodiment. Multiple contacts VBP are each included in the peripheral region PR and are disposed through a portion of the insulating portion BA. The region where the multiple contacts VBP are formed is adjacent to the through-hole TV in the Y direction and is arranged in a manner that does not overlap with the through-hole TV. The multiple contacts VBP are arranged, for example, in a grid pattern. The multiple contacts VBP overlap with multiple contacts C3. The overlapping set of contacts VBP and contacts C3 are electrically connected.

[0171] <2-1-2> Cross-sectional structure of the pad portion PDA

[0172] Figure 23 It is along Figure 22 The cross-sectional view along lines XXIII-XXIII shows an example of the cross-sectional structure near the solder pad portion PDa in the storage device 1A of the second embodiment. For example... Figure 23 As shown, the pad portion PDa has the features used in the first embodiment. Figure 11 The pad portion PD described herein omits the through-hole VB and adds multiple contacts VBP. Each of the multiple contacts VBP is disposed through an insulating component 302 corresponding to the insulating portion BA. The bottom of each of the multiple contacts VBP is connected to the upper part of a contact C3 that overlaps in the Z direction. In the pad portion PDa, the upper surfaces of the insulating component 302, the upper surfaces of the contacts VBP, and the upper surface of the insulating layer 301 are aligned.

[0173] A conductive layer 303 corresponding to the conductive portion MA is provided on the upper surface of the planarized insulating component 302 and the contact VBP. In the second embodiment, the conductive portion MA does not have a step difference at the interface between the insulating layer 301 and the insulating component 302. The other configurations of the pad portion PDa are the same as those of the pad portion PD in the first embodiment.

[0174] <2-2> Manufacturing Method

[0175] Secondly, regarding the manufacturing method of the storage device 1A in the second embodiment, please refer appropriately. Figure 24The method for forming the pad portion PDa after the semiconductor substrate W1 and the semiconductor substrate W2 are described. Figure 24 This is a flowchart illustrating an example of a method for manufacturing the storage device 1A according to the second embodiment. Figures 25-27 These are cross-sectional views illustrating an example of the cross-sectional structure during the manufacturing process of the storage device 1A according to the second embodiment, showing a section including the area near the solder pad portion PDa.

[0176] First, similar to the first embodiment, the semiconductor substrate W2 is removed (step ST11), an opening BAH is formed (step ST12), and an insulating member 302 is formed in the opening BAH (step ST13).

[0177] Next, as Figure 25 As shown, multiple holes VBH are formed (step ST21). Specifically, first, a mask with openings overlapping each contact C3 in top view is formed. Then, an anisotropic etching process is performed, thereby removing the insulating component 302 at the opening of the mask to form multiple holes VBH. At the bottom of each hole VBH, the upper part of the corresponding contact C3 is exposed.

[0178] Next, as Figure 26 As shown, conductive components 310 are formed in each VBH (step ST22). Specifically, firstly, conductive components 310 are formed by filling each VBH using methods such as CVD. Then, for example, by CMP processing, the conductive components 310 formed on the outside of each VBH are removed to form multiple contacts VBP. Through this CMP processing, the upper surface of the conductive components 310 (contacts VBP) in each VBH, the upper surface of the insulating component 302, and the upper surface of the insulating layer 301 are aligned.

[0179] Next, as Figure 27 As shown, a conductive layer 303 is formed (step ST23). Specifically, for example, first, a conductive layer 303 is formed, and a mask covering the portion of the conductive part MA is formed. Then, an anisotropic etching process is performed, thereby processing the conductive layer 303 into the shape of the conductive part MA.

[0180] Subsequently, similarly to the first embodiment, insulating layers 304, 305, and 306 are formed (step ST16), and a through-hole TV is formed (step ST17). Thus, with... Figure 23 The structure corresponding to the pad portion PDa shown is now complete.

[0181] <2-3> Effects of the second implementation method

[0182] The memory device 1A of the second embodiment, like that of the first embodiment, has a structure in which the structure corresponding to the source line SL within the dummy region DA is removed, and the dummy region DA overlaps with the pad portion PDa in the Z direction. Therefore, the memory device 1A of the second embodiment, like that of the first embodiment, can reduce the parasitic capacitance of the pad, thereby suppressing interface speed degradation and reducing chip size.

[0183] Furthermore, in the second embodiment of the storage device 1A, the connection between the conductive portion MA and the contact C3 is not achieved using a through-hole VB as in the first embodiment, but rather using a contact VBP. Moreover, in the storage device 1A, when the contact VBP is formed, the upper surfaces of both the insulating portion BA and the contact VBP are planarized. As a result, the second embodiment of the storage device 1A can suppress defects caused by the step difference in the conductive portion MA formed along the through-hole VB as in the first embodiment. Therefore, compared to the first embodiment, the second embodiment of the storage device 1A can improve yield.

[0184] <3> Third Implementation Method

[0185] The storage device 1B of the third embodiment has a structure in which a conductive member 320 is formed to cover the upper part of the plurality of contacts C3 described in the first embodiment, and the conductive layer 303 is electrically connected to each contact C3 via the conductive member 320. Hereinafter, details of the storage device 1B of the third embodiment will be described.

[0186] <3-1> Composition

[0187] The storage device 1B of the third embodiment has the same configuration as the storage device 1 of the first embodiment, except for the structure of the solder pad portion PD. Hereinafter, the planar layout and cross-sectional structure of the solder pad portion PDb in the storage device 1B of the third embodiment will be described.

[0188] <3-1-1> Planar Layout of the Pad Section PDb

[0189] Figure 28 This is a top view showing an example of the planar layout near the pad portion PDb in the storage device 1B of the third embodiment. Figure 28 The diagram shows a portion of the solder pad PDb for connection to the input / output circuit 11 and the logic controller 12, as well as a portion of the core region CR and the peripheral region PR in the storage device 1B.

[0190] like Figure 28As shown, the pad portion PDb overlaps with both the core region CR and the peripheral region PR. Furthermore, the pad portion PDb overlaps with the dummy region DA within the core region CR, but not with the active region AA. The pad portion PDb includes a conductive portion MA, an insulating portion BA, a through-hole TV, a conductive portion ZB, and multiple through-holes VBa.

[0191] The conductive portion MA, insulating portion BA, and through-hole TV in the pad portion PDb are each configured the same as in the pad portion PD of the first embodiment. The conductive portion ZB is contained in the peripheral region PR and is arranged overlapping the conductive portion MA and insulating portion BA, respectively. Furthermore, the conductive portion ZB is adjacent to the through-hole TV in the Y direction, but is arranged in a manner that does not overlap with the through-hole TV. The conductive portion ZB is connected to a plurality of contacts C3 electrically connected to the conductive portion MA. A plurality of through-holes VBa are arranged overlapping the conductive portion ZB in top view and are provided to penetrate a portion of the insulating portion BA. The plurality of through-holes VBa are, for example, arranged in a grid pattern. The conductive portion MA is electrically connected to the conductive portion ZB via the plurality of through-holes VBa. That is, the conductive portion MA is electrically connected to the plurality of contacts C3 via the conductive portion ZB.

[0192] <3-1-2> Cross-sectional structure of the PDb pad

[0193] Figure 29 It is along Figure 28 The cross-sectional view along line XXIX-XXIX shows an example of the cross-sectional structure near the solder pad portion PDb in the storage device 1B of the third embodiment. For example... Figure 29 As shown, the solder pad portion PDb has the features used in the first embodiment. Figure 11 Within the pad portion PD described, the through-hole VB is replaced with multiple through-holes VBa, and a conductive portion ZB is added. The conductive member 320 corresponding to the conductive portion ZB is provided to cover the upper part of the multiple contacts C3. Furthermore, the upper part of the conductive member 320 has a portion covered by an insulating member 302 corresponding to the insulating portion BA. The multiple through-holes VBa penetrate the insulating member 302. Moreover, the bottom of each of the multiple through-holes VBa reaches the conductive member 320.

[0194] A conductive layer 303 corresponding to the conductive portion MA is disposed on the insulating member 302, and has a portion disposed along a plurality of through holes VBa. Furthermore, the conductive layer 303 is embedded in the plurality of through holes VBa and is connected to the conductive member 320 at the bottom of the through holes VBa. Additionally, the conductive layer 303 is electrically connected to a plurality of contacts C3 via the conductive member 320, and is electrically connected to the transistor TR2 via the plurality of contacts C3. The conductive layer 303 may also have a concave portion at the top of the through holes VBa. The other configurations of the pad portion PDb are the same as those of the pad portion PD in the first embodiment.

[0195] <3-2> Manufacturing Method

[0196] Secondly, regarding the manufacturing method of the storage device 1B in the third embodiment, please refer appropriately. Figure 30 The method for forming the pad portion PDb after the semiconductor substrate W1 and semiconductor substrate W2 are described. Figure 30 This is a flowchart illustrating an example of a method for manufacturing the storage device 1B according to the third embodiment. Figures 31-34 These are cross-sectional views illustrating an example of the cross-sectional structure during the manufacturing process of the storage device 1B according to the third embodiment, showing a cross-section including the area near the solder pad portion PDb.

[0197] First, similar to the first embodiment, the semiconductor substrate W2 is removed (step ST11) to form the opening BAH (step ST12).

[0198] Next, as Figure 31 As shown, a conductive component 320 is formed in a portion of the opening BAH (step ST31). Specifically, for example, firstly, the conductive component 320 is formed by CVD or the like, and a mask covering the portion of the conductive portion ZB is formed. Then, an anisotropic etching process is performed, thereby processing the conductive component 320 into the shape of the conductive portion ZB.

[0199] Next, as Figure 32 As shown, an insulating member 302 is formed in the opening BAH (step ST32). Specifically, firstly, the insulating member 302 is formed by filling the opening BAH. Then, for example, the insulating member 302 formed outside the opening BAH is removed by CMP treatment. The insulating member 302 remaining in the opening BAH corresponds to the insulating portion BA. Alternatively, the CMP treatment in step ST32 can also be used to maintain a step difference between the insulating layer 301 and the insulating member 302.

[0200] Next, as Figure 33 As shown, a through-hole VBa is formed (step ST33). Specifically, first, a mask is formed to partially open the through-hole VBa as seen from above. Then, through anisotropic etching, the insulating component 302 is removed from the opening of the mask to form the through-hole VBa. At the through-hole VBa, the upper part of the conductive portion ZB is exposed.

[0201] Next, as Figure 34 As shown, a conductive layer 303 is formed (step ST34). Specifically, for example, firstly, the conductive layer 303 is formed by embedding it into a via VBa using CVD or the like, and a mask covering the portion of the conductive part MA is formed. Then, an anisotropic etching process is performed, thereby processing the conductive layer 303 into the shape of the conductive part MA.

[0202] Subsequently, similarly to the first embodiment, insulating layers 304, 305, and 306 are formed (step ST16), and a through-hole TV is formed (step ST17). Thus, with... Figure 29 The structure corresponding to the pad portion PDb shown is now complete.

[0203] <3-3> Effects of the third implementation method

[0204] The storage device 1B of the third embodiment, like that of the first embodiment, has a structure in which the structure corresponding to the source line SL within the dummy region DA is removed, and the dummy region DA overlaps with the pad portion PDb in the Z direction. Therefore, the storage device 1B of the third embodiment, like that of the first embodiment, can reduce the parasitic capacitance of the pads, thereby suppressing interface speed degradation and reducing chip size.

[0205] Furthermore, in the storage device 1B of the third embodiment, the conductive part MA and the contact C3 are connected via the conductive part ZB. Therefore, compared to the case where the conductive layer 303 is directly connected to the protrusion of the contact C3, the electrical connection between the conductive layer 303 and the contact C3 can be made more reliable. Thus, compared to the first embodiment, the storage device 1B of the third embodiment can improve yield.

[0206] <4> Fourth Implementation Method

[0207] The storage device 1C of the fourth embodiment has a structure in which the region where the contacts VBP and C3 are formed overlaps with the region where the through hole TV is formed in the Z direction, as in the storage device 1A of the second embodiment. Details of the storage device 1C of the fourth embodiment will be described below.

[0208] <4-1> Composition

[0209] The storage device 1C of the fourth embodiment has the same configuration as the storage device 1A of the second embodiment, except for the structure of the solder pad portion PDa. Hereinafter, the planar layout and cross-sectional structure of the solder pad portion PDc in the storage device 1C of the fourth embodiment will be described.

[0210] <4-1-1> Planar Layout of the Pad Part PDc

[0211] Figure 35 This is a top view showing an example of the planar layout near the pad portion PDc in the storage device 1C of the fourth embodiment. Figure 35 The diagram shows a portion of the pad PDc for connection to the input / output circuit 11 and the logic controller 12, as well as a portion of the core region CR and the peripheral region PR in the storage device 1C.

[0212] like Figure 35As shown, the pad portion PDc overlaps with both the core region CR and the peripheral region PR. Furthermore, the pad portion PDc overlaps with the dummy region DA within the core region CR, but not with the active region AA. The pad portion PDc includes a conductive portion MA, an insulating portion BA, a through-hole TV, and multiple contacts VBP.

[0213] The conductive portion MA, insulating portion BA, and through-hole TV in the pad portion PDc are each configured the same as those in the pad portion PDa of the second embodiment. Multiple contacts VBP are each included in the peripheral region PR and are disposed through a portion of the insulating portion BA. Furthermore, the region where the multiple contacts VBP are formed overlaps with the through-hole TV when viewed from above. The multiple contacts VBP overlap with multiple contacts C3. A set of overlapping contacts VBP and contacts C3 are electrically connected.

[0214] <4-1-2> Cross-sectional structure of the PDc pad

[0215] Figure 36 It is along Figure 35 The cross-sectional view along lines XXXVI-XXXVI shows an example of the cross-sectional structure near the solder pad portion PDc in the storage device 1C of the fourth embodiment. For example... Figure 36 As shown, the pad portion PDc has the features used in the second embodiment. Figure 23 The pad portion PDa described herein has a configuration in which multiple contacts VBP and through-holes TV are arranged overlapping in the Z direction. Therefore, compared to the pad portion PDa of the second embodiment, the pad portion PDc of the fourth embodiment can be designed to be smaller. The other configurations of the pad portion PDc are the same as those of the pad portion PDa of the second embodiment.

[0216] <4-2> Manufacturing Method

[0217] The manufacturing method of the storage device 1C in the fourth embodiment is equivalent to: using Figures 24-27 In the manufacturing method of the storage device 1A of the second embodiment described herein, the arrangement is modified such that the regions forming the contacts VBP and C3 overlap with the region forming the through hole TV in the Z direction.

[0218] <4-3> Effects of the fourth embodiment

[0219] The memory device 1C of the fourth embodiment, like that of the first embodiment, has a structure in which the structure corresponding to the source line SL within the dummy region DA is removed, and the dummy region DA overlaps with the pad portion PDc in the Z direction. Therefore, the memory device 1C of the fourth embodiment, like that of the first embodiment, can reduce the parasitic capacitance of the pads, thereby suppressing interface speed degradation and reducing chip size.

[0220] Furthermore, in the storage device 1C of the fourth embodiment, the through-hole TV and the plurality of contacts VBP are arranged overlapping in the Z direction. Therefore, compared to the storage device 1A of the second embodiment, the storage device 1C of the fourth embodiment can reduce chip area. As a result, compared to the storage device 1A of the second embodiment, the storage device 1C of the fourth embodiment can reduce manufacturing costs.

[0221] <5> Fifth Implementation Method

[0222] The storage device 1D of the fifth embodiment has a structure in which the region where a plurality of contacts C3 and conductive members 320 are formed overlaps with the region where a through hole TV is formed in the third embodiment of the storage device 1B in the Z direction. Details of the storage device 1D of the fifth embodiment will be described below.

[0223] <5-1> Composition

[0224] The storage device 1D of the fifth embodiment has the same configuration as the storage device 1B of the third embodiment, except for the structure of the solder pad portion PDb. Hereinafter, the planar layout and cross-sectional structure of the solder pad portion PDd in the storage device 1D of the fifth embodiment will be described.

[0225] <5-1-1> Planar layout of the solder pad PDd

[0226] Figure 37 This is a top view showing an example of the planar layout near the pad portion PDd in the storage device 1D of the fifth embodiment. Figure 37 The diagram shows a portion of the pad PDd for connection to the input / output circuit 11 and the logic controller 12, as well as a portion of the core region CR and the peripheral region PR in the storage device 1D.

[0227] like Figure 37 As shown, the pad portion PDd overlaps with both the core region CR and the peripheral region PR. Furthermore, the pad portion PDd overlaps with the dummy region DA within the core region CR, but not with the active region AA. The pad portion PDd includes a conductive portion MA, an insulating portion BA, a through-hole TV, a conductive portion ZB, and multiple through-holes VBa.

[0228] The conductive portion MA, insulating portion BA, and through-hole TV in the pad portion PDd are each configured the same as those in the pad portion PDb of the third embodiment. The conductive portion ZB is contained in the peripheral region PR and is disposed overlapping with both the conductive portion MA and the insulating portion BA. Furthermore, the conductive portion ZB overlaps with the through-hole TV when viewed from above. The conductive portion ZB is connected to multiple contacts C3 electrically connected to the conductive portion MA. Multiple through-holes VBa are disposed overlapping with the conductive portion ZB when viewed from above and are provided to penetrate a portion of the insulating portion BA. The conductive portion MA is electrically connected to the conductive portion ZB via the multiple through-holes VBa. That is, the conductive portion MA is electrically connected to the multiple contacts C3 via the conductive portion ZB.

[0229] <5-1-2> Cross-sectional structure of the PDd pad

[0230] Figure 38 It is along Figure 37 The cross-sectional view along lines XXXVIII-XXXVIII shows an example of the cross-sectional structure near the solder pad portion PDd in the storage device 1D of the fifth embodiment. For example... Figure 38 As shown, the solder pad portion PDd has the features used in the third embodiment. Figure 29 The conductive portion ZB and the through-hole TV in the described pad portion PDb are arranged to overlap in the Z direction. Therefore, the pad portion PDd in the fifth embodiment can be designed to be smaller than the pad portion PDb in the third embodiment. The other configurations of the pad portion PDd are the same as those of the pad portion PDb in the third embodiment.

[0231] <5-2> Manufacturing Method

[0232] The manufacturing method of the storage device 1D in the fifth embodiment is equivalent to: using Figures 30-34 In the manufacturing method of the storage device 1B of the third embodiment described herein, the arrangement is modified such that the regions forming the conductive part ZB and the contact C3 overlap with the region forming the through hole TV in the Z direction.

[0233] <5-3> Effects of the fifth embodiment

[0234] The storage device 1D of the fifth embodiment, like that of the first embodiment, has a structure in which the structure corresponding to the source line SL within the dummy region DA is removed, and the dummy region DA overlaps with the pad portion PDd in the Z direction. Therefore, the storage device 1D of the fifth embodiment, like that of the first embodiment, can reduce the parasitic capacitance of the pads, thereby suppressing interface speed degradation and reducing chip size.

[0235] Furthermore, in the storage device 1D of the fifth embodiment, the through-hole TV and the conductive portion ZB are arranged overlapping in the Z direction. Therefore, compared to the storage device 1B of the third embodiment, the storage device 1D of the fifth embodiment can reduce chip area. As a result, compared to the storage device 1B of the third embodiment, the storage device 1D of the fifth embodiment can reduce manufacturing costs.

[0236] <6> 6th Implementation Method

[0237] The sixth embodiment relates to a storage device that uses a source line SL with a structure different from that of the storage device 1E of the first embodiment. Details of the storage device 1E of the sixth embodiment will be described below.

[0238] <6-1> Composition

[0239] The storage device 1E of the sixth embodiment has the same configuration as the storage device 1 of the first embodiment, except for the structure of the source line SL. Hereinafter, the cross-sectional structure of the storage cell array 10 and the planar layout and cross-sectional structure of the pad portion PD in the storage device 1E of the sixth embodiment will be described.

[0240] <6-1-1> Cross-sectional structure of memory cell array 10

[0241] Figure 39 This is a cross-sectional view showing an example of the cross-sectional structure of the storage cell array 10 included in the storage device 1E of the sixth embodiment. Figure 39 An example of the structure of a memory cell array 10 formed on a semiconductor substrate W2 before being bonded to a semiconductor substrate W1 is shown, and coordinate axes with the semiconductor substrate W2 as a reference are indicated. Figure 39 The area shown corresponds to that described in the first embodiment. Figure 6 The same area. For example... Figure 39 As shown, in the storage device 1E, the storage cell array 10 formed on the semiconductor substrate W2 before bonding with the semiconductor W1 has, for example, a structure in the storage cell array 10 of the first embodiment, in which the conductor layer 21 is replaced by the semiconductor layer 214, component 215 and semiconductor layer 216.

[0242] Semiconductor layer 216 is disposed on semiconductor substrate W2, for example, with insulating layer 301 in between. Component 215 is disposed on semiconductor layer 216. Semiconductor layer 214 is disposed on component 215. Insulating layer 31 is disposed on semiconductor layer 214. Semiconductor layers 214 and 216 are, for example, amorphous silicon. Semiconductor layer 216 is used, for example, as an etch stop layer when forming memory pillars MP and slits SLT. For example, memory pillars MP and slits SLT penetrate semiconductor layer 214. Moreover, the bottom of each memory pillar MP and slit SLT reaches semiconductor layer 216. Other structures of the memory cell array 10 of the sixth embodiment are the same as those of the memory cell array 10 of the first embodiment.

[0243] <6-1-2> Planar Layout of the Pad Section (PD)

[0244] Figure 40 This is a top view showing an example of the planar layout near the pad portion PD in the storage device 1E of the sixth embodiment. Figure 40 The diagram shows a portion of the pad PD for connection to the input / output circuit 11 and the logic controller 12, as well as a portion of the core region CR and the peripheral region PR in the storage device 1E.

[0245] like Figure 40 As shown, the storage device 1E has a configuration in the storage device 1 of the first embodiment, in which the effective region AA and the dummy region DA of the core region CR are replaced with the effective region AAa and the dummy region DAa, respectively. Within the effective region AAa and the dummy region DAa, the structure of the portion corresponding to the source line SL differs from that of the effective region AA and the dummy region DA, respectively. The detailed structure of the source line SL in the storage device 1E will be described below. The pad portion PD of the sixth embodiment overlaps with both the core region CR and the peripheral region PR. Furthermore, the pad portion PD of the sixth embodiment has a portion that overlaps with the dummy region DAa in the core region CR, but does not have a portion that overlaps with the effective region AAa. The pad portion PD of the sixth embodiment, like the pad portion PD of the first embodiment, includes a conductive portion MA, an insulating portion BA, a through-hole TV, and a through-hole VB.

[0246] <6-1-3> Cross-sectional structure near the pad PD

[0247] Figure 41 It is along Figure 40 The cross-sectional view along the XLI-XLI line shows an example of the cross-sectional structure near the pad portion PD in the storage device 1E of the sixth embodiment. Figure 41The diagram shows the effective region AAa, the dummy region DAa, and a portion of the peripheral region PR after semiconductor substrates W1 and W2 are bonded together to form wiring layer 300, and is marked with coordinate axes based on semiconductor substrate W1. Furthermore, in the memory device 1E, the structure within the wall region WR is similar to that of the peripheral region PR, therefore, a description of the structure within the wall region WR is omitted.

[0248] like Figure 41 As shown, in the storage device 1E, the stacked film 42 on the upper part of the storage column MP is removed. Additionally, the stacked film 42 on the upper part of the dummy column DMP is removed. In the effective region AAa, the dummy region DA, and the peripheral region PRa, a semiconductor layer 214 is provided on the stacked body or insulating layer 210 corresponding to the storage cell array 10. On the semiconductor layer 214, in the portion on the peripheral region PR and the peripheral region PR side of the dummy region DAa, a component 215, a semiconductor layer 216, and an insulating layer 310 are sequentially provided. Furthermore, on the semiconductor layer 214, in the portion on the effective region AAa and the dummy region DAa side, a semiconductor layer 217, a conductive layer 218, and an insulating layer 330 are sequentially provided.

[0249] Semiconductor layers 214, 216, and 217 are, for example, polycrystalline silicon. Semiconductor layer 217 is doped with impurities. Therefore, semiconductor layer 217 functions as a conductor. When impurities are doped into semiconductor layer 217, the impurities may diffuse into semiconductor layer 214 within the effective region AAa. Therefore, semiconductor layer 214 within the effective region AAa may contain impurities and function as a conductor. On the other hand, when impurities are doped into semiconductor layer 217, the peripheral region PR is excluded from the region targeted for impurity doping. Therefore, semiconductor layer 214 within the peripheral region PR does not contain such impurities.

[0250] Semiconductor layer 217 is provided in such a way that it covers the upper part of semiconductor layer 41 of each memory pillar MP, the upper part of semiconductor layer 41 (not shown) of each dummy pillar DMP, and the upper part of slit SLT. Therefore, conductor layer 217 and conductor layer 218 each have a portion provided along the upper part of the memory pillar MP, dummy pillar DMP, and slit SLT. Furthermore, semiconductor layer 217 is electrically connected to semiconductor layer 41 of each memory pillar MP. In memory device 1E, the group of semiconductor layers 214 and 217 and conductor layer 218 functions as part of source line SL. The upper surface of insulating layer 330 is aligned, for example, with the upper surface of insulating layer 301 within peripheral region PR.

[0251] The insulating member 302 of the storage device 1E is disposed within a portion of the peripheral region PR, penetrating the insulating layer 301, the semiconductor layer 216, the component 215, and the semiconductor layer 214. Additionally, the insulating member 302 is disposed within a portion of the dummy region DAa, penetrating the insulating layer 330, the conductive layer 218, the semiconductor layer 217, and the semiconductor layer 214. The upper surface of the insulating member 302 can be aligned with the upper surfaces of the insulating layers 301 and 330, or a step difference can be formed between the insulating member 302 and the insulating layers 301 and 330. The lower surface of the insulating member 302 can be aligned with the lower surface of the semiconductor layer 214, or it can be located at the height between the lower surface of the semiconductor layer 214 and the conductive layer 26.

[0252] The conductive layer 303 of the storage device 1E is disposed on the insulating layers 301 and 330. Furthermore, the conductive layer 303 may have a portion disposed on the insulating member 302 within the dummy region DAa and the peripheral region PR. Insulating layers 304, 305, and 306 are sequentially disposed on the insulating layers 301 and 330 and the conductive layer 303.

[0253] The pad portion PD in the sixth embodiment has the same characteristics as that used in the first embodiment. Figure 11 The pad portion PD described herein has the same configuration. In the pad portion PD of the sixth embodiment, semiconductor layers 214, 216, and 217, and conductive layer 218 are not provided in the region overlapping with via TV in the Z direction. That is, in the storage device 1E, the portion of the conductive layer 303 corresponding to the conductive portion MA that is exposed through via TV does not have a portion overlapping with semiconductor layers 214, 216, and 217, and conductive layer 218 in the Z direction. The other configurations of the storage device 1E of the sixth embodiment are the same as those of the storage device 1 of the first embodiment.

[0254] <6-2> Manufacturing Method

[0255] Secondly, regarding the manufacturing method of the storage device 1E in the sixth embodiment, please refer appropriately. Figure 42 The method for forming the source line SL and the pad portion PD after the semiconductor substrates W1 and W2 are joined is described. Figure 42 This is a flowchart illustrating an example of a method for manufacturing the storage device 1E according to the sixth embodiment. Figure 43 and Figure 44 These are cross-sectional views illustrating an example of the cross-sectional structure during the manufacturing process of the storage device 1E according to the sixth embodiment, showing a cross-section including the area near the solder pad portion PD.

[0256] First, similar to the first embodiment, the semiconductor substrate W2 is removed (step ST11).

[0257] Next, as Figure 43 As shown, the insulating layer 301, semiconductor layer 216, component 215, and a portion of the multilayer film 42 within the effective region AAa are removed (step ST61). Specifically, first, a mask is formed to partially open the effective region AAa. Then, through anisotropic etching, the insulating layer 301, semiconductor layer 216, and component 215 are removed at the opening of the mask. At this time, component 215 and semiconductor layer 214 can be used as etching stop layers, respectively. Afterward, for example, through wet etching, the multilayer film 42 disposed above the semiconductor layer 214 within the effective region AAa is selectively removed. Furthermore, in step ST61, depending on the shape of the mask used, a portion of the insulating layer 301, semiconductor layer 216, component 215, and multilayer film 42 within the dummy region DAa may also be removed.

[0258] Next, a semiconductor layer 217 and a conductive layer 218 are formed (step ST62). Specifically, first, amorphous silicon corresponding to semiconductor layer 217 is formed on the exposed surface of semiconductor layer 214. Then, impurities are diffused into semiconductor layers 214 and 217 through impurity introduction toward the formed amorphous silicon and subsequent heat treatment, and the formed amorphous silicon is modified into polycrystalline silicon. Next, a conductive layer 218 is formed on semiconductor layer 217. Conductive layer 218 includes, for example, at least one of tungsten, aluminum, titanium, and titanium nitride. Furthermore, in step ST62, semiconductor layers 214 and 216 are modified from amorphous silicon to polycrystalline silicon during the heat treatment that modifies semiconductor layer 217 into polycrystalline silicon.

[0259] After that, as Figure 44 As shown, an insulating layer 330 is formed (step ST63). In step ST63, for example, firstly, an insulating layer 330 is formed on the conductive layer 218 and the insulating layer 301. Then, the upper surfaces of the insulating layers 330 and 301 are planarized by CMP processing or the like. In this example, the insulating layer 330 formed on the insulating layer 301 is removed. Alternatively, the insulating layer 330 may remain on the upper surface of the insulating layer 301.

[0260] Then, similarly to the first embodiment, steps ST12 to ST17 are executed sequentially. Thus, with... Figure 41 The structures corresponding to the source line SL and the solder pad portion PD shown are respectively completed. Thus, the manufacturing method of the storage device 1E according to the sixth embodiment has the capability to... Figure 12 In the manufacturing method of the storage device 1 of the first embodiment shown, the process of inserting steps ST61, ST62 and ST63 between steps ST11 and ST12 is configured.

[0261] <6-3> Effects of the 6th Embodiment

[0262] The memory device 1E of the sixth embodiment has a structure in which the structure corresponding to the source line SL within the dummy region DAa is removed, and the dummy region DAa overlaps with the pad portion PD in the Z direction. Therefore, like the memory device 1E of the first embodiment, the memory device 1E of the sixth embodiment can reduce the parasitic capacitance of the pads, thereby suppressing interface speed degradation and reducing chip size.

[0263] <7> 7th Implementation Method

[0264] The storage device 1F of the seventh embodiment has a structure that combines the pad portion PDa described in the second embodiment with the source line SL described in the sixth embodiment. Hereinafter, details of the storage device 1F of the seventh embodiment will be described.

[0265] <7-1> Composition

[0266] The storage device 1F of the seventh embodiment has the same configuration as the storage device 1A of the second embodiment, except for the structure of the source line SL. Hereinafter, the planar layout and cross-sectional structure of the pad portion PDa in the storage device 1F of the seventh embodiment will be described.

[0267] <7-1-1> Planar layout of the pad portion PDA

[0268] Figure 45 This is a top view showing an example of the planar layout near the pad portion PDa in the storage device 1F of the seventh embodiment. Figure 45 The diagram shows a portion of the pad PDa for connection to the input / output circuit 11 and the logic controller 12, as well as a portion of the core region CR and the peripheral region PR in the storage device 1F.

[0269] like Figure 45 As shown, the storage device 1F has the configuration of the storage device 1A in the second embodiment, where the effective area AA and the dummy area DA of the core region CR are replaced with the effective area AAa and the dummy area DAa of the sixth embodiment, respectively. The pad portion PDa of the seventh embodiment overlaps with both the core region CR and the peripheral region PR. Furthermore, the pad portion PDa of the seventh embodiment has a portion that overlaps with the dummy area DAa in the core region CR, but does not have a portion that overlaps with the effective area AAa. Like the pad portion PDa of the second embodiment, the pad portion PDa of the seventh embodiment includes a conductive portion MA, an insulating portion BA, a through-hole TV, and multiple contacts VBP.

[0270] <7-1-2> Cross-sectional structure of the pad portion PDA

[0271] Figure 46 It is along Figure 45 The cross-sectional view along lines XLVI-XLVI shows an example of the cross-sectional structure near the solder pad portion PDa in the storage device 1F of the seventh embodiment. For example... Figure 46 As shown, the storage device 1F has the features used in the sixth embodiment. Figure 41 The source line SL within the effective region AAa and the dummy region DAa described herein is the same as that used in the second embodiment. Figure 23 The structure of the solder pad PDa assembly is described. Other configurations of the storage device 1F in the seventh embodiment are the same as those of the storage device 1A in the second embodiment.

[0272] <7-2> Manufacturing Method

[0273] The manufacturing method of the storage device 1F in the seventh embodiment is equivalent to: Figure 24 In the manufacturing method of the storage device 1A of the second embodiment shown, an insertion is made between steps ST11 and ST12. Figure 42 The processes shown are ST61, ST62, and ST63. That is, in the manufacturing method of the memory device 1F of the seventh embodiment, similarly to the sixth embodiment, after removing the semiconductor substrate W2, the source line SL is formed, and then, similarly to the second embodiment, a structure corresponding to the pad portion PDa is formed.

[0274] <7-3> Effects of the 7th Embodiment

[0275] The memory device 1F of the seventh embodiment has a structure in the dummy region DAa corresponding to the source line SL removed, and similarly to the sixth embodiment, the dummy region DAa overlaps with the pad portion PDa in the Z direction. Therefore, the memory device 1F of the seventh embodiment, like the sixth embodiment, can reduce the parasitic capacitance of the pad, thus suppressing interface speed degradation and reducing chip size. Furthermore, the memory device 1F of the seventh embodiment can suppress defects caused by the step difference in the conductive portion MA, and similarly to the second embodiment, can improve yield.

[0276] <8> 8th Implementation Method

[0277] The storage device 1G of the eighth embodiment has a structure that combines the pad portion PDb described in the third embodiment with the source line SL described in the sixth embodiment. Hereinafter, details of the storage device 1G of the eighth embodiment will be described.

[0278] <8-1> Composition

[0279] The storage device 1G of the eighth embodiment has the same configuration as the storage device 1B of the third embodiment, except for the structure of the source line SL. Hereinafter, the planar layout and cross-sectional structure of the pad portion PDb in the storage device 1G of the eighth embodiment will be described.

[0280] <8-1-1> Planar Layout of the Pad Section PDb

[0281] Figure 47 This is a top view showing an example of the planar layout near the pad portion PDb in the storage device 1G of the eighth embodiment. Figure 47 The diagram shows a portion of the pad PDb for connection to the input / output circuit 11 and the logic controller 12, as well as a portion of the core region CR and the peripheral region PR in the storage device 1G.

[0282] like Figure 47 As shown, the storage device 1G has the configuration of the storage device 1B of the third embodiment, where the effective area AA and the dummy area DA of the core region CR are replaced with the effective area AAa and the dummy area DAa of the sixth embodiment, respectively. The pad portion PDb of the eighth embodiment overlaps with both the core region CR and the peripheral region PR. Furthermore, the pad portion PDb of the eighth embodiment has a portion that overlaps with the dummy area DAa in the core region CR, but does not have a portion that overlaps with the effective area AAa. Like the pad portion PDb of the third embodiment, the pad portion PDb of the eighth embodiment includes a conductive portion MA, an insulating portion BA, a through-hole TV, a conductive portion ZB, and multiple through-holes VBa.

[0283] <8-1-2> Cross-sectional structure of the PDb pad

[0284] Figure 48 It is along Figure 47 The cross-sectional view along line XLVIII-XLVIII shows an example of the cross-sectional structure near the solder pad portion PDb in the storage device 1G of the eighth embodiment. For example... Figure 48 As shown, the storage device 1G has the features used in the sixth embodiment. Figure 41 The source line SL within the effective region AAa and the dummy region DAa described herein is the same as that used in the third embodiment. Figure 29 The structure of the PDb assembly of the solder pads is described. Other configurations of the storage device 1G in the eighth embodiment are the same as those of the storage device 1B in the third embodiment.

[0285] <8-2> Manufacturing Method

[0286] The method for manufacturing the storage device 1G in the eighth embodiment is equivalent to: Figure 30 In the manufacturing method of the storage device 1B according to the third embodiment shown, an insertion is made between steps ST11 and ST12. Figure 42 The processes shown are ST61, ST62, and ST63. That is, in the manufacturing method of the memory device 1G in the eighth embodiment, similarly to the sixth embodiment, after removing the semiconductor substrate W2, the source line SL is formed, and then, similarly to the third embodiment, a structure corresponding to the pad portion PDb is formed.

[0287] <8-3> Effects of the 8th Embodiment

[0288] The memory device 1G of the eighth embodiment, like that of the sixth embodiment, has a structure in which the structure corresponding to the source line SL within the dummy region DAa is removed, and the dummy region DAa overlaps with the pad portion PDb in the Z direction. Therefore, like that of the sixth embodiment, the memory device 1G of the eighth embodiment can reduce the parasitic capacitance of the pad, thus suppressing interface speed degradation and reducing chip size. Furthermore, because the conductive portion MA and the contact C3 are connected via the conductive portion ZB, the memory device 1G of the eighth embodiment, like that of the third embodiment, can improve yield.

[0289] <9> 9th Implementation Method

[0290] The storage device 1H of the ninth embodiment has a structure that combines the pad portion PDc described in the fourth embodiment with the source line SL described in the sixth embodiment. Hereinafter, details of the storage device 1H of the ninth embodiment will be described.

[0291] <9-1> Composition

[0292] The storage device 1H of the ninth embodiment has the same configuration as the storage device 1C of the fourth embodiment, except for the structure of the source line SL. Hereinafter, the planar layout and cross-sectional structure of the pad portion PDc in the storage device 1H of the ninth embodiment will be described.

[0293] <9-1-1> Planar layout of the pad portion PDc

[0294] Figure 49 This is a top view showing an example of the planar layout near the pad portion PDc in the storage device 1H of the ninth embodiment. Figure 49 The diagram shows a portion of the pad PDc for connection to the input / output circuit 11 and the logic controller 12, as well as a portion of the core region CR and the peripheral region PR in the storage device 1H.

[0295] like Figure 49As shown, the storage device 1H has the configuration of the storage device 1C in the fourth embodiment, where the effective area AA and the dummy area DA of the core region CR are replaced with the effective area AAa and the dummy area DAa of the sixth embodiment, respectively. The pad portion PDc of the ninth embodiment overlaps with both the core region CR and the peripheral region PR. Furthermore, the pad portion PDc of the ninth embodiment has a portion that overlaps with the dummy area DAa in the core region CR, but does not have a portion that overlaps with the effective area AAa. Like the pad portion PDc of the fourth embodiment, the pad portion PDc of the ninth embodiment includes a conductive portion MA, an insulating portion BA, a through-hole TV, and multiple contacts VBP.

[0296] <9-1-2> Cross-sectional structure of the PDc pad

[0297] Figure 50 It is along Figure 49 The LL-line cross-sectional view shows an example of the cross-sectional structure near the solder pad portion PDc in the storage device 1H of the ninth embodiment. For example... Figure 50 As shown, the storage device 1H has the features used in the sixth embodiment. Figure 41 The source line SL within the effective region AAa and the dummy region DAa described herein is the same as that used in the fourth embodiment. Figure 36 The structure of the PDc assembly of the solder pad portion is described. Other configurations of the storage device 1H in the 9th embodiment are the same as those of the storage device 1C in the 4th embodiment.

[0298] <9-2> Manufacturing Method

[0299] The manufacturing method of the storage device 1H in the ninth embodiment is equivalent to: in the case of Figure 24 In the manufacturing method of the storage device 1C of the fourth embodiment, which is based on the manufacturing method of the storage device 1A of the second embodiment shown, an insertion is made between steps ST11 and ST12. Figure 42 The processes shown are ST61, ST62, and ST63. That is, in the manufacturing method of the memory device 1H of the 9th embodiment, similarly to the 6th embodiment, after removing the semiconductor substrate W2, the source line SL is formed, and then, similarly to the 4th embodiment, a structure corresponding to the pad portion PDc is formed.

[0300] <9-3> Effects of the 9th Embodiment

[0301] The memory device 1H of the ninth embodiment, like the sixth embodiment, has a structure in which the structure corresponding to the source line SL within the dummy region DAa is removed, and the dummy region DAa overlaps with the pad portion PDc in the Z direction. Therefore, like the sixth embodiment, the memory device 1H of the ninth embodiment can reduce the parasitic capacitance of the pads, thus suppressing interface speed degradation and reducing chip size. Furthermore, because the via TV and multiple contacts VBP are arranged to overlap in the Z direction, the memory device 1H of the ninth embodiment, like the fourth embodiment, can reduce chip area.

[0302] <10> 10th Implementation Method

[0303] The storage device 1I of the tenth embodiment has a structure that combines the solder pad portion PDd described in the fifth embodiment with the source line SL described in the sixth embodiment. Hereinafter, details of the storage device 1I of the tenth embodiment will be described.

[0304] <10-1> Composition

[0305] The storage device 1I of the tenth embodiment has the same configuration as the storage device 1D of the fifth embodiment, except for the structure of the source line SL. Hereinafter, the planar layout and cross-sectional structure of the pad portion PDd in the storage device 1I of the tenth embodiment will be described.

[0306] <10-1-1> Planar layout of the solder pad PDd

[0307] Figure 51 This is a top view showing an example of the planar layout near the pad portion PDd in the storage device 1I of the 10th embodiment. Figure 51 The diagram shows a portion of the pad PDd for connection to the input / output circuit 11 and the logic controller 12, as well as a portion of the core region CR and the peripheral region PR in the storage device 1I.

[0308] like Figure 51 As shown, the storage device 1I has the configuration of the storage device 1D in the fifth embodiment, where the effective area AA and the dummy area DA of the core region CR are replaced with the effective area AAa and the dummy area DAa of the sixth embodiment, respectively. The pad portion PDd of the tenth embodiment overlaps with both the core region CR and the peripheral region PR. Furthermore, the pad portion PDd of the tenth embodiment has a portion that overlaps with the dummy area DAa in the core region CR, but does not have a portion that overlaps with the effective area AAa. Similar to the pad portion PDd of the fifth embodiment, the pad portion PDd of the tenth embodiment includes a conductive portion MA, an insulating portion BA, a through-hole TV, a conductive portion ZB, and multiple through-holes VBa.

[0309] <10-1-2> Cross-sectional structure of the PDd pad

[0310] Figure 52 It is along Figure 51 The cross-sectional view along line LII-LII shows an example of the cross-sectional structure near the solder pad portion PDd in the storage device 1I of the tenth embodiment. For example... Figure 52 As shown, the storage device 1I has the features used in the sixth embodiment. Figure 41 The source line SL within the effective region AAa and the dummy region DAa described herein is the same as that used in the 5th embodiment. Figure 38 The structure of the solder pad PDd assembly is described. Other configurations of the storage device 1I in the 10th embodiment are the same as those of the storage device 1D in the 5th embodiment.

[0311] <10-2> Manufacturing Method

[0312] The manufacturing method of the storage device 1I in the tenth embodiment is equivalent to: in the case of Figure 30 In the manufacturing method of the storage device 1D based on the manufacturing method of the storage device 1B of the third embodiment shown, an insertion is made between steps ST11 and ST12. Figure 42 The processes shown are ST61, ST62, and ST63. That is, in the manufacturing method of the memory device 1I of the 10th embodiment, similarly to the 6th embodiment, after removing the semiconductor substrate W2, the source line SL is formed, and then, similarly to the 5th embodiment, a structure corresponding to the pad portion PDd is formed.

[0313] <10-3> Effects of the 10th Embodiment

[0314] The storage device 1I of the tenth embodiment, like that of the sixth embodiment, has a structure in which the structure corresponding to the source line SL within the dummy region DAa is removed, and the dummy region DAa overlaps with the pad portion PDd in the Z direction. Therefore, the storage device 1I of the tenth embodiment, like that of the sixth embodiment, can reduce the parasitic capacitance of the pads, thus suppressing interface speed degradation and reducing chip size. Furthermore, because the via TV and the conductive portion ZB are arranged to overlap in the Z direction, the storage device 1I of the tenth embodiment, like that of the fifth embodiment, can reduce chip area.

[0315] <11> 11th Embodiment

[0316] The storage device 1J of the 11th embodiment has a structure in which the top view dimension of the conductive portion MA of the pad portion PD is designed to be smaller than the top view dimension of the insulating portion BA in the storage device 1 of the 11th embodiment. Details of the storage device 1J of the 11th embodiment will be described below.

[0317] <11-1> Composition

[0318] The storage device 1J of the 11th embodiment has the same configuration as the storage device 1 of the 1st embodiment, except for the structure of the solder pad portion PD. Hereinafter, the planar layout and cross-sectional structure of the solder pad portion PDe in the storage device 1J of the 11th embodiment will be described.

[0319] <11-1-1> Planar Layout of PDE Pad

[0320] Figure 53 This is a top view showing an example of the planar layout near the pad portion PDe in the storage device 1J of the 11th embodiment. Figure 53 The diagram shows a portion of the pad PDe for connection to the input / output circuit 11 and the logic controller 12, as well as a portion of the core region CR and the peripheral region PR in the storage device 1J.

[0321] like Figure 53 As shown, the pad portion PDe overlaps with both the core region CR and the peripheral region PR. Furthermore, the pad portion PDe overlaps with the dummy region DA within the core region CR, but not with the active region AA. The pad portion PDe includes a conductive portion MA, an insulating portion BA, a through-hole TV, and a through-hole VB. The insulating portion BA is rectangular in shape, for example, when viewed from above. The outer edge of the insulating portion BA corresponds to the outer edge of the pad portion PDe. The conductive portion MA is rectangular in shape, for example, when viewed from above, and overlaps with the conductive portion MA. Compared to the outer edge of the insulating portion BA, the outer edge of the conductive portion MA is located further inward. The configurations of the through-holes TV and VB in the pad portion PDe are the same as those described in the first embodiment.

[0322] <11-1-2> Cross-sectional structure of the pad portion PDe

[0323] Figure 54 It is along Figure 53 The cross-sectional view along the LIV-LIV line shows an example of the cross-sectional structure near the pad portion PDe in the storage device 1J of the 11th embodiment. For example... Figure 54 As shown, the pad portion PDe has the features used in the first embodiment. Figure 11 In the described pad portion PD, the outer edge of the conductive portion MA is positioned further inward than the outer edge of the insulating portion BA. Therefore, the conductive layer 303 corresponding to the conductive portion MA does not have a portion overlapping with the conductive layers 21, 211, and 213 in the Z direction. The other configurations of the storage device 1J in the 11th embodiment are the same as those in the storage device 1 of the 1st embodiment.

[0324] <11-2> Manufacturing Method

[0325] The manufacturing method of the storage device 1J in the 11th embodiment is equivalent to: using Figures 12-17 In the manufacturing method of the storage device 1 of the first embodiment described herein, the conductive part MA is arranged in a position further inside when viewed from above compared to the insulating part BA.

[0326] <11-3> Effects of the 11th Embodiment

[0327] In the storage device 1J of the 11th embodiment, compared with the first embodiment, the area of ​​the portion of the conductive part MA and the source line SL facing each other in the Z direction can be reduced. As a result, compared with the first embodiment, the storage device 1J of the 11th embodiment can reduce the parasitic capacitance of the solder pads and suppress the degradation of the interface speed.

[0328] Furthermore, the ideas described in Embodiment 11 can also be combined with Embodiments 2 through 10. That is, in Embodiments 2 through 10, the outer edge of the conductive portion MA can be configured such that it is located further inward than the outer edge of the insulating portion BA. As a result, Embodiments 2 through 10 can achieve the same effects as Embodiment 11.

[0329] <12> Examples of variations, etc.

[0330] The storage device 1 described above can be modified in various ways.

[0331] Figure 55 This is an example cross-sectional view showing a detailed cross-sectional structure near the two opposing bonding pads in the storage device 1 of the first embodiment. Figure 55 The diagram shows a conductive layer 105 (bonding pad) formed using a semiconductor substrate W1 (not shown), a conductive layer 25 (bonding pad) formed using a semiconductor substrate W2 (not shown), a portion of contacts C2 and V2 connected to them, and conductive layers 104 and 24. Figure 55As shown, the two opposing bonding pads may have different conical shapes based on the etching direction during formation. Specifically, the conductive layer 105 formed using the semiconductor substrate W1 has, for example, an inverted conical shape. The conductive layer 25 formed using the semiconductor substrate W2 has, for example, a conical shape. Therefore, the sidewalls of the cross-section along the Z direction of the portion where the conductive layers 105 and 25 are joined may not be straight, but may be non-rectangular. Furthermore, the two opposing bonding pads may be staggered during bonding depending on their alignment during the bonding process. Therefore, a step difference may form between the side surfaces of the conductive layer 105 and the conductive layer 25. The two opposing bonding pads may have an interface or be integrated. The bonding pads and the contacts C2 and V2 connected to them may also be integrally formed. Multiple corresponding contacts C2 and V2 may also be connected to the bonding pads. For example, the conductive layer 105 may be connected to the conductive layer 104 via multiple contacts C2. Similarly, conductor layer 25 can also be connected to conductor layer 24 via multiple contacts V2.

[0332] In the described embodiment, the storage device 1 may also include multiple storage cell arrays 10. When the storage device 1 includes multiple storage cell arrays 10, each storage device 10 may include a sense amplifier module 17 and a line decoder module 16. In this case, each storage cell array 10 is provided with multilayer wiring containing multiple word lines WL. Furthermore, the groups of conductive layers 21, 211, and 213 corresponding to the source line SL, or the groups of semiconductor layers 214 and 217 and conductive layer 218 corresponding to the source line SL, are interrupted in each storage cell array 10.

[0333] In the embodiments described, the circuit configuration, planar layout, and cross-sectional structure of the storage device 1 can be appropriately modified. Other contacts can be inserted between the storage pillar MP and the conductive layer 23. Other contacts can also be inserted between contact C3 and the conductive layer 26. Conductive layers can also be inserted at the connection points of multiple contacts. The number of wiring layers and contacts in the storage device 1 can be appropriately modified according to the circuit design. The storage pillar MP and each contact can also have a conical shape, an inverted conical shape, or a curved shape. The XY cross-sectional structure of the storage pillar MP can be circular or elliptical. Each wiring in the multilayer wiring can also be wiring with a metal oxide film surrounding a conductor such as tungsten. The conductive layers alternately stacked with insulating layers in the multilayer wiring can also be considered as containing such a metal oxide film.

[0334] In this specification, "connection" refers to an electrical connection, excluding cases where other components are in between. An "electrical connection" is defined as any connection that functions as an electrical connection, even if it is separated by an insulator. "Semiconductor substrate" can also be simply referred to as "substrate." "Semiconductor layer" can also be called "conductive layer." "Region" can also be considered as a component contained within the substrate. For example, if the semiconductor substrate W1 is specified to include a storage region SA and a contact region CA, the storage region SA and the contact region CA are associated with different regions above the semiconductor substrate W1. "Height" corresponds, for example, to the distance in the Z direction between the component being measured and the semiconductor substrate W1. A component other than the semiconductor substrate W1 can also be used as a reference for "height." "View from top surface (top view)" corresponds, for example, to the view of the front side of the semiconductor substrate W1 viewed from the vertical direction. "Through-hole" can also be called an opening.

[0335] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention and its equivalents as described in the claims.

[0336] [Explanation of Symbols]

[0337] 1,1A,1B,1C,1D,1E,1F,1G,1H,1I,1J,1Y,1Z Storage devices

[0338] 2. Memory controller

[0339] 10-cell array

[0340] 11 Input / Output Circuit

[0341] 12 Logic Controller

[0342] 13 Register Circuit

[0343] 14 Sequencer

[0344] 15 Driver Circuit

[0345] 16-line decoder module

[0346] 17. Sensing Amplifier Module

[0347] 21~26,24W,25W,26W,103~105,103W,104W,105W,211,213,218,303,303A,303B Conductor layer

[0348] 310, 320 Conductive components

[0349] 31~35, 110, 111, 210, 301, 304~307, 330 Insulating layer

[0350] 215 components

[0351] 36,302 Insulating components

[0352] 40 core components

[0353] 41,214,217 Semiconductor layer

[0354] 42. Laminated film

[0355] 43 Tunnel insulation film

[0356] 44 Insulating film

[0357] 45 insulating films

[0358] 100 CMOS layers

[0359] 101 Gate insulating film

[0360] 102 Gate electrode

[0361] 200 Storage Layer

[0362] 212 Sacrificial Parts

[0363] 300 wiring layer

[0364] V1, V2, C0~C3, C1W, C2W, C3W, VBP contacts

[0365] ES1, ES2 sealing sections

[0366] B1,B2 bonding layer

[0367] CR core area

[0368] PR peripheral area

[0369] WR wall area

[0370] KR slot area

[0371] SA Storage Area

[0372] CA contact area

[0373] AA,AAa Valid region

[0374] DA,DAa are virtual regions.

[0375] DS (Decorative Steps)

[0376] VA, VB, VBa, VC, TV through holes

[0377] BA insulation section

[0378] MA,ZB conductive parts

[0379] W1, W2 semiconductor substrates

[0380] BLK block

[0381] DBLK Dummy Block

[0382] SL source line

[0383] BL bitline

[0384] WL lettering

[0385] MT memory cell transistor

[0386] ST1, ST2 select transistors

[0387] RD line decoder

[0388] SAU Sensing Amplifier Unit

[0389] TR1 and TR2 are transistors.

Claims

1. A storage device having a mating surface and comprising: The substrate has a first region and a second region arranged in a first direction; The first circuit layer, disposed between the substrate and the bonding surface, contains CMOS circuitry. The second circuit layer is disposed above the bonding surface; and A wiring layer, disposed above the second circuit layer, includes pads electrically connected to the CMOS circuit via the second circuit layer; The second circuit layer includes: a stacked body comprising, within the first region, alternatingly stacked first insulating layers and first conductive layers in a second direction intersecting the first direction, and within the second region, alternatingly stacked first insulating layers and first conductive layers in the second direction, or alternatingly stacked first insulating layers and first components in the second direction, wherein the material of the first component is different from that of the first insulating layers and the first conductive layers; and a plurality of first pillars, within the first region, penetrating the stacked body in the second direction, and electrically connected to a source line above the stacked body; The pad has a portion that overlaps with the stack in the second direction, but does not have a portion that overlaps with the source line in the second direction.

2. The storage device according to claim 1, wherein The laminated body in the second region has a laminated body portion formed by alternating layers of the first insulating layer and the first component in the second direction, and the end of the first component of the laminated body is arranged in a stepped shape.

3. The storage device according to claim 1, wherein The second circuit layer further includes a plurality of second pillars, which penetrate the laminate in the second direction within the second region; and The plurality of first pillars are configured to store data in the portion intersecting with the first conductive layer, and the plurality of second pillars are not used for storing data. The bonding pad has a portion that overlaps with the plurality of second pillars in the second direction. The plurality of second pillars are electrically insulated from the source electrode line.

4. The storage device according to claim 1, wherein The pads are electrically connected to the interface circuits included in the CMOS circuitry.

5. The storage device according to claim 1, wherein The wiring layer includes a second conductive layer having portions corresponding to the solder pads, and a second insulating layer disposed to cover the upper portion of the second conductive layer. The second insulating layer is provided with a first opening such that the surface of the portion of the second conductive layer corresponding to the solder pad is exposed.

6. The storage device according to claim 5, wherein The wiring layer further includes an insulating component that insulates the source line from the second conductor layer, and the insulating component has a portion in the second region that is disposed at the same height as the source line and between the first opening and the stack.

7. The storage device according to claim 6, wherein The substrate further has a third region disposed in a manner that surrounds the first region and the second region when viewed from above, and The second circuit layer further includes at least one first contact, wherein the at least one first contact has a portion disposed at the same height as the stack body in the third region and is electrically connected to the CMOS circuit; The second conductive layer has a portion in the second region that overlaps with the laminate in the second direction, and a portion in the third region that is electrically connected to the at least one first contact.

8. The storage device according to claim 7, wherein The insulating member has a second opening at the portion overlapping with the at least one first contact in the second direction, and The second conductive layer is disposed along the second opening in the third region and is connected to the at least one first contact at the bottom of the second opening.

9. The storage device according to claim 7, wherein The wiring layer further includes at least one second contact, the at least one second contact passing through the insulating component and respectively connected to the at least one first contact; and The second conductive layer is electrically connected to the at least one first contact via the at least one second contact.

10. The storage device according to claim 9, wherein The first opening has a portion that overlaps with the at least one second contact point in the second direction.

11. The storage device according to claim 7, wherein The wiring layer further includes a conductive component, the upper part of which is covered by the insulating component, and the conductive component is connected to the at least one first contact point; and The insulating component has a third opening at the portion that overlaps with the conductive component in the second direction, the second conductive layer is embedded in the third opening, and is connected to the conductive component at the bottom of the third opening.

12. The storage device according to claim 11, wherein The first opening has a portion that overlaps with the conductive component in the second direction.

13. The storage device according to claim 5, wherein The substrate further has a third region disposed in a manner that surrounds the first region and the second region when viewed from above, and The second circuit layer further includes a first sublayer and a second sublayer. The first sublayer is disposed in the same layer as the source line in the third region and contains at least a portion of the same material as the source line as the main component. The second sublayer is disposed above the first sublayer, separated by the second component. The first opening does not have a portion that overlaps with the first sub-layer and the second sub-layer in the second direction.

14. The storage device according to claim 1, wherein The second circuit layer further includes a third conductor layer used as part of the source line within the first region, and The plurality of first pillars each contain a semiconductor layer extending in the second direction. The semiconductor layer and the third conductor layer are electrically connected via the side surfaces of the plurality of first pillars.

15. The storage device according to claim 1, wherein The wiring layer in the first region further includes a third conductor layer used as part of the source line, and The plurality of first pillars each contain a semiconductor layer extending in the second direction. The third conductive layer has a portion disposed along the upper part of the semiconductor layer and is electrically connected to the semiconductor layer.

16. The storage device according to claim 1, further comprising: The first bonding pad is disposed adjacent to the bonding surface and electrically connected to the CMOS circuit; and The second solder pad is disposed adjacent to the mating surface and is electrically connected between one of the plurality of first posts and the first solder pad; and The direction of the cone shape of the first solder pad is different from the direction of the cone shape of the second solder pad.

17. A storage device having a mating surface and comprising: The first circuit layer, disposed between the substrate and the bonding surface, contains CMOS circuitry. The second circuit layer includes: a stack body disposed above the first circuit layer across the bonding surface, comprising alternating layers of a first insulating layer and a first conductive layer in the stacking direction; and a plurality of pillars, including a first pillar and a second pillar extending in the stack body along the stacking direction, the first pillar being electrically connected to a source line above the stack body and configured to store data at an intersection with the first conductive layer, the second pillar not used for storing data; and The second conductive layer is disposed above the source line in the stacking direction, includes a portion corresponding to the pad, and is electrically connected to the CMOS circuit. The second conductor layer has a portion that overlaps with the second post in the stacking direction. This portion of the second conductor layer is not separated from the source line, but is separated from the source line by an insulating member disposed at the same height as the source line, and is opposite to the second post in the stacking direction.

18. The storage device according to claim 17, wherein The pad has a portion that overlaps with the second pillar in the stacking direction, but does not have a portion that overlaps with the source line in the stacking direction.

19. The storage device according to claim 18, It also includes a second insulating layer disposed in such a manner as to cover the upper part of the second conductive layer, and The second insulating layer is provided with a first opening such that the surface of the portion of the second conductive layer corresponding to the solder pad is exposed.

20. The storage device according to claim 17, wherein The second circuit layer further includes: a third insulating layer disposed around the stack in top view; and at least one first contact, a portion of which is disposed at the same height as the stack and extends along the stacking direction within the third insulating layer, and is electrically connected to the CMOS circuit; and The second conductive layer also has a portion electrically connected to the at least one first contact.

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