Semiconductor device and forming method thereof

Abstract

The invention relates to a semiconductor device and a forming method thereof. The semiconductor device comprises a second grid electrode, a grid electrode material block, a first medium-voltage device side wall, a second medium-voltage device side wall, a second source region and a second drain region which are formed in a medium-voltage device forming region in a substrate surface region, the side wall structure of the medium-voltage device is formed by the grid material block located on the side face of the second grid, the first medium-voltage device side wall and the second medium-voltage device side wall, and by means of the side wall structure, the thickness of the side wall of the medium-voltage device can be larger than that of the side wall, formed in the low-voltage device forming area, of the low-voltage device. The problem of serious GIDL electric leakage caused by the fact that the side wall of the medium-voltage device is too thin can be avoided. In addition, the side wall of the first medium-voltage device can be of a wide-end-up structure, so that the quality of the side wall and the performance of the semiconductor device can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit manufacturing, and in particular to a semiconductor device and a method for forming a semiconductor device. BACKGROUND

[0002] GIDL (Gate induced Drain Leakage) effect is a main leakage mechanism of MOSFET (hereinafter referred to as MOS device). When the gate is not applied with voltage or is applied with negative voltage, and the drain is applied with high voltage, the gate-drain voltage Vgd is very high, a strong electric field is formed from the drain to the gate in the gate-drain overlapping region, the energy band near the interface of the overlapping region is strongly bent and the depletion region is very narrow, and the carriers are easy to tunnel and generate electron-hole pairs, the electrons flow to the drain, and the holes are swept into the base well, forming a GIDL current from the drain to the base well. DG The GIDL current is very large, and a strong electric field is formed from the drain to the gate in the gate-drain overlapping region, the energy band near the interface of the overlapping region is strongly bent and the depletion region is very narrow, and the carriers are easy to tunnel and generate electron-hole pairs, the electrons flow to the drain, and the holes are swept into the base well, forming a GIDL current from the drain to the base well.

[0003] In order to reduce the GIDL current, the interface morphology of the gate-drain overlapping region needs to be improved, and the distance between the gate and the drain needs to be reduced to reduce the electric field formed in the gate-drain overlapping region. However, some products integrate MOS devices with different working voltages, for example, at least two of high-voltage (HV) devices, medium-voltage (MV) devices and low-voltage (LV) devices are fabricated on a substrate, wherein the low-voltage devices (such as logic devices) require a thin sidewall to be arranged on the side surface of the gate. For the medium-voltage devices, if the same sidewall process is used as the low-voltage devices to form a thin sidewall, when the drain is applied with voltage, a strong electric field is easy to form between the gate and the drain which are close in the gate-drain overlapping region, and a serious GIDL leakage problem is caused. SUMMARY

[0004] In order to simultaneously form low-voltage devices and medium-voltage devices on a substrate and avoid the serious GIDL leakage problem of the medium-voltage devices, the present application provides a semiconductor device and a method for forming a semiconductor device.

[0005] In one aspect, the present application provides a method for forming a semiconductor device, the forming method comprising:

[0006] stacking a gate dielectric layer and a gate material layer on a substrate surface in sequence, wherein a low-voltage device forming region and a medium-voltage device forming region are arranged laterally on the substrate surface region;

[0007] performing patterning on the gate material layer to form a first gate in the low-voltage device forming region, and to form a second gate and gate material blocks on both sides of the second gate in the medium-voltage device forming region, wherein the second gate and the gate material blocks have an isolation trench with a wide top and a narrow bottom therebetween;

[0008] covering a layer of side wall material on the substrate, the layer of side wall material filling the isolation trench; and

[0009] removing part of the layer of side wall material and part of the gate dielectric layer under the layer of side wall material, exposing top surfaces of the first gate, the second gate and the gate material block and the substrate surface, forming a low-voltage device side wall on a side of the first gate, a first medium-voltage device side wall in the isolation trench and a second medium-voltage device side wall on a side of the gate material block opposite to the first medium-voltage device side wall from the layer of side wall material; and

[0010] performing source-drain ion implantation to form a first source region and a first drain region on two sides of the first gate respectively and outside the low-voltage device side wall, and to form a second source region and a second drain region on two sides of the second gate respectively and outside the second medium-voltage device side wall.

[0011] Optionally, the substrate surface region is further arranged with a high-voltage device formation region; when the gate material layer is patterned, a third gate is formed in the high-voltage device formation region; by removing part of the layer of side wall material, a high-voltage device side wall is formed on a side of the third gate; by the source-drain ion implantation, a third source region and a third drain region are formed on two sides of the third gate respectively and outside the high-voltage device side wall.

[0012] Optionally, before the substrate surface is stacked with the gate dielectric layer, the forming method further comprises:

[0013] performing LDD implantation to form an LDD region in the substrate in the medium-voltage device formation region, wherein the LDD region extends from below an end of the second gate to a side of the gate material block away from the second gate.

[0014] Optionally, the patterning of the gate material layer comprises:

[0015] forming a photoresist layer on the substrate and exposing the photoresist layer using a half-tone mask plate;

[0016] developing, the photoresist layer forming a first photoresist block for defining the first gate, a second photoresist block for defining the second gate and a third photoresist block for defining the gate material block, a height of a part of the third photoresist block close to the second photoresist block being less than a height of a part of the third photoresist block away from the second photoresist block;

[0017] The photoresist layer is used as an etching mask to etch the gate material layer to form the first gate, the second gate, the gate material block and the isolation trench, and the height of the part of the gate material block close to the second gate is less than the height of the part of the gate material block away from the second gate, so that the isolation trench is wide at the top and narrow at the bottom.

[0018] Optionally, before removing part of the sidewall material layer, the sidewall material layer fills the isolation trench and is stacked above the isolation trench, and the height of the part of the sidewall material layer located at the source / drain ion implantation region is less than the height of the second gate.

[0019] Optionally, removing part of the sidewall material layer and part of the gate dielectric layer under the sidewall material layer comprises:

[0020] The sidewall material layer is etched by a self-aligned etching process to expose the top surfaces of the first gate, the second gate and the gate material block, part of the gate dielectric layer surface under the sidewall material layer, and further etch the exposed gate dielectric layer to expose the substrate surface.

[0021] Optionally, before removing part of the sidewall material layer, the sidewall material layer fills the isolation trench and is stacked above the isolation trench, and the height of the part of the sidewall material layer located at the source / drain ion implantation region is greater than or equal to the height of the second gate.

[0022] Optionally, removing part of the sidewall material layer and part of the gate dielectric layer under the sidewall material layer comprises:

[0023] A planarization process is performed to expose the top surfaces of the first gate, the second gate and the gate material block, and the top surface of the remaining sidewall material layer is flush with the top surface of the second gate.

[0024] A patterned mask layer is formed on the substrate, which covers the surface of the first gate and part of the sidewall material layer surface on both sides of the first gate in the low-voltage device formation area, and covers the surfaces of the second gate and the gate material block, the sidewall material layer surface in the isolation trench and part of the sidewall material layer surface located outside the gate material block in the medium-voltage device formation area.

[0025] The sidewall material layer and the gate dielectric layer in the area not covered by the mask layer are removed using the mask layer as an etching mask to form the low-voltage device sidewall, the first medium-voltage device sidewall and the second medium-voltage device sidewall.

[0026] In another aspect, the present application provides a semiconductor device, comprising:

[0027] a substrate having a surface area laterally distributed with a low-voltage device formation region and a medium-voltage device formation region;

[0028] a first gate formed corresponding to the low-voltage device formation region, a low-voltage device sidewall formed laterally to the first gate, and a first source region and a first drain region respectively formed laterally to the first gate and outside the low-voltage device sidewall; and

[0029] a second gate formed corresponding to the medium-voltage device formation region, a gate material block laterally to the second gate, a first medium-voltage device sidewall, a second medium-voltage device sidewall, a second source region and a second drain region, wherein the gate material block is laterally to the second gate, the gate material block and the second gate have an isolation trench therebetween with a width increasing from top to bottom, the first medium-voltage device sidewall is filled in the isolation trench, the second medium-voltage device sidewall is laterally to the gate material block opposite to the first medium-voltage device sidewall, and the second source region and the second drain region are respectively formed laterally to the second gate and outside the second medium-voltage device sidewall.

[0030] Optionally, the substrate is further arranged with a high-voltage device formation region; the semiconductor device further comprises a third gate formed corresponding to the high-voltage device formation region, a high-voltage device sidewall formed laterally to the third gate, and a third source region and a third drain region respectively formed laterally to the third gate and outside the high-voltage device sidewall.

[0031] Optionally, a height of a portion of the gate material block close to the second gate is less than a height of a portion of the gate material block away from the second gate, such that the isolation trench and the first medium-voltage device sidewall have a width increasing from top to bottom.

[0032] By using the forming method of the semiconductor device provided by the application, the low-voltage device including the first gate, the low-voltage device side wall, the first source region and the first drain region can be formed corresponding to the low-voltage device forming region, the medium-voltage device including the second gate, the gate material block, the first medium-voltage device side wall, the second medium-voltage device side wall, the second source region and the second drain region can be formed corresponding to the medium-voltage device forming region, and for the medium-voltage device, the gate material block, the first medium-voltage device side wall and the second medium-voltage device side wall on the side surface of the second gate together constitute a side wall structure, by using the side wall structure, the side wall thickness of the medium-voltage device is larger than the low-voltage device side wall, when the low-voltage device side wall is thin, the problem that the second gate and the second drain region are too close to each other to cause serious GIDL leakage can be avoided, and further, the problem of serious GIDL leakage caused by the second gate and the second drain region being too close to each other can be avoided; in addition, the isolation groove between the second gate and the gate material block is wide at the top and narrow at the bottom, the filling quality of the first medium-voltage device side wall formed in the isolation groove can be improved, and the process control is facilitated.

[0033] The semiconductor device provided by the application and the forming method of the semiconductor device provided by the application have the same overall concept and the same or similar advantages. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is a flowchart of the forming method of the semiconductor device of the embodiment of the application.

[0035] Figures 2A to 2L is a cross-sectional view of the forming method of the semiconductor device according to an embodiment of the application. DETAILED DESCRIPTION

[0036] The semiconductor device and the forming method thereof of the application will be further described in detail below in combination with the drawings and specific embodiments. According to the following description, the advantages and features of the application will be more apparent. It should be understood that the drawings of the specification are very simplified and use non-precise proportions, only to facilitate and clarify the purpose of assisting the description of the embodiments of the application. It should be noted that the order of the steps in the methods presented herein is not necessarily the only order in which the steps are performed, some of the steps described can be omitted and / or some other steps not described herein can be added to the method. It should be understood that the spatial relative terms are intended to include different orientations in use or operation in addition to the orientation of the device described in the drawings. For example, if the structure in the drawings is inverted or positioned in other different ways (such as rotated), the exemplary term "on" can also include "under" and other orientation relationships.

[0037] Firstly, the semiconductor device provided by the application will be described below in combination with Figures 1 to 2LA method for forming a semiconductor device according to an embodiment of the present application is introduced.

[0038] Referring to Figure 1 and Figure 2A , the method for forming a semiconductor device according to an embodiment of the present application, in step S1, stacks a gate dielectric layer 110 and a gate material layer 120 on the surface of a substrate 100, and the surface region of the substrate 100 is arranged with a low-voltage device formation region 10 and a medium-voltage device formation region 20 laterally.

[0039] The substrate 100 can be a silicon substrate, a germanium-silicon substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator substrate, a germanium-silicon-on-insulator substrate, or a Ⅲ-Ⅴ compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate), etc., or can be other substrates known to those skilled in the art for carrying MOS devices, and the substrate 100 can be formed with a doped region and / or an isolation structure. In this embodiment, at least one doped well region can be formed in the substrate 100, and at least one low-voltage device formation region 10 for forming a low-voltage device with a lower working voltage and at least one medium-voltage device formation region 20 for forming a medium-voltage device with a higher working voltage can be defined on the top of the substrate 100 by an isolation region (such as a shallow trench isolation (STI)). As an example, the working voltage of the low-voltage device is less than 3V, and the working voltage of the medium-voltage device is about 3V-10V, but the present application is not limited thereto, and the working voltages of the low-voltage device and the medium-voltage device can be set according to actual conditions.

[0040] The surface region of the substrate 100 can also be arranged with a high-voltage device formation region for forming a high-voltage device with a higher working voltage than the low-voltage device and the medium-voltage device, and the following embodiments are described by taking the surface region of the substrate 100 with the low-voltage device formation region 10, the medium-voltage device formation region 20, and the high-voltage device formation region (not shown in the figure) as an example.

[0041] As shown in Figure 2A , before forming the gate dielectric layer 110 on the surface of the substrate 100, the method can further include a step of forming an LDD region in the substrate 100 in the medium-voltage device formation region 20. For example, an ion implantation mask can be first formed on the substrate 200 to expose a portion of the substrate 100 corresponding to the medium-voltage device formation region 20, and then LDD implantation and annealing are performed, so that an LDD region can be formed in the medium-voltage device formation region 20, which is located on both sides of a second gate to be subsequently formed in the medium-voltage device formation region 20, and one end of the LDD region extends to below the end of the second gate.

[0042] The gate dielectric layer 110 is formed on the surface of the substrate 100, and the gate material layer 120 can be silicon oxide or other suitable materials. AsFigure 2A As shown, the gate dielectric layer 110 can include a first gate dielectric layer 111 formed on the surface of the substrate 100 in the low-voltage device formation region 10 and a second gate dielectric layer 112 formed on the surface of the substrate 100 in the medium-voltage device formation region 20, the thickness of the second gate dielectric layer 112 being greater than the thickness of the first gate dielectric layer 111, for example.

[0043] The gate material layer 120 is formed on the surface of the gate dielectric layer 110, and the gate material layer 120 can be made of polysilicon or other suitable material. In the following embodiments, the gate dielectric layer 110 is made of silicon oxide, for example. The gate material layer 120 is made of polysilicon, for example.

[0044] Referring to Figure 1 , Figures 2B to 2D In step S2, the gate material layer 120 is patterned to form the first gate G1 in the low-voltage device formation region 10, the second gate G2 and the gate material blocks 121 on both sides of the second gate G2 in the medium-voltage device formation region 20, and the isolation trenches 122 with the width decreasing from top to bottom between the second gate G2 and the gate material blocks 121. In this embodiment, the third gate is also formed in the high-voltage device formation region by patterning the gate material layer 120.

[0045] In the process of patterning the gate material layer 120, a patterned mask layer (such as a photoresist layer) can be formed on the substrate 100 first, and the positions of the first gate G1, the second gate G2, the gate material blocks 121 and the third gate are defined by using the patterned mask layer. Then, the patterned mask layer is used as an etching mask to etch the gate material layer 120, and the first gate G1, the second gate G2, the gate material blocks 121 and the third gate can be obtained.

[0046] In this embodiment, in the process of patterning the gate material layer 120, the shape of the gate material blocks 121 and / or the second gate G2 can be adjusted by setting appropriate etching parameters or using a half-tone mask plate and other methods, so that the isolation trenches 122 between the second gate G2 and the gate material blocks 121 have the width decreasing from top to bottom. In this way, when the dielectric material is filled in the isolation trenches 122 later, the difficulty of filling is reduced, and the risk of forming a hollow defect in the filling process can be reduced.

[0047] Figure 2B A part of a half-tone mask plate 200 in an embodiment is shown in FIG. 2. As shown in FIG. 2, the half-tone mask plate 200 includes a first mask plate 210 and a second mask plate 220. The first mask plate 210 is used to define the positions of the first gate G1 and the third gate, and the second mask plate 220 is used to define the positions of the second gate G2 and the gate material blocks 121. Figure 2BAs shown, the half-tone mask plate 200 includes a light-transmissive substrate 210, a first light-blocking layer 220 and a second light-blocking layer 230 formed on the surface of the light-transmissive substrate 210, wherein the light-blocking effect of the first light-blocking layer 220 is better than that of the second light-blocking layer 230 for the exposure process, the light transmittance of the first light-blocking layer 220 is very small and can be regarded as substantially non-transparent, and the light transmittance of the second light-blocking layer 230 can be set as required (e.g. 95% to 5%) so that it can achieve partial light transmission. In this way, for the area of the light-transmissive substrate 210 provided with the superimposed layer of the first light-blocking layer 220 and the second light-blocking layer 230, light cannot pass through and thus cannot change the photoresist properties of the corresponding area, while for the area where the second light-blocking layer 230 is used alone for light blocking, part of the light can pass through, but the light is not sufficient compared with the area of the light-transmissive substrate 210 without the second light-blocking layer 230, and thus can only change the photoresist properties of part of the thickness of the corresponding area. For example, Figure 2B As shown, in this embodiment, for the area used to define the first gate G1 and the second gate G2, the half-tone mask plate 200 blocks light using the superimposed layer of the first light-blocking layer 220 and the second light-blocking layer 230, and for the area used to define the gate material block 121, part of the area blocks light using the superimposed layer of the first light-blocking layer 220 and the second light-blocking layer 230, and the other part of the area blocks light using the second light-blocking layer 230.

[0048] The following will be described in combination with Figure 2B and Figure 2C Step S2 will be described. As an example, step S2 includes the following process.

[0049] First, referring to Figure 2B a photoresist layer PR is formed on the substrate 100, and the photoresist layer PR is exposed using the above half-tone mask plate 200, so that the properties of different areas of the photoresist layer PR can be changed, wherein for the area used to define the first gate G1, the second gate G2, the third gate and part of the gate material block 121, the entire thickness of the photoresist layer PR does not change in properties, while for the other part of the area used to define the gate material block 121, the upper part of the photoresist layer PR changes in properties due to the irradiation of light, while the lower part does not change in properties due to the absence of irradiation of light.

[0050] Next, referring to Figure 2C, the photoresist layer exposed to light during exposure is removed, forming a first photoresist block PR10 for defining the first gate G1, a second photoresist block PR20 for defining the second gate G2, and a third photoresist block PR30 for defining the gate material block 121 (this embodiment also includes a photoresist block for defining a third gate to be formed in the high-voltage device formation area, not shown in the figure), wherein the height of the part of the third photoresist block PR30 close to the second photoresist block PR20 is less than the height of the part away from the second photoresist block PR20, specifically, as shown in Figure 2C , the third photoresist block PR30 includes a first sub-photoresist block PR31 and a second sub-photoresist block PR32, the first sub-photoresist block PR31 is close to the second photoresist block PR20 and the second sub-photoresist block PR32 is away from the second photoresist block PR20, and the height of the second sub-photoresist block PR32 is greater than the height of the first sub-photoresist block PR31. The height of the second sub-photoresist block PR32 is equal to the height of the second photoresist block PR20, for example. It should be noted that the above is only an example of forming a third photoresist block PR30 with different surface heights using a half-tone mask 200, and the present application is not limited to this example, and the structure of the above-mentioned half-tone mask 200 is only an example, and various suitable masks can be used according to the requirements of patterning the gate material layer 120. In addition, for the first sub-photoresist block PR31 closer to the second photoresist block PR20, it can also be other shapes in addition to the rectangular cross-section as shown in Figure 2C , for example, in another embodiment, the side of the first sub-photoresist block PR31 towards the second photoresist block PR20 can also be beveled or have multiple steps, and the height of the first sub-photoresist block PR31 and the second sub-photoresist block PR32 refers to the average height, for example.

[0051] Then, referring to Figure 2D , the gate material layer 120 is etched using the above-mentioned patterned photoresist layer PR as an etching mask, forming the first gate G1, the second gate G2, the gate material block 121, and the third gate, wherein the isolation trench 122 is formed between the second gate G2 and the gate material block 121, and through the above-mentioned patterned photoresist layer PR, the height of the part of the gate material block 121 close to the second gate G2 is less than the height of the part away from the second gate G2, so that the isolation trench 122 is wide at the top and narrow at the bottom (from the cross-section), so that the cross-sectional area of the top of the isolation trench 122 is greater than the cross-sectional area of the lower part of the isolation trench 122, which makes it easier for the dielectric material to fill, and avoids the formation of void defects. As shown in Figure 2DAs shown, the gate material block 121 includes, for example, a first material block 121a and a second material block 121b, wherein the first material block 121a is close to the corresponding second gate G2 while the second material block 121b is far from the second gate G2, and the height of the second material block 121b is greater than the height of the first material block 121a. The height of the second material block 121b is, for example, equal to the height of the second gate G2. It should be noted that, for the first material block 121a, which is closer to the second gate G2, it can be formed as follows: Figure 2D Besides the rectangular cross-section shown, it can also be other shapes. For example, in another embodiment, the side of the first material block 121a facing the second gate G2 can also be a slope or have multiple steps. The height of the first material block 121a and the second material block 121b refers to, for example, the average height.

[0052] like Figure 2D As shown, in the medium-voltage device formation region 20, the LDD region is located below the isolation trench 122 and the gate material block 121, and the LDD region extends from the side of the gate material block 121 away from the second gate G2 to below the end of the second gate G2.

[0053] Reference Figure 1 , Figure 2E and Figure 2F In step S3, a sidewall material layer is deposited on the substrate 100, the sidewall material layer filling the isolation trench 122. In this embodiment, the sidewall material layer also covers the high-voltage device formation region.

[0054] The sidewall material layer may include at least one dielectric material selected from silicon nitride, silicon oxide, and silicon oxynitride. The sidewall material layer may be one or more layers. As an example, before forming the sidewall material layer, LDD implantation may be performed on the substrate 100 of a portion of the low-voltage device formation region 10 to form LDD regions on both sides of the first gate G1, such as... Figure 2E and Figure 2F As shown. However, the present invention is not limited to this. In another embodiment, an offset sidewall can be formed on the side of the first gate G1 before the LDD implantation is performed. The offset sidewall can be formed with reference to existing processes.

[0055] like Figure 2E As shown, in one embodiment, in step S3, by depositing sidewall material, the formed sidewall material layer 130 fills the isolation trench 122 and accumulates above the isolation trench 122, and the height of the sidewall material layer 130 portion located in the source / drain ion implantation region is less than the height of the second gate G2. However, the present invention is not limited thereto, such as... Figure 2FAs shown, in another embodiment, in step S3, by depositing sidewall material, the formed sidewall material layer 130' fills the isolation trench 122 and accumulates above the isolation trench 122, and the height of the portion of the sidewall material layer 130' located in the source / drain ion implantation region is greater than or equal to the height of the second gate G2.

[0056] Reference Figure 1 , Figures 2G to 2J In step S4, a portion of the sidewall material layer and a portion of the gate dielectric layer 110 below the sidewall material layer are removed, exposing the top surfaces of the first gate G1, the second gate G2, and the gate material block 121, as well as the surface of the substrate 100. The sidewall material layer forms a low-voltage device sidewall SP1 located on the side of the first gate G1, a first medium-voltage device sidewall SP2 located within the isolation trench 122, and a second medium-voltage device sidewall SP3 located on the side of the gate material block 121 opposite to the first medium-voltage device sidewall SP2. In some embodiments, step S4 also forms a high-voltage device sidewall located on the side of the third gate in the high-voltage device formation region.

[0057] In one embodiment, step S3 yields the following: Figure 2E The thinner sidewall material layer 130 shown is used as a basis for step S4, which may include the following process: using a self-aligned etching process, the sidewall material layer 130 is etched to expose the top surfaces of the first gate G1, the second gate G2, and the gate material block 121, as well as a portion of the gate dielectric layer 110 surface below the sidewall material layer 130, and the exposed gate dielectric layer 110 is further etched to expose the substrate 100 surface, forming a low-voltage device sidewall SP1 and a second medium-voltage device sidewall SP3, as shown in 2G; and during this process, the sidewall material layer 130 deposited above the isolation trench 122 is etched. By setting appropriate thickness and etching parameters for the sidewall material layer 130, the sidewall material layer 130 in the isolation trench 122 is basically not damaged after the self-aligned etching process is completed, and the first medium-voltage device sidewall SP2 is formed on the side of the second gate G2.

[0058] In another embodiment, step S3 yields the following result: Figure 2F Based on the thicker sidewall material layer 130' shown, step S4 may include the following process:

[0059] Reference Figure 2H A planarization process (such as CMP) is performed to expose the top surfaces of the first gate G1, the second gate G2 and the gate material block 121, and the top surface of the remaining sidewall material layer 130' is flush with the top surface of the second gate G2.

[0060] Then, refer to Figure 2IIn the substrate 100, a patterned mask layer 140 is formed, wherein in the low-voltage device forming region 10, the mask layer 140 covers the surface of the first gate G1 and the surfaces of the partial sidewall material layer 130' on both sides of the first gate G1; in the medium-voltage device forming region 20, the mask layer 140 covers the surfaces of the second gate G2 and the gate material block 121, and also covers the surfaces of the partial sidewall material layer 130' in the isolation groove 122 and outside the gate material block 121 (i.e. on the side away from the second gate G2); in addition, in the high-voltage device forming region, the mask layer 140 can also cover the surface of the third gate and the surfaces of the partial sidewall material layer 130' on both sides of the third gate.

[0061] Then, referring to Figure 2J , the mask layer 140 is used as an etching mask to etch and remove the sidewall material layer 130' and the gate dielectric layer 110 in the regions not covered by the mask layer 140, thereby forming the low-voltage device sidewall SP1 on the side of the first gate G1, the first medium-voltage device sidewall SP2 in the isolation groove 122, and the second medium-voltage device sidewall SP3 on the side of the gate material block 121 opposite to the first medium-voltage device sidewall SP2; in addition, the high-voltage device sidewall on the side of the third gate can also be formed in the high-voltage device forming region.

[0062] Referring to Figure 1 , Figure 2K and Figure 2L , in step S5, source-drain ion implantation is performed to form the first source S1 and the first drain D1 in the low-voltage device forming region 10 on both sides of the first gate G1 and outside the low-voltage device sidewall SP1, and to form the second source S2 and the second drain D2 in the medium-voltage device forming region 20 on both sides of the second gate G2 and outside the second medium-voltage device sidewall SP3.

[0063] The source-drain ion implantation can be n-type implantation or p-type implantation, and when the types of devices to be formed in the low-voltage device forming region 10, the medium-voltage device forming region 20 and the high-voltage device forming region are different, n-type implantation and p-type implantation can be performed respectively. After the source-drain ion implantation is completed, annealing is performed to form the first source S1, the first drain D1, the second source S2 and the second drain D2. In this embodiment, the surface region of the substrate 100 also has the high-voltage device forming region, and the third gate and the high-voltage device sidewall on the side of the third gate are formed in the high-voltage device forming region. Through step S5, the third source and the third drain can also be formed in the high-voltage device forming region on both sides of the third gate and outside the high-voltage device sidewall.

[0064] In one embodiment, step S5 is performed based on the structure shown in Figure 2G , and the structure formed is as shown in Figure 2Kas shown. In another embodiment, step S5 is performed on the basis of the structure as shown in Figure 2J as shown in Figure 2L .

[0065] In the method for forming the semiconductor device described in the above embodiment, the first sidewall SP1 is formed on the first gate G1 side of the low-voltage device formation region 10, and the gate material block 121, the first medium-voltage device sidewall SP2 and the second medium-voltage device sidewall SP3 are formed on the second gate G2 side of the medium-voltage device formation region 20, the gate material block 121, the first medium-voltage device sidewall SP2 and the second medium-voltage device sidewall SP3 together constitute the sidewall structure of the medium-voltage device, by using the sidewall structure, the sidewall thickness of the medium-voltage device can be made larger than the low-voltage device sidewall SP1 while keeping the low-voltage device sidewall SP1 at a proper thin thickness, which can avoid the second gate G2 and the second drain D2 being too close due to the sidewall being too thin, and thus help to avoid the more serious GIDL leakage problem caused by the second gate G2 and the second drain D2 being too close. In addition, when the gate material layer 120 is patterned, the shape of the gate material block 121 can be adjusted so that the isolation trench 122 is wide at the top and narrow at the bottom, which can improve the filling quality of the first medium-voltage device sidewall SP2 formed in the isolation trench 122, and facilitate process control.

[0066] The embodiments of the present application also relate to a semiconductor device. The semiconductor device can be formed by using the method for forming the semiconductor device described in the above embodiment or other methods. Referring to Figure 2K and Figure 2L , the semiconductor device comprises:

[0067] a substrate 100, the surface area of the substrate 100 laterally distributes a low-voltage device formation region 10 and a medium-voltage device formation region 20;

[0068] a first gate G1 formed corresponding to the low-voltage device formation region 10, a low-voltage device sidewall SP1 formed on the side of the first gate G1, and a first source S1 and a first drain D1 formed on both sides of the first gate G1 and outside the low-voltage device sidewall SP1 (i.e. the side away from the first gate G1);

[0069] A second gate G2, a gate material block 121, a first mid-voltage device side wall SP2, a second mid-voltage device side wall SP3, a second source region S2 and a second drain region D2 are formed in the mid-voltage device formation region 20, wherein the gate material block 121 is located on both sides of the corresponding second gate G2, the gate material block 121 and the corresponding second gate G2 have an isolation trench 122 with a wide top and a narrow bottom therebetween, the first mid-voltage device side wall SP2 is filled in the isolation trench 122, the second mid-voltage device side wall SP3 is located on the side of the gate material block 121 opposite to the first mid-voltage device side wall SP2, and the second source region S2 and the second drain region D2 are formed on both sides of the second gate G2 and outside the second mid-voltage device side wall SP3, respectively.

[0070] The semiconductor device further includes a gate dielectric layer 110 located between the first gate G1, the second gate G2 and the substrate 100, and the gate dielectric layer 110 can also be located between the low-voltage device side wall SP1, the first mid-voltage device side wall SP2 and the second mid-voltage device side wall SP3 and the substrate 100. In addition, an LDD region is formed in the substrate 100 in the low-voltage device formation region 10 and the mid-voltage device formation region 20, wherein in the mid-voltage device formation region 20, the LDD region extends from below the end of the second gate G2 to the side of the gate material block 121 away from the second gate G2.

[0071] The substrate 100 can be a silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator substrate, a germanium-silicon-on-insulator substrate or a Ⅲ-Ⅴ compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate), etc., or can be other substrates well known to those skilled in the art for carrying MOS devices, and the substrate 100 can have doped regions and / or isolation structures formed therein. In the embodiment, at least one doped well region can be formed in the substrate 100, and at least one low-voltage device formation region for forming low-voltage devices with a lower operating voltage and at least one mid-voltage device formation region for forming mid-voltage devices with a higher operating voltage can be defined on the top of the substrate 100 by an isolation region (such as a shallow trench isolation (STI)).

[0072] In some embodiments, a high-voltage device formation region (not shown) can also be arranged on the surface region of the substrate 100. The semiconductor device can further include a third gate formed corresponding to the high-voltage device formation region, a high-voltage device side wall formed on the side of the third gate, and a third source region and a third drain region formed on both sides of the third gate and outside the high-voltage device side wall, respectively.

[0073] In an optional embodiment, the part of the gate material block 121 close to the second gate G2 (such as the part of the gate material block 121 close to the second gate G2 shown in FIG. 2) can be removed, and the first mid-voltage device side wall SP2 can be formed on the surface of the substrate 100. Figure 2DThe height of the first material block 121a) shown is less than the portion away from the second gate G2 (as shown by the arrow A1). Figure 2D The height of the second material block 121b) shown is such that the isolation trench 122 is wider at the top and narrower at the bottom, so that the cross-sectional area of the top of the isolation trench 122 is greater than the cross-sectional area of the lower portion of the isolation trench 122, which can improve the quality of the first medium voltage device side wall SP2 formed in the isolation trench 122, and help to improve the performance of the semiconductor device.

[0074] In the semiconductor device described in the above embodiment, the gate material block 121 on the side of the second gate G2, the first medium voltage device side wall SP2 and the second medium voltage device side wall SP3 together form a side wall structure of the medium voltage device formed in the medium voltage device formation region 20. With this side wall structure, the thickness of the side wall of the medium voltage device can be greater than the thickness of the side wall of the low voltage device formed in the low voltage device formation region 10. When the low voltage device side wall SP1 is relatively thin, it can avoid the side wall of the medium voltage device being too thin, which can cause the second gate G2 and the second drain D2 to be too close, and thus help to avoid the problem of more serious GIDL leakage caused by the second gate G2 and the second drain D2 being too close.

[0075] It should be noted that each of the embodiments in the present specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can be mutually referred to.

[0076] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present application without departing from the spirit and scope of the present application, using the methods and technical contents disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the technical solutions of the present application, all fall within the protection scope of the present application.

Claims

1. A method for forming a semiconductor device, characterized by, The method comprises: stacking a gate dielectric layer and a gate material layer on a substrate surface region, which is laterally arranged with low-voltage device forming areas and medium-voltage device forming areas; performing patterning on the gate material layer to form a first gate in the low-voltage device forming areas and a second gate and gate material blocks on both sides of the second gate in the medium-voltage device forming areas, the second gate and the gate material blocks being separated by an isolation trench with a top wide and a bottom narrow; covering the substrate with a sidewall material layer, which fills the isolation trench; and removing part of the sidewall material layer and part of the gate dielectric layer under the sidewall material layer to expose top surfaces of the first gate, the second gate and the gate material blocks and the substrate surface, forming a low-voltage device sidewall on the side of the first gate, a first medium-voltage device sidewall in the isolation trench and a second medium-voltage device sidewall on the side of the gate material block opposite to the first medium-voltage device sidewall from the sidewall material layer; and performing ion implantation of source and drain to form a first source region and a first drain region on both sides of the first gate and outside the low-voltage device sidewall respectively, and a second source region and a second drain region on both sides of the second gate and outside the second medium-voltage device sidewall respectively.

2. The formation method of claim 1, wherein, The substrate surface region is also arranged with high-voltage device forming areas; a third gate is formed in the high-voltage device forming areas when the gate material layer is patterned; a high-voltage device sidewall is formed on the side of the third gate by removing part of the sidewall material layer; and a third source region and a third drain region are formed on both sides of the third gate and outside the high-voltage device sidewall by the ion implantation of source and drain.

3. The formation process of claim 1 wherein, Before stacking the gate dielectric layer on the substrate surface, the method further comprises: performing LDD implantation to form an LDD region in the substrate in the medium-voltage device forming areas, wherein the LDD region extends from below the end of the second gate to the side of the gate material block away from the second gate.

4. The formation process of claim 1 wherein, The patterning of the gate material layer comprises: forming a photoresist layer on the substrate and exposing the photoresist layer with a half-tone mask plate; developing the photoresist layer to form a first photoresist block for defining the first gate, a second photoresist block for defining the second gate and a third photoresist block for defining the gate material blocks, the height of the part of the third photoresist block close to the second photoresist block being less than the height of the part away from the second photoresist block; and using the photoresist layer as an etching mask to etch the gate material layer to form the first gate, the second gate, the gate material blocks and the isolation trench, and the height of the part of the gate material block close to the second gate is less than the height of the part away from the second gate, so that the isolation trench is top wide and bottom narrow.

5. The forming method according to any one of claims 1 to 4, wherein Before removing part of the sidewall material layer, the sidewall material layer fills the isolation trench and piles up above the isolation trench, and the height of the part of the sidewall material layer in the ion implantation region of source and drain is less than the height of the second gate.

6. The formation method of claim 5, wherein, The removing of the part of the sidewall material layer and the part of the gate dielectric layer under the sidewall material layer comprises: The sidewall material layer is etched by a self-aligned etching process to expose the top surfaces of the first gate, the second gate and the gate material block and the part of the gate dielectric layer surface under the sidewall material layer, and further etch the exposed gate dielectric layer to expose the substrate surface.

7. The forming method according to any one of claims 1 to 4, wherein Before the part of the sidewall material layer is removed, the sidewall material layer fills the isolation trench and piles up above the isolation trench, and the height of the part of the sidewall material layer located at the source / drain ion implantation region is greater than or equal to the height of the second gate.

8. The formation method of claim 7, wherein, The removing of the part of the sidewall material layer and the part of the gate dielectric layer under the sidewall material layer comprises: A planarization process is performed to expose the top surfaces of the first gate, the second gate and the gate material block, and the top surface of the remaining sidewall material layer is flush with the top surface of the second gate; A patterned mask layer is formed on the substrate, which covers the surface of the first gate and the part of the sidewall material layer surface on both sides of the first gate in the low-voltage device formation area, and covers the surfaces of the second gate and the gate material block, the sidewall material layer surface in the isolation trench and the part of the sidewall material layer surface outside the gate material block in the medium-voltage device formation area; and The sidewall material layer and the gate dielectric layer in the area not covered by the mask layer are removed using the mask layer as an etching mask to form the low-voltage device sidewall, the first medium-voltage device sidewall and the second medium-voltage device sidewall.

9. A semiconductor device, characterized by comprising: It comprises: A substrate, the surface area of which is laterally distributed with low-voltage device formation areas and medium-voltage device formation areas; A first gate formed corresponding to the low-voltage device formation area, a low-voltage device sidewall formed on the side of the first gate, and a first source region and a first drain region respectively formed on both sides of the first gate and outside the low-voltage device sidewall; and A second gate, a gate material block, a first medium-voltage device sidewall, a second medium-voltage device sidewall, a second source region and a second drain region formed corresponding to the medium-voltage device formation area, wherein the gate material block is located on both sides of the corresponding second gate, and there is an isolation trench with a top wide and a bottom narrow between the gate material block and the corresponding second gate, the first medium-voltage device sidewall fills in the isolation trench, the second medium-voltage device sidewall is located on the side of the gate material block opposite to the first medium-voltage device sidewall, and the second source region and the second drain region are respectively formed on both sides of the second gate and outside the second medium-voltage device sidewall.

10. The semiconductor device according to claim 9, wherein The substrate is further provided with a high-voltage device formation area; and the semiconductor device further comprises a third gate formed corresponding to the high-voltage device formation area, a high-voltage device sidewall formed on the side of the third gate, and a third source region and a third drain region respectively formed on both sides of the third gate and outside the high-voltage device sidewall.

11. The semiconductor device according to claim 9, wherein A height of a portion of the gate material mass proximate the second gate is less than a height of a portion of the gate material mass distal the second gate, such that the isolation trench and the first mid-voltage device sidewall are wider at a top and narrower at a bottom.

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