High-speed large-size pixel unit for improving charge transfer efficiency and image sensor

By designing a PPD-TG-FD pixel unit with dual PPDs and dual transfer gates, and employing a semi-gear-shaped PPD and complementary toothed P-regions, combined with gradient doping and a dual transfer gate structure, the problem of slow charge transfer speed in large-size pixels was solved, achieving high-speed charge transfer and efficient imaging.

CN121463554APending Publication Date: 2026-02-03TIANJIN UNIV
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Patent Information

Application Number
CN202511328066.8
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-09-17
Publication Date
2026-02-03

AI Technical Summary

Technical Problem

The existing large-size pixels have slow and incomplete charge transfer speeds, making it difficult to meet the requirements of ultra-high frame rate imaging.

Method used

The PPD-TG-FD pixel unit, based on dual PPDs and dual transfer gates, is designed as a semi-gear-shaped PPD and a complementary tooth-shaped P region. Combined with gradient doping and dual transfer gate structure, it improves the electric field driving force, shortens the charge transfer distance, and reduces the potential barrier.

Benefits of technology

It achieves high-speed charge transfer efficiency for large-size pixels, improves photocharge detection and collection efficiency in ultra-high frame rate imaging, and reduces dark current.

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Abstract

The invention discloses a high-speed large-size pixel unit capable of improving charge transfer efficiency and an image sensor. The high-speed large-size pixel unit is a PPD-TG-FD pixel unit based on double PPDs and double transmission gates, and comprises two symmetrically distributed half-gear-shaped PPDs forming an N region, a complementary tooth-shaped P region matched with the half-gear-shaped PPDs, and an FD located at a pixel center position between the two half-gear-shaped PPDs; a first transmission gate TG1 and a second transmission gate TG2 are arranged between the FD and each half-gear-shaped PPD in a spaced mode, the two first transmission gates TG1 and the two second transmission gates TG2 are symmetrically arranged, the second transmission gates TG2 are arranged close to the half-gear-shaped PPD, and the first transmission gates TG1 are arranged close to the FD. Through the special design of the PPD shape, the doping process and the transmission gate, the charge transfer efficiency of large-size pixels is improved, so that the photoelectric charge detection and collection efficiency of ultrahigh frame rate imaging is improved.
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Description

Technical Field

[0001] This invention relates to the field of CMOS image sensor (CIS) technology, and in particular to a high-speed, large-size pixel unit and image sensor with improved charge transfer efficiency. Background Technology

[0002] With advancements in CMOS technology, CIS (CMOS Image Sensors) employing clamped photodiodes (PPDs) have gradually captured the mainstream image sensor market due to their advantages such as low noise levels, low cost, high quantum efficiency, and low dark current. In specialized applications such as medical, industrial production, and scientific research, many ultra-high-speed phenomena exist, including shock waves, microbubbles, breakdown, high-speed collisions, discharges, explosions, and material fractures. Therefore, ultra-high-speed imaging is essential for analyzing rapid transient events.

[0003] Ultra-high-speed image sensors can directly capture these rapidly changing details by imaging at rates exceeding one million frames per second. The higher the frame rate, the shorter the pixel exposure time of the image sensor chip; however, extremely short exposure times can lead to insufficient photon counts, necessitating the use of pixels with larger photosensitive areas for compensation. Therefore, in the field of ultra-high frame rate imaging, large-size pixels still hold significant research and application value.

[0004] The main problem with large-size pixels currently lies in the flat potential gradient within the PPD (Photogenerated Diode), resulting in a low speed of photogenerated charge transfer along the potential path. This prevents the charge from being transferred to the floating diffusion node (FD) via the transfer gate (TG) in a short time. If the charge transfer time within the pixel is too long, it limits the imaging frame rate; if the transfer time is insufficient, the charge remaining in the PPD will participate in the imaging of the next frame, causing image trailing. Therefore, optimizing the PPD-TG-FD design for large pixels and improving its charge transfer efficiency is key to achieving high-performance imaging.

[0005] To address the aforementioned issues, existing research primarily focuses on maximizing pixel photosensitive size while improving the shape and manufacturing process design of large-size photodiodes (PPDs) to achieve rapid and complete charge transfer. Regarding PPD shape design, the clamping voltage modulation effect is utilized: the wider the N-zone, the higher the depletion potential. Therefore, designing a gradually widening N-zone shape along the charge transport path establishes a potential gradient, thereby creating a transverse electric field that accelerates charge movement along this path. Based on this principle, designing traditional rectangular PPDs as triangular, flared, or trapezoidal structures can effectively improve the transfer speed of photogenerated charges within the pixel. Combining these different geometries yields PPDs with larger areas and more complex shapes, facilitating efficient charge transfer in large-size pixels. In terms of PPD manufacturing process design, gradient doping is employed to create a vertical potential gradient in the N-well of the PPD, prompting photogenerated charges at the bottom of the PPD to move rapidly towards the top.

[0006] The above-mentioned improved method can meet the requirement that the photosensitive area does not exceed 10×10μm. 2 The charge transfer efficiency of pixels is required, but for pixels with larger photosensitive areas (hundreds of square micrometers), the improvement effect is very limited and it is difficult to meet the requirements of charge transfer efficiency under ultra-high frame rate imaging conditions. Summary of the Invention

[0007] The purpose of this invention is to address the problems of slow and incomplete charge transfer speed in large-size pixels by providing a high-speed large-size pixel unit and image sensor with improved charge transfer efficiency. It is based on a PPD-TG-FD pixel unit with dual PPDs and dual transfer gates. Through special design of PPD shape, doping process and transfer gate, the charge transfer efficiency of large-size pixels is improved, thereby improving the photocharge detection and collection efficiency of ultra-high frame rate imaging.

[0008] One objective of this invention is to provide a high-speed, large-size pixel unit with improved charge transfer efficiency. The high-speed, large-size pixel unit is a PPD-TG-FD pixel unit based on two PPDs and two transmission gates. It includes two symmetrically distributed semi-gear-shaped PPDs forming an N-region, a complementary toothed P-region cooperating with the semi-gear-shaped PPDs, and an FD located at the pixel center between the two semi-gear-shaped PPDs. A first transmission gate TG1 and a second transmission gate TG2 are arranged at intervals between the FD and each semi-gear-shaped PPD. The two first transmission gates TG1 and the two second transmission gates TG2 are symmetrically arranged, with the second transmission gates TG2 positioned near the semi-gear-shaped PPDs and the first transmission gates TG1 positioned near the FD.

[0009] The N region of the semi-gear-shaped PPD is formed by the overlapping of the semi-gear-shaped N1 region, the semi-gear-shaped N2 region, and the semi-gear-shaped N3 region from the center outwards. The semi-gear-shaped N1 region is placed inside the semi-circle of the semi-gear-shaped N2 region, and the semi-gear-shaped N2 region is placed inside the semi-circle of the semi-gear-shaped N3 region.

[0010] Among them, the semi-gear-shaped N1 region, semi-gear-shaped N2 region, and semi-gear-shaped N3 region form a stepped structure with progressively increasing ion implantation depth from the outside to the center.

[0011] Among them, complementary teeth constituting complementary tooth-shaped P regions are arranged in the N3 tooth groove of the semi-gear-shaped N3 region. Each N3 tooth groove has one complementary tooth. The complementary tooth is T-shaped, with its large end away from the bottom of the tooth groove and its small end close to the bottom of the tooth groove.

[0012] The semi-gear-shaped PPD is topped by a P-type heavily doped clamping layer p. +The region was formed by boron difluoride ion implantation, the semi-cog-shaped N1 region and the semi-cog-shaped N2 region were formed by phosphorus ion implantation, the semi-cog-shaped N3 region was formed by arsenic ion implantation, and the complementary tooth-shaped P region was formed by boron ion implantation.

[0013] The first transfer gate TG1 and the second transfer gate TG2 are connected through a local N-type doped region. The first transfer gate TG1 is connected to the FD, and the second transfer gate TG2 is connected to the semi-gear-shaped PPD.

[0014] Wherein, the first transmission gate TG1 is a short gate, and the second transmission gate TG2 is a long gate in the shape of a U. The second transmission gate TG2 forms a semi-enclosed structure on the adjacent side of the first transmission gate TG1.

[0015] A second objective of the present invention is to provide an image sensor including the aforementioned high-speed, large-size pixel unit.

[0016] The high-speed, large-size pixel unit proposed in this invention, which improves charge transfer efficiency, is based on a PPD-TG-FD pixel unit with dual PPDs and dual transfer gates. Specifically, the PPD-TG-FD pixel unit employing a semi-gear-shaped PPD and dual transfer gate structure not only significantly expands the pixel size but also enhances the charge transfer speed by strengthening the electric field driving force. Furthermore, the wide-toothed N-region design at the edge reduces pixel dark current; the dual-layer transfer gate design lowers the PPD-TG charge transfer barrier, preventing incomplete charge transfer. Ultimately, this invention achieves high-speed charge transfer efficiency for large-size pixels, thereby improving the imaging performance of ultra-high frame rate image sensors. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a PPD-TG-FD pixel unit based on a semi-gear-shaped PPD and a dual transmission gate structure, according to an embodiment of the present invention.

[0018] Figure 2 This is a cross-sectional view of the dual transmission gate PPD-TG-FD pixel unit according to an embodiment of the present invention.

[0019] Figure 3 This is a cross-sectional view of the doped N-region and complementary P-region of the semi-gear-shaped PPD according to an embodiment of the present invention.

[0020] Figure 4 This is a schematic diagram of the dual transmission gate operating voltage and PPD charge transfer in an embodiment of the present invention. Detailed Implementation

[0021] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0022] See Figure 1 As shown in the exemplary embodiment of this application, the high-speed large-size pixel unit is a PPD-TG-FD pixel unit based on dual PPDs and dual transfer gates, including two symmetrically distributed semi-gear-shaped PPDs forming an N-region, a complementary toothed P-region cooperating with the semi-gear-shaped PPDs, and an FD located at the center of the pixel between the two semi-gear-shaped PPDs; a first transfer gate TG1 and a second transfer gate TG2 are arranged separately from each semi-gear-shaped PPD, the two first transfer gates TG1 and the two second transfer gates TG2 are arranged symmetrically, and the second transfer gates TG2 are arranged near the semi-gear-shaped PPDs, the first transfer gates TG1 are arranged near the FD, and the first transfer gates TG1 and the second transfer gates TG2 are connected through an N-type doped region.

[0023] In this embodiment, the photosensitive element (FD) is placed at the center of the pixel, with two symmetrically distributed semi-gear-shaped photosensitive elements (PPDs) located on either side, sharing the same charge-to-voltage conversion node. By placing the FD at the center of the photosensitive area, the average and maximum distances for charge transfer to the FD are shortened, thus improving the charge transfer speed. To improve pixel conversion gain, existing FDs typically employ smaller geometric dimensions, resulting in narrower transmission channels in traditional single-TG (transmission gate) structures, limiting the charge transfer speed. Simultaneously, a potential barrier easily forms on one side of the PPD in the TG, further reducing charge transfer efficiency. Using a dual-transmission gate effectively solves this problem. In this embodiment, the photosensitive area of ​​a large pixel is divided into symmetrical PPD1 and PPD2, which share a single FD located at the pixel center. The N-region of the PPD adopts a semi-gear shape design. By adjusting the width and spacing of the edge-toothed N-region and the complementary-toothed P-region, the pixel edge is still occupied by the depleted area, becoming an effective photosensitive area.

[0024] In this embodiment, the N region of the semi-gear-shaped PPD is formed by the overlapping of the semi-gear-shaped N1 region, the semi-gear-shaped N2 region, and the semi-gear-shaped N3 region from the center outwards. The semi-gear-shaped N1 region is placed inside the semi-circle of the semi-gear-shaped N2 region, and the semi-gear-shaped N2 region is placed inside the semi-circle of the semi-gear-shaped N3 region.

[0025] In this embodiment, the semi-gear-shaped N1 region, semi-gear-shaped N2 region, and semi-gear-shaped N3 region form a stepped structure with progressively increasing ion implantation depth from the outside to the center.

[0026] In this embodiment of the application, complementary teeth constituting complementary tooth-shaped P regions are arranged in the N3 tooth groove of the semi-gear-shaped N3 region. Each N3 tooth groove has one complementary tooth. The complementary tooth has a T-shaped opening, with its large end away from the bottom of the tooth groove and its small end close to the bottom of the tooth groove.

[0027] The N3 slot adopts a wide-tooth structure. Through the design of a wide-tooth PPD and a complementary toothed P-region, the driving force of the edge electric field can be improved. The design principle is as follows: First, this invention utilizes the clamping voltage modulation effect to design the edge of the semi-gear-shaped PPD as a wide-tooth N-region structure, increasing the width variation of the N-region and improving the potential gradient of the internal transverse electric field. Furthermore, since the sharp PPD shape can lead to dark current, the wide-spacing design at the top of the N-region can reduce dark current. Second, based on the built-in potential difference V of the PN junction... D formula:

[0028]

[0029] Where q is the charge of the electron, k0 is the Boltzmann constant, and n D and n A These are the concentrations of N-type and P-type doping, respectively, n i It is the intrinsic carrier concentration of silicon material at temperature T.

[0030] The above equation shows that increasing the doping concentration of the P-region can improve the built-in potential difference of the PN junction. Therefore, adding a toothed P-region ion implantation layer to the P-substrate region complementary to the N-region helps to strengthen the edge electric field of the PPD, thereby increasing the drift speed of photogenerated charges moving to the N-region.

[0031] In this embodiment, the p-type heavily doped clamping layer is located above the semi-gear-shaped PPD. + Located on the surface of the semi-gear-shaped PPD, it is formed by boron difluoride ion implantation. The semi-gear-shaped N1 region and the semi-gear-shaped N2 region of the N region of the semi-gear-shaped PPD are each formed by phosphorus ion implantation, the semi-gear-shaped N3 region is formed by arsenic ion implantation, and the complementary tooth-shaped P region is formed by boron ion implantation.

[0032] Specifically, in the embodiments of this application, the ion implantation layer of the PPD includes a p-type heavily doped clamping layer (p + The system consists of N-type ion implantation layers N1, N2, and N3, and a complementary serrated P-region implantation layer. The N-region employs three layers with different ion implantation ranges. Figure 2 for Figure 1 A pixel cell profile along curve AA', where layer N3 contains layer N2, and layer N2 contains layer N1. Figure 3 for Figure 1 The PPD cross-section along the BB' curve shows the PN junction structure formed by the N3 region and the complementary P region of the PPD. The ion implantation of the above five layers is as follows:

[0033] (1)p + The layer was implanted with boron difluoride ions at a dose of 5 × 10⁻⁶. 12 cm -2 The energy is 15keV;

[0034] (2) Phosphorus ion implantation was performed on the N1 layer at a dose of 4 × 10⁻⁶. 11 cm -2 The energy is 900 keV;

[0035] (3) The N2 layer was implanted with phosphorus ions at a dose of 5 × 10⁻⁶. 11 cm -2 The energy is 600keV;

[0036] (4) The N3 layer was implanted with arsenic ions at a dose of 2 × 10⁻⁶. 12 cm -2 The energy is 150keV;

[0037] (5) Boron ion implantation is used for the complementary dentate P region. To ensure uniform ion distribution, multiple implantations with the same dose can be performed, such as at a dose of 1×10⁻⁶. 12 cm -2 The energy levels are 90, 150, and 350 keV.

[0038] In this embodiment, the first transfer gate TG1 and the second transfer gate TG2 are connected by a local N-type doped region. The local N-type doped region connects the channels under the two transfer gates to form a continuous charge transfer channel. The first transfer gate TG1 is connected to the FD, and the second transfer gate TG2 is connected to the semi-gear-shaped PPD.

[0039] In this embodiment, the first transmission gate TG1 is a short gate, and the second transmission gate TG2 is a long gate in the shape of a U. The second transmission gate TG2 forms a semi-enclosed structure on the adjacent side of the first transmission gate TG1.

[0040] Figure 4 This diagram illustrates the dual transfer gate operating voltage and corresponding PPD charge transfer in an embodiment of this application. In this embodiment, in the dual transfer gate structure, TG1 is close to the FD. Due to the small size of the FD, TG1 on the side closest to the FD is typically designed as a short gate to meet the small size requirements of the FD. TG2 is close to the PPD, and TG2 on the side closest to the PPD can be designed as a long gate to increase the contact area with the PPD. The longer gate helps drive the PPD charge to transfer to the FD node. Simultaneously, TG2 can penetrate deep into the N-region to fully contact the PPD, reducing the charge barrier between the PPD and TG, and accelerating the movement of charge transferred from the semi-circular N-region. TG2 and TG1 are connected by an N-type doped region. This local N-type doped region connects the channels under the two transfer gates, forming a continuous charge transfer channel, eliminating a significant barrier between the two adjacent gates. Therefore, the dual-layer transfer gate design allows the charge gathered in the central region of the PPD to be quickly and completely transferred to the FD. Furthermore, when the pixel size is further increased, the number of transfer gates in the central region can be further increased. The working process of the dual transfer gate is as follows:

[0041] When the PPD resets or the signal charge within the PPD begins to transfer at 100 ns, TG1 and TG2 are simultaneously turned on at 100 ns. To create a potential gradient where TG1 is higher than TG2, allowing the charge to be rapidly transferred to the FD through the two transmission gate channels, the voltage of TG1 must be higher than that of TG2. For example, the voltage of TG1 can be set to 3.3V and the voltage of TG2 can be set to 2.8V. When the charge transfer ends, the turn-off of TG1 must lag behind that of TG2. For example, TG2 can be turned off at 500 ns and TG1 can be turned off at 550 ns, thus ensuring that the charge in the region between TG1 and TG2 is completely transferred out.

[0042] See Figure 2 As shown, when the double-layer transmission gate is turned on, the photogenerated charge generated at the far end of TG is directed along the gradient electric field. Figure 2 The transition from path CC' to FD occurs as follows:

[0043] First, see Figure 3 As shown, since the toothed N-region extending to the four corners of the pixel forms a PN junction with its complementary toothed P-region, the photogenerated charge moves to the N-region under the action of the built-in electric field of the edge PN junction, and moves to the semi-circular region along the potential gradient of the N-region; secondly, the photogenerated charge in the semi-circular N-region moves to the vicinity of the transfer gate TG under the action of the transverse electric field formed by the gradient doping at different levels; finally, the photogenerated charge gathered on one side of the PPD is transferred to the FD by the potential pull of the transfer gate channel.

[0044] In summary, the PPD-TG-FD structure applicable to large-sized pixels in this application significantly shortens the charge transfer distance by placing the FD at the center of the pixel; the PPD is designed in a semi-gear shape to enhance the transverse electric field inside the N region, and a complementary toothed P region injection layer is added to strengthen the edge electric field; a transfer gate is added to the central semi-circular N region to reduce the charge transfer barrier, thereby improving the charge transfer efficiency.

[0045] This application embodiment further provides an image sensor, including the aforementioned high-speed large-size pixel unit.

[0046] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. It will be apparent to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention.

[0047] Therefore, the embodiments should be regarded as exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of the equivalents of the claims be included within the invention.

[0048] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A high-speed, large-size pixel unit with improved charge transfer efficiency, characterized in that, The high-speed, large-size pixel unit is a PPD-TG-FD pixel unit based on dual PPDs and dual transmission gates. It includes two symmetrically distributed semi-gear-shaped PPDs forming an N region, a complementary toothed P region that cooperates with the semi-gear-shaped PPDs, and an FD located at the center of the pixel between the two semi-gear-shaped PPDs. A first transmission gate TG1 and a second transmission gate TG2 are arranged at intervals between the FD and each semi-gear-shaped PPD. The two first transmission gates TG1 and the two second transmission gates TG2 are arranged symmetrically, with the second transmission gates TG2 arranged near the semi-gear-shaped PPDs and the first transmission gates TG1 arranged near the FD.

2. The high-speed, large-size pixel unit for improving charge transfer efficiency according to claim 1, characterized in that, The N region of the semi-gear-shaped PPD is formed by the overlapping of the semi-gear-shaped N1 region, the semi-gear-shaped N2 region, and the semi-gear-shaped N3 region from the center outwards. The semi-gear-shaped N1 region is placed inside the semi-circle of the semi-gear-shaped N2 region, and the semi-gear-shaped N2 region is placed inside the semi-circle of the semi-gear-shaped N3 region.

3. The high-speed, large-size pixel unit for improving charge transfer efficiency according to claim 2, characterized in that, The semi-gear-shaped N1 region, semi-gear-shaped N2 region, and semi-gear-shaped N3 region form a stepped structure with progressively increasing ion implantation depth from the outside to the center.

4. The high-speed, large-size pixel unit for improving charge transfer efficiency according to claim 3, characterized in that, The N3 tooth groove of the semi-gear-shaped N3 region is provided with complementary teeth that constitute the complementary tooth-shaped P region. Each N3 tooth groove is provided with one complementary tooth. The complementary tooth is T-shaped, with its large end away from the bottom of the tooth groove and its small end close to the bottom of the tooth groove.

5. The high-speed, large-size pixel unit for improving charge transfer efficiency according to claim 4, characterized in that, Above the semi-gear-shaped PPD is a P-type heavily doped clamping layer. + The region was formed by boron difluoride ion implantation, the semi-cog-shaped N1 region and the semi-cog-shaped N2 region were formed by phosphorus ion implantation, the semi-cog-shaped N3 region was formed by arsenic ion implantation, and the complementary tooth-shaped P region was formed by boron ion implantation.

6. The high-speed, large-size pixel unit for improving charge transfer efficiency according to claim 1, characterized in that, The first transfer gate TG1 and the second transfer gate TG2 are connected through a local N-type doped region. The first transfer gate TG1 is connected to FD, and the second transfer gate TG2 is connected to a semi-gear-shaped PPD.

7. The high-speed, large-size pixel unit for improving charge transfer efficiency according to claim 6, characterized in that, The first transmission gate TG1 is a short gate, and the second transmission gate TG2 is a long gate in the shape of a U. The second transmission gate TG2 forms a semi-enclosed structure on the adjacent side of the first transmission gate TG1.

8. An image sensor, characterized in that, Includes the high-speed large-size pixel unit as described in any one of claims 1-7.