CMOS integrated circuit and preparation method
By employing a transistor layer structure arranged vertically and internally doped with carbon nanotubes in CMOS integrated circuits, the problem of simultaneous doping of carbon nanotubes was solved, reducing the difficulty and cost of the process and improving performance.
Patent Information
- Application Number
- CN202511445323.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-10
- Publication Date
- 2026-02-03
AI Technical Summary
In existing CMOS integrated circuits, it is difficult to achieve both n-type and p-type doping of carbon nanotubes simultaneously, and carbon-based NMOS transistors have poor performance, resulting in high process difficulty and increased cost.
The transistors are arranged in a vertically arranged structure. The first transistor layer is a silicon-based NMOS or PMOS, and the second transistor layer is a carbon-based PMOS or NMOS. They are doped with internally doped carbon nanotubes and connected by metal interconnects to avoid the impact of high-temperature processes on the lower transistors.
This reduces the process difficulty and manufacturing cost of CMOS integrated circuits, while improving overall performance and avoiding the problem of low on-state current in carbon-based NMOS transistors.
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Figure CN121463631A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a CMOS integrated circuit and its fabrication method. Background Technology
[0002] As semiconductor technology continues to shrink to nodes below 3 nm, silicon-based integrated circuits face limitations imposed by silicon materials and quantum mechanics, hindering the continuation of Moore's Law. There is an urgent need for materials with potential and advantages to provide superior electrical performance and break through the limits of Moore's Law. Carbon nanotubes (CNTs), due to their high mobility, better scalability, and low power consumption, are considered one of the best channel materials for building field-effect transistors in integrated circuits in the future.
[0003] Compared to carbon-based PMOS transistors, the development of carbon-based NMOS transistors has been relatively slow. Therefore, current CMOS integrated circuits are all formed using silicon-based PMOS transistors and silicon-based NMOS transistors. Furthermore, existing technologies have attempted to improve performance by enhancing the contact metal between carbon nanotubes and the metal, or by doping the carbon nanotubes, but these methods still fail to achieve the desired results. Additionally, in doping methods, effective doping is difficult to achieve due to the lack of dangling bonds on the sides of carbon nanotubes. Summary of the Invention
[0005] This disclosure presents a CMOS integrated circuit and a method for fabricating the same.
[0006] According to one aspect of this disclosure, a CMOS integrated circuit is provided, comprising: N transistor layers, N≥2, wherein the N transistor layers are arranged vertically in the vertical direction of the CMOS integrated circuit, the N transistor layers comprising: a first transistor layer located at the bottom layer of the CMOS integrated circuit, wherein a first type field-effect transistor is formed in the first transistor layer; and M second transistor layers disposed above the first transistor layer, wherein the M second transistor layers are arranged vertically in the vertical arrangement, wherein M=N-1, and each of the M second transistor layers is formed with a first type field-effect transistor. The first type field-effect transistor (FET) and at least one of the M second transistor layers is formed with a second type FET; and a metal interconnect for interconnecting the source, drain, and / or gate of the FET in the first transistor layer with the source, drain, and / or gate of the FET in the M second transistor layers, respectively, wherein the first type FET and the second type FET are one of an NMOS transistor and a PMOS transistor, respectively, the FET in the M second transistor layers is a carbon-based FET, and the FET in the first transistor layer is a silicon-based FET or a carbon-based FET.
[0007] This technical solution addresses the challenges of simultaneously and precisely achieving n-type and p-type doping on the same carbon nanotube, as well as the difficulty of laying these doped nanotubes flat on a substrate as required. The top-and-bottom arrangement facilitates the fabrication of CMOS integrated circuits. The field-effect transistors in the second transistor layer are carbon-based, avoiding silicon-based transistors. This prevents the high temperatures of the ion implantation process in silicon-based transistor fabrication from damaging the metal interconnects of the underlying transistors. Specifically, by configuring silicon-based NMOS transistors in the first transistor layer and carbon-based PMOS transistors in the second, the performance of the CMOS integrated circuit is maintained while reducing fabrication complexity and cost. While silicon-based transistors are easier to fabricate, their processes are more complex; combining them with carbon-based transistors achieves a balance between fabrication difficulty and cost. Meanwhile, carbon-based NMOS transistors have poor performance, exhibiting a small on-state current. By replacing carbon-based NMOS transistors with silicon-based or two-dimensional material NMOS transistors and combining them with carbon-based PMOS transistors to form CMOS integrated circuits, the problem of small on-state current of carbon-based NMOS transistors can be avoided, thereby improving the overall performance of CMOS integrated circuits.
[0008] According to at least one embodiment of the CMOS integrated circuit of the present disclosure, the channel material in the carbon-based field-effect transistor is an internally doped carbon nanotube, wherein the internal doping is used to realize the n-type doping of the NMOS transistor or the p-type doping of the PMOS transistor.
[0009] According to the technical solution of this embodiment, internally doped carbon nanotubes are used. Compared with externally doped carbon nanotubes, internally doped carbon nanotubes can ensure the stability of doping.
[0010] According to at least one embodiment of the CMOS integrated circuit of the present disclosure, the n-type doped doping material includes C-amyl. 60 , basification C 60 Or a one-dimensional Sn-based perovskite; and the p-type doped material includes C 60 Or one-dimensional Pb-based perovskites containing halide vacancies.
[0011] According to the technical solution of this embodiment, the internal doping concentration of perovskite materials can be precisely controlled, but using C 60 Compared to perovskite materials, internally doped materials exhibit higher stability.
[0012] According to at least one embodiment of the CMOS integrated circuit of the present disclosure, an isolation layer is disposed between adjacent transistor layers of the first transistor layer and M second transistor layers, the material of the isolation layer being the substrate material of the field-effect transistor.
[0013] According to at least one embodiment of the CMOS integrated circuit of the present disclosure, the source-drain direction angle θ of the field-effect transistors in the first transistor layer and the second transistor layer are configured as 0° < θ < 180° or θ = 0°.
[0014] According to the technical solution of this embodiment, when 0° < θ < 180°, a larger installation space for metal interconnects can be provided.
[0015] According to at least one embodiment of the CMOS integrated circuit of the present disclosure, the CMOS integrated circuit includes a first transistor layer and a second transistor layer, wherein the field effect transistor in the first transistor layer is a silicon-based NMOS transistor and the field effect transistor in the second transistor layer is a carbon-based PMOS transistor.
[0016] According to another aspect of this disclosure, a method for fabricating a CMOS integrated circuit is provided, comprising: fabricating a first transistor layer on a substrate, wherein a field-effect transistor (FET) is formed in the first transistor layer, the FET being a first type FET, and having a channel layer, a source, a drain, and a gate, and having metal interconnects for at least one of the source, drain, and gate; filling a substrate material and performing a first planarization treatment on the upper surface of the substrate material, wherein the upper surface of the filled substrate material extends beyond the upper surface of the first type FET; and fabricating a second transistor layer on the upper surface of the first planarized substrate material, wherein a FET is formed in the second transistor layer, the FET being a second type FET. The second transistor layer has a field-effect transistor having a channel layer, a source, a drain, and a gate, and having metal interconnects formed for at least one of the source, drain, and gate, and the metal interconnects of the first transistor layer and the second transistor layer are correspondingly connected; and a substrate material is filled and the upper surface of the substrate material is subjected to a second planarization process, wherein the upper surface of the filled substrate material exceeds the upper surface of the field-effect transistor of the second transistor layer, wherein the first type field-effect transistor and the second type field-effect transistor are respectively an NMOS transistor and a PMOS transistor, the field-effect transistor of the second transistor layer is a carbon-based field-effect transistor, and the field-effect transistor of the first transistor layer is a silicon-based field-effect transistor or a carbon-based field-effect transistor.
[0017] According to at least one of the preparation methods of the present disclosure, the channel material of the channel layer of the carbon-based field-effect transistor is an internally doped carbon nanotube. When the carbon-based field-effect transistor is an NMOS transistor, the internally doped carbon nanotube is an n-type doped carbon nanotube. When the carbon-based field-effect transistor is a PMOS transistor, the internally doped carbon nanotube is a p-type doped carbon nanotube.
[0018] According to at least one method of preparation of the present disclosure, the preparation of the n-type doped carbon nanotubes includes: obtaining aminated C 60 or alkali metallization C 60 Aminated C 60 or alkali metallization C 60 Dissolved in an aromatic solvent to obtain a saturated solution; carbon nanotubes are added to the saturated solution, and the aminated C... 60 or alkali metallization C 60 Deposition inside carbon nanotubes; and removal of aminated C from the outer surface of carbon nanotubes. 60 or alkali metallization C 60 The n-type doped carbon nanotubes were obtained.
[0019] According to at least one method of preparation of the present disclosure, the preparation of the p-type doped carbon nanotubes includes: preparing C60 Dissolved in an aromatic solvent to obtain a saturated solution; carbon nanotubes are added to the saturated solution, wherein the C... 60 Deposition inside carbon nanotubes; and removal of C from the outer surface of carbon nanotubes. 60 The p-type doped carbon nanotubes were obtained. Attached Figure Description
[0020] The accompanying drawings illustrate exemplary embodiments of the present disclosure and, together with the description thereof, serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.
[0021] Figure 1 This is the structure of a field-effect transistor in a CMOS integrated circuit according to an embodiment of the present disclosure.
[0022] Figure 2 It is a cross-shaped structure at an angle of the field-effect transistor of a CMOS integrated circuit according to an embodiment of the present disclosure.
[0023] Figure 3 It is a cross-shaped structure of the field-effect transistor of a CMOS integrated circuit according to one embodiment of the present disclosure.
[0024] Figure 4 This is an angled structure of a field-effect transistor in a CMOS integrated circuit according to an embodiment of the present disclosure.
[0025] Figures 5 to 8 A method for fabricating a CMOS integrated circuit according to an embodiment of the present disclosure is shown.
[0026] Figure 9 A method for fabricating a CMOS integrated circuit according to an embodiment of the present disclosure is shown.
[0027] Figure 10 A method for fabricating a CMOS integrated circuit according to an embodiment of the present disclosure is shown.
[0028] Figure 11 A flowchart illustrating a method for preparing p-type doped carbon nanotubes according to an embodiment of the present disclosure is shown.
[0029] Figure 12 A flowchart illustrating a method for preparing p-type doped carbon nanotubes according to an embodiment of the present disclosure is shown.
[0030] Figure 13 A flowchart illustrating a method for preparing n-type doped carbon nanotubes according to an embodiment of the present disclosure is shown.
[0031] Figure 14A flowchart illustrating a method for preparing n-type doped carbon nanotubes according to an embodiment of the present disclosure is shown. Detailed Implementation
[0032] The present disclosure will now be described in further detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are for illustrative purposes only and are not intended to limit the scope of the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present disclosure are shown in the accompanying drawings.
[0033] It should be noted that, where there is no conflict, the embodiments and features described in this disclosure can be combined with each other. The technical solutions of this disclosure will now be described in detail with reference to the accompanying drawings and embodiments.
[0034] Due to the inherent limitations of silicon, as semiconductor processes continue to scale down to nodes below 3 nm, they will face even greater challenges, making it difficult to break through the limits of Moore's Law. Therefore, the development of silicon-based devices will be significantly restricted. Current CMOS integrated circuits are all composed of silicon-based field-effect transistors; similarly, the future development of such CMOS integrated circuits will also be limited. Carbon-based devices formed from carbon nanotubes are not limited by Moore's Law; therefore, carbon nanotubes are considered one of the best channel materials for constructing field-effect transistors in future integrated circuits.
[0035] Extensive research has been conducted on carbon nanotubes. They are used as channel materials in the formation of PMOS and NMOS transistors for CMOS integrated circuits. However, it is difficult to precisely achieve both n-type and p-type doping simultaneously on the same carbon nanotube, and it is also challenging to lay both n-type and p-type doped carbon nanotubes evenly on the substrate as required.
[0036] Therefore, this disclosure proposes a technical solution for a CMOS integrated circuit incorporating carbon-based field-effect transistors. In this technical solution, the field-effect transistors are arranged in a vertically stacked manner to form the CMOS integrated circuit. This eliminates the need to simultaneously achieve n-type doping (for NMOS transistors) and p-type doping (for PMOS transistors) on the same carbon nanotube, and also eliminates the need to lay the n-type and p-type doped carbon nanotubes flat onto the substrate as required. In this disclosure, NMOS transistors and PMOS transistors are fabricated in layers, and then the CMOS integrated circuit is fabricated through metal interconnects.
[0037] According to embodiments of this disclosure, a CMOS (Complementary Metal Oxide Semiconductor) device is provided. Figure 1The accompanying drawings show a schematic diagram of a CMOS integrated circuit according to the present disclosure. It should be noted that, in order to clearly illustrate the technical solution, the drawings in this disclosure are not drawn to scale, nor are they drawn as strictly cross-sectional views.
[0038] The CMOS integrated circuit according to this disclosure may include N transistor layers, where N ≥ 2. The N transistor layers are arranged vertically in the vertical direction of the CMOS integrated circuit. That is, if there are two transistor layers, they are arranged vertically; if there are three or more transistor layers, they are arranged sequentially vertically. The CMOS integrated circuit can be in the form of an integrated circuit, for example, each transistor layer may include multiple transistors arranged horizontally (in...). Figure 1 (Only one transistor structure is shown in a transistor layer).
[0039] The N transistor layers can include one first transistor layer and M second transistor layers, where M = N-1. The first transistor layer serves as the bottom layer of the CMOS integrated circuit, and the M second transistor layers are arranged sequentially above and below this first transistor layer. For example, in... Figure 1 A first transistor layer is shown by reference numeral 200, and a second transistor layer is shown by reference numeral 300, wherein ellipses indicate that there may be more than two second transistor layers.
[0040] In this document, a first-type field-effect transistor refers to an NMOS transistor and a second-type field-effect transistor refers to a PMOS transistor, or vice versa. The transistors in the first transistor layer 200 are first-type field-effect transistors (NMOS transistors or PMOS transistors). M second transistor layers are respectively formed with first-type field-effect transistors (NMOS transistors or PMOS transistors) or second-type field-effect transistors (PMOS transistors or NMOS transistors), and at least one of the M second transistor layers is formed with a second-type field-effect transistor (PMOS transistor or NMOS transistor).
[0041] When M=1, a CMOS integrated circuit includes a first transistor layer and a second transistor layer. The first transistor layer may include NMOS transistors, while the second transistor layer may include PMOS transistors.
[0042] When M ≥ 2, the CMOS integrated circuit includes one first transistor layer and M-1 second transistor layers. The first transistor layer may include NMOS transistors, and at least one of the M-1 second transistor layers may include a PMOS transistor, while the other second transistor layers may include NMOS transistors. For example, when M = 3, the CMOS integrated circuit includes one first transistor layer and two second transistor layers. The first transistor layer may include NMOS transistors, and one of the two second transistor layers may include a PMOS transistor, while the other second transistor layer may include either an NMOS transistor or a PMOS transistor. The principle remains the same for other values of M, and will not be elaborated further.
[0043] Figure 1 The figure shows one structure of a field-effect transistor for a CMOS integrated circuit. It should be noted that, for ease of explanation, some parts of the structure shown in the figure may be omitted. Those skilled in the art should understand that field-effect transistors with various suitable structures can be used in the technical solutions of this disclosure.
[0044] The first transistor layer 200 can be an NMOS transistor, including a channel layer 210, a source 220, a drain 230, and a gate 240. The field-effect transistors in the first transistor layer can be silicon-based field-effect transistors or carbon-based field-effect transistors. The second transistor layer 300 can include PMOS transistors or NMOS transistors. Figure 1 The diagram illustrates the structure of a field-effect transistor in a second transistor layer 300, comprising a channel layer 310, a source 320, a drain 330, and a gate 340. The field-effect transistor in the second transistor layer is a carbon-based field-effect transistor. In this application, the channel layer of the carbon-based field-effect transistor is formed of carbon nanotubes, wherein the carbon nanotubes are internally doped, and the internal doping is used to achieve n-type doping of the NMOS transistor or p-type doping of the PMOS transistor. Furthermore, the functions and relative relationships of the field-effect transistors can be referred to in the prior art and will not be described further herein.
[0045] CMOS integrated circuits also include metal interconnects. Metal interconnects are conductive paths in CMOS integrated circuits that connect the source, drain, and gate of transistors, as well as multilayer structures. As an example, metal interconnects can be used for signal transmission or power distribution via metal lines and vertical vias. The materials for metal interconnects are typically copper, silver, or gold.
[0046] In this application, metal interconnects can be used to interconnect the source, drain, and / or gate of the field-effect transistors in the first transistor layer with the source, drain, and / or gate of the field-effect transistors in the M second transistor layers, respectively. For example, metal interconnect 420 connects the sources of the field-effect transistors in each transistor layer, metal interconnect 430 connects the drains of the field-effect transistors in each transistor layer, and / or metal interconnect 440 connects the gates of the field-effect transistors in each transistor layer. Although in Figure 1 In this diagram, the drain, source, and gate are all marked as interconnected, but whether the drain, source, or gate is interconnected can be set according to the actual situation. For example, for a CMOS integrated circuit used as an inverter, both the gate and drain can be interconnected.
[0047] In this application, if a silicon-based field-effect transistor (FET) is present, it will be disposed in the first transistor layer. The fabrication process for the silicon-based FET can be selected according to the actual situation. A carbon-based FET will necessarily be disposed in the second transistor layer. The fabrication process for the carbon-based FET can be selected according to the actual situation. For the carbon-based FET, as mentioned above, internally doped carbon nanotubes are used, that is, p-doping or n-doping is performed inside the carbon nanotube. Compared with external doping (doping outside the carbon nanotube), internal doping of the carbon nanotube ensures doping stability. In the process of fabricating the carbon-based FET, the interior of the carbon nanotube is first doped to obtain internally doped carbon nanotubes. Then, the internally doped carbon nanotubes are transferred to a substrate to fabricate the FET.
[0048] In the technical solution of this disclosure, preferably, the first transistor layer is a silicon-based field-effect transistor (FET), more preferably, the silicon-based FET in the first transistor layer is a silicon-based NMOS transistor, and the second transistor layer uses a carbon-based PMOS transistor. Carbon-based NMOS transistors are difficult to fabricate, and two-dimensional material PMOS transistors are also difficult to fabricate. Therefore, the solution of this disclosure can combine carbon-based PMOS transistors with silicon-based or two-dimensional material NMOS transistors to form a CMOS integrated circuit. This reduces the process difficulty and thus lowers the manufacturing cost while ensuring the performance of the CMOS integrated circuit. Silicon-based FETs are easier to fabricate, but the process is more complex. Combining them with carbon-based FETs can achieve a balance between process difficulty and cost. Meanwhile, carbon-based NMOS transistors have poor performance, exhibiting a small on-state current. By replacing carbon-based NMOS transistors with silicon-based or two-dimensional material NMOS transistors and combining them with carbon-based PMOS transistors to form a CMOS integrated circuit, the problem of small on-state current of carbon-based NMOS transistors can be avoided, thereby improving the overall performance of the CMOS integrated circuit.
[0049] In the technical solution disclosed herein, the field-effect transistors in the upper and lower transistor layers can be arranged in parallel or at an angle. For example, in Figure 1 The image shows an example of parallel arrangement, where the field-effect transistors in the upper and lower transistor layers can be arranged in the source-drain direction (e.g., ...). Figure 1 The electrodes are arranged in parallel in the horizontal direction (from source to drain).
[0050] Preferably, the field-effect transistors in the upper and lower transistor layers are arranged at an angle (cross-shaped), for example in... Figure 2 and Figure 3 The image shows examples of field-effect transistors (FETs) arranged in a cross shape in the vertical direction from two angles. The cross-shaped arrangement referred to herein means that the source-drain directions of corresponding FETs in adjacent transistor layers form a cross (displayed as a cross in the projection). For example, in the case of two transistor layers, the FETs in the lower and upper transistor layers are arranged in a cross shape. In the case of three transistor layers, the FETs in the lower and middle transistor layers are arranged in a cross shape, and the FETs in the middle and upper transistor layers are arranged in a cross shape. The same principle applies to cases with more transistor layers.
[0051] exist Figure 4 The image shows an example of field-effect transistors arranged at an angle in the vertical direction. Figure 4 In the example shown, the source and drain directions of the corresponding field-effect transistors in the upper and lower transistor layers are at an angle other than 90 degrees.
[0052] In this disclosure, preferably, the field-effect transistors of the upper and lower transistor layers are arranged at an angle, for example, the angle θ between them in the source-drain direction can be 0° < θ < 180°. Compared to the parallel arrangement above, the angled arrangement allows the source, drain, and gate of the upper and lower field-effect transistors to be in a non-overlapping state, thus leaving more space for metal interconnects. In the figures, only the connection method of the metal interconnects is schematically shown, and other suitable methods can also be used.
[0053] According to a further embodiment of this disclosure, a method for fabricating a CMOS integrated circuit is provided. Generally, the method for fabricating a CMOS integrated circuit includes: fabricating a first transistor layer on a substrate, wherein a field-effect transistor (FET) is formed in the first transistor layer, the FET being a type I FET, and having a channel layer, a source, a drain, and a gate, and having metal interconnects for at least one of the source, drain, and gate; filling a substrate material and performing a first planarization treatment on the upper surface of the substrate material, wherein the upper surface of the filled substrate material extends beyond the upper surface of the type I FET; and fabricating a second transistor layer on the upper surface of the first planarized substrate material, wherein a FET is formed in the second transistor layer, the FET being a type I or a type II FET. The field-effect transistor of the second transistor layer has a channel layer, a source, a drain, and a gate, and a metal interconnect formed for at least one of the source, drain, and gate, and the metal interconnects of the first transistor layer and the second transistor layer are correspondingly connected; and a substrate material is filled and the upper surface of the substrate material is subjected to a second planarization treatment, wherein the upper surface of the filled substrate material exceeds the upper surface of the field-effect transistor of the second transistor layer, wherein the first type field-effect transistor and the second type field-effect transistor are respectively an NMOS transistor and a PMOS transistor, the field-effect transistor of the second transistor layer is a carbon-based field-effect transistor, and the field-effect transistor of the first transistor layer is a silicon-based field-effect transistor or a carbon-based field-effect transistor.
[0054] The preparation method disclosed herein will be described in detail below. Figures 5 to 8 A method for fabricating a CMOS integrated circuit according to an embodiment of the present disclosure is shown.
[0055] like Figure 5 As shown, a field-effect transistor (FET) of a first transistor layer is fabricated on a substrate 100, wherein the FET includes a channel layer 210, a source 220, a drain 230, and a gate 240. The FET of this first transistor layer may include one or more FETs, and in the case of multiple FETs, the multiple FETs may be located in the same plane.
[0056] The field-effect transistor (FET) of the first transistor layer can be either a silicon-based FET or a carbon-based FET. Regardless of whether it is silicon-based or carbon-based, its structure is not limited in this paper, and the fabrication process can be tailored to the specific circumstances. If the FET of the first transistor layer is a carbon-based FET, the carbon nanotubes used are internally doped carbon nanotubes. Furthermore, the FET of the first transistor layer can be a type I FET, i.e., an NMOS transistor or a PMOS transistor. If an NMOS transistor is used, the carbon nanotubes used are n-type doped carbon nanotubes. If a PMOS transistor is used, the carbon nanotubes used are p-type doped carbon nanotubes. After n-doping or p-doping the carbon nanotubes, the doped carbon nanotubes are transferred to the substrate.
[0057] In this application, the substrate material can be a suitable material such as SiO2 (silicon oxide).
[0058] In addition, during the fabrication of the field-effect transistor in the first transistor layer, metal interconnects for the source, drain, and / or gate of the field-effect transistor are fabricated. The figure shows metal interconnect 420 for the source 220, metal interconnect 430 for the drain 230, and metal interconnect 440 for the source 240. However, in actual fabrication, the fabrication of metal interconnects can be selected according to actual needs. For example, in the case of an inverter application, only metal interconnect 420 for the source 220 and metal interconnect 430 for the drain 230 are fabricated.
[0059] like Figure 6 As shown, a substrate material is filled. After filling the substrate material, the surface (the upper surface in the figure) is planarized. Additionally, a portion of the metal interconnect can be fabricated during the substrate material filling process, or the desired metal interconnect can be prepared within the substrate. Figure 5 The preparation is completed in the following steps. Additionally, the filled substrate material is... Figure 5 Fabricated field-effect transistors and Figure 7 An isolation layer is formed between the fabricated field-effect transistors.
[0060] like Figure 7 As shown, a field-effect transistor (FET) with a second transistor layer is fabricated on a planarized substrate. The FET includes a channel layer 310, a source 320, a drain 330, and a gate 340. This second transistor layer may include one or more FETs; in the case of multiple FETs, they may be located in the same plane.
[0061] The field-effect transistor (FET) of the second transistor layer is a carbon-based FET. Its structure is not limited in this paper, and the fabrication process can be tailored to the specific circumstances. The carbon nanotubes used in the carbon-based FET are internally doped carbon nanotubes. Furthermore, if there is only one second transistor layer, the carbon-based FET is a type II FET, which differs from the type of the first FET. For example, if the first FET is an NMOS transistor, the second FET is a PMOS transistor; if the first FET is a PMOS transistor, the second FET is an NMOS transistor. If an NMOS FET is used, the carbon nanotubes used are n-type doped. If a PMOS FET is used, the carbon nanotubes used are p-type doped. After n-doping or p-doping the carbon nanotubes, the doped carbon nanotubes are transferred to a planarized substrate.
[0062] like Figure 8 As shown, fill the substrate material. After filling the substrate material, the surface ( Figure 8 The upper surface of the substrate is planarized. Additionally, a portion of the metal interconnect can be fabricated during the filling of the substrate material, or the desired metal interconnect can be placed within the substrate. Figure 7 The preparation is completed in the following steps.
[0063] If the desired CMOS integrated circuit includes only one second transistor layer, the fabrication is complete. If it includes two or more second transistor layers, the process is repeated. Figure 7 and Figure 8 The steps are as follows. It is important to note that the field-effect transistors in the second transistor layer, which are fabricated again, are also carbon-based field-effect transistors. Furthermore, depending on the actual design requirements, the field-effect transistors in two or more second transistor layers can have a different doping type than the field-effect transistors in the first transistor layer.
[0064] The fabrication method of the CMOS integrated circuit disclosed herein will be described in detail below with reference to the embodiments. The embodiments below are all described with the case of having one second transistor layer. Based on the above description, those skilled in the art should understand that in the case of multiple second transistor layers, the fabrication of the first second transistor layer can be repeated (the difference may be between PMOS and NOMOS).
[0065] In one embodiment, the field-effect transistors in the first transistor layer of the CMOS integrated circuit are carbon-based field-effect transistors, and the field-effect transistors in one or more second transistor layers are also carbon-based field-effect transistors. Figure 9 A flowchart of the preparation method M900 of this embodiment is shown, including steps S910 to S960.
[0066] In step S910, the internally doped carbon nanotubes are transferred onto the substrate, wherein the internally doped carbon nanotubes refer to carbon nanotubes that have undergone n-type doping inside. The n-type doping material may include: aminated C 60 (C60) or alkali metallized C 60 For example, C 60 -NH3,C 60 K3, etc.; or one-dimensional Sn (tin)-based perovskites. The details regarding n-type internal doping will be described below.
[0067] In step S920, a field-effect transistor (FET) is formed, which is an NMOS transistor. The n-type doped carbon nanotubes mentioned in step S910 serve as the channel layer of the NMOS transistor. The formed NMOS transistor includes a source, a drain, and a gate, as well as metal interconnects for at least one of the source, drain, and gate. For the specific fabrication process of this FET, please refer to relevant content in the prior art.
[0068] In step S930, a substrate material is filled and planarized. The substrate material can be, for example, SiO2, as mentioned above. The planarized filled substrate material serves as the substrate for the field-effect transistors in the upper field-effect transistor layer. Furthermore, the substrate material between the upper and lower field-effect transistors can serve as an isolation layer between them.
[0069] In step S940, the internally doped carbon nanotubes are transferred onto the substrate. The internally doped carbon nanotubes refer to carbon nanotubes that have undergone p-type doping within them. The p-type doping material may include: C 60 Or, one-dimensional Pb (lead)-based perovskites containing halogen vacancies. The details of p-type internal doping will be described below.
[0070] In step S950, a field-effect transistor (FET) is formed, which is a PMOS transistor. The p-type doped carbon nanotubes mentioned in step S940 serve as the channel layer of the PMOS transistor. The formed PMOS transistor includes a source, a drain, and a gate, as well as metal interconnects for at least one of the source, drain, and gate. For the specific fabrication process of this FET, please refer to relevant content in the prior art.
[0071] In step S960, a substrate material is filled and planarization is performed. The substrate material can be, for example, SiO2, as mentioned above. This forms a CMOS integrated circuit, where multiple field-effect transistors can be formed in each layer.
[0072] The planarized, filled substrate material serves as the substrate for the field-effect transistors in the upper layer. Furthermore, the substrate material between the upper and lower layers of field-effect transistors can act as an isolation layer between them.
[0073] If it is necessary to form more second transistor layers on top, steps S940 to S960 can be repeated. If the field-effect transistors in these more second transistor layers are NMOS transistors, then the internally doped carbon nanotubes used are n-type doped carbon nanotubes.
[0074] In another embodiment, the field-effect transistors in the first transistor layer of the CMOS integrated circuit are silicon-based field-effect transistors, and the field-effect transistors in one or more second transistor layers are carbon-based field-effect transistors. Figure 10 A flowchart of the preparation method M1000 of this embodiment is shown, including steps S1010 to S1050.
[0075] In step S1010, a silicon-based field-effect transistor (FET) is formed, which is an NMOS transistor. The formed NMOS transistor includes a source, a drain, and a gate, as well as a metal interconnect for at least one of the source, drain, and gate. For the specific fabrication process of this silicon-based FET, please refer to relevant content in the prior art.
[0076] In step S1020, a substrate material is filled and planarized. The substrate material can be, for example, SiO2, as mentioned above. The planarized filled substrate material serves as the substrate for the field-effect transistors in the upper field-effect transistor layer. Furthermore, the substrate material between the upper and lower field-effect transistors can serve as an isolation layer between them.
[0077] In step S1030, the internally doped carbon nanotubes are transferred onto the substrate. In the case of a single second transistor layer, the internally doped carbon nanotubes are p-type doped carbon nanotubes. In the case of two or more second transistor layers, the internally doped carbon nanotubes can be either p-type or n-type doped carbon nanotubes. However, in the case of two or more second transistor layers, at least one must be a second transistor layer comprising a PMOS transistor made of p-type doped carbon nanotubes. The p-type doping material may include: C 60 Or, one-dimensional Pb (lead)-based perovskites containing halogen vacancies. n-type doped materials may include: amino-modified C...60 (C60) or alkali metallized C 60 For example, C 60 -NH3,C 60 K3, etc.; or one-dimensional Sn (tin)-based perovskites.
[0078] In this embodiment, a second transistor layer is used as an example for explanation. In step S1040, a field-effect transistor (FET) is formed, which is a PMOS transistor. The p-type doped carbon nanotubes mentioned in step S1030 serve as the channel layer of the PMOS transistor. The formed PMOS transistor includes a source, a drain, and a gate, as well as metal interconnects for at least one of the source, drain, and gate. For the specific fabrication process of this FET, please refer to relevant content in the prior art.
[0079] In step S1050, a substrate material is filled and planarization is performed. The substrate material can be, for example, SiO2, as mentioned above. This forms a CMOS integrated circuit, where multiple field-effect transistors can be formed in each layer.
[0080] The planarized, filled substrate material serves as the substrate for the field-effect transistors in the upper layer. Furthermore, the substrate material between the upper and lower layers of field-effect transistors can act as an isolation layer between them.
[0081] If it is necessary to form more second transistor layers on top, steps S1030 to S1050 can be repeated.
[0082] In the embodiments or examples described above, the field-effect transistors of the first transistor layer can be carbon-based or silicon-based field-effect transistors, but the field-effect transistors of the second transistor layer must be carbon-based. In the fabrication of silicon-based field-effect transistors, an ion implantation process is required. The typical temperature in the ion implantation process is usually 800-1100°C, or even as high as 1700°C. At this temperature, the formed metal interconnects will be destroyed. For example, if a second transistor layer needs to be fabricated on top of the first transistor layer's field-effect transistor, and if the second transistor layer's field-effect transistor is a silicon-based field-effect transistor, then the ion implantation process in silicon-based technology will inevitably destroy the metal interconnects in the underlying transistor layer. In this application, metal interconnects are formed simultaneously in each transistor layer during the fabrication process, and ultimately, the metal interconnects of each transistor layer are connected vertically.
[0083] The internal doping of carbon nanotubes will be described in detail below. Internally doped carbon nanotubes formed in the following manner can be used in the aforementioned CMOS integrated circuits. The method for internal doping of carbon nanotubes proposed in this disclosure involves performing n-type doping and p-type doping inside the carbon nanotubes, respectively, to realize NMOS transistors and PMOS transistors. Compared to doping the exterior of carbon nanotubes, internal doping ensures doping stability.
[0084] According to one embodiment of the present disclosure, a p-type doped carbon nanotube is provided. Figure 11 A flowchart illustrating the preparation method of p-type doped carbon nanotubes is shown. Figure 11 As shown, the preparation method M1100 of p-type doped carbon nanotubes may include steps S1110 to S1140.
[0085] In step S1110, a precursor with the general chemical formula APbX3 is prepared in proportion, wherein A is selected from one or more of Cs (cesium), methylamine, or formamidinium, and X is selected from one or more of Cl (chlorine), Br (bromine), or I (iodine). The precursor includes PbX2 and AX, wherein the mass ratio of PbX2 to AX can be 0.90 to 0.95.
[0086] In step S1120, the precursor and carbon nanotubes are mixed in an organic solvent, wherein the organic solvent is selected from one or more of DMF (dimethylformamide) or DMSO (dimethyl sulfoxide). The precursor and carbon nanotubes can be mixed in the organic solvent by stirring.
[0087] In step S1130, the mixture formed after mixing is heated to crystallize the perovskite. During the crystallization process, Pb (lead) vacancies are generated based on the PbX2 / AX mass ratio, thereby achieving p-type doping inside the carbon nanotubes.
[0088] In step S1140, the outer surface of the carbon nanotubes is washed and dried to remove residual solvent. This forms p-type doped internally doped carbon nanotubes. Organic solvents such as toluene can be used during the washing process.
[0089] In particular, the threshold voltage (the minimum gate voltage required to enable electron conduction) of transistors made from p-type doped internally doped carbon nanotubes shifts in the positive direction (making them easier to turn on) as the doping concentration increases. The shift in threshold voltage varies from approximately 0 to 2V depending on the doping concentration.
[0090] According to another embodiment of this disclosure, a p-type doped carbon nanotube is provided. Figure 12The diagram shows a flowchart of a method for preparing p-type doped carbon nanotubes. After careful research, the inventors innovatively proposed this method for preparing p-type doped carbon nanotubes, which utilizes C... 60 Internal doping of carbon nanotubes can be achieved within the nanotubes themselves. For example... Figure 12 As shown, the preparation method M1200 of p-type doped carbon nanotubes may include steps S1210 to S1230.
[0091] In step S1210, C 60 Dissolved in an aromatic solvent to form a saturated solution with a concentration of 1-5 mg / mL, wherein the aromatic solvent is selected from one or more of toluene, chlorobenzene, or 1,2,4-trichlorobenzene; In step S1220, the pretreated carbon nanotubes are added to the above saturated solution, C 60 Gradually deposited inside carbon nanotubes. During the deposition process, ultrasonic treatment and heat treatment can be performed.
[0092] In step S1230, the C adsorbed on the outer surface of the carbon nanotubes is removed. 60 For example, carbon nanotubes can be repeatedly washed with aromatic solvents (such as toluene).
[0093] Alternatively, the internally doped carbon nanotubes can be dried to remove residual solvents.
[0094] p-type doped carbon nanotubes were obtained through C 60 This is achieved through contact with carbon nanotubes, where electrons are transferred from the conduction band of the carbon nanotubes to the C-band. 60 The presence of LUMO orbitals (lowest unoccupied molecular orbitals) leads to an increase in the hole concentration in carbon nanotubes, resulting in p-type characteristics.
[0095] According to yet another embodiment of this disclosure, an n-type doped carbon nanotube is provided. Figure 13 The flowchart illustrates a method for preparing n-type doped carbon nanotubes. (For example...) Figure 13 As shown, the method M1300 for preparing the n-type doped carbon nanotubes may include steps S1310 to S1340.
[0096] In step S1310, a precursor with the chemical formula APbX3 is prepared in proportion, wherein A is selected from one or more of Cs, methylamine, or formamidinium, and X is selected from one or more of Cl, Br, or I. The precursor includes PbX2 and AX, wherein the mass ratio of PbX2 to AX is 1.05 to 1.1.
[0097] In step S1320, the precursor and carbon nanotubes are mixed in an organic solvent. The organic solvent is selected from one or more of DMF or DMSO. The precursor and carbon nanotubes can be mixed in the organic solvent by stirring.
[0098] In step S1330, the mixture formed after mixing is heated to crystallize the perovskite. During the crystallization process, X vacancies are generated based on the PbX2 / AX mass ratio, thereby achieving n-type doping inside the carbon nanotubes.
[0099] In step S1340, the outer surface of the carbon nanotubes is washed and dried to remove residual solvent. Organic solvents such as toluene can be used during the washing process.
[0100] In the above method, replacing Pb with Sn can enhance the n-type doping effect. The threshold voltage of a transistor made from n-type doped internally doped carbon nanotubes shifts negatively (making it easier to turn on) as the n-type doping concentration increases. The threshold voltage shift ranges from approximately 0 to 2V, depending on the doping concentration or the Pb×2 / AX mass ratio.
[0101] According to yet another embodiment of this disclosure, an n-type doped carbon nanotube is provided. Figure 14 The diagram shows a flowchart of a method for preparing n-type doped carbon nanotubes. After careful research, the inventors innovatively proposed this method for preparing n-type doped carbon nanotubes, which utilizes C... 60 Internal doping of carbon nanotubes can be achieved within the nanotubes themselves. For example... Figure 14 As shown, the method M1400 for preparing n-type doped carbon nanotubes may include steps S1410 to S1440.
[0102] In step S1410, for C 60 Amination or alkali metallization can be performed. This allows C to... 60 Become an electron donor. Amide or alkali metallization of C 60 It can be used for n-type doping of the interior of carbon nanotubes.
[0103] In step S1420, the amination C is... 60 or alkali metallization C 60 Dissolved in an aromatic solvent to form a saturated solution with a concentration of 1-5 mg / mL, wherein the aromatic solvent is selected from one or more of toluene, chlorobenzene, or 1,2,4-trichlorobenzene; In step S1430, the pretreated carbon nanotubes are added to the above saturated solution to amination C. 60 or alkali metallization C 60Gradually deposited inside carbon nanotubes. During the deposition process, ultrasonic treatment and heat treatment can be performed.
[0104] In step S1440, the amination of C adsorbed on the outer surface of the carbon nanotubes is removed. 60 or alkali metallization C 60 For example, carbon nanotubes can be repeatedly washed with aromatic solvents (such as toluene).
[0105] Alternatively, the internally doped carbon nanotubes can be dried to remove residual solvents.
[0106] In the description of this specification, the references to terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., refer to specific features, structures, or characteristics described in connection with that embodiment / mode or example, which are included in at least one embodiment / mode or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Moreover, the specific features, structures, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.
[0107] Those skilled in the art should understand that the above embodiments are merely for illustrating the present disclosure and are not intended to limit the scope of the disclosure. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of the present disclosure.
Claims
1. A CMOS integrated circuit, characterized in that, include: N transistor layers, N≥2, wherein the N transistor layers are arranged vertically in the vertical direction of the CMOS integrated circuit, and the N transistor layers include: A first transistor layer, the first transistor layer being located at the bottom layer of the CMOS integrated circuit, wherein a first type field-effect transistor is formed in the first transistor layer; M second transistor layers, wherein the M second transistor layers are disposed above the first transistor layer, and the M second transistor layers are arranged in the above-below configuration, wherein M = N-1, and each of the M second transistor layers is formed with a first-type or a second-type field-effect transistor, and at least one of the M second transistor layers is formed with a second-type field-effect transistor; and Metal interconnects are used to interconnect the source, drain, and / or gate of the field-effect transistors in the first transistor layer with the source, drain, and / or gate of the M field-effect transistors in the second transistor layer, respectively. Among them, the first type field-effect transistor and the second type field-effect transistor are respectively a type of NMOS transistor and a PMOS transistor. The field-effect transistors in the M second transistor layers are carbon-based field-effect transistors, and the field-effect transistors in the first transistor layer are silicon-based field-effect transistors or carbon-based field-effect transistors.
2. The CMOS integrated circuit as described in claim 1, characterized in that, The channel material in the carbon-based field-effect transistor is an internally doped carbon nanotube, and the internal doping is used to achieve n-type doping of the NMOS transistor or p-type doping of the PMOS transistor.
3. The CMOS integrated circuit as described in claim 2, characterized in that, The n-type doped material includes C-aminated carbon. 60 , basification C 60 Or a one-dimensional Sn-based perovskite; and the p-type doped material includes C 60 Or one-dimensional Pb-based perovskites containing halide vacancies.
4. The CMOS integrated circuit as described in any one of claims 1 to 3, characterized in that, An isolation layer is disposed between adjacent transistor layers in the first transistor layer and the M second transistor layers, and the material of the isolation layer is the substrate material of the field-effect transistor.
5. The CMOS integrated circuit as described in claim 4, characterized in that, The source-drain angle θ of the field-effect transistors in adjacent transistor layers in the first and second transistor layers is configured to be 0° < θ < 180° or θ = 0°.
6. The CMOS integrated circuit as described in claim 4, characterized in that, The CMOS integrated circuit includes a first transistor layer and a second transistor layer. The field-effect transistors in the first transistor layer are silicon-based NMOS transistors, and the field-effect transistors in the second transistor layer are carbon-based PMOS transistors.
7. A method for fabricating a CMOS integrated circuit, characterized in that, A first transistor layer is fabricated on a substrate, wherein a field-effect transistor is formed on the first transistor layer, the field-effect transistor being a first type field-effect transistor, and having a channel layer, a source, a drain, and a gate, and having metal interconnects formed for at least one of the source, drain, and gate. A substrate material is filled and a first planarization process is performed on the upper surface of the substrate material, wherein the upper surface of the filled substrate material exceeds the upper surface of the first type field-effect transistor; A second transistor layer is prepared on the upper surface of the first planarized substrate material. The second transistor layer has a field-effect transistor. The field-effect transistor of the second transistor layer is a type II field-effect transistor. The field-effect transistor of the second transistor layer has a channel layer, a source, a drain, and a gate, and has metal interconnects for at least one of the source, drain, and gate. The metal interconnects of the first transistor layer and the second transistor layer are correspondingly connected. as well as A substrate material is filled, and the upper surface of the substrate material is subjected to a second planarization process, wherein the upper surface of the filled substrate material extends beyond the upper surface of the field-effect transistor in the second transistor layer. Among them, the first type field-effect transistor and the second type field-effect transistor are respectively an NMOS transistor and a PMOS transistor, the field-effect transistor of the second transistor layer is a carbon-based field-effect transistor, and the field-effect transistor of the first transistor layer is a silicon-based field-effect transistor or a carbon-based field-effect transistor.
8. The preparation method according to claim 7, characterized in that, The channel material of the channel layer of the carbon-based field-effect transistor is an internally doped carbon nanotube. When the carbon-based field-effect transistor is an NMOS transistor, the internally doped carbon nanotube is an n-type doped carbon nanotube. When the carbon-based field-effect transistor is a PMOS transistor, the internally doped carbon nanotube is a p-type doped carbon nanotube.
9. The preparation method according to claim 8, characterized in that, The preparation of the n-type doped carbon nanotubes includes: Amination C was obtained 60 or alkali metallization C 60 ; Amination C 60 or alkali metallization C 60 Dissolved in an aromatic solvent, it yields a saturated solution; Carbon nanotubes are added to the saturated solution, and the aminated C 60 or alkali metallization C 60 Deposition inside carbon nanotubes; and Removal of aminated C from the outer surface of carbon nanotubes 60 or alkali metallization C 60 The n-type doped carbon nanotubes were obtained.
10. The preparation method according to claim 8, characterized in that, The preparation of the p-type doped carbon nanotubes includes: C 60 Dissolved in an aromatic solvent, it yields a saturated solution; Carbon nanotubes are added to the saturated solution, and the C 60 Deposition inside carbon nanotubes; and Removing C from the outer surface of carbon nanotubes 60 The p-type doped carbon nanotubes were obtained.