Semiconductor device and electronic apparatus

Abstract

A semiconductor device according to an embodiment of the present disclosure includes: a transistor provided on a semiconductor substrate and having a gate electrode, a source electrode, and a drain electrode; a terminal electrically connected to the transistor; and a diode provided on the semiconductor substrate and electrically connected to the terminal. The interval between the anode and the cathode of the diode is shorter than the interval between the gate electrode and the source or drain of the transistor.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device and an electronic apparatus. BACKGROUND

[0002] A proposed semiconductor device includes a heterojunction field-effect transistor and a protection diode coupled between a gate and a source of the heterojunction field-effect transistor.

[0003] LIST OF CITATIONS

[0004] PATENT LITERATURE

[0005] PTL 1: Japanese Unexamined Patent Application Publication No. 2007-59882 SUMMARY

[0006] It is desirable for a semiconductor device to improve surge resistance.

[0007] It is desirable to provide a semiconductor device with good surge resistance.

[0008] A semiconductor device of an embodiment of the present disclosure includes a transistor provided in a semiconductor substrate and including a gate electrode, a source, and a drain; a terminal electrically coupled to the transistor; and a diode provided in the semiconductor substrate and electrically coupled to the terminal. A separation between an anode and a cathode of the diode is shorter than a separation between the gate electrode and the source or the drain of the transistor.

[0009] An electronic apparatus of an embodiment of the present disclosure includes a circuit including a transistor provided in a semiconductor substrate and including a gate electrode, a source, and a drain; a terminal electrically coupled to the transistor; and a diode provided in the semiconductor substrate and electrically coupled to the terminal. A separation between an anode and a cathode of the diode is shorter than a separation between the gate electrode and the source or the drain of the transistor. BRIEF DESCRIPTION OF DRAWINGS

[0010] [ Figure 1 ] Figure 1 is a diagram illustrating a configuration example of a semiconductor device according to an embodiment of the present disclosure.

[0011] [ Figure 2A ] Figure 2A is a diagram illustrating a configuration example of a semiconductor device according to an embodiment of the present disclosure.

[0012] [ Figure 2B ] Figure 2B is a diagram illustrating a configuration example of a semiconductor device according to an embodiment of the present disclosure.

[0013] [ Figure 3A ] Figure 3A is a diagram illustrating a configuration example of a semiconductor device according to an embodiment of the present disclosure.

[0014] [ Figure 3B ] Figure 3B is a diagram illustrating a configuration example of a semiconductor device according to an embodiment of the present disclosure.

[0015] [ Figure 4 ] Figure 4 is a graph illustrating an example of electrical characteristics of a diode and a transistor of a semiconductor device according to an embodiment of the present disclosure.

[0016] [ Figure 5A ] Figure 5A is a diagram illustrating an example of a manufacturing method of a semiconductor device according to an embodiment of the present disclosure.

[0017] [ Figure 5B ] Figure 5B is a diagram illustrating an example of a manufacturing method of a semiconductor device according to an embodiment of the present disclosure.

[0018] [ Figure 5C ] Figure 5C is a diagram illustrating an example of a manufacturing method of a semiconductor device according to an embodiment of the present disclosure.

[0019] [ Figure 5D ] Figure 5D is a diagram illustrating an example of a manufacturing method of a semiconductor device according to an embodiment of the present disclosure.

[0020] [ Figure 5E ] Figure 5E is a diagram illustrating an example of a manufacturing method of a semiconductor device according to an embodiment of the present disclosure.

[0021] [ Figure 5F ] Figure 5F is a diagram illustrating an example of a manufacturing method of a semiconductor device according to an embodiment of the present disclosure.

[0022] [ Figure 5G ] Figure 5G is a diagram illustrating an example of a manufacturing method of a semiconductor device according to an embodiment of the present disclosure.

[0023] [ Figure 6A ] Figure 6A is a diagram illustrating a configuration example of a semiconductor device according to Modification 1 of the present disclosure.

[0024] [ Figure 6B ] Figure 6B is a diagram illustrating a configuration example of a semiconductor device according to Modification 1 of the present disclosure.

[0025] [ Figure 7 ] Figure 7 is a diagram illustrating a configuration example of a semiconductor device according to Modification 2 of the present disclosure.

[0026] [ Figure 8 ] Figure 8 is a explanatory diagram of a configuration example of a semiconductor device according to a modification 2 of the present disclosure.

[0027] [ Figure 9 ] Figure 9 is a explanatory diagram of a configuration example of a semiconductor device according to a modification 3 of the present disclosure.

[0028] [ Figure 10 ] Figure 10 is a explanatory diagram of a configuration example of a semiconductor device according to a modification 3 of the present disclosure.

[0029] [ Figure 11 ] Figure 11 is a explanatory diagram of a configuration example of a semiconductor device according to a modification 4 of the present disclosure.

[0030] [ Figure 12 ] Figure 12 is a explanatory diagram of a configuration example of a semiconductor device according to a modification 5 of the present disclosure.

[0031] [ Figure 13 ] Figure 13 is a explanatory diagram of another configuration example of a semiconductor device according to a modification 5 of the present disclosure.

[0032] [ Figure 14 ] Figure 14 is a diagram illustrating a configuration example of a wireless communication device of the present disclosure. DETAILED DESCRIPTION

[0033] Some embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. Note that the description is given in the following order.

[0034] 1. Embodiment

[0035] 2. Modification

[0036] 3. Application

[0037] <1. Embodiment>

[0038] Figure 1 is a explanatory diagram of a configuration example of a semiconductor device according to an embodiment of the present disclosure. The semiconductor device 1 includes a transistor 10, a terminal 20, and a protection circuit 30. The semiconductor device 1 can be suitably used as a device (circuit) that processes a high-frequency signal, for example. In one example, the semiconductor device 1 includes a compound semiconductor (e.g., a III-V group compound semiconductor) and can be suitably used as a high-frequency circuit of a communication device.

[0039] The semiconductor device 1 is, for example, an integrated circuit such as an MMIC (Monolithic Microwave Integrated Circuit). The semiconductor device 1 can be used for an electronic device using a frequency band such as a microwave band or a millimeter wave band. The semiconductor device 1 is, for example, a switching circuit, a power amplifier circuit, or a filter circuit of an RF signal.

[0040] Note that the high frequency can be a frequency in a frequency band of several megahertz to several hundred gigahertz, or can be a frequency in a frequency band higher than several hundred gigahertz. In one example, the semiconductor device 1 can receive and output a high frequency signal in a millimeter wave band or a microwave band, for example. The frequency of the high frequency signal can be, for example, 100 MHz or higher, or 1 GHz or higher. Further, the frequency of the high frequency signal can be, for example, 300 GHz or lower, or 100 GHz or lower.

[0041] The semiconductor device 1 includes an input portion or an output portion provided with an electrostatic protection element. In the example illustrated in FIG. 1, the semiconductor device 1 includes the input portion and the output portion. The input portion is provided with the electrostatic protection element. The output portion is provided with the electrostatic protection element. Figure 1 In the example illustrated in FIG. 1, the protection circuit 30 is provided to the terminal 20 and the transistor 10. The protection circuit 30 is an electrostatic discharge (ESD) protection circuit. The semiconductor device 1 can be regarded as an integrated circuit including an electrostatic protection element.

[0042] The semiconductor device 1 includes a nitride semiconductor such as GaN (Gallium Nitride). GaN is a wide bandgap semiconductor material having a wide bandgap. Further, GaN is characterized by, for example, a high dielectric breakdown voltage, a high saturation drift velocity, and operability at high temperatures.

[0043] Further, a two-dimensional electron gas (2DEG) formed at a GaN heterojunction is characterized by a high mobility and a high sheet electron density. This characteristic allows a GaN hetero FET (HFET) to have a low resistance and operate at a high speed and a high withstand voltage. The GaN HFET can be suitable for, for example, a power device or an RF device.

[0044] The terminal 20 of the semiconductor device 1 is electrically coupled to the transistor 10. The terminal 20 is, for example, a signal terminal for transmitting a signal to and from the outside. In one example, the terminal 20 is an input terminal through which a signal is input from the outside of the semiconductor device 1. The transistor 10 can form at least a part of an input portion (input circuit) of the semiconductor device 1.

[0045] It should be noted that terminal 20 can be an input / output terminal through which signals are input and output. In this case, transistor 10 can form at least a portion of the input / output section (input / output circuit) of semiconductor device 1. Furthermore, terminal 20 can be an output terminal through which signals are output to the outside of semiconductor device 1. Semiconductor device 1 can be provided with multiple terminals 20. The multiple terminals 20 include, for example, input terminals through which signals are input from the outside of semiconductor device 1, output terminals through which signals are output to the outside of semiconductor device 1, and input / output terminals through which signals are input and output.

[0046] Protection circuit 30 is the internal circuit of semiconductor device 1 that is to be protected. Figure 1 The circuit of transistor 10 in the semiconductor device 1. Protection circuit 30 is electrically coupled to terminal 20 and is configured to protect the semiconductor device 1 from abnormal currents and voltages generated through terminal 20. Protection circuit 30 can be considered as an ESD protection circuit for the semiconductor device 1. Figure 1 In the example shown, the protection circuit 30, which serves as an ESD protection circuit, is provided to the terminal 20, which acts as an input terminal.

[0047] The protection circuit 30 includes, for example, a diode 31 as an ESD protection element. The protection circuit 30 prevents surges caused by, for example, static electricity accumulated on a person or device, from being applied to the internal circuitry of the semiconductor device 1. The transistor 10, the protection circuit 30 including the diode 31, and other elements to be protected can be disposed on the same substrate. For example, the transistor 10, the diode 31, and other elements are formed on the same compound semiconductor substrate (e.g., a GaN substrate).

[0048] It is important to note that Figure 1 The illustration shows an example with only one terminal 20 and one protection circuit 30; however, the semiconductor device 1 may be provided with multiple terminals and multiple protection circuits. The protection circuit 30 may be provided for each of, for example, the terminal 20 that serves as an input terminal, the terminal 20 that serves as an input / output terminal, and the terminal 20 that serves as an output terminal.

[0049] Transistor 10 of semiconductor device 1 is electrically coupled to terminal 20. Transistor 10 is a field-effect transistor (FET), which includes a gate terminal, a source terminal, and a drain terminal. Figure 1 In the example shown, the gate of transistor 10 is electrically coupled to terminal 20.

[0050] Transistor 10 is, for example, a heterojunction FET (HFET) and includes a compound semiconductor. Transistor 10 includes a two-dimensional electron gas (two-dimensional electron gas layer) formed using a heterojunction. Transistor 10 may include a gate formed, for example, using a Schottky junction, and may be constructed from a transistor including a Schottky gate. Transistor 10 has a Schottky gate structure and can be considered as a Schottky FET.

[0051] Diode 31 is an ESD protection element and is electrically coupled to terminal 20. Diode 31 is positioned between terminal 20 and the reference potential line L1. Figure 1 In the example shown, reference potential line L1 is ground (grounding line). Diode 31 is electrically coupled between terminal 20 and ground terminal (GND terminal). Note that, depending on the component or circuit to be protected, diode 31 may be electrically coupled between terminal 20 and power supply terminal (or power supply line).

[0052] exist Figure 1 In the example illustrated, diode 31 has one electrode, the anode, electrically coupled to terminal 20. Diode 31 has another electrode, the cathode, which is electrically coupled to a reference potential line L1 that serves as ground (GND line). For example, 0V, as GND potential (ground potential), is supplied to the cathode of diode 31.

[0053] Corresponding to the potential difference (voltage) between the anode of diode 31 electrically coupled to terminal 20 and the cathode of diode 31 electrically coupled to ground, current (reverse current or forward current) flows through diode 31. In the event of a surge at terminal 20, current can flow through diode 31 between terminal 20 and the reference potential line L1 to release the surge.

[0054] For example, in response to a negative surge, semiconductor device 1 allows reverse current to flow through diode 31, which protects transistor 10. When a negative surge voltage, i.e., a rapidly decreasing surge voltage, is supplied to terminal 20, diode 31 enters a low-impedance state and outputs current caused by the surge voltage. This allows the voltage applied between the gate and source (or drain) of transistor 10 to be reduced, and suppresses characteristic degradation and ESD damage to transistor 10.

[0055] Figure 2A , Figure 2B , Figure 3A and Figure 3B These are all explanatory diagrams illustrating examples of the construction of semiconductor devices according to embodiments. Figure 2A An example of the cross-sectional structure of the transistor 10 of the semiconductor device 1 is illustrated. Figure 2B An example of a planar configuration of transistor 10 is illustrated. Figure 3A An example of the cross-sectional structure of the diode 31 of the semiconductor device 1 is illustrated.Figure 3B An example of a planar configuration of diode 31 is illustrated.

[0056] Semiconductor device 1 includes a semiconductor layer 41, a buffer layer 42, a back barrier layer 43, a channel layer 44, a barrier layer 45, semiconductor regions 46a and 46b, and a wiring layer 50. Semiconductor device 1 also includes electrodes 47a and 47b, an insulating film 48, and a gate electrode 49. Figure 2A and Figure 3A In the example illustrated, electrodes 47a and 47b, insulating film 48, and gate electrode 49 are disposed in wiring layer 50.

[0057] Semiconductor device 1 includes a substrate 100, which includes, for example, a semiconductor layer 41, a buffer layer 42, a back barrier layer 43, a channel layer 44, a barrier layer 45, semiconductor regions 46a and 46b, and a wiring layer 50. The substrate 100 includes, for example, a nitride semiconductor.

[0058] The substrate 100 has, for example, an input section (or output section) including a transistor 10 and a protection circuit 30 including a diode 31. The transistor 10 of the semiconductor device 1 may have… Figure 2A and Figure 2B The structure shown in the figure, and diode 31 can have Figure 3A and Figure 3B The structure shown in the diagram.

[0059] Semiconductor layer 41 comprises a semiconductor material, such as a III-V compound semiconductor material. In one example, semiconductor layer 41 may be constructed from a GaN substrate. Semiconductor layer 41 may be any other substrate, such as a Si (silicon) substrate, a SiC (silicon carbide) substrate, or a sapphire substrate. In semiconductor device 1, the lattice constant can be controlled by providing a buffer layer 42, which will be described later, and Si substrates, SiC substrates, sapphire substrates, etc., may be used as semiconductor layer 41.

[0060] A buffer layer 42 is disposed on the semiconductor layer 41. Figure 2A , Figure 3A In the example illustrated, buffer layer 42 is stacked on semiconductor layer 41 and located between semiconductor layer 41 and back barrier layer 43. Buffer layer 42 includes, for example, AlN, AlGaN, or GaN. In one example, buffer layer 42 may include a compound semiconductor layer epitaxially grown on semiconductor layer 41.

[0061] When the semiconductor layer 41 and the channel layer 44 have different lattice constants, the channel layer 44 can be brought into a favorable crystallization state by controlling (adjusting) the lattice constant of the buffer layer 42. This allows warping of the wafer (e.g., substrate 100) to be suppressed. For example, when the semiconductor layer 41 is constructed of a Si substrate and the channel layer 44 includes GaN, the buffer layer 42 may include AlN, AlGaN, GaN, etc.

[0062] It should be noted that the buffer layer 42 may comprise a single layer or multiple stacked layers. The buffer layer 42 may have a structure of multiple stacked layers (films) such as AlN, AlGaN, GaN, etc. In the case where the buffer layer 42 comprises a ternary material, the buffer layer 42 may have a structure in which the composition of its components gradually changes.

[0063] like Figure 2A and Figure 3A As illustrated, the semiconductor device 1 may be provided with a back barrier layer 43. The back barrier layer 43 is disposed on the buffer layer 42. Figure 2A and Figure 3A In the example illustrated, a back barrier layer 43 is stacked on top of a buffer layer 42 and is located between a channel layer 44 and a buffer layer 42. The back barrier layer 43 comprises, for example, a compound semiconductor material.

[0064] The back barrier layer 43 may include a semiconductor material that can be bonded to the channel layer 44 by band bending. The back barrier layer 43 includes, for example, a compound semiconductor material that raises the band structure of the region of the channel layer 44 adjacent to the back barrier layer 43. In one example, the back barrier layer 43 includes Al. 1-x-y Ga x In y N (0≤x<1, 0≤y<1) or u-Al without impurities (undoped) 1-x-y Ga x In y N epitaxial growth layer.

[0065] The back barrier layer 43 may comprise a single layer or multiple stacked layers. The back barrier layer 43 may have layers stacked with Al. 1-x-y Ga x In y N is a stacked structure of multiple layers with different compositions, or has a stacked structure across its Al 1-x-y Ga x In y The semiconductor device 1 is a stacked structure of multiple layers with gradually changing composition of N. It is expected that the back barrier layer 43 in the semiconductor device 1 suppresses the short-channel effect. It should be noted that the semiconductor device 1 may not include the back barrier layer 43.

[0066] The channel layer 44 comprises a compound semiconductor, such as GaN. Figure 2A and Figure 3A In the example illustrated, channel layer 44 is formed on back barrier layer 43 and located between barrier layer 45 and back barrier layer 43. Channel layer 44 and barrier layer 45 can comprise different materials. In one example, channel layer 44 is an epitaxial growth layer of GaN and is a region where charge carriers (signal charges) accumulate due to polarization between channel layer 44 and barrier layer 45. Channel layer 44 can generate and accumulate charge through polarization.

[0067] Polarization-induced charge carriers in the channel layer 44 and the barrier layer 45 form a two-dimensional electron gas (2DEG) at the interface between the channel layer 44 and the barrier layer 45. The transistor 10 that forms the two-dimensional electron gas is also called a high electron mobility transistor (HEMT).

[0068] It is important to note that the channel layer 44 may comprise impurity-free u-GaN. In this case, impurity scattering of charge carriers in the channel layer 44 can be suppressed to achieve high carrier mobility. Furthermore, the channel layer 44 may comprise any other semiconductor material.

[0069] The barrier layer 45 comprises, for example, a compound semiconductor material and is disposed on the channel layer 44. The barrier layer 45 comprises, for example, Al. 1-x-y Ga x In y N (0≤x<1, 0≤y<1) is located on the channel layer 44. Furthermore, the barrier layer 45 includes, for example, Al. 1-x In x N (0≤x≤1). Polarization may occur in the barrier layer 45 and the channel layer 44, and a two-dimensional electron gas layer 60 can be generated at the heterojunction interface, such as Figure 2A and Figure 3A As illustrated in the example diagram. Including Al 1-x In x The barrier layer 45 of N (0≤x≤1) allows for improved current capability of diode 31 and transistor 10.

[0070] Barrier layer 45 may include, for example, Al 1-x-y Ga x In y N (0≤x<1, 0≤y<1). The barrier layer 45 can be, for example, Al. 1-x-y Ga x In y The N-epitaxial growth layer. Furthermore, the barrier layer 45 can be, for example, an impurity-free u-Al. 1-x-y Ga x In yN layers. In this case, impurity scattering of carriers in channel layer 44 can be suppressed to increase carrier mobility.

[0071] It should be noted that the barrier layer 45 may comprise a single layer or multiple stacked layers. For example, the barrier layer 45 may have layers with Al stacked within it. 1-x-y Ga x In y N is a stacked structure of multiple layers with different compositions, or has a stacked structure across its Al 1-x-y Ga x In y N is a stacked structure of multiple layers whose composition gradually changes.

[0072] Semiconductor device 1 may include a cap layer. The cap layer may include, for example, GaN or SiN, and may be disposed in the surface portion of barrier layer 45. Semiconductor device 1 may include, for example, a GaN cap layer or a SiN cap layer between barrier layer 45 and insulating film 48.

[0073] For example, wiring layer 50 includes a conductor film and an insulating film, and includes multiple wirings, vias (VIAs), etc. Figure 2A and Figure 3A In the example illustrated, wiring layer 50 includes an insulating film 48. The wiring of wiring layer 50 includes, for example, metallic materials such as aluminum (Al), copper (Cu), or tungsten (W). The wiring of wiring layer 50 may include any other conductive material.

[0074] Semiconductor regions 46a and 46b are each, for example, n+ type semiconductor regions including n-type impurities (dopersants). Semiconductor regions 46a and 46b each include, for example, GaN. As n-type impurities (dopersants), for example, Si (silicon) or Ge (germanium) is used. The impurity concentration is, for example, 1 × 10⁻⁶. 18 cm -3 That's all. Semiconductor regions 46a and 46b are both high-concentration N+ layers. It should be noted that semiconductor regions 46a and 46b can include InGaN or any other material.

[0075] For example, semiconductor regions 46a and 46b are each deployed to contact a channel layer 44 in which a two-dimensional electron gas layer 60 is formed. Figure 2A and Figure 3A In the example illustrated, semiconductor region 46a is disposed from electrode 47a into channel layer 44. Semiconductor region 46b is disposed from electrode 47b into channel layer 44. Semiconductor regions 46a and 46b may be formed in barrier layer 45 and channel layer 44, respectively.

[0076] In one example, semiconductor regions 46a and 46b may each be formed to extend deeper than a portion of the channel layer 44 adjacent to the barrier layer 45 and in which a two-dimensional electron gas layer 60 is formed. Providing semiconductor regions 46a and 46b in the semiconductor device 1 allows the two-dimensional electron gas layer 60 in the channel layer 44 to be electrically coupled to electrodes 47a and 47b with low resistance.

[0077] It should be noted that semiconductor regions 46a and 46b may not be in contact with the two-dimensional electron gas layer 60. Depending on the structure of the channel layer 44 and the barrier layer 45, semiconductor region 46a (or semiconductor region 46b) and the two-dimensional electron gas layer 60 may not be in direct contact with each other.

[0078] The barrier layer 45 and the channel layer 44 can be partially removed, for example, by etching, and selectively regrown with a high concentration of N+ layers (e.g., n-type In). 1-x Ga x The removed regions are selectively filled with an N-layer (0≤x<1) to form semiconductor regions 46a and 46b. Alternatively, semiconductor regions 46a and 46b can be formed by ion implantation, for example.

[0079] Furthermore, semiconductor regions 46a and 46b may each comprise a single layer or multiple stacked layers. For example, semiconductor regions 46a and 46b may each have layers in which In are stacked. 1-x Ga x A stacked structure of multiple layers with different compositions of N (0≤x<1), or having a stack across its In 1-x Ga x The composition of N (0≤x<1) is a stacked structure of multiple layers with gradually changing composition.

[0080] Electrodes 47a and 47b each comprise, for example, titanium (Ti), aluminum (Al), nickel (Ni), or gold (Au). Electrodes 47a and 47b are ohmic electrodes. It should be noted that electrodes 47a and 47b may each comprise any other metallic material. Electrode 47a is provided to semiconductor region 46a, and electrode 47b is provided to semiconductor region 46b.

[0081] exist Figure 2A and Figure 3A In the example illustrated, electrode 47a is formed to cover semiconductor region 46a, and electrode 47b is formed to cover semiconductor region 46b. Electrode 47a is ohmically bonded to semiconductor region 46a, and electrode 47b is ohmically bonded to semiconductor region 46b. It should be noted that the respective upper portions of electrodes 47a and 47b can each be coupled to wiring in wiring layer 50 via contacts.

[0082] The insulating film 48 comprises, for example, insulating materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), silicon oxide (SiO2), or silicon nitride (SiN). Figure 2A and Figure 3A In the example illustrated, an insulating film 48 is disposed in the wiring layer 50 to cover electrodes 47a and 47b. In one example, the insulating film 48 may be an alumina film formed by an ALD (atomic vapor deposition) method.

[0083] In another example, the insulating film 48 may be a silicon oxide film or a silicon nitride film formed by a CVD (chemical vapor deposition) method. Furthermore, the insulating film 48 may comprise a single-layer film containing one of aluminum oxide, hafnium oxide, silicon oxide, silicon nitride, etc., or a stacked film containing any two or more of them. It should be noted that the insulating film 48 may comprise any other material having insulating properties.

[0084] In addition, such as Figure 2A to Figure 3B As illustrated in the example, the insulating film 48 has a gate opening 55. The gate opening 55 is formed, for example, by etching away a portion of the insulating film 48 between electrodes 47a and 47b. A gate electrode 49 is disposed in the gate opening 55. The gate electrode 49 is configured to fill the gate opening 55. In one example, the gate electrode 49 has a T-shaped cross-section.

[0085] The gate electrode 49 comprises, for example, nickel (Ni) or gold (Au). The gate electrode 49 is formed to be embedded in the gate opening 55 and may have a T-shape. The gate electrode 49 has a bottom (lower end) disposed on the barrier layer 45. The gate electrode 49 may have any other shape. Note that the wiring of the wiring layer 50 can be coupled to the upper part of the gate electrode 49 via contacts.

[0086] As described above, the transistor 10 and diode 31 of the semiconductor device 1 are disposed on the same substrate 100 and electrically coupled to terminal 20 (see [reference]). Figure 1 Transistor 10 and diode 31 can be formed in the same step. (For example...) Figure 2A , Figure 3A As illustrated in the example shown, transistor 10 and diode 31 can have the same vertical structure.

[0087] One of the semiconductor regions 46a and 46b of transistor 10, such as semiconductor region 46a, forms part of the source of transistor 10. Semiconductor region 46a is the source region, and electrode 47a can be considered as the source electrode. The other of the semiconductor regions 46a and 46b, such as semiconductor region 46b, forms part of the drain of transistor 10. Semiconductor region 46b is the drain region, and electrode 47b can be considered as the drain electrode.

[0088] In diode 31, for example, electrodes 47a and 47b are electrically coupled to each other. Figure 3B In the example illustrated, semiconductor regions 46a and 46b of diode 31 are coupled together via electrodes 47a and 47b. Electrodes 47a and 47b of diode 31 can be integrally formed. Note that electrodes 47a and 47b of diode 31 can be coupled via wiring of wiring layer 50.

[0089] For example, the gate electrode 49 of diode 31 forms the anode, and the electrodes 47 and 47b of diode 31 and the semiconductor regions 46a and 46b form the cathode. The anode of diode 31 may include the gate electrode 49 disposed in substrate 100 (semiconductor substrate). Diode 31 has a Schottky gate structure similar to that of transistor 10 and is a diode including a Schottky junction.

[0090] In semiconductor device 1, the distance between the anode and cathode of diode 31 is shorter than the distance between the gate and source or drain of transistor 10. Figure 3A and Figure 3B In the example illustrated, the spacing (distance) between the gate electrode 49, which acts as the anode of diode 31, and the semiconductor region 46a (or semiconductor region 46b), which acts as the cathode of diode 31, is represented by Lgo. Figure 3A and Figure 3B As illustrated in the example, the spacing Lgo is, for example, the distance from the gate opening 55 to the semiconductor region 46a (or semiconductor region 46b).

[0091] exist Figure 2A and Figure 2B In the example illustrated, the spacing between the gate electrode 49 of transistor 10 and the semiconductor region 46a, which serves as the source region of transistor 10, is represented by Lgs. Furthermore, the spacing between the gate electrode 49 of transistor 10 and the semiconductor region 46b, which serves as the drain region of transistor 10, is represented by Lgd. Figure 2A and Figure 2B In the example illustrated, the spacing Lgs is the distance from the gate opening 55 to the semiconductor region 46a. The spacing Lgd is the distance from the gate opening 55 to the semiconductor region 46b.

[0092] In semiconductor device 1, the spacing Lgo is shorter than the spacing Lgs and shorter than the spacing Lgd. This allows current to flow through diode 31 of protection circuit 30 at a voltage lower than that of transistor 10. This allows transistor 10 to be protected from surges.

[0093] The spacings Lgs and Lgd can each be, for example, 0.5 μm or more. The spacing Lgo can be less than 0.5 μm. The semiconductor device 1 having this structure allows for improved surge withstand voltage. Furthermore, for example, the spacings Lgs and Lgd can each be 0.4 μm or more. The spacing Lgo can be less than 0.4 μm.

[0094] In semiconductor device 1, such as Figure 2A to Figure 3B As illustrated in the example, the spacing between the gate electrode 49 of transistor 10 and the electrode 47a, which serves as the source electrode of transistor 10, can be shorter than the spacing Lgs between the gate electrode 49 and the semiconductor region 46a. Furthermore, the spacing between the gate electrode 49 of transistor 10 and the electrode 47b, which serves as the drain electrode of transistor 10, can be shorter than the spacing Lgd between the gate electrode 49 and the semiconductor region 46b.

[0095] like Figure 2A to Figure 3B As illustrated in the example, the spacing between the gate electrode 49, which acts as the anode of the diode 31, and the electrode 47a, which acts as the cathode of the diode 31, can be shorter than the spacing between the gate electrode 49 and the semiconductor region 46a. Furthermore, the spacing between the gate electrode 49, which acts as the anode of the diode 31, and the electrode 47b, which acts as the cathode of the diode 31, can be shorter than the spacing between the gate electrode 49 and the semiconductor region 46b.

[0096] Figure 4 This is a graph illustrating an example of the electrical characteristics of the diodes and transistors in the semiconductor device according to this embodiment. Figure 4 In the diagram, the horizontal axis represents the voltage applied to the gate electrode 49. The vertical axis represents the current flowing through each of the diode 31 and the transistor 10. For example, the diode 31 has a voltage of [missing information - likely a voltage rating]. Figure 4 The solid line in the figure indicates the current-voltage characteristic, and transistor 10 has a current-voltage characteristic indicated by the solid line in the figure. Figure 4 The dashed line in the figure indicates the current-voltage characteristic.

[0097] In the case of a negative surge input through terminal 20 (see...) Figure 1 A bias voltage in the reverse direction is applied to the gate of transistor 10 and the gate of diode 31. As described above, the spacing Lgo between the gate, which acts as the anode of diode 31, and the semiconductor region 46a (or semiconductor region 46b), which acts as the cathode of diode 31, is relatively short. In diode 31, the depletion layer below the gate electrode 49 is therefore unlikely to extend, which allows current to flow at low voltages, such as... Figure 4 As illustrated in the example. This enhances the ability to handle negative surge currents and prevents transistor 10 from being damaged by surges.

[0098] In semiconductor device 1, for example, when a negative surge voltage is applied through terminal 20, diode 31 is brought into a low-impedance state before transistor 10, allowing current to flow between terminal 20 and reference potential line L1. Diode 31 forms a charge discharge path between terminal 20 and reference potential line L1. This allows excess charge generated at terminal 20 to be discharged through diode 31 to suppress excess voltage and current in the internal circuitry of semiconductor device 1. This improves the surge tolerance of semiconductor device 1.

[0099] When a positive surge is input through terminal 20, a forward bias is applied to the gate of transistor 10 and the gate of diode 31. In this situation, transistor 10 is brought into a low-impedance state to allow forward current to flow. Diode 31 is also brought into a low-impedance state to allow forward current to flow between terminal 20 and the reference potential line L1. Setting diode 31 improves ESD tolerance.

[0100] In this embodiment, transistor 10 and diode 31 can be formed in the same step. Therefore, the protective element can be formed while preventing an increase in the number of steps in the manufacturing process. This allows for the suppression of an increase in the manufacturing cost of semiconductor device 1. The size of diode 31 can also be reduced compared to the size of transistor 10, thus suppressing an increase in chip size. This, for example, allows for the prevention of an increase in the size of the protective element (and protective circuitry) and suppresses the degradation of circuit characteristics caused by parasitic capacitance.

[0101] It is important to note that the differences between diode 31 and transistor 10 may lie in structural aspects such as the gate width, the length of gate electrode 49, the lengths of electrodes 47a and 47b, or the presence or absence of a field plate. In both diode 31 and transistor 10, the spacing Lgo can be in the depth direction ( Figure 2B and Figure 3B At least a portion of the plan view (in the vertical direction) is shorter than each of the intervals Lgs and Lgd.

[0102] Figure 5A to Figure 5G These are all explanatory diagrams illustrating examples of a semiconductor device manufacturing method according to this embodiment. Figure 5A As illustrated, a buffer layer 42 is first formed on a semiconductor layer 41 comprising Si (silicon). Subsequently, impurity-free u-AlGaN (e.g., u-Al) is epitaxially grown on the buffer layer 42. 0.05 Ga 0.95 (N mixed crystal) to form a back barrier layer 43. Thereafter, for example, a GaN layer as a channel layer 44 is formed on the back barrier layer 43 by epitaxial growth.

[0103] Subsequently, impurity-free u-AlGaN (e.g., u-Al) is epitaxially grown on the channel layer 44. 0.3 Ga 0.7 (N mixed crystal) to form a barrier layer 45. Subsequently, as... Figure 5A As illustrated, an insulating film 110 is formed as a selection mask used in the case of performing regrowth. Subsequently, a component separation section (not shown) is formed. The component separation section separates components such as transistor 10.

[0104] For example, inactive regions where resistance increases through boron ion implantation are formed as component separation regions. As a result, for example, Figure 2B and 3B The active region 80 shown in the figure is separated into islands. It should be noted that the step of separating the elements, which will be described later, can be performed after the steps of forming semiconductor regions 46a and 46b, which will be described later, or after the step of forming the gate.

[0105] After that, as Figure 5B As illustrated, a portion of the insulating film 110, barrier layer 45, and channel layer 44 are selectively removed through patterning (e.g., etching and photolithography) to form regions for semiconductor regions 46a and 46b. Subsequently, as... Figure 5C As illustrated, semiconductor regions 46a and 46b are formed by selective regrowth. Subsequently, the insulating film 110 is removed by etching.

[0106] After that, as Figure 5D As illustrated, electrodes 47a and 47b are formed by patterning. In this case, for example, electrodes 47a and 47b are formed by sequentially depositing titanium (Ti), aluminum (Al), nickel (Ni), and gold (Au).

[0107] After that, as Figure 5E As illustrated, an insulating film 48 comprising silicon oxide is formed on the barrier layer 45 and electrodes 47a and 47 by, for example, a CVD method. Subsequently, as... Figure 5F As illustrated, the insulating film 48 is patterned by etching to form a gate opening 55 in the insulating film 48. In the gate opening 55, the surface of the barrier layer 45 is exposed.

[0108] After that, as Figure 5G As illustrated, a gate electrode 49 is formed in the insulating film 48 to fill the gate opening 55. In this case, for example, the gate electrode 49 is formed by sequentially depositing nickel (Ni) and gold (Au). The above manufacturing method allows for the fabrication of... Figure 2A to Figure 3B The semiconductor device 1 is illustrated in the figure. It should be noted that the above manufacturing method is merely an example, and any other manufacturing method may be used.

[0109] [Work and Results]

[0110] The semiconductor device (semiconductor device 1) according to this embodiment includes: a transistor (transistor 10) disposed in a semiconductor substrate (e.g., substrate 100) and including a gate electrode, a source electrode, and a drain electrode; a terminal (terminal 20) electrically coupled to the transistor; and a diode (diode 31) disposed in the semiconductor substrate and electrically coupled to the terminal. The spacing between the anode and cathode of the diode is shorter than the spacing between the gate electrode and the source or drain electrode of the transistor.

[0111] In the semiconductor device 1 according to this embodiment, the distance Lgo between the anode and cathode of the diode 31 is shorter than the distance Lgs (or distance Lgd) between the gate electrode and the source (or drain) of the transistor. Therefore, in the event of a surge at terminal 20, the surge can be released through the diode 31. This makes it possible to realize the semiconductor device 1 with good surge tolerance.

[0112] In the semiconductor device 1 according to this embodiment, the anode of the diode (diode 31) is the gate electrode (gate electrode 49) of the diode disposed in the semiconductor substrate (substrate 100). The anode of the diode comprises the same material as the gate electrode of the transistor. Furthermore, the cathode of the diode comprises the same material as the source or drain of the transistor. In this embodiment, the transistor 10 and the diode 31 can be formed in the same step. Protective elements can be formed while suppressing an increase in the number of steps in the manufacturing process. This prevents an increase in the manufacturing cost of the semiconductor device 1.

[0113] Next, variations of this disclosure will be described. In the following, components similar to those in the foregoing embodiments will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0114] <2. Variations>

[0115] (2-1. Variation Example 1)

[0116] Figure 6A and Figure 6B These are all explanatory diagrams illustrating the construction examples of semiconductor devices according to Modification 1 of this disclosure. Figure 6A An example of the cross-sectional structure of the diode 31 of the semiconductor device 1 is illustrated. Figure 6B An example of a planar configuration of diode 31 in semiconductor device 1 is illustrated. Electrode 47a may have a width smaller than the width of semiconductor region 46a. Figure 6A and Figure 6B In the example illustrated, electrode 47a has a width W2a that is smaller than the width W1a of semiconductor region 46a.

[0117] Furthermore, electrode 47b can have a width smaller than that of semiconductor region 46b. Figure 6A and Figure 6B In the example illustrated, electrode 47b has a width W2b smaller than the width W1b of semiconductor region 46b. This configuration of the semiconductor device 1 allows electrode 47a (and electrode 47b) to be separated from gate electrode 49 while maintaining the spacing Lgo. This allows for precise handling of gate electrode 49. Furthermore, it prevents large parasitic capacitances from being added between gate electrode 49 and electrode 47a (or electrode 47b), and suppresses the occurrence of characteristic degradation of the semiconductor device 1.

[0118] (2-2. Variation Example 2)

[0119] Figure 7 and Figure 8 These are all explanatory diagrams based on the construction example of the semiconductor device according to Modification 2. Figure 7 An example of the cross-sectional structure of the transistor 10 of the semiconductor device 1 is illustrated. Figure 8 An example of the cross-sectional structure of the diode 31 of the semiconductor device 1 is illustrated.

[0120] In the foregoing embodiments and modifications, examples of the construction of transistor 10 and diode 31 have been described; however, these examples are merely illustrative, and the construction of transistor 10 and diode 31 is not limited to the examples described above. For example, as... Figure 7 and Figure 8 As illustrated in the example, the insulating film 48 can be disposed along the electrode 47a, the barrier layer 45, and the electrode 47b.

[0121] Furthermore, for example, diode 31 can have a gate width larger than that of transistor 10. In this case, the current capability of diode 31 can be enhanced, and surge-induced current can be effectively released through diode 31. This allows for improved surge tolerance of semiconductor device 1.

[0122] (2-3. Variation Example 3)

[0123] Figure 9 and Figure 10 These are all explanatory diagrams based on the construction example of the semiconductor device according to Modification 3. Figure 9 and Figure 10 Examples of cross-sectional structures of the transistor 10 and diode 31 of the semiconductor device 1 are illustrated respectively. Figure 9 As illustrated in the example, transistor 10 may not include semiconductor regions 46a and 46b. Furthermore, as... Figure 10 As illustrated in the example, diode 31 may not include semiconductor regions 46a and 46b.

[0124] existFigure 9 In the example illustrated, the spacing between the gate electrode 49 of transistor 10 and the electrode 47a, which serves as the source electrode of transistor 10, is represented by Lgs. Furthermore, the spacing between the gate electrode 49 of transistor 10 and the electrode 47b, which serves as the drain electrode of transistor 10, is represented by Lgd. Figure 9 In the example illustrated, the spacing Lgs is the distance from the gate opening 55 to the electrode 47a. The spacing Lgd is the distance from the gate opening 55 to the electrode 47b.

[0125] In addition, Figure 10 In the example illustrated, the spacing (distance) between the gate electrode 49, which acts as the anode of diode 31, and the electrode 47a (or electrode 47b), which acts as the cathode of diode 31, is represented by Lgo. Figure 10 As illustrated in the example, the spacing Lgo is, for example, the distance from the gate opening 55 to the electrode 47a (or electrode 47b).

[0126] In the semiconductor device 1 according to this variation, the spacing Lgo is shorter than the spacing Lgs and shorter than the spacing Lgd. This allows current to flow through diode 31 at a voltage lower than that of transistor 10. This allows the internal circuitry of semiconductor device 1 (e.g., transistor 10) to be protected from surges.

[0127] As described above, semiconductor device 1 may not include semiconductor regions 46a and 46b. In this case, annealing can be performed after forming electrodes 47a and 47b. This allows the two-dimensional electron gas layer 60 to be coupled to electrodes 47a and 47b with relatively low resistance. In this variation, effects similar to those of the semiconductor device in the aforementioned embodiment can also be achieved.

[0128] (2-4. Variation Example 4)

[0129] Figure 11 This is an explanatory diagram illustrating the construction example of a semiconductor device according to Modification 4. In the foregoing embodiments, an example in which diode 31 is coupled between terminal 20 and the source of transistor 10 has been described. However, as... Figure 11 As illustrated in the example, the cathode of diode 31 can be coupled to the GND terminal (ground terminal). In this variation, a similar effect to that of the semiconductor device in the aforementioned embodiment can also be achieved.

[0130] (2-5. Variation Example 5)

[0131] Figure 12This is an explanatory diagram illustrating the construction example of the semiconductor device according to Modification 5. The protection circuit 30 of the semiconductor device 1 includes a resistor R1 in addition to the diode 31. The resistor R1 is a resistor and is disposed between the terminal 20 and the transistor 10. Furthermore, the resistor R1 is located between the terminal 20 and the diode 31 of the protection circuit 30.

[0132] Transistor 10 and diode 31 are electrically coupled to terminal 20 via resistor R1. It should be noted that the resistance value of resistor R1 can be appropriately adjusted depending on the type of ESD, the operating frequency of semiconductor device 1, etc., and the resistance value can be, for example, 1kΩ or more. The resistance value of resistor R1 can be, for example, 10kΩ or more. The resistance value of resistor R1 can be selected to give the time constant a desired value. The resistance value of resistor R1 can be set, for example, between 1kΩ and 100kΩ.

[0133] Some time constants of ESD could potentially damage transistor 10 before protection circuit 30 releases the surge. To address this issue, in the semiconductor device 1 according to this variation, a resistive element R1 is formed between transistor 10 and terminal 20. This delays the surge propagation to transistor 10. This allows the semiconductor device 1 to be protected by releasing the surge through protection circuit 30 before the surge voltage reaches the withstand voltage of the internal circuitry of the semiconductor device 1.

[0134] Figure 13 This is an illustrative diagram of another construction example of the semiconductor device according to Modification 5. The protection circuit 30 may include resistors R2 and R3. For example, resistor R2 is electrically coupled between terminal 20 and transistor 10. Resistor R3 is electrically coupled between terminal 20 and diode 31. The arrangement of resistors R2 and R3 allows transistor 10 and diode 31 to have different surge delays.

[0135] Resistor R2 and resistor R3 have, for example, different resistance values. Resistor R2 coupled to transistor 10 can have a higher resistance value than resistor R3 coupled to diode 31. This allows for an increase in the delay of the surge applied to transistor 10 and efficient discharge of charge through diode 31. By delaying the surge's propagation to the gate of transistor 10 and allowing the surge-induced current to flow through diode 31, damage to the gate of transistor 10 can be prevented.

[0136] (2-6. Variation Example 6)

[0137] The diode 31 of the semiconductor device 1 may include only one of electrode 47a (and semiconductor region 46a) and electrode 47b (and semiconductor region 46b). For example, the diode 31 includes at least one of semiconductor region 46a disposed in the substrate 100 around gate electrode 49 and semiconductor region 46b disposed in the substrate 100 opposite to semiconductor region 46a opposite to gate electrode 49.

[0138] For example, diode 31 may include electrode 47a and semiconductor region 46a, but may not include electrode 47b and semiconductor region 46b. Furthermore, electrode 47b and semiconductor region 46b may be deployed in the region of diode 31, but electrode 47a and semiconductor region 46a may not be deployed. One of semiconductor regions 46a and 46b of diode 31 may be used as a cathode (or anode), and the other of semiconductor regions 46a and 46b of diode 31 may be used as an inactive region.

[0139] (2-7. Variation Example 7)

[0140] Semiconductor device 1 may include any semiconductor other than GaN semiconductor. For example, semiconductor device 1 may include GaAs compound semiconductor, InP compound semiconductor, or SiGe compound semiconductor. Diode 31, used as a protection element, may include GaAs compound semiconductor material, InP compound semiconductor material, or any other compound semiconductor material.

[0141] <3. Application Examples>

[0142] For example, the semiconductor device 1 described above is suitable for various electronic devices with communication functions. Figure 14 This is a diagram illustrating an example of the construction of the wireless communication device 200 disclosed herein. For example... Figure 14 As illustrated, the wireless communication device 200 includes an antenna ANT, an antenna switch circuit 201, a high-power amplifier HPA, a radio frequency integrated circuit (RFIC), a baseband unit BB, an audio output unit MIC, a data output unit DT, and an interface I / F.

[0143] Interface I / F is, for example, an interface circuit using wireless LAN (Wireless Local Area Network or W-LAN), Bluetooth (registered trademark), etc. Wireless communication device 200 is, for example, a multi-functional mobile phone system for audio or data communication, LAN connection, etc.

[0144] In the wireless communication device 200, a semiconductor device including a protection circuit, according to any of the foregoing embodiments and variations, is applied to the antenna switch circuit 201, the high-power amplifier HPA, the radio frequency integrated circuit (RFIC), the baseband unit BB, etc. For example, applying the technology according to this disclosure to the antenna switch circuit 201, the baseband unit BB, etc., can effectively suppress ESD damage to the wireless communication device 200.

[0145] Although the present disclosure has been described above with reference to embodiments, modifications, and application examples, the technology is not limited to the foregoing embodiments and various modifications can be made. For example, the foregoing modifications have been described as modifications of the foregoing embodiments; however, any two or more of the various constructions of the modifications can be appropriately combined with each other.

[0146] It should be noted that the effects described in this specification are merely illustrative and are not restrictive. Any other effects can also be achieved. This disclosure may also have any of the following constructions. (1)

[0148] A semiconductor device, comprising:

[0149] A transistor is disposed in a semiconductor substrate and includes a gate electrode, a source electrode, and a drain electrode;

[0150] Terminals, electrically coupled to the transistor; and

[0151] A diode, disposed in the semiconductor substrate and electrically coupled to the terminal, wherein

[0152] The spacing between the anode and cathode of the diode is shorter than the spacing between the gate electrode and the source or drain of the transistor. (2)

[0154] According to the semiconductor device described in (1), wherein,

[0155] The gate electrode of the transistor is electrically coupled to the terminal, and

[0156] The anode of the diode is electrically coupled to the terminal. (3)

[0158] According to the semiconductor device described in (1) or (2), wherein,

[0159] The anode of the diode is the gate electrode of the diode disposed in the semiconductor substrate, and

[0160] The anode of the diode comprises the same material as the gate electrode of the transistor. (4)

[0162] The semiconductor device according to any one of (1) to (3), wherein the cathode of the diode comprises the same material as the source or drain of the transistor. (5)

[0164] The semiconductor device according to any one of (1) to (4), wherein the cathode of the diode includes at least one of an n-type first semiconductor region and an n-type second semiconductor region, the first semiconductor region being disposed in the semiconductor substrate around the gate electrode of the diode, and the second semiconductor region being disposed in the semiconductor substrate opposite to the gate electrode of the diode and opposite to the first semiconductor region. (6)

[0166] The semiconductor device according to any one of (1) to (5), wherein the semiconductor substrate comprises a nitride semiconductor. (7)

[0168] The semiconductor device according to any one of (1) to (6), wherein the transistor includes a channel layer and a barrier layer disposed between the gate electrode and the channel layer. (8)

[0170] According to the semiconductor device of (7), wherein the barrier layer comprises Al 1-x-y Ga x In y N, where 0≤x<1 and 0≤y<1. (9)

[0172] The semiconductor device according to any one of (1) to (8), wherein,

[0173] The diode includes a channel layer and a barrier layer disposed between the anode and the channel layer, and

[0174] The transistor includes the channel layer and the barrier layer. (10)

[0176] The semiconductor device according to any one of (1) to (9), wherein,

[0177] The gate electrode of the transistor is electrically coupled to the terminal.

[0178] The anode of the diode is electrically coupled to the terminal, and

[0179] The cathode of the diode is electrically coupled to the source of the transistor. (11)

[0181] The semiconductor device according to any one of (1) to (10), wherein,

[0182] The anode of the diode is electrically coupled to the terminal, and

[0183] The cathode of the diode is electrically coupled to ground. (12)

[0185] The semiconductor device according to any one of (1) to (11) wherein the spacing between the gate electrode and the source or the drain of the transistor is 0.5 μm or more. (13)

[0187] The semiconductor device according to any one of (1) to (12) wherein the spacing between the anode and the cathode of the diode is less than 0.5 μm. (14)

[0189] The semiconductor device according to any one of (1) to (13), wherein,

[0190] The source and drain of the transistor each include an n-type semiconductor region and an ohmic electrode, and

[0191] The spacing between the gate electrode and the ohmic electrode of the transistor is shorter than the spacing between the gate electrode and the semiconductor region. (15)

[0193] The semiconductor device according to any one of (1) to (14), wherein,

[0194] The cathode of the diode includes an n-type semiconductor region and an ohmic electrode, and

[0195] The spacing between the anode and the ohmic electrode of the diode is shorter than the spacing between the anode and the semiconductor region. (16)

[0197] The semiconductor device according to any one of (1) to (15) further includes a first resistive element electrically coupled to the terminal, wherein,

[0198] The transistor is electrically coupled to the terminal through the first resistive element, and

[0199] The diode is electrically coupled to the terminal through the first resistive element. (17)

[0201] The semiconductor device according to (16) further includes a second resistive element and a third resistive element, each electrically coupled to the terminal, wherein

[0202] The transistor is electrically coupled to the terminal via the second resistive element, and

[0203] The diode is electrically coupled to the terminal via the third resistive element. (18)

[0205] According to the semiconductor device of (17), the second resistive element has a resistance value that is higher than that of the third resistive element. (19)

[0207] An electronic device includes a circuit, the circuit comprising:

[0208] A transistor is disposed in a semiconductor substrate and includes a gate electrode, a source electrode, and a drain electrode.

[0209] Electrically coupled to the terminals of the transistor, and

[0210] A diode disposed in the semiconductor substrate and electrically coupled to the terminal, wherein

[0211] The spacing between the anode and cathode of the diode is shorter than the spacing between the gate electrode and the source or drain of the transistor.

[0212] This application claims the benefit of Japanese priority patent application JP2023-114180, filed with the Japan Patent Office on July 12, 2023, the entire contents of which are incorporated herein by reference.

[0213] Those skilled in the art will understand that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors, as long as they are within the scope of the appended claims or their equivalents.

Claims

1. A semiconductor device comprising: a transistor provided in a semiconductor substrate and including a gate electrode, a source, and a drain; a terminal electrically coupled to the transistor; and a diode provided in the semiconductor substrate and electrically coupled to the terminal, wherein a separation between an anode and a cathode of the diode is shorter than a separation between the gate electrode and the source or the drain of the transistor.

2. The semiconductor device according to claim 1, wherein the gate electrode of the transistor is electrically coupled to the terminal, and the anode of the diode is electrically coupled to the terminal.

3. The semiconductor device according to claim 1, wherein the anode of the diode is a gate electrode of the diode provided in the semiconductor substrate, and the anode of the diode includes a same material as a material of the gate electrode of the transistor. the cathode of the diode includes a same material as a material of the source or the drain of the transistor.

4. The semiconductor device according to claim 1, wherein the cathode of the diode includes at least one of a first semiconductor region of an n-type provided around the gate electrode of the diode in the semiconductor substrate and a second semiconductor region of an n-type provided opposite to the first semiconductor region across the gate electrode of the diode in the semiconductor substrate.

5. The semiconductor device according to claim 1, wherein the semiconductor substrate includes a nitride semiconductor.

6. The semiconductor device according to claim 1, wherein the transistor includes a channel layer and a barrier layer provided between the gate electrode and the channel layer.

7. The semiconductor device according to claim 1, wherein 9. The semiconductor device according to claim 1, wherein 8. The semiconductor device according to claim 7, wherein The barrier layer includes Al 1-x-y Ga x In y N, where 0≤x<1 and 0≤y<1 are satisfied. the diode includes a channel layer and a barrier layer provided between the anode and the channel layer, and the transistor includes the channel layer and the barrier layer.

10. The semiconductor device according to claim 1, wherein the gate electrode of the transistor is electrically coupled to the terminal, the anode of the diode is electrically coupled to the terminal, and the cathode of the diode is electrically coupled to the source of the transistor.

11. The semiconductor device according to claim 1, wherein the anode of the diode is electrically coupled to the terminal, and the cathode of the diode is electrically coupled to a ground line. a separation between the gate electrode and the source or the drain of the transistor is 0.5 pm or more.

12. The semiconductor device according to claim 1, wherein a separation between the anode and the cathode of the diode is less than 0.5 pm.

13. The semiconductor device according to claim 1, wherein 14. The semiconductor device according to claim 1, wherein the source and the drain of the transistor each include a semiconductor region of an n-type and an ohmic electrode, and a separation between the gate electrode of the transistor and the ohmic electrode is shorter than a separation between the gate electrode and the semiconductor region.

15. The semiconductor device according to claim 1, wherein the cathode of the diode includes a semiconductor region of an n-type and an ohmic electrode, and a separation between the anode of the diode and the ohmic electrode is shorter than a separation between the anode and the semiconductor region.

16. The semiconductor device according to claim 1, further comprising a first resistive element electrically coupled to the terminal, wherein the transistor is electrically coupled to the terminal through the first resistive element, and the diode is electrically coupled to the terminal through the first resistive element. ​ 17. The semiconductor device according to claim 1, further comprising a second resistive element and a third resistive element each electrically coupled to the terminal, wherein the transistor is electrically coupled to the terminal through the second resistive element, and the diode is electrically coupled to the terminal through the third resistive element. The second resistive element has a higher resistance value than a resistance value of the third resistive element.

19. An electronic device comprising a circuit, the circuit comprising: a transistor provided in a semiconductor substrate and including a gate electrode, a source, and a drain, a terminal electrically coupled to the transistor, and a diode provided in the semiconductor substrate and electrically coupled to the terminal, wherein a separation between an anode and a cathode of the diode is shorter than a separation between the gate electrode and the source or the drain of the transistor.

18. The semiconductor device according to claim 17, wherein ​ ​ ​ ​ ​ ​

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