Conductive materials for direct bonding

Abstract

A structure includes: a first substrate including a first layer having at least one electrically conductive first portion and at least one electrically insulating second portion; and a second substrate, the second substrate comprising a second layer, the second layer having at least one electrically conductive third portion and at least one electrically insulating fourth portion. The structure also includes an interface layer between the first layer and the second layer having at least one electrically conductive oxide material. The at least one electrically conductive oxide material includes: at least one first region between and in electrical communication with the at least one electrically conductive first portion and the at least one electrically conductive third portion; and at least one second region between the at least one electrically insulating second portion and the at least one electrically insulating fourth portion.

Description

TECHNICAL FIELD

[0001] The field relates to systems and methods for wafer-to-wafer, die-to-die, and / or die-to-wafer hybrid bonding of semiconductor devices and optoelectronic devices. BACKGROUND

[0002] Semiconductor elements, such as semiconductor wafers or integrated device dies, can be stacked and directly bonded to one another without adhesives, thereby forming a bonded structure. Non-conductive (e.g., dielectric; semiconductive) surfaces can be made extremely smooth and treated to enhance direct covalent bonding, even at room temperature and without the application of pressure beyond that of contact. In some hybrid bonded structures, non-conductive field regions of the elements can be directly bonded to one another, and corresponding conductive contact structures can also be directly bonded to one another.

[0003] For example, semiconductor elements can be mounted on a carrier, such as a packaging substrate, an interposer, a reconstituted wafer or element, a flat plate, glass, etc. The semiconductor elements can be stacked on top of one another (e.g., a first integrated device die can be stacked on a second integrated device die). Each of the semiconductor elements can have conductive pads for mechanically and electrically bonding the semiconductor elements to one another, with the conductive pads mechanically and electrically bonded to one another. SUMMARY

[0004] Certain implementations described herein provide a structure including a first substrate including a first layer having at least one electrically conductive first portion and at least one electrically insulating second portion. The structure also includes a second substrate including a second layer having at least one electrically conductive third portion and at least one electrically insulating fourth portion. The structure also includes an interface layer between the first layer and the second layer. The interface layer includes at least one electrically conductive oxide material. The at least one electrically conductive oxide material includes at least one first region between and in electrical communication with the at least one electrically conductive first portion and the at least one electrically conductive third portion. The at least one electrically conductive oxide material also includes at least one second region between the at least one electrically insulating second portion and the at least one electrically insulating fourth portion. The at least one second region is electrically isolated from the at least one first region.

[0005] Certain implementations described herein provide a structure including a first substrate having a first electrically conductive feature including a first region of a first deposited electrically conductive oxide material. The structure also includes a second substrate having a second electrically conductive feature directly bonded to the first electrically conductive feature.

[0006] Certain embodiments described herein provide a method comprising providing a first substrate and a second substrate, each substrate comprising one or more electrically conductive surface portions and one or more electrically insulating surface portions. At least one of the first substrate and the second substrate further comprises an electrically conductive oxide layer having a first region over and in electrical communication with the one or more electrically conductive surface portions and a second region over the one or more electrically insulating surface portions. The second region is electrically isolated from the first region. The method further comprises directly bonding the first substrate and the second substrate to one another without an intervening adhesive. The directly bonding the first substrate and the second substrate comprises bringing the first substrate and the second substrate into contact with one another with the electrically conductive oxide layer between the first substrate and the second substrate.

[0007] Certain embodiments described herein provide a method comprising providing a first substrate having a first patterned electrically conductive contact feature. The first patterned electrically conductive contact feature comprises a first region of a first electrically conductive oxide material. The method further comprises providing a second substrate having a second electrically conductive contact feature. The method further comprises directly bonding the first electrically conductive contact feature to the second electrically conductive contact feature.

[0008] Certain embodiments described herein provide a method comprising providing a first patterned electrically conductive contact feature in a first substrate. The method further comprises providing a second patterned electrically conductive contact feature in a second substrate. The method further comprises directly bonding the first patterned electrically conductive contact feature to the second patterned electrically conductive contact feature. The first substrate and the second substrate are not activated after the first patterned electrically conductive contact feature is patterned and before the direct bonding.

[0009] Certain embodiments described herein provide a method comprising providing a first patterned electrically conductive contact feature in a first substrate. The method further comprises providing a second patterned electrically conductive contact feature in a second substrate. The method further comprises directly bonding the first patterned electrically conductive contact feature to the second patterned electrically conductive contact feature. The first substrate is not planarized after the first electrically conductive contact feature is patterned and before the direct bonding.

[0010] Certain embodiments described herein provide a structure comprising: a first substrate comprising a first layer comprising a dielectric oxide portion and an electrically conductive portion; a second substrate comprising a second layer comprising a dielectric oxide portion and an electrically conductive portion; and an interface layer between the first layer and the second layer. The interface layer comprises at least one electrically conductive oxide material and comprises a first portion between the dielectric oxide portions of the first layer and the second layer and a second portion between the electrically conductive portions of the first layer and the second layer, the first portion of the interface layer being electrically isolated from the second portion of the interface layer.

[0011] Certain embodiments described herein provide a method comprising: providing a first element comprising a first surface layer comprising a dielectric oxide portion and an electrically conductive portion. The method further comprises providing a second element comprising a second surface layer comprising a dielectric oxide portion and an electrically conductive portion. The method further comprises depositing an electrically conductive oxide layer over at least one of the first surface layer and the second surface layer. The deposited layer comprises a first portion over the dielectric oxide portion of at least one of the first surface layer and the second surface layer, and the deposited layer further comprises a second portion over the electrically conductive portion of at least one of the first surface layer and the second surface layer. The first portion of the deposited layer is electrically isolated from the second portion of the deposited layer. The method further comprises directly bonding the first element and the second element to one another without an intervening adhesive. The direct bonding comprises bonding the first surface layer and the second surface layer together with the electrically conductive oxide layer between the first surface layer and the second surface layer.

[0012] Certain embodiments described herein provide a method comprising: providing a first substrate having a first electrically conductive contact feature. The first electrically conductive contact feature comprises a first region of a first deposited electrically conductive oxide material. The method further comprises providing a second substrate having a second electrically conductive contact feature. The method further comprises directly bonding the first electrically conductive contact feature to the second electrically conductive contact feature. BRIEF DESCRIPTION OF DRAWINGS

[0013] A specific implementation will be described below with reference to the accompanying drawings, which are provided by way of example and not limitation.

[0014] FIG. 1A is a schematic cross-sectional side view of two elements prior to bonding in accordance with certain embodiments described herein.

[0015] FIG. 1B is a schematic cross-sectional side view of two elements after bonding in accordance with certain embodiments described herein. FIG. 1A is a schematic cross-sectional side view of two elements after bonding in accordance with certain embodiments described herein.

[0016] FIG. 2A and FIG. 2B schematically illustrates two cross-sectional views of an example structure in accordance with certain embodiments described herein.

[0017] FIG. 2C and FIG. 2D schematically illustrates a cross-sectional view of another example structure in accordance with certain embodiments described herein.

[0018] FIG. 3A and FIG. 3Bschematically illustrates two cross-sectional views of another example structure according to certain embodiments described herein.

[0019] FIG. 3C and FIG. 3D schematically illustrates a cross-sectional view of other example structures according to certain embodiments described herein.

[0020] FIG. 4A and FIG. 4B schematically illustrates two cross-sectional views of another example structure according to certain embodiments described herein.

[0021] FIG. 4C schematically illustrates a cross-sectional view of another example structure according to certain embodiments described herein.

[0022] FIG. 4D-FIG. 4F schematically illustrates a cross-sectional view of a section of an example die, an example first die layout, and an example second die layout according to certain embodiments described herein.

[0023] FIG. 5 is a flowchart of an example method for forming a structure compatible with certain embodiments described herein.

[0024] FIG. 6A and FIG. 6B schematically illustrates an example method for forming an example structure of FIG. 2A and FIG. 2B according to certain embodiments described herein.

[0025] FIG. 7A and FIG. 7B schematically illustrates an example method for forming an example structure of FIG. 3A and FIG. 3B according to certain embodiments described herein.

[0026] FIG. 8A and FIG. 8B schematically illustrates another example of a method for forming a structure according to certain embodiments described herein. FIG. 5

[0027] FIG. 9A and FIG. 9B schematically illustrates another example structure according to certain embodiments described herein and an example method for forming the structure.

[0028] FIG. 10 schematically illustrates an example build process flow for forming the structure according to certain embodiments described herein. DETAILED DESCRIPTION ​

[0029] Various embodiments disclosed herein relate to direct bonding structures in which two or more elements can be directly bonded to one another without the need for an intervening adhesive. Such processes and structures are referred to herein as "direct bonding" processes or "direct bonding" structures. Direct bonding can involve bonding one material on one element and bonding one material on another element (also referred to herein as "uniform" direct bonding), where the materials on the different elements need not be the same, without the need for a traditional adhesive material. Direct bonding can also involve bonding multiple materials on one element to multiple materials on another element (e.g., hybrid bonding).

[0030] In some implementations (not shown), each bonding layer has one material. In these uniform direct bonding processes, only one material on each element is directly bonded. For example, an example uniform direct bonding process includes the ZIBOND® technology commercially available from Adeia Corporation (located in San Jose, California). The materials of the opposing bonding layers on different elements can be the same or different, and can include elemental or compound materials. For example, in some embodiments, a non-conductive bonding layer can be blanket deposited over a base substrate portion without being patterned with conductive features (e.g., no pads). In other embodiments, the bonding layers can be patterned on one or both elements, and can be the same or different from one another, but one material from each element is directly bonded across the element surface (if the element sizes are different, the bonding is across the surface of the smaller element) without an adhesive. In another implementation of uniform direct bonding, one or both of the non-conductive bonding layers can include one or more conductive features, but these conductive features do not participate in the bonding. For example, in some implementations, opposing non-conductive bonding layers can be uniformly directly bonded to one another, and then a through-substrate via (TSV) is formed through one element after bonding to provide electrical communication with the other element.

[0031] In various embodiments, the bonding layers 108a and / or 108b can include a non-conductive material, such as a dielectric material or an undoped semiconductor material, such as undoped silicon, which can include native oxide. Suitable dielectric bonding surfaces or materials for direct bonding include, but are not limited to, inorganic dielectric materials, such as silicon oxide, silicon nitride, or silicon oxynitride, or can include carbon, such as silicon carbide, silicon carbon oxynitride, low-K dielectric constant materials, SiCOH dielectrics, silicon carbonitride, or diamond-like carbon, or materials that include a diamond surface. Such carbon-containing ceramic materials can still be considered inorganic materials, despite containing carbon. In some embodiments, the dielectric material at the bonding surface does not include a polymeric material, such as an epoxy (e.g., an epoxy adhesive, cured epoxy, or an epoxy composite material, such as an FR-4 material), a resin, or a molding material.

[0032] In other embodiments, the bonding layer can include an electrically conductive material, such as depositing a conductive oxide material, for example indium tin oxide (ITO), as disclosed in U.S. Provisional Patent Application No. 63 / 524,564, filed June 30, 2023, the entirety of which is incorporated by reference herein in its entirety, to provide an example of a conductive bonding layer that does not cause a short circuit of the contact through the interface.

[0033] In direct bonding, the first and second elements can be bonded directly to one another without an adhesive, which is different from the deposition process, and also different in structure compared to the interface created by deposition. In one application, the width of the first element in the bonded structure is similar to the width of the second element. In some other embodiments, the width of the first element in the bonded structure is different from the width of the second element. The width or area of the larger element in the bonded structure can be at least 10% larger than the width or area of the smaller element. Further, unlike the interface under the deposited layer, the interface between the directly bonded structures can include a defect region with nanoscale voids (nanovoids) present in the defect region. The formation of nanovoids can be due to activation of one or both of the bonding surfaces (e.g., exposure to a plasma, as explained below).

[0034] The bonding interface between the non-conductive bonding surfaces can include a higher concentration of material from the activation and / or final chemical treatment process compared to the bulk of the bonding layer. For example, in embodiments utilizing a nitrogen plasma for activation, a peak in nitrogen concentration can be formed at the bonding interface. In some embodiments, the peak in nitrogen concentration can be detected using secondary ion mass spectrometry (SIMS) techniques. For example, in various embodiments, a nitrogen termination process (e.g., exposing the bonding surfaces to a nitrogen-containing plasma) can replace OH groups of a hydroxyl (OH-terminated) surface with NH2molecules, resulting in a nitrogen-terminated surface. In embodiments utilizing an oxygen plasma for activation, a peak in oxygen concentration can be formed at the bonding interface between the non-conductive bonding surfaces. In some embodiments, the bonding interface can include silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. Direct bonding can include covalent bonds, which are stronger than van der Waals bonds. The bonding layer can also include a surface that is planarized to a highly smooth, post-polished surface.

[0035] In direct bonding processes, such as uniform direct bonding and hybrid bonding, two elements are bonded together without the need for an intermediate adhesive. In non-direct bonding processes that utilize an adhesive, an intermediate material is typically applied to one or both elements to achieve a physical connection between the elements. For example, in some adhesive-based processes, a flowable adhesive (e.g., an organic adhesive such as an epoxy) that can include a conductive filler material can be applied to one or both elements and cured to form a physical connection (as opposed to a chemical or covalent connection) between the elements. Typical organic adhesives lack strong chemical or covalent bonds to either element. In such processes, the connection between the elements is weak, and / or easily reversible, such as due to reheating or de-bonding.

[0036] By contrast, direct bonding processes join two elements by forming strong chemical bonds (e.g., covalent bonds) between opposing non-conductive materials. For example, in a direct bonding process between non-conductive materials, one or both non-conductive surfaces of the two elements are planarized and chemically prepared (e.g., activated and / or terminated) such that, when the elements are brought into contact, strong chemical bonds (e.g., covalent bonds) are formed that are stronger than van der Waals or hydrogen bonds. In some embodiments (e.g., between opposing dielectric surfaces, such as opposing silicon oxide surfaces), the chemical bonds can occur spontaneously at room temperature upon contact. In some embodiments, the chemical bonds between the opposing non-conductive materials can be enhanced after the elements are annealed.

[0037] As noted above, hybrid bonding is a type of direct bonding in which non-conductive features are directly bonded to non-conductive features, and conductive features are directly bonded to conductive features of the bonded elements. The non-conductive bonding materials and interfaces can be as described above, while the conductive bonding can be formed, for example, by direct metal-to-metal connections. In a traditional metal bonding process, a fusible metal alloy (e.g., solder) can be provided between the conductors of the two elements, heated to melt the alloy, and then cooled to form a connection between the two elements. The resulting bond often exhibits a clear interface with the conductors of the two elements, and can be reversed by reheating. By contrast, the direct metal bonding employed in hybrid bonding does not require a melting or intermediate fusible metal alloy, and can result in a strong mechanical and electrical connection, often exhibiting inter-diffusion of the bonded conductive features and grain growth across the bonding interface between the elements, even without the relatively high temperatures and pressures of thermal compression bonding.

[0038] FIG. 1A and FIG. 1B Cross-sectional side views of a first element 102 and a second element 104, respectively, prior to and after a process for forming a direct bonded structure (more specifically, a hybrid bonded structure) in accordance with some embodiments are schematically illustrated. In the process, the first element 102 and the second element 104 are brought into contact with each other, and a direct bond is formed between the two elements. In some embodiments, the direct bond is a hybrid bond, in which non-conductive features are directly bonded to non-conductive features, and conductive features are directly bonded to conductive features of the bonded elements. FIG. 1BIn particular embodiments, the bonded structure 100 includes a first element 102 and a second element 104 that are directly bonded to one another at a bonding interface 118 without an intervening adhesive. Electrically conductive features 106a of the first element 102 can be electrically connected to corresponding electrically conductive features 106b of the second element 104. In the illustrated hybrid bonded structure 100, the electrically conductive features 106a are directly bonded to the corresponding electrically conductive features 106b without an intervening solder or electrically conductive adhesive.

[0039] The electrically conductive features 106a and 106b of the illustrated embodiment are respectively embedded in first and second bonding layers 108a and 108b of the first and second elements 102 and 104, and can be considered part thereof. Field regions of the bonding layers 108a and 108b extend between and partially or completely surround the electrically conductive features 106a and 106b. As noted above, the bonding layers 108a and 108b can include layers of non-conductive material suitable for direct bonding, and the field regions are directly bonded to one another without an intervening adhesive. The non-conductive bonding layers 108a and 108b can be disposed on respective front sides 114a and 114b of the base substrate portions 110a and 110b.

[0040] The first and second elements 102 and 104 can include microelectronic elements, such as semiconductor elements including, for example, integrated device dies, wafers, passive devices, discrete active devices such as power switches, MEMS, etc. In some embodiments, the base substrate portions can include device portions such as bulk semiconductor (e.g., silicon) portions of the elements 102 and 104, and back end of line (BEOL) interconnect layers over such semiconductor portions. The bonding layers 108a and 108b can be provided as part of such BEOL layers, as part of a redistribution layer (RDL), or as a particular bonding layer added to an existing device with bonding pads extending from underlying contacts during device fabrication. Active devices and / or circuitry can be patterned and / or otherwise disposed in or on the base substrate portions 110a and 110b, and can be in electrical communication with at least some of the electrically conductive features 106a and 106b. The active devices and / or circuitry can be disposed at or near the front sides 114a and 114b of the base substrate portions 110a and 110b, and / or at or near the opposing back sides 116a and 116b of the base substrate portions 110a and 110b. In other embodiments, the base substrate portions 110a and 110b can not include active circuitry, but can include dummy substrates, passive intermediate layers, passive optical elements (e.g., glass substrates, gratings, lenses), etc. The bonding layers 108a and 108b are shown as being provided on the front sides of the elements, but similar bonding layers can additionally or alternatively be provided on the back sides of the elements.

[0041] In some embodiments, the base substrate portions 110a and 110b can have substantially different coefficients of thermal expansion (CTEs), and the bonded element including these different base substrate portions can form a hetero-bonded structure. The CTE difference between the base substrate portions 110a and 110b, and in particular the CTE difference between the bulk semiconductor (typically single-crystalline) portions of the base substrate portions 110a and 110b, can be greater than 5 ppm / °C or greater than 10 ppm / °C. For example, the CTE difference between the base substrate portions 110a and 110b can be in a range from 5 ppm / °C to 100 ppm / °C, from 5 ppm / °C to 40 ppm / °C, from 10 ppm / °C to 100 ppm / °C, or from 10 ppm / °C to 40 ppm / °C.

[0042] In some embodiments, one of the base substrate portions 110a, 110b can include an optoelectronic single-crystalline material (including a perovskite material) that can be used for optical piezoelectric or pyroelectric applications, while the other of the base substrate portions 110a, 110b includes a more traditional substrate material. For example, one of the base substrate portions 110a, 110b includes lithium tantalate (LiTaO3) or lithium niobate (LiNbO3), while the other of the base substrate portions 110a, 110b includes silicon (Si), quartz, fused quartz glass, sapphire, or glass. In other embodiments, one of the base substrate portions 110a, 110b includes a III-V single-crystalline semiconductor material, such as gallium arsenide (GaAs) or gallium nitride (GaN), while the other of the base substrate portions 110a, 110b can include a non-III-V semiconductor material, such as silicon (Si), or can include other materials with similar CTEs, such as quartz, fused quartz glass, sapphire, or glass. In still other embodiments, one of the base substrate portions 110a, 110b includes a semiconductor material, while the other of the base substrate portions 110a, 110b includes an encapsulation material, such as a glass, an organic substrate, or a ceramic substrate.

[0043] In some arrangements, the first element 102 can comprise a singulated element, such as a singulated integrated device die. In other arrangements, the first element 102 can comprise a carrier or substrate (e.g., a semiconductor wafer) that includes a plurality (e.g., tens, hundreds, or more) of device regions that, when singulated, form a plurality of integrated device dies; although in other embodiments, such a carrier can be a package substrate or a passive / active interposer. Similarly, the second element 104 can comprise a singulated element, such as a singulated integrated device die. In other arrangements, the second element 104 can comprise a carrier or substrate (e.g., a semiconductor wafer). Accordingly, the embodiments disclosed herein can be applicable to wafer-to-wafer (W2W), die-to-die (D2D), or die-to-wafer (D2W) bonding processes. In a W2W process, two or more wafers can be bonded directly to one another (e.g., direct hybrid bonding) and singulated using a suitable singulation process. After singulation, the side edges of the singulated structure (e.g., the side edges of the two bonded elements) can be substantially flush (the x-y dimensions are substantially aligned), and / or the edges of the bonded interfaces for the bonded and singulated elements can be collinear, and can include a mark indicative of the common singulation process of the bonded structure (e.g., a saw cut mark if a saw cut singulation process is used).

[0044] Although only two elements 102 and 104 are shown, any suitable number of elements can be stacked in the bonded structure 100. For example, a third element (not shown) can be stacked on the second element 104, a fourth element (not shown) can be stacked on the third element, and so on. In such implementations, through-substrate vias (TSVs) can be formed to provide vertical electrical communication between or among the vertically stacked elements. Additionally or alternatively, one or more additional elements (not shown) can be stacked laterally adjacent to one another along the first element 102. In some embodiments, the laterally stacked additional elements can be smaller than the second element. In some embodiments, the bonded structure can be encapsulated with an insulating material, such as an inorganic dielectric (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.). One or more insulating layers can be provided over the bonded structure. For example, in some implementations, a first insulating layer can be conformally deposited over the bonded structure, and a second insulating layer can be provided over the first insulating layer (the second insulating layer can comprise the same material as the first insulating layer, or a different material than the first insulating layer).

[0045] To enable direct bonding between the bonding layers 108a, 108b, the bonding layers 108a, 108b can be prepared for direct bonding. By polishing (e.g., by chemical mechanical polishing (CMP)), the non-conductive bonding surfaces 112a and 112b can be prepared at the upper or outer surfaces of the bonding layers 108a, 108b for direct bonding. The roughness of the polished bonding surfaces 112a, 112b can be less than 30 A rms. For example, the roughness of the bonding surfaces 112a and 112b can be in a range from about 0.1 A rms to 15 A rms, 0.5 A rms to 10 A rms, or 1 A rms to 5 A rms. The polishing can also be adjusted to recess the conductive features 106a, 106b relative to the field regions of the bonding layers 108a, 108b.

[0046] The preparation for direct bonding can also include cleaning one or both of the bonding surfaces 112a, 112b and exposing one or both of the bonding surfaces 112a, 112b to a plasma and / or an etchant to activate at least one of the surfaces 112a, 112b. In some embodiments, one or both of the surfaces 112a, 112b can be terminated with a substance after or during activation, for example, during a plasma and / or etching process. In some embodiments, without being limited by theory, the activation process can be performed to break chemical bonds at the bonding surfaces 112a, 112b, while the termination process can provide additional chemical species at the bonding surfaces 112a, 112b that alter the chemical bonds and / or increase the bonding energy during direct bonding. In some embodiments, the activation and termination are provided in the same step, for example, using a plasma to activate and terminate the surfaces 112a, 112b. In other embodiments, one or both of the bonding surfaces 112a, 112b can be terminated in a separate process to provide additional species for direct bonding. In various embodiments, the termination species can include nitrogen. For example, in some embodiments, the bonding surfaces 112a, 112b can be exposed to a nitrogen-containing plasma. Other termination species can be suitable to increase the bonding energy, depending on the material of the bonding surfaces 112a, 112b. Further, in some embodiments, the bonding surfaces 112a, 112b can be exposed to fluorine. For example, there can be one or more fluorine concentration peaks at or near the bonding interface 118 between the first element 102 and the second element 104. Generally, fluorine concentration peaks occur at interfaces between layers of material. Additional examples of activation and / or termination processes can be found in U.S. Patent No. 9,391,143 at col. 5, line 55, to col. 7, line 3, col. 8, line 52, to col. 9, line 45, col. 10, lines 24-36, col. 11, lines 24-32, lines 42-47, lines 52-55, and lines 60-64, col. 12, lines 3-14, lines 31-33, and lines 55-67, col. 14, lines 38-40, and 44-50; and U.S. Patent No. 10,434,749 at col. 4, lines 41-50, col. 5, lines 7-22, line 39, lines 55-61, col. 8, lines 25-31, lines 35-40, and lines 49-56, and col. 12, lines 46-61, the teachings of which activation and termination are incorporated herein by reference.

[0047] Accordingly, in the direct bond structure 100, the bond interface 118 between the two non-conductive materials (e.g., bond layers 108a, 108b) can include a very smooth interface with a higher nitrogen (or other termination species) content and / or a fluorine concentration peak at the bond interface 118. In some embodiments, various types of inspection techniques, such as SIMS techniques, can be used to detect the nitrogen and / or fluorine concentration peaks. After the activation process, the polished bond surfaces 112a and 112b can be slightly rougher (e.g., about 1 A rms to 30 A rms, 3 A rms to 20 A rms, or possibly rougher). In some embodiments, the activation and / or termination can result in a slightly smoother surface prior to bonding, such as a plasma treatment preferentially etching high points on the bond surface.

[0048] The non-conductive bond layers 108a and 108b can be bonded directly to each other without an adhesive. In some embodiments, the elements 102, 104 are brought into contact at room temperature without the need to apply a voltage, nor an external pressure or force beyond that needed to bring the two elements 102, 104 into contact. The mere contact can cause a direct bond (e.g., covalent dielectric bond) between the non-conductive surfaces of the bond layers 108a, 108b. Subsequent annealing of the bond structure 100 can cause the conductive features 106a, 106b to be directly bonded.

[0049] In some embodiments, prior to the direct bond, the conductive features 106a, 106b are recessed relative to the surrounding field region, such that the total gap between the opposing contacts is less than 15 nm or less than 10 nm after the dielectric bond and prior to annealing. The gap can represent the maximum gap or average gap between the corresponding conductive features 106a, 106b of the two joined elements (prior to annealing) due to the different recess depths for the conductive features 106a and 106b, which can vary across each element. Upon annealing, the conductive features 106a and 106b can expand and contact each other to form a metal-to-metal direct bond.

[0050] During annealing, the conductive features 106a, 106b (e.g., metallic material) can expand, while the direct bond between the non-conductive materials surrounding the bond layers 108a, 108b prevents the elements from separating, causing the thermal expansion to increase the internal contact pressure between the opposing conductive features. The annealing also causes the metal grains to grow across the bond interface, such that grains from one element at least partially migrate into the other element across the bond interface, and vice versa. Accordingly, in some hybrid bond embodiments, the opposing conductive materials need not be heated above the melting point of the conductive material to join, allowing the bond to be formed at a lower annealing temperature compared to soldering or thermal compression bonding.

[0051] In various embodiments, conductive features 106a, 106b may include discrete pads, contacts, electrodes, or traces at least partially embedded in non-conductive field regions of bonding layers 108a, 108b. In some embodiments, conductive features 106a, 106b may include exposed contact surfaces of TSVs (e.g., vias through silicon).

[0052] As noted above, in some embodiments, in FIG. 1A In elements 102 and 104, prior to direct bonding, portions of the corresponding conductive features 106a and 106b can be recessed below the non-conductive bonding surfaces 112a and 112b, for example, recessed by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, recessed in the range of 2 nm to 20 nm, or in the range of 4 nm to 10 nm. Due to different processes, the dielectric thickness and conductor recess depth may vary across the same element. Therefore, the aforementioned recess depth range can be applied to individual conductive features 106a and 106b, or can be applied to the average recess depth relative to local non-conductive field regions. Even for individual conductive features 106a and 106b, the vertical recess may vary across features, and therefore can be measured at or near the lateral midpoint or center of the cavity in which a given conductive feature 106a or 106b is formed, or can be measured on the side of the cavity.

[0053] Advantageously, high-density connections (e.g., for fine-pitch or small-pitch arrays) between conductive features 106a, 106b across the direct bonding interface 118 can be achieved using hybrid bonding technologies such as Direct Bond Interconnect (DBI®) technology, which is commercially available from Adeia Corporation (located in San Jose, California).

[0054] In some embodiments, the pitch p of the conductive features 106a, 106b, such as conductive traces embedded in the bonding surface of one of the bonding elements, can be less than 40 pm, less than 20 pm, less than 10 pm, less than 5 pm, less than 2 pm, or even less than 1 pm. For some applications, the ratio of the pitch of the conductive features 106a and 106b to the lateral dimension (e.g., diameter) of the bonding pads is less than 20, or less than 10, or less than 5 or less than 3, and is sometimes desirably less than 2. In various embodiments, the conductive features 106a and 106b and / or traces can comprise copper or a copper alloy, although other metals such as nickel, aluminum, or alloys thereof can also be applicable. The conductive features disclosed herein, such as the conductive features 106a and 106b, can comprise fine-grained metal (e.g., fine-grained copper). Moreover, their major lateral dimension (e.g., pad diameter) can also be small, e.g., in the range of about 0.25 pm to 30 pm, in the range of about 0.25 pm to 5 pm, or in the range of about 0.5 pm to 5 pm.

[0055] For the illustrated hybrid bonding elements 102, 104, the orientation of one or more conductive features 106a, 106b from the opposing element can be opposite one another. As known in the art, the conductive features can generally be formed with near-vertical sidewalls, particularly where the conductor sidewalls are defined directly by etching the conductive material in a directional reactive ion etch (RIE), or indirectly by etching the surrounding insulator in a damascene process. However, the conductor sidewalls can exhibit a slight taper, where the conductor gradually narrows away from the surface that was initially exposed to the etch. This tapering can be more pronounced when the conductive sidewalls are defined directly or indirectly by isotropic wet or dry etching. In the illustrated embodiments, at least one conductive feature 106b (and / or at least one internal conductive feature, such as a BEOL feature) in the bonding layer 108b of the upper element 104 can taper or narrow upwardly away from the bonding surface 112b. By contrast, at least one conductive feature 106a (and / or at least one internal conductive feature, such as a BEOL feature) in the bonding layer 108a of the lower element 102 can taper or narrow downwardly away from the bonding surface 112a. Similarly, any bonding layers (not shown) on the backside 116a, 116b of the elements 102, 104 can taper or narrow from the backside, with a tapering orientation opposite that of the frontside conductive features 106a, 106b of the same element.

[0056] As described above, during the annealing phase of hybrid bonding, the conductive features 106a, 106b can expand and contact one another to form a metal-to-metal direct bond. In some embodiments, the materials of the conductive features 106a, 106b of the opposing elements 102, 104 can interdiffuse during the annealing process. In some embodiments, metal grains grow into one another across the bonding interface 118. In some embodiments, the metal is copper or includes copper, which can have grains oriented along 111 crystal planes to improve diffusion of copper across the bonding interface 118. In some embodiments, the conductive features 106a and 106b can include a nanotwinned copper grain structure, which can help fuse the conductive features during annealing. At or near the bonded conductive features 106a and 106b, there is substantially no gap between the non-conductive bonding layers 108a and 108b. In some embodiments, a conductive layer can be provided under and / or laterally around the conductive features 106a and 106b (e.g., the conductive features 106a and 106b can include copper). However, in other embodiments, there can be no barrier layer under the conductive features 106a and 106b.

[0057] Certain embodiments disclosed herein relate to optoelectronic devices that include directly bonded contacts that include optically transparent or optically translucent electrically conductive materials (collectively referred to herein as transparent conductors or TCs) rather than metal directly bonded contacts. For example, the optoelectronic devices can include optical elements or devices (e.g., photodiodes; light emitting diodes (LEDs); quantum dot light emitting diodes (QLEDs); lasers; vertical cavity surface emitting lasers (VCSELs); transparency control pixels; liquid crystal pixels; adaptive optics; solar cells; waveguides; spatial light modulators; diode lasers; electrochromic devices) that are stacked on one another or bonded to one another to form a bonded structure. The TCs on separate substrates can be planarized, and the planarized substrate surfaces can be placed in contact with one another to form the bonded structure as described herein.

[0058] In certain embodiments, the optoelectronic devices described herein are configured to be used in various area-constrained application environments (e.g., displays for virtual reality (VR) or augmented reality (AR) applications; multi-junction solar cells) or other designs that include optoelectronic (e.g., electro-optical) elements within a stack of other optical elements, thereby advantageously utilizing TCs to provide electrical connections between electronic elements without significantly obstructing light.

[0059] As used herein, the term "optically transparent" includes, but is not limited to, optically translucent, optically semi-transparent, and / or having an optical transmittance of at least 50% (e.g., at least 60%; at least 75%; at least 88%; greater than or equal to 95%) at a predetermined range of optical wavelengths. For example, the predetermined range of an optically transparent component (e.g., element, substrate, layer, device, feature) can be visible wavelengths (e.g., 390 nanometers to 750 nanometers; 400 nanometers to 700 nanometers), ultraviolet wavelengths (e.g., 100 nanometers to 400 nanometers), infrared wavelengths (e.g., 800 nanometers to 1 millimeter), and / or short-wave infrared (SWIR) wavelengths (e.g., 1400 nanometers to 3000 nanometers).

[0060] As described herein, some electrically conductive oxides (e.g., indium tin oxide or ITO) or nitrides have the ability to self-bond at moderate temperatures (e.g., in the range of 75 °C to 400 °C; in the range of 120 °C to 300 °C; in the range of 150 °C to 300 °C). In certain embodiments, using an electrically conductive oxide or nitride layer can simplify the process for bonding (e.g., blanket wafer and hybrid bonding surfaces) by omitting one or more other process steps (e.g., planarization and / or surface activation). For example, if an electrically conductive oxide or nitride layer is planarized prior to patterning, the electrically conductive oxide or nitride layer can be self-levelling. In combination with certain layout structures, such an electrically conductive oxide or nitride layer can be used to bond multiple input / output components with a single material interface. For example, ITO can be used to bond two substrates without a surface activation step, and in certain embodiments, even without a surface planarization (e.g., chemical mechanical polishing or CMP) step. Electrically conductive oxide or nitride layers also allow for bonding at moderate temperatures (e.g., below 300 °C), and can be used for surface mounting. In view of their electrical conductivity, such layers can provide electromagnetic shielding for other components of an electronic package. Furthermore, as certain such materials are substantially optically transparent, they can be used to bond optoelectronic applications, as well as other structures where photon transmissivity is not a high priority.

[0061] FIG. 2A and FIG. 2B two cross-sectional views schematically illustrating an example structure 200 according to certain embodiments described herein, FIG. 3A and FIG. 3B two cross-sectional views schematically illustrating another example structure 200 according to certain embodiments described herein. FIG. 2A and FIG. 3A the cross-sectional view of FIG. 1 is in a first plane, and FIG. 2B and FIG. 3B the cross-sectional view of FIG. 2 is in a second plane (e.g., cross-sectional plan view), the second plane being respectively perpendicular to the first plane.FIG. 2A and FIG. 3A a first plane of the first portion 214 and a third portion 224 of the second portion 226 are substantially perpendicular. The structure 200 includes a first substrate 210 (e.g., the first element 102) including a first layer 212 having at least one electrically conductive first portion 214 (e.g., the electrically conductive feature 106a) and at least one electrically insulating second portion 216. The structure 200 also includes a second substrate 220 (e.g., the second element 104) including a second layer 222 having at least one electrically conductive third portion 224 (e.g., the electrically conductive feature 106b) and at least one electrically insulating fourth portion 226. The structure 200 also includes an interface layer 230 (e.g., formed by a direct bonding of two opposing layers of at least one electrically conductive oxide material 232) between the first layer 212 and the second layer 222. The interface layer 230 includes at least one electrically conductive oxide material 232. The at least one electrically conductive oxide material 232 includes at least one first region 234 between and in electrical communication with the at least one electrically conductive first portion 214 and the at least one electrically conductive third portion 224. The at least one electrically conductive oxide material 232 also includes at least one second region 236 between the at least one electrically insulating second portion 216 and the at least one electrically insulating fourth portion 226.

[0062] In certain embodiments, the first substrate 210 includes at least one first device 240, and the second substrate 220 includes at least one second device 250. The at least one first device 240 and / or the at least one second device 250 can be optically transparent (e.g., optoelectronic devices; optoelectronic elements; electro-optical elements; solar cells), or can be optically non-transparent (e.g., opaque). The at least one first device 240 and / or the at least one second device 250 can also include electrically conductive pathways (e.g., optically transparent; non-optically transparent). In certain embodiments, the first substrate 210 includes at least one electrical contact 242 (e.g., large-area lateral contacts on the backside 116a of the corresponding device portion 110a) in electrical communication with the at least one first device 240, and the second substrate 220 includes at least one electrical contact 252 (e.g., on the backside 116b of the corresponding device portion 110b) in electrical communication with the at least one second device 250. The electrical contacts 242, 252 can be configured to transmit electrical signals to and / or from the first device 240 and / or the second device 250. Example materials for the electrical contacts 242, 252 include, but are not limited to, copper or copper alloys, although other metals and alloys can also be suitable. In addition, the electrical contacts 242, 252 can include additional electrically conductive layers between the copper and the corresponding at least one first device 240 and / or second device 250. In certain embodiments, at least one of the electrical contacts 242, 252 includes an electro-optical (EO) contact including a transparent electrically conductive material (e.g., an electrically conductive oxide material disclosed herein) in electrical and optical communication with the at least one first device 240 and the at least one second device 250, respectively, to transmit electrical and optical signals to and / or from the first device 240 and / or the second device 250.

[0063] In certain embodiments, the at least one electrically conductive first portion 214 and / or the at least one electrically conductive third portion 224 comprises at least one electrically conductive material, examples of which include, but are not limited to: copper; tungsten; cobalt; doped and undoped metal oxides; aluminum zinc oxide (AZO); indium tin oxide (ITO, In2O3); zinc oxide (ZnO); zinc tin oxide (ZnSnO3, Zn2SnO4); indium-doped zinc oxide (IZO); indium oxide; cadmium tin oxide (Cd2SnO4); tin oxide (SnO2); titanium dioxide (TiO2); niobium-doped titanium dioxide (Nb-TiO2); titanium nitride (TiN); tin nitride (Sn3N4); other metal nitrides (e.g., A3N2, where A = Mg, Zn, Sn); transition metal nitrides including Group III B, Group IV B, or Group V B transition metals. In certain embodiments, the first portion 214 and / or the third portion 224 is optically transparent, while in certain other embodiments, the first portion 214 and / or the third portion 224 is optically non-transparent (e.g., opaque). Each of the first portion 214 and / or the third portion 224 can comprise a single layer or multiple layers. The first portion 214 and the third portion 224 can comprise the same electrically conductive material, or can comprise different electrically conductive materials (e.g., materials having different elemental compositions and / or different stoichiometric ratios). The electrically conductive material of the first portion 214 and / or the third portion 224 can be different from the electrically conductive oxide material 232, and the junction of the first portion 214 and / or the third portion 224 with the interface layer 230 can comprise a hybrid junction.

[0064] In certain embodiments, the at least one electrically insulating second portion 216 and / or the at least one electrically insulating fourth portion 226 comprises at least one dielectric material (e.g., an inorganic dielectric material), examples of which include, but are not limited to: a semiconducting oxide; a semiconducting nitride; silicon dioxide (SiO2); silicon nitride (SiN x , Si3N4); silicon oxynitride (SiO x N y C z ); titanium oxide. In certain embodiments, the second portion 216 and / or the fourth portion 226 is optically transparent, while in certain other embodiments, the second portion 216 and / or the fourth portion 226 is optically non-transparent (e.g., opaque). Each of the second portion 216 and / or the fourth portion 226 can comprise a single layer or multiple layers. The second portion 216 and the fourth portion 226 can comprise the same dielectric material, or can comprise different dielectric materials (e.g., materials having different elemental compositions and / or different stoichiometric ratios). The dielectric material of the second portion 216 and / or the fourth portion 226 is different from the electrically conductive oxide material 232, and the junction of the second portion 216 and / or the fourth portion 226 with the interface layer 230 can comprise a hybrid junction.

[0065] In certain embodiments, the at least one electrically conductive oxide material 232 is selected from the group consisting of: indium tin oxide (ITO); zinc oxide (ZnO); indium-doped zinc oxide (IZO); tin oxide (Sn02). In certain embodiments, the at least one electrically conductive oxide material 232 is optically transparent, while in certain other embodiments, the at least one electrically conductive oxide material 232 is optically non-transparent (e.g., opaque). As described herein, the at least one electrically conductive oxide material 232 can include a first electrically conductive oxide material 232a on the first layer 212 and a second electrically conductive oxide material 232b on the second layer 222, and the interface layer 230 can be formed by directly bonding the first electrically conductive oxide material 232a to the second electrically conductive oxide material 232b. In certain embodiments, the interface layer 230 has a thickness in the range of 5 nm to 3 μιη. In certain embodiments, the electrically conductive oxide has an electrical resistivity in the range of less than 500 x 10 6 Ω-cm (e.g., 200 x 10 6 Ω-cm to 40 x 10 6 Ω-cm; 500 x 10 6 Ω-cm to 20 x 10 6 Ω-cm; less than 120 x 10 6 Ω-cm). In certain embodiments, the optical transmittance in a wavelength range of interest is greater than 40% (e.g., greater than 60%; greater than 80%).

[0066] In certain embodiments, the interface layer 230 is patterned such that the at least one first region 234 is electrically isolated from the at least one second region 236. For example, as FIG. 2A and FIG. 2B schematically illustrated, the structure 200 further includes a gap 238 between the at least one first region 234 and the at least one second region 236. In certain embodiments, the gap 238 includes a gas (e.g., air; nitrogen), and can be at atmospheric pressure, below atmospheric pressure (e.g., vacuum pressure), or above atmospheric pressure. As FIG. 2A schematically illustrated, the at least one electrically conductive oxide material 232 is not embedded within the at least one electrically insulating second portion 216 and / or the at least one electrically insulating fourth portion 226.

[0067] For another example, as FIG. 3A and FIG. 3B schematically illustrated, the interface layer 230 includes at least one solid dielectric material 239 (e.g., silicon oxynitride or SiON) between the at least one first region 234 and the at least one second region 236. x N y Cz The at least one solid dielectric material 239 can be different from the material of the at least one electrically insulating second portion 216 and / or the at least one electrically insulating fourth portion 226, or the at least one solid dielectric material 239 can be the same as the material of the at least one electrically insulating second portion 216 and / or the at least one electrically insulating fourth portion 226. As FIG. 3A Illustratively, the at least one electrically conductive oxide material 232 is at least partially embedded (e.g., completely embedded) within the at least one electrically insulating second portion 216 and / or the at least one electrically insulating fourth portion 226.

[0068] In cross-sectional views of FIG. 2B and FIG. 3B , the first regions 234 of the at least one electrically conductive oxide material 232 are hatched (to distinguish them from the underlying first portions 214 and the overlying third portions 224) to distinguish them from the second regions 236 of the at least one electrically conductive oxide material 232 (which have the underlying second portions 216 and the overlying fourth portions 226). As FIG. 2B and FIG. 3B illustrate, the first regions 234 are electrically isolated from the second regions 236 and the first regions 234 are electrically isolated from one another (e.g., by the gaps 238 in FIG. 2A or by the at least one solid dielectric material 239 in FIG. 3A ), such that the interface layer 230 does not electrically short the first portions 214 to one another or the third portions 224 to one another.

[0069] FIG. 2C , FIG. 2D , FIG. 3C and FIG. 3D illustrate cross-sectional plan views of other example structures 200 according to certain embodiments described herein. Like FIG. 2B and FIG. 3B , FIG. 2C , FIG. 2D , FIG. 3C and FIG. 3D , the cross-sectional views of FIG. 2A and FIG. 3A are in a second plane that is substantially perpendicular to the first plane of FIG. 2C , FIG. 2D , FIG. 3C and FIG. 3D illustrate that at least some second regions 236 of the at least one electrically conductive oxide material 232 can be between at least some adjacent first regions 234 of the at least one electrically conductive oxide material 232 (e.g., as illustrated in FIG. 2C and FIG. 3C , between each pair of adjacent first regions 234). As FIG. 2B, FIG. 2C , FIG. 3B and FIG. 3C As shown, at least a portion of an electrically conductive oxide material 232 (e.g., a second region 236) may be located at the periphery 260 of the first substrate 210 and the second substrate 220. In some embodiments (e.g., see...), FIG. 2B , FIG. 2C , FIG. 3B and FIG. 3C At least one portion of an electrically conductive oxide material 232 at perimeter 260 substantially surrounds (e.g., encircles) the first region 234 and / or the second region 236, and can be configured to seal at least one portion of the electrically conductive oxide material 232 relative to the surrounding environment (e.g., outside perimeter 260). FIG. 2D and FIG. 3D As shown, at least one electrically conductive oxide material 232 may be spaced apart from the periphery 260 and / or not substantially surround (e.g., encircle) the first region 234 and / or the second region 236, or not seal other portions of at least one electrically conductive oxide material 232 relative to the surrounding environment.

[0070] FIG. 4A and FIG. 4B Two cross-sectional views of another example structure 200 according to certain embodiments described herein are schematically illustrated. FIG. 4A The cross-sectional view is in the first plane, and FIG. 4B Cross-sectional view in relation to FIG. 4A The first plane is essentially perpendicular to the second plane. For example... FIG. 4A As schematically illustrated, at least one conductive oxide material 232 is embedded within at least one electrically insulating second portion 216 and / or at least one electrically insulating fourth portion 226 (e.g., embedded in at least one solid dielectric material 270). FIG. 4C A cross-sectional view of another example structure 200 according to certain embodiments described herein is schematically illustrated. FIG. 4B similar, FIG. 4C Cross-sectional view in relation to FIG. 4A The first plane is basically perpendicular to the second plane.

[0071] In some implementations (e.g., as FIG. 4A-FIG. 4C As shown in the diagram), the first layer 212 contains a solid dielectric material 270 (e.g., silicon oxycarbonate or SiO2). x N y C zA portion of the first substrate 210 and the second substrate 220 is located at a periphery 260. The solid dielectric material at the periphery 260 substantially surrounds (e.g., encircles) at least one first region 234 and / or at least one second region 236 and can be configured to seal at least one first region 234 and / or at least one second region 236 relative to the surrounding environment (e.g., outside the periphery 260).

[0072] FIG. 4D-FIG. 4F Cross-sectional views of an example die 300, an example first die layout 310, and an example second die layout 320 according to certain embodiments described herein are schematically illustrated. FIG. 4D-FIG. 4F Cross-sectional view in relation to FIG. 4A The first plane is substantially perpendicular to the second plane. FIG. 4D-FIG. 4F In the first layer 212, a first portion 214 is embedded in the solid dielectric material 270 of the second portion 216 of the first layer 212, a third portion 224 of the second layer 222 is embedded in the solid dielectric material 270 of the fourth portion 226 of the second layer 222, and at least one first region 234 and a second region 236 of an electrically conductive oxide material 232 are located between the first layer 212 and the second layer 222. FIG. 4E In the first die layout 310, at least one electrically conductive oxide material 232 is patterned such that the first portions 214 are electrically insulated from each other, and the third portions 224 are electrically insulated from each other. FIG. 4F In the second die layout 320, at least one electrically conductive oxide material 232 electrically connects a plurality of underlying first portions 214 to each other, and / or electrically connects a plurality of top third portions 224 to each other. In the die 300, the first die layout 310, and the second die layout 320, a solid dielectric material 270 substantially surrounds (e.g., encircles) at least one electrically conductive oxide material 232, thereby hermetically sealing (e.g., providing a hermetically sealed ring) the first region 234 and the second region 236 relative to the surrounding environment. In some embodiments, the solid dielectric material 270 (e.g., silicon oxycarbonate or SiO2) x N y C z It provides higher sealing performance (e.g., lower gas leakage rate) than at least one electrically conductive oxide material 232.

[0073] FIG. 5 This is a flowchart of an example method 500 for forming a structure 200 compatible with some of the embodiments described herein. FIG. 6A and FIG. 6B The diagram schematically illustrates the formation according to certain embodiments described herein. FIG. 2A and FIG. 2B Example structure 200 and method 500 in the example.FIG. 7A and FIG. 7B schematically illustrates another example of a method 500 of forming an example structure 200 according to certain embodiments described herein. While the example method 500 is described herein with reference to various example structures in FIG. 3A and FIG. 3B schematically illustrates another example of a method 500 of forming an example structure 200 according to certain embodiments described herein. While the example method 500 is described herein with reference to various example structures in FIG. 8A and FIG. 8B schematically illustrates another example of a method 500 of forming an example structure 200 according to certain embodiments described herein. While the example method 500 is described herein with reference to various example structures in FIG. 2A , FIG. 2B , FIG. 3A and FIG. 3B schematically illustrates another example of a method 500 of forming an example structure 200 according to certain embodiments described herein. While the example method 500 is described herein with reference to various example structures in

[0074] In operation block 510, the method 500 includes providing a first substrate 210 (e.g., the first element 102) and a second substrate 220 (e.g., the second element 104). The first substrate 210 includes one or more electrically conductive surface portions (e.g., the first portion 214; the electrically conductive features 106a) and one or more electrically insulating surface portions (e.g., the second portion 216), and the second substrate 220 includes one or more electrically conductive surface portions (e.g., the third portion 224; the electrically conductive features 106b) and one or more electrically insulating surface portions (e.g., the fourth portion 226). At least one of the first substrate 210 and the second substrate 220 further includes an electrically conductive oxide layer (e.g., the interface layer 230 includes at least one electrically conductive oxide material 232) having a first region 234 over and in electrical communication with the one or more electrically conductive surface portions and a second region 236 over the one or more electrically insulating surface portions, the second region 236 being electrically isolated from the first region 234. In operation block 520, the method 500 further includes directly bonding the first substrate 210 and the second substrate 220 to one another without an intervening adhesive. The direct bonding includes bringing the first substrate 210 and the second substrate 220 into contact with one another with the electrically conductive oxide surface layer between the first substrate 210 and the second substrate 220.

[0075] In certain embodiments, after the room temperature bonding operation, the bonded substrate 100 is annealed at a temperature higher than room temperature (e.g., in a range from 120 °C to 500 °C; in a range from 120 °C to 150 °C; in a range from 150 °C to 350 °C) for a time in a range from 10 minutes to more than 2 hours (e.g., using a shorter anneal time and employing a higher anneal temperature). The anneal environment can include at least one of: nitrogen, forming gas, hydrogen plasma, vacuum, or other predetermined environment. The anneal chamber can include one or more furnaces (e.g., a rapid thermal anneal (RTA) furnace; a microwave furnace; a furnace for processing semiconductor wafers, flat panels, etc.). After the anneal process, the opposing first bonding layer 108a and second bonding layer 108b can be permanently bonded, and their bonding interface 118 can have a bonding energy of at least 1000 mJ m -2 (e.g., higher than 2000 mJ m -2 ). Similarly, the opposing conductive features 106a, 106b can be mechanically bonded to each other and electrically coupled to each other. The bonding interface 118 at the bonded first bonding layer 108a and second bonding layer 108b can be linear or non-linear within the bonded conductive features 106a, 106b. In certain embodiments, the grain size of the annealed conductive features 106a, 106b is greater than 20% (e.g., greater than 30%) of the width of the bonded conductive features 106a, 106b.

[0076] In certain embodiments, the first element 102 and the second element 104 are annealed in a suitable furnace at a first temperature that is high enough to increase the grain structure of the conductive oxide prior to the bonding operation. The bonding surfaces of the first element 102 and the second element 104 that include the conductive oxide with large grains can be cleaned and bonded. In certain such embodiments, the cleaned surfaces can be activated prior to the bonding operation. The bonded first element 102 and the second element 104 can be annealed at a second temperature that can be substantially equal to or greater than the first temperature. In certain embodiments, the first element 102 and the second element 104 are annealed at the first temperature (e.g., below 250 °C) prior to the planarization step to form the smooth bonding surfaces 112a, 112b.

[0077] As FIG. 6A , FIG. 7A and FIG. 8AIllustratively, the one or more electrically conductive surface portions can include electrically conductive first portions 214 (e.g., Cu, Al, Cu alloy, Al alloy) of the first layer 212 on the at least one first device 240, and the one or more electrically insulating surface portions can include electrically insulating second portions 216 (e.g., silicon oxynitride or SiO x N y C z ). Similarly, the one or more electrically conductive surface portions can include electrically conductive third portions 224 of the second layer 222 on the at least one second device 250, and the one or more electrically insulating surface portions can include electrically insulating fourth portions 226 of the second layer 222 on the at least one second device 250. A top surface of the first portions 214 can be recessed relative to a top surface of the second portions 216 (e.g., by less than 10 nanometers), and / or a top surface of the third portions 224 can be recessed relative to a top surface of the fourth portions 226 (e.g., by less than 10 nanometers).

[0078] FIG. 6A An example fabrication process for providing the operation block 510 of the first substrate 210 is illustratively shown. Providing the first substrate 210 in operation block 510 can include depositing a first electrically conductive oxide layer 233a (e.g., ITO) over the first layer 212, with the first regions 234a over and in electrical communication with the one or more electrically conductive first portions 214, and the second regions 236a over the one or more electrically insulating second portions 216. For example, depositing the first electrically conductive oxide layer 233a can include sputtering, activated chemical vapor deposition (CVD), directional physical vapor deposition (PVD), or atomic layer deposition (ALD) to a micron-scale thickness. In certain implementations, after depositing the first electrically conductive oxide layer 233a, the first electrically conductive oxide layer 233a can be planarized (e.g., using CMP; for ITO, a CMP rate of 50-60 nm / min).

[0079] Providing the first substrate 210 in operation block 510 can also include patterning the first electrically conductive oxide layer 233a to electrically isolate the first regions 234a from the second regions 236a. For example, as FIG. 6AAs shown in FIG. 6, a photoresist layer 610 can be deposited on the first electrically conductive oxide layer 233a, the photoresist layer 610 can be patterned (e.g., using photolithography techniques) to expose portions of the first electrically conductive oxide layer 233a, and the exposed portions of the first electrically conductive oxide layer 233a can be etched away, thereby forming gaps 238 between the first regions 234a and the second regions 236a (e.g., such that the second regions 236a do not electrically short the first regions 234a to each other). For example, ITO can be patterned using dilute HC1 or HC1 vapor in a plasma dry etching process, or using CI2, BCI3, CH4, or H2 as a dry etchant. After etching, the remaining photoresist layer 610 can be stripped, and the first substrate 210 (including the first regions 234a and the second regions 236a of the first electrically conductive oxide layer 233a) can be thoroughly cleaned (e.g., rinsed and spun dry) in preparation for subsequent direct bonding.

[0080] FIG. 6A An example fabrication process for fabricating the first substrate 210 from the first device 240 and the first layer 212 is as follows. The same fabrication process can also be used to fabricate the second substrate 220 from the second device 250 and the second layer 222. For example, providing the second substrate 220 can include depositing a second electrically conductive oxide layer 233b over the second layer 222, with first regions 234b over and in electrical communication with one or more electrically conductive third portions 224, and second regions 236b over one or more electrically insulating fourth portions 226. In some embodiments, after depositing the second electrically conductive oxide layer 233b, the second electrically conductive oxide layer 233b can be planarized (e.g., using CMP). The providing the second substrate 220 in operation block 510 can also include patterning the second electrically conductive oxide layer 233b to electrically isolate the first regions 234b from the second regions 236b (e.g., depositing a photoresist layer over the second electrically conductive oxide layer 233b, patterning the photoresist layer using photolithography techniques to expose portions of the second electrically conductive oxide layer, and etching away the exposed portions of the second electrically conductive oxide layer to form gaps between the first regions 234b and the second regions 236b), such that the second regions 236b do not electrically short the first regions 234b to each other. After etching, the remaining photoresist layer can be stripped, and the second substrate 220 (including the first regions 234b and the second regions 236b of the second electrically conductive oxide layer 233b) can be thoroughly cleaned (e.g., rinsed and spun dry) in preparation for subsequent direct bonding.

[0081] As FIG. 6BIllustratively, directly joining the first substrate 210 and the second substrate 220 to one another without an intervening adhesive includes bringing the first substrate 210 and the second substrate 220 into contact with one another with at least one electrically conductive oxide surface layer between the first substrate 210 and the second substrate 220 (e.g., at room temperature; at a temperature below 35 °C). For example, as shown in FIG. 6B The first patterned electrically conductive oxide layer 233a and the second patterned electrically conductive oxide layer 233b can be in contact with one another (e.g., the first regions 234a and 234b are in contact with one another, while the second regions 236a and 236b are in contact with one another), as shown in FIG. 6B Illustrative embodiments are shown in which the second substrate 220 includes a second electrically conductive oxide layer 233b over the second layer 222; but in certain other embodiments, the second substrate 220 does not include a second electrically conductive oxide layer 233b over the second layer 222, and the first substrate 210 and the second substrate 220 are directly joined to one another using only the first electrically conductive oxide layer 233a between the first substrate 210 and the second substrate 220 (e.g., the first regions 234a are in electrical contact with the first portion 214 and the third portion 224, while the second regions 236a are in contact with the second portion 216 and the fourth portion 226). The alignment between the first regions 234 and the first portion 214 and the third portion 224, and the alignment between the second regions 236 and the second portion 216 and the fourth portion 226, can be sufficient to provide substantial electrical contact between the first portion 214 and the third portion 224 when desired, while avoiding electrical shorting of the first regions 234 to one another (e.g., the alignment can not be perfect).

[0082] In certain embodiments, the method 500 can further include annealing (e.g., heating to a predetermined temperature above room temperature and holding for a predetermined period of time; at a temperature in the range of 120 °C to 300 °C) the structure 200 after bringing the first substrate 210 and the second substrate 220 into contact with one another. The annealing process can cause the electrically conductive oxide layers 233a, 233b to expand, thereby increasing the contact pressure between the opposing conductive regions. Additionally or alternatively, the annealing can also cause grains to grow across the joining interface, such that the grains at least partially migrate into the opposing element. In certain embodiments, the method 500 does not include activating (e.g., exposing to plasma and / or chemical etchants) at least one of the first electrically conductive oxide layer 233a and the second electrically conductive oxide layer 233b (e.g., both of the electrically conductive oxide layers 233a, 233b) after cleaning. As shown in FIG. 6B The perimeter 260 of the structure 200 includes electrically conductive oxide material 232 (e.g., ITO), which can provide hermeticity to components within the area bounded by the perimeter 260, as shown in

[0083] FIG. 7A Another example manufacturing process for the operating block 510 used to provide the first substrate 210 is schematically illustrated. (See diagram below.) FIG. 7A As shown, a first portion 214 of the first layer 212 includes a recess 710a relative to a second portion 216 of the first layer 212 (e.g., the top surface of the first portion 214 is recessed to a depth in the range of 3 nm to 40 nm relative to the top surface of the second portion 216; this recess can be formed by copper polishing), and includes a recess 710b at the top surface of the second portion 216 (e.g., having a depth in the range of 3 nm to 40 nm). Providing a first substrate 210 in the operating block 510 may include depositing a first electrically conductive oxide layer 233a (e.g., ITO; SnO) over the first layer 212, such that the recesses 710a, 710b are substantially filled with the first electrically conductive oxide material 232. For example, depositing the first electrically conductive oxide layer 233a may include sputtering, activated CVD, directional PVD, or ALD to a thickness on the micrometer scale. After depositing the first electrically conductive oxide layer 233a, the first electrically conductive oxide layer 233a can be planarized (e.g., using CMP) to remove portions of the first electrically conductive oxide material 232 outside the recesses 710a, 710b, thereby forming a first region 234a and a second region 236a. The first region 234a is above and electrically connected to one or more electrically conductive first portions 214, and the second region 236a is above one or more electrically insulating second portions 216. The top surface of the first electrically conductive oxide material 232 can be recessed relative to the top surface of the adjacent second portion 216 (e.g., in the range of 2 nm to 8 nm) to address the different coefficients of thermal expansion (CTE) of the electrically conductive oxide material 232 and the second portion 216 materials (e.g., different amounts of thermal expansion in a direction perpendicular to the top surface during subsequent annealing). For example, the CTE of ITO is approximately 5.8 × 10⁻⁶. -6 / K to 9×10 -6 / K, while the CTE of silicon dioxide is approximately 0.5 × 10⁻⁶. -6 / K. In comparison, the CTE of Cu is approximately 16.7 × 10⁻⁶. -6 / g. The thickness of ITO can be made thicker, and the size of the depression between ITO and adjacent silicon oxide can be more strictly controlled to solve the small CTE difference of ITO / SiO2.

[0084] In this way, the first region 234a and the second region 236a can be formed, and they can be electrically isolated from each other without a patterning step. After planarization, the first substrate 210 (including the first region 234a and the second region 236a comprising the first electrically conductive oxide layer 233a) can be thoroughly cleaned (e.g., rinsed and spin-dried) for subsequent direct bonding.

[0085] While FIG. 7A The example fabrication process is for fabricating the first substrate 210 from the first device 240 and the first layer 212, but the same example fabrication process can also be used to fabricate the second substrate 220 from the second device 250 and the second layer 222.

[0086] As FIG. 7B Illustratively, joining the first substrate 210 and the second substrate 220 directly to each other without an adhesive includes bringing the first substrate 210 and the second substrate 220 into contact with each other, with the first electrically conductive oxide surface layer 233a and the second electrically conductive oxide surface layer 233b between the first substrate 210 and the second substrate 220 (e.g., at room temperature; at a temperature below 35°C). For example, as shown in FIG. 3, the first electrically conductive oxide layer 233a and the second electrically conductive oxide layer 233b can be in contact with each other (e.g., the first regions 234a, 234b are in contact with each other, and the second regions 236a, 236b are in contact with each other). Moreover, the first dielectric region 720a of the first layer 212 and the second dielectric region 720b of the second layer 222 can also be in contact with each other and joined directly to each other. For example, if the first dielectric region 720a and / or the second dielectric region 720b are polished and activated, the first dielectric region 720a and the second dielectric region 720b can be joined to each other at room temperature (e.g., prior to annealing; prior to the first electrically conductive oxide layer 233a and the second electrically conductive oxide layer 233b being joined to each other). While FIG. 7B Illustratively, joining the first substrate 210 and the second substrate 220 directly to each other without an adhesive includes bringing the first substrate 210 and the second substrate 220 into contact with each other, with the first electrically conductive oxide surface layer 233a and the second electrically conductive oxide surface layer 233b between the first substrate 210 and the second substrate 220 (e.g., at room temperature; at a temperature below 35°C). For example, as shown in FIG. 3, the first electrically conductive oxide layer 233a and the second electrically conductive oxide layer 233b can be in contact with each other (e.g., the first regions 234a, 234b are in contact with each other, and the second regions 236a, 236b are in contact with each other). Moreover, the first dielectric region 720a of the first layer 212 and the second dielectric region 720b of the second layer 222 can also be in contact with each other and joined directly to each other. For example, if the first dielectric region 720a and / or the second dielectric region 720b are polished and activated, the first dielectric region 720a and the second dielectric region 720b can be joined to each other at room temperature (e.g., prior to annealing; prior to the first electrically conductive oxide layer 233a and the second electrically conductive oxide layer 233b being joined to each other). While FIG. 7B Illustratively, joining the first substrate 210 and the second substrate 220 directly to each other without an adhesive includes bringing the first substrate 210 and the second substrate 220 into contact with each other, with the first electrically conductive oxide surface layer 233a and the second electrically conductive oxide surface layer 233b between the first substrate 210 and the second substrate 220 (e.g., at room temperature; at a temperature below 35°C). For example, as shown in FIG. 3, the first electrically conductive oxide layer 233a and the second electrically conductive oxide layer 233b can be in contact with each other (e.g., the first regions 234a, 234b are in contact with each other, and the second regions 236a, 236b are in contact with each other). Moreover, the first dielectric region 720a of the first layer 212 and the second dielectric region 720b of the second layer 222 can also be in contact with each other and joined directly to each other. For example, if the first dielectric region 720a and / or the second dielectric region 720b are polished and activated, the first dielectric region 720a and the second dielectric region 720b can be joined to each other at room temperature (e.g., prior to annealing; prior to the first electrically conductive oxide layer 233a and the second electrically conductive oxide layer 233b being joined to each other). While

[0087] In some embodiments, method 500 may further include annealing structure 200 (e.g., heating to a predetermined temperature above room temperature and holding for a predetermined period of time; within a temperature range of 150°C to 300°C) after bringing the first substrate 210 and the second substrate 220 into contact with each other. As explained above, the annealing process can cause the electrically conductive oxide layers 233a, 233b to expand, thereby increasing the contact pressure between the opposing conductive regions. Additionally or alternatively, annealing may also cause grain growth across the bonding interface, such that the grains migrate at least partially into the opposing elements. In some embodiments, method 500 does not include activating (e.g., exposing to plasma and / or chemical etchants) at least one of the first electrically conductive oxide layers 233a and 233b (e.g., both of electrically conductive oxide layers 233a and 233b) after cleaning (e.g., exposure to plasma and / or chemical etchants). FIG. 7B As shown, the periphery 260 of structure 200 includes a solid dielectric material 270 (e.g., silicon oxycarbonate or SiO2). x N y C z The solid dielectric material 270 provides a higher level of sealing to components within the area defined by the perimeter 260 compared to the sealing provided by at least one electrically conductive oxide material 232.

[0088] The advantage is that, FIG. 6A-FIG. 7B In some embodiments of the method shown, the first substrate 210 and the second substrate 220 can be directly bonded without activating either substrate. For example, the first substrate 210 and the second substrate 220 may not be activated after patterning of the conductive oxide layers 233a, 233b (which can be used as conductive contact features) and before direct bonding. Additionally or alternatively, in some embodiments, at least one of the substrates 210 and 220 may not be planarized after patterning of the conductive oxide layers 233a, 233b and before direct bonding. Omitting one or both of these steps can simplify the direct bonding process and reduce manufacturing costs. Without being theoretically limited, the material properties of the conductive oxide layers 233a, 233b can allow for direct bonding after low-temperature annealing without planarization and / or activation. As explained above, annealing can cause expansion of the conductive oxide layers 233a, 233b and / or can cause grain growth, thereby promoting electrical connections between opposing conductive regions. In other embodiments, after the layers 233a, 233b are patterned and before direct bonding, one or both substrates 210, 220 may be planarized and / or activated.

[0089] FIG. 8A An example manufacturing process for providing the first substrate 210 is schematically illustrated. FIG. 8Athe manufacturing process of the first substrate 210 as described herein FIG. 6A the manufacturing process of the first substrate 210 as described herein FIG. 6A Providing the first substrate 210 in the operation block 510 can include depositing a first electrically conductive oxide layer 233a (e.g., ITO) over the first layer 212 (e.g., by sputtering, activated CVD, directional PVD, or ALD to a micron-scale thickness), for example. In certain embodiments, after depositing the first electrically conductive oxide layer 233a, the first electrically conductive oxide layer 233a can be planarized (e.g., using CMP) to remove the conductive oxide material 232 over the solid dielectric layer 810.

[0090] Providing the first substrate 210 in the operation block 510 can also include patterning the first electrically conductive oxide layer 233a to electrically isolate the first region 234a from the second region 236a. For example, as shown in FIG. 8A the first electrically conductive oxide layer 233a, the photoresist layer 610 can be patterned (e.g., using photolithography techniques) to expose portions of the planarized first electrically conductive oxide layer 233a, and then the exposed portions of the planarized first electrically conductive oxide layer 233a can be etched away, thereby forming a gap 238 between the first region 234a and the second region 236a (e.g., such that the second region 236a is not electrically shorted to the first region 234a to one another). After etching, the remaining photoresist layer 610 can be stripped, and the first substrate 210 (including the first region 234a and the second region 236a of the first electrically conductive oxide layer 233a) can be thoroughly cleaned (e.g., rinsed and spun dry) to be ready for direct bonding later. Although FIG. 8A the manufacturing process of the first substrate 210 as described herein

[0091] the manufacturing process of the first substrate 210 as described herein FIG. 8BIllustratively, directly bonding the first substrate 210 and the second substrate 220 to one another without an adhesive can include bringing the first substrate 210 and the second substrate 220 into contact with one another with at least one electrically conductive oxide surface layer between the first substrate 210 and the second substrate 220 (e.g., at room temperature; at a temperature less than 35°C). Although FIG. 8B Illustrative embodiments are described in which the second substrate 220 includes an electrically conductive oxide layer over the second layer 222; however, in certain other embodiments, the second substrate 220 does not include an electrically conductive oxide layer over the second layer 222, and the first substrate 210 and the second substrate 220 are directly bonded to one another using only the first electrically conductive oxide layer 233a between the first substrate 210 and the second substrate 220 (e.g., the first region 234a is in electrical contact with the first portion 214 and the third portion 224, and the second region 236a is in contact with the second portion 216 and the fourth portion 226). The alignment between the first region 234 and the first portion 214 and the third portion 224, and the alignment between the second region 236 and the second portion 216 and the fourth portion 226, can be sufficient to provide substantial electrical contact between the first portion 214 and the third portion 224 when desired, while avoiding electrical shorting of the first region 234 to one another (e.g., the alignment can not be perfect).

[0092] As described herein with respect to FIG. 6B and FIG. 7B the method 500 can further include annealing the structure 200 after bringing the first substrate 210 and the second substrate 220 into contact with one another, and / or deactivating the electrically conductive oxide layer after cleaning. As shown in FIG. 8B the perimeter 260 of the structure 200 includes a solid dielectric layer 810 that provides hermeticity to components within the area bounded by the perimeter 260.

[0093] FIG. 9A is an illustrative side cross-sectional view of a bonded structure according to certain embodiments described herein. FIG. 9B is an example process flow diagram for forming a bonded structure of FIG. 9A Unless otherwise indicated, components of FIG. 9A-FIG. 9B may be the same as, or substantially similar to, components numbered the same in FIG. 2A-FIG. 4F and FIG. 6A-FIG. 8B However, unlike certain embodiments described above, in FIG. 9A-FIG. 9BIn this process, the electrically conductive oxide material 232 can be blanket-deposited over one or both of the first substrate 210 and the second substrate 220, wherein a portion of the electrically conductive oxide material 232 deposited on the dielectric oxide material is electrically isolated from a portion of the electrically conductive oxide material 232 deposited on a conductive material (e.g., a metal pad). For example, as... FIG. 7B As shown, a first device 240 (which may include a semiconductor portion, such as a silicon portion) may be provided, and a first layer 212 including a first dielectric material may be deposited over the first device 240. An electrically conductive oxide material 232 may be deposited over the first dielectric material of the first layer 212. In some embodiments, the first dielectric material of the first layer 212 may include an inorganic dielectric, such as silicon oxide, silicon nitride, etc. In some embodiments, a second device 250 (which may include a semiconductor portion, such as a silicon portion) may be fabricated in a similar manner. For example, a second layer 222 including a second dielectric material may be deposited over the second device 250. In some embodiments, portions of the conductive oxide material 232 may also be blanket-deposited over the second dielectric material of the second layer 222. In some embodiments, the conductive oxide material 232 may be deposited only on the first substrate 210. The first substrate 210 and the second substrate 220 may be directly bonded to each other. As explained above, in some embodiments, either the first substrate 210 or the second substrate 220 may not be activated prior to direct bonding. Alternatively or additionally, one or both of the first substrate 210 and the second substrate 220 may not be planarized or polished prior to direct bonding. However, in some other embodiments, one or both of the first substrate 210 and the second substrate 220 may be planarized and / or activated prior to direct bonding.

[0094] Table 1 lists example combinations of materials for the first regions 234a, 234b (e.g., the at least one conductive oxide material 232) and the materials of the electrically conductive first and third portions 214, 224 of the first and second substrates 210, 220, according to certain embodiments described herein. Table 2 lists example combinations of materials for the second regions 236a, 236b (e.g., the at least one conductive oxide material 232) and the materials of the electrically insulating second and fourth portions 216, 226 of the first and second substrates 210, 220, according to certain embodiments described herein. In each of Table 1 and Table 2, the absence of a material designation indicates that the at least one conductive oxide material 232 is only on one of the first and second substrates 210, 220 prior to contacting the first and second substrates 210, 220 to one another. Various stoichiometric ratios of the at least one conductive oxide material 232 are compatible with certain embodiments described herein and can play a role in the strength of the bond. Table 1: Table 2:

[0095] In certain embodiments, the bonded structure 200 can be coated with a protective layer, mounted on a dicing sheet, and singulated (e.g., by saw dicing, laser dicing, reactive ion etching dicing, wet etching, or a combination thereof) to form singulated dies on a dicing frame. The protective layer can be removed (e.g., peeled off) from the singulated dies and the exposed dicing sheet (e.g., using a solvent, reactive ion etching, etc.). The singulated dies can be cleaned (e.g., rinsed and dried using spin-drying or other processes) to clean the singulated dies. The cleaned dies can be configured for subsequent processes. For example, the cleaned dies can be further bonded to a prepared surface of another substrate (e.g., including power pads, ground pads, and / or other passive elements configured to transmit power to the bonded dies).

[0096] FIG. 10An example build process flow for forming a structure according to certain embodiments described herein is schematically illustrated. At least one conductive oxide material 232 (e.g., ITO) can facilitate the build process flow. In addition, similar processes can also be used for structures with multiple metal layers (e.g., with a transparent conductive layer on top of Cu or Al pads). For example, the at least one conductive oxide material 232 can be deposited onto the first substrate 210 or the functional wafer device 240, a photoresist layer 610 can be deposited on the at least one conductive oxide material 232, the photoresist layer 610 can be patterned (e.g., using photolithography techniques) to expose portions of the at least one conductive oxide material 232, and the exposed portions of the at least one conductive oxide material 232 are etched away to form gaps. For example, the patterning of ITO can be performed using dilute HC1 or HC1 vapor in a plasma dry etch process, or using CI2, BCI3, CH4, or H2 as a dry etchant. After etching, the remaining photoresist layer 610 can be stripped, and a dielectric layer 910 can be deposited over the functional wafer device 240 or the first substrate 210 and the at least one conductive oxide material 232 within the gaps, and excess dielectric material can be removed (e.g., using CMP), thereby forming a planar first layer 212 for bonding, which can be sufficiently cleaned (e.g., rinsed and spin-dried) for subsequent direct bonding. The planar first layer 212 can include the at least one conductive oxide material 232 as the first portion 214, and the dielectric material in the gaps as the second portion 216. The at least one conductive oxide material 232 can be configured to mate with active input / output pads on the second functional wafer device 250.

[0097] While some common terms are used to describe systems and methods of certain embodiments for ease of understanding, these terms used herein are intended to be interpreted fairly. Although various aspects of this disclosure are described with respect to illustrative examples and embodiments, the disclosed examples and embodiments should not be construed as limiting. Unless expressly stated otherwise, or understood otherwise in the context, conditional language such as “can,” “could,” “might,” or “may” is generally intended to convey that some embodiments include certain features, elements, and / or steps, while others do not. Therefore, such conditional language is not generally intended to imply that one or more embodiments are required in any way to include certain features, elements, and / or steps, or that one or more embodiments must include logic for determining (whether or not user input or prompting is required) whether such features, elements, and / or steps are included in a particular embodiment or whether they need to be performed. In particular, the terms “comprises” and “comprising” should be interpreted as referring to various elements, components or steps in a non-exclusive manner, indicating that the mentioned elements, components or steps may be present, used, or combined with other elements, components or steps not explicitly mentioned.

[0098] It should be understood that the embodiments disclosed herein are not mutually exclusive and can be combined with each other in various arrangements. Furthermore, although the disclosed methods and apparatus are primarily described in the context of direct bonding processes, the various embodiments described herein can also be incorporated into various other suitable devices, methods, and contexts.

[0099] As used herein, the degree language, such as "approximately," "about," "generally," and "substantially," mean that the value, amount, or characteristic is close to the stated value, amount, or characteristic, but still performs a desired function or achieves a desired result. For example, the terms "approximately," "about," "generally," and "substantially" can refer to an amount that is within ±10% of, ±5% of, ±2% of, ±1% of, or ±0.1% of the stated amount. As another example, the terms "generally parallel" and "substantially parallel" refer to a value, amount, or characteristic that is within ±10 degrees, ±5 degrees, ±2 degrees, ±1 degree, or ±0.1 degree of being perfectly parallel; the terms "generally perpendicular" and "substantially perpendicular" refer to a value, amount, or characteristic that is within ±10 degrees, ±5 degrees, ±2 degrees, ±1 degree, or ±0.1 degree of being perfectly perpendicular. The ranges disclosed herein also encompass any and all overlap ranges, sub-ranges, and combinations thereof. Language such as "up to," "at least," "greater than," "less than," "between," and the like include the number mentioned. As used herein, "a," "an," and "the" are meant to include plural references unless the context clearly dictates otherwise. Additionally, as used in the description herein, the meaning of "in" includes "into" and "on," unless the context clearly dictates otherwise.

[0100] Although the methods and systems herein are discussed with elements labeled by ordinal adjectives (e.g., first, second, etc.), the ordinal adjectives are used merely as labels to distinguish one element from another (e.g., one substrate from another substrate or one surface layer from another surface layer), and the ordinal adjectives are not meant to signify order or sequence of the elements.

[0101] The disclosure described and claimed herein is not to be limited in scope by the specific examples as many variations of the examples are possible while maintaining the spirit and nature of the disclosure described and claimed herein. Any equivalent embodiments are intended to fall within the scope of the disclosure. Indeed, various modifications of the foregoing, in addition to those shown and described herein will become apparent to those skilled in the art in view of the foregoing description. Such modifications are also intended to fall within the scope of the claims. Nothing herein is to be construed as an admission that the disclosure is not entitled to antedate such disclosure by virtue of prior disclosure. The disclosure of the examples described herein does not constitute admission that any aspect of the disclosure described and / or claimed herein, or any specific example described herein, is essential, critical, or required, or necessary for the practice of the disclosure.

Claims

1. A structure comprising: A first substrate, the first substrate comprising a first layer having at least one electrically conductive first portion and at least one electrically insulating second portion; The second substrate includes a second layer having at least one electrically conductive third portion and at least one electrically insulating fourth portion; as well as An interface layer, situated between the first layer and the second layer, comprises at least one electrically conductive oxide material, the at least one electrically conductive oxide material comprising: At least one first region, the at least one first region being between the at least one first portion of the electrical conduction and the at least one third portion of the electrical conduction, and being electrically connected to the at least one first portion of the electrical conduction and the at least one third portion of the electrical conduction; as well as At least one second region, the at least one second region being between the at least one second portion of the electrical insulation and the at least one fourth portion of the electrical insulation, the at least one second region being electrically isolated from the at least one first region.

2. The structure according to claim 1, wherein the at least one electrically conductive oxide material is optically transparent.

3. The structure according to claim 2, wherein the at least one electrically conductive oxide material comprises indium tin oxide or zinc oxide.

4. The structure according to claim 1, wherein the at least one electrically conductive oxide material comprises a first electrically conductive oxide material on the first layer and a second electrically conductive oxide material on the second layer, the first electrically conductive oxide material being directly bonded to the second electrically conductive oxide material.

5. The structure according to claim 1, wherein the at least one electrically conductive first portion and / or the at least one electrically conductive third portion is selected from the group consisting of copper, tungsten, cobalt, or zinc oxide.

6. The structure according to claim 1, wherein the second portion of the at least one electrically insulating material and / or the fourth portion of the at least one electrically insulating material are selected from the group consisting of silicon oxide, silicon nitride, copper nitride, and titanium nitride.

7. The structure according to claim 1, wherein the at least one first region is electrically isolated from the at least one second region.

8. The structure of claim 7, wherein a portion of the at least one electrically conductive oxide material at the periphery of the first substrate and the second substrate seals a second portion of the at least one electrically conductive oxide material relative to the surrounding environment.

9. The structure according to claim 7, further comprising a gap between the at least one first region and the at least one second region.

10. The structure according to claim 9, wherein the at least one electrically conductive oxide material is not embedded within the second portion and / or the fourth portion of the at least one electrically insulating material.

11. The structure of claim 7, wherein the interface layer further comprises at least one solid dielectric material between the at least one first region and the at least one second region.

12. The structure according to claim 11, wherein the at least one electrically conductive oxide material is embedded within the second portion and / or the fourth portion of the at least one electrically insulating material.

13. The structure according to claim 11, wherein the at least one solid dielectric material comprises silicon oxycarbonitrile.

14. The structure of claim 11, wherein a portion of the at least one solid dielectric material at the periphery of the first substrate and the second substrate seals the at least one first region and the at least one second region relative to the surrounding environment.

15. The structure of claim 14, wherein the at least one solid dielectric material substantially surrounds the first region and the second region.

16. The structure according to claim 11, wherein the at least one electrically conductive oxide material is embedded in the at least one solid dielectric material.

17. A structure comprising: A first substrate, the first substrate having a first conductive feature, the first conductive feature including a first region of a first deposited electrically conductive oxide material; as well as A second substrate having a second conductive feature directly bonded to the first conductive feature.

18. The structure of claim 17, wherein the first substrate comprises a first layer having at least one electrically conductive first portion and at least one electrically insulating second portion, the first region of the first deposited electrically conductive oxide material being above and electrically connected to the at least one electrically conductive first portion.

19. The structure of claim 18, wherein the second region of the first deposited electrically conductive oxide material is above the at least one electrically insulating second portion.

20. The structure of claim 19, wherein the second region of the first deposited electrically conductive oxide layer is directly bonded to at least a portion of the second deposited electrically conductive oxide material.

21. The structure according to claim 19, further comprising at least one gap between the first region and the second region.

22. The structure of claim 17, wherein the second conductive feature comprises a second deposited electrically conductive oxide material.

23. The structure of claim 17, wherein the first substrate includes a first non-conductive field region, and the second substrate includes a second non-conductive field region directly bonded to the first non-conductive field region, the first deposited electrically conductive oxide material being at least partially embedded in the first non-conductive field region.

24. The structure of claim 17, wherein the first deposited electrically conductive oxide material is optically transparent.

25. The structure of claim 17, wherein the first deposited electrically conductive oxide material comprises indium tin oxide or zinc oxide.

26. A method comprising: A first substrate and a second substrate are provided, each substrate including one or more electrically conductive surface portions and one or more electrically insulating surface portions, at least one of the first substrate and the second substrate further including an electrically conductive oxide layer, the electrically conductive oxide layer having a first region above and electrically connected to the one or more electrically conductive surface portions; And a second region, which is above the one or more electrically insulating surface portions, and is electrically isolated from the first region; as well as The first substrate and the second substrate are directly bonded to each other without an intermediate adhesive, wherein directly bonding the first substrate and the second substrate includes: bringing the first substrate and the second substrate into contact with each other, wherein the electrically conductive oxide layer is between the first substrate and the second substrate.

27. The method of claim 26, wherein providing the first substrate comprises: A first electrically conductive oxide layer is deposited over the one or more electrically conductive surface portions and the one or more electrically insulating surface portions; as well as The first electrically conductive oxide layer is patterned to electrically isolate the first region from the second region.

28. The method of claim 27, wherein providing the second substrate comprises: A second electrically conductive oxide layer is deposited over the one or more electrically conductive surface portions and the one or more electrically insulating surface portions; as well as The second electrically conductive oxide layer is patterned to electrically isolate the first region from the second region.

29. The method of claim 28, wherein directly bonding the first substrate and the second substrate further comprises: The patterned first electrically conductive oxide layer and the patterned second electrically conductive oxide layer are brought into contact with each other.

30. The method of claim 27, wherein patterning the first electrically conductive oxide layer comprises: A photoresist layer is deposited over the first electrically conductive oxide layer; The photoresist layer is patterned to expose a portion of the first electrically conductive oxide layer; The exposed portion of the first electrically conductive oxide layer is etched away; as well as The photoresist layer is peeled off.

31. The method of claim 27, wherein patterning the first electrically conductive oxide layer comprises: The first electrically conductive oxide layer is planarized.

32. The method of claim 31, wherein the one or more electrically conductive surface portions have a recess relative to the one or more electrically insulating surface portions, wherein depositing the first electrically conductive oxide layer comprises filling the recess with the first electrically conductive oxide layer, and wherein planarizing the first electrically conductive oxide layer comprises removing a portion of the first electrically conductive oxide layer outside the recess.

33. The method of claim 31, wherein the one or more electrically insulating surface regions have depressions, wherein depositing the first electrically conductive oxide layer includes filling the depressions with the first electrically conductive oxide layer, and wherein planarizing the first electrically conductive oxide layer includes removing portions of the first electrically conductive oxide layer outside the depressions.

34. The method of claim 33, further comprising: A photoresist layer is deposited over the planarized first electrically conductive oxide layer; The photoresist layer is patterned to expose a portion of the planarized first electrically conductive oxide layer; The exposed portion of the planarized first electrically conductive oxide layer is etched away; as well as The photoresist layer is peeled off.

35. The method of claim 26, further comprising: Before bringing the first substrate and the second substrate into contact with each other, at least one of the first substrate and the second substrate is cleaned.

36. The method of claim 26, further comprising: After the first substrate and the second substrate are brought into contact with each other, the first substrate and the second substrate are annealed.

37. A method comprising: A first substrate is provided having a patterned first conductive contact feature, the patterned first conductive contact feature including a first region of a first electrically conductive oxide material; A second substrate having a second conductive contact feature is provided; as well as The first conductive contact feature is directly bonded to the second conductive contact feature.

38. The method of claim 37, wherein the first substrate is not activated prior to the direct bonding.

39. The method of claim 37, wherein the first substrate was not activated with plasma prior to the direct bonding.

40. The method of claim 37, wherein the first substrate was not activated with nitrogen-containing plasma prior to the direct bonding.

41. The method of claim 37, wherein the first substrate is not planarized after the first conductive contact feature is patterned and before the direct bonding.

42. The method of claim 41, further comprising: The first electrically conductive oxide material is deposited on the base layer of the first substrate, and the deposited first electrically conductive oxide material is patterned.

43. The method of claim 37, wherein the second conductive contact feature comprises a deposited second electrically conductive oxide material.

44. The method of claim 37, wherein providing the first substrate comprises: A first layer is provided on a base layer, the first layer having at least one electrically conductive first portion and at least one electrically insulating second portion, the first region of the first electrically conductive oxide material being above and electrically connected to the at least one electrically conductive first portion.

45. The method of claim 44, wherein providing the first substrate comprises: A second region of the first electrically conductive oxide material is provided above the second portion of the at least one electrically insulating material.

46. ​​The method of claim 37, wherein providing the first substrate comprises: A first non-conductive field region is provided on a first base layer of the first substrate, and wherein providing the second substrate includes: providing a second non-conductive field region on a second base layer of the second substrate, wherein the first electrically conductive oxide material is at least partially embedded in the first non-conductive field region, and the second conductive contact feature is at least partially embedded in the second non-conductive field region.

47. The method of claim 46, further comprising: The first non-conductive field region is directly bonded to the second non-conductive field region.

48. The method of claim 37, wherein the direct bonding comprises contacting the first substrate and the second substrate, and annealing the first substrate and the second substrate after contacting the first substrate and the second substrate.

49. The method of claim 48, wherein the annealing comprises annealing at a temperature not exceeding 300°C.

50. The method of claim 48, wherein the annealing comprises heating to a temperature in the range of 120°C to 350°C.

51. The method of claim 50, wherein the annealing comprises heating to a temperature in the range of 150°C to 300°C.

52. A method comprising: A first patterned conductive contact feature is provided in the first substrate; A second patterned conductive contact feature is provided in the second substrate; The first patterned conductive contact feature is directly bonded to the second patterned conductive contact feature, wherein the first substrate and the second substrate are not activated after the first patterned conductive contact feature is patterned and before the direct bonding.

53. The method of claim 52, wherein the first substrate is not planarized after the first patterned conductive contact feature is patterned and before the direct bonding.

54. The method of claim 52, wherein the first patterned conductive contact feature comprises a first region of a deposited first electrically conductive oxide material.

55. The method of claim 54, further comprising: The first electrically conductive oxide material is deposited on the base layer of the first substrate, and the deposited first electrically conductive oxide material is patterned.

56. The method of claim 55, wherein the second patterned conductive contact feature comprises a deposited second electrically conductive oxide material.

57. The method of claim 54, wherein providing the first substrate comprises providing a first layer on a base layer, the first layer having at least one electrically conductive first portion and at least one electrically insulating second portion, the first region of the deposited first electrically conductive oxide material being above and electrically connected to the at least one electrically conductive first portion.

58. The method of claim 57, wherein providing the first substrate includes providing a second region of the deposited first electrically conductive oxide material over the at least one electrically insulating second portion.

59. The method of claim 54, wherein providing the first substrate includes providing a first non-conductive field region on a first base layer of the first substrate, and wherein providing the second substrate includes providing a second non-conductive field region on a second base layer of the second substrate, wherein the deposited first electrically conductive oxide material is at least partially embedded in the first non-conductive field region, and the second patterned conductive contact feature is at least partially embedded in the second non-conductive field region.

60. The method of claim 59 further comprises directly bonding the first non-conductive field region to the second non-conductive field region.

61. The method of claim 52, wherein the direct bonding comprises contacting the first substrate and the second substrate, and annealing the first substrate and the second substrate after contacting the first substrate and the second substrate.

62. The method of claim 61, wherein the annealing comprises annealing at a temperature not exceeding 300°C.

63. The method of claim 62, wherein the annealing comprises heating to a temperature in the range of 120°C to 350°C.

64. The method of claim 63, wherein the annealing comprises heating to a temperature in the range of 150°C to 300°C.

65. A method comprising: A patterned first conductive contact feature is provided in the first substrate; A patterned second conductive contact feature is provided in the second substrate; The patterned first conductive contact feature is directly bonded to the patterned second conductive contact feature, wherein the first substrate is not planarized after the first conductive contact feature is patterned and before the direct bonding.

66. The method of claim 65, wherein neither of the first substrate nor the second substrate is activated prior to the direct bonding.

67. The method of claim 65, wherein the second substrate is not planarized after the patterned second conductive contact feature is patterned and before the direct bonding.

68. The method of claim 65, wherein the patterned first conductive contact feature comprises a first region of a deposited first electrically conductive oxide material.

69. The method of claim 65, further comprising: A first electrically conductive oxide material is deposited on the base layer of the first substrate, and the deposited first electrically conductive oxide material is patterned.

70. The method of claim 69, wherein the patterned second conductive contact feature comprises a deposited second electrically conductive oxide material.

71. The method of claim 65, wherein providing the patterned first conductive contact feature comprises providing a first layer on a base layer, the first layer having at least one electrically conductive first portion and at least one electrically insulating second portion.

72. The method of claim 65, wherein providing the patterned first conductive contact feature comprises: A first non-conductive field region is provided on a first base layer of the first substrate, and wherein providing the patterned second conductive contact feature includes providing a second non-conductive field region on a second base layer of the second substrate.

73. The method of claim 72, further comprising: The first non-conductive field region is directly bonded to the second non-conductive field region.

74. The method of claim 65, wherein the direct bonding comprises contacting the first substrate and the second substrate, and annealing the first substrate and the second substrate after contacting the first substrate and the second substrate.

75. The method of claim 74, wherein the annealing comprises heating at a temperature not exceeding 300°C.

76. The method of claim 74, wherein the annealing comprises heating to a temperature in the range of 120°C to 350°C.

77. The method of claim 76, wherein the annealing comprises heating to a temperature in the range of 150°C to 300°C.

78. A structure comprising: A first substrate, the first substrate comprising a first layer, the first layer comprising a dielectric oxide portion and an electrically conductive portion; The second substrate includes a second layer, which includes a dielectric oxide portion and an electrically conductive portion; as well as An interface layer is located between a first layer and a second layer. The interface layer includes at least one electrically conductive oxide material and includes a first portion between the dielectric oxide portions of the first layer and the second layer and a second portion between the electrically conductive portions of the first layer and the second layer, wherein the first portion of the interface layer is electrically isolated from the second portion of the interface layer.

79. The structure of claim 78, wherein the first layer comprises at least one material selected from the group consisting of silicon oxide, silicon nitride, copper nitride, and titanium nitride.

80. The structure of claim 79, wherein the second layer comprises at least one material selected from the group consisting of silicon oxide, silicon nitride, copper nitride, and titanium nitride.

81. The structure according to claim 78, wherein the at least one electrically conductive oxide material is optically transparent.

82. The structure according to claim 78, wherein the at least one electrically conductive oxide material comprises indium tin oxide or zinc oxide.

83. A method comprising: A first element is provided, the first element comprising a first surface layer, the first surface layer comprising a dielectric oxide portion and an electrically conductive portion; A second element is provided, the second element including a second surface layer, the second surface layer including a dielectric oxide portion and an electrically conductive portion; An electrically conductive oxide layer is deposited over at least one of the first surface layer and the second surface layer. The deposited layer includes a first portion over the dielectric oxide portion of at least one of the first surface layer and the second surface layer, and the deposited layer also includes a second portion over the electrically conductive portion of at least one of the first surface layer and the second surface layer. The first portion of the deposited layer is electrically isolated from the second portion of the deposited layer. as well as The first element and the second element are directly bonded to each other without an intermediate adhesive, the direct bonding including bonding the first surface layer and the second surface layer together, wherein the electrically conductive oxide layer is between the first surface layer and the second surface layer.

84. The method of claim 83, wherein providing the first element comprises: The first surface layer is deposited on the first element, the first surface layer comprising a first dielectric film stack.

85. The method of claim 84, wherein providing the second element comprises: The second surface layer is deposited on the second element, the second surface layer comprising a second dielectric film stack.

86. The method of claim 83, further comprising: At least one of the first surface layer and the second surface layer is planarized.

87. The method of claim 83, further comprising: The deposited electrically conductive oxide layer is planarized prior to the direct bonding.

88. The method of claim 83, wherein the direct engagement further comprises: Before bonding the first surface layer and the second surface layer together, at least one of the first element and the second element is cleaned.

89. The method of claim 83, wherein the direct engagement further comprises: After the first surface layer and the second surface layer are bonded together, the first element and the second element are annealed.

90. A method comprising: A first substrate is provided having a first conductive contact feature, the first conductive contact feature comprising a first region of a deposited first electrically conductive oxide material; A second substrate having a second conductive contact feature is provided; as well as The first conductive contact feature is directly bonded to the second conductive contact feature.

91. The method of claim 90, wherein the first substrate is not activated prior to the direct bonding.

92. The method of claim 90, wherein the first substrate was not activated with plasma prior to the direct bonding.

93. The method of claim 90, wherein the first substrate was not activated with nitrogen-containing plasma prior to the direct bonding.

94. The method of claim 90, wherein the first substrate is not planarized after the first conductive contact feature is patterned and before the direct bonding.

95. The method of claim 94, further comprising: The first electrically conductive oxide material is deposited on the base layer of the first substrate, and the deposited first electrically conductive oxide material is patterned.

96. The method of claim 90, wherein the second conductive contact feature comprises a deposited second electrically conductive oxide material.

97. The method of claim 90, wherein providing the first substrate comprises: A first layer is provided on a base layer, the first layer having at least one electrically conductive first portion and at least one electrically insulating second portion, the first region of the deposited first electrically conductive oxide material being disposed above and electrically connected to the at least one electrically conductive first portion.

98. The method of claim 97, wherein providing the first substrate comprises: A second region of the first electrically conductive oxide material deposited thereon is provided above the second portion of the at least one electrically insulating material.

99. The method of claim 90, wherein providing the first substrate comprises: A first non-conductive field region is provided on a first base layer of the first substrate, and wherein providing the second substrate includes: providing a second non-conductive field region on a second base layer of the second substrate, wherein the deposited first electrically conductive oxide material is at least partially embedded in the first non-conductive field region, and the second conductive contact feature is at least partially embedded in the second non-conductive field region.

100. The method of claim 99, further comprising: The first non-conductive field region is directly bonded to the second non-conductive field region.

101. The method of claim 90, wherein the direct bonding comprises contacting the first substrate and the second substrate, and annealing the first substrate and the second substrate after contacting the first substrate and the second substrate.

102. The method of claim 101, wherein the annealing comprises annealing at a temperature not exceeding 300°C.

103. The method of claim 101, wherein the annealing comprises heating to a temperature in the range of 120°C to 350°C.

104. The method of claim 103, wherein the annealing comprises heating to a temperature in the range of 150°C to 300°C.

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