Ceramic coating structure and preparation method thereof

Abstract

The invention provides a ceramic coating structure and a preparation method thereof. The ceramic coating structure includes: a substrate; a transition layer disposed on the substrate; the transition layer is arranged on the substrate, the ceramic coating is arranged on the transition layer, the transition layer is formed by alternately depositing at least one first metal layer and at least one second metal layer, the surface of the substrate is in direct contact with the lowermost first metal layer serving as the transition layer, and the uppermost second metal layer serving as the transition layer is in direct contact with the ceramic coating. The ratio of the larger one to the smaller one of the stacking fault energy of the first metal layer and the stacking fault energy of the second metal layer is greater than 3; the lattice mismatch degree between the first metal layer and the second metal layer is greater than 2% and less than 15%; and the ratio of the thermal expansion coefficient of the second metal layer to the thermal expansion coefficient of the first metal layer is greater than 1.2 and less than 5.

Description

Technical Field

[0001] The following description relates to a ceramic coating structure and its preparation method, and more specifically, to a ceramic coating structure for stabilizing high-temperature, high-density stacking faults and its preparation method. Background Technology

[0002] Hard coatings are widely used to protect substrates, thereby improving their wear resistance, corrosion resistance, and toughness, and thus increasing the service life of parts or the cutting speed of cutting tools. However, due to the significant difference in properties such as modulus between hard coatings and substrates, coatings are prone to detaching from the substrate, thus losing their protective function. Therefore, transition layers are introduced to increase the adhesion between the coating and the substrate. However, researchers often only focus on the influence of the transition layer on the adhesion between the coating and the substrate. There is relatively little research on the influence of the transition layer structure on the coating structure and properties. On the other hand, the stacking fault energy (SFE) of transition metal nitride ceramics is extremely high, making it difficult to form stacking faults or twins. A large body of literature has studied the induction of twins by metals with low stacking fault energy into metals with high stacking fault energy, such as Ag / Al, Mg / Al, and Cu / Fe. However, research on the introduction of stacking faults into ceramic materials is still scarce. Low stacking fault energy metal-induced stacking faults in nitride ceramics is a research hotspot in this field. Meanwhile, since the presence of stacking faults or twins can improve the strength and toughness of metals, the influence of introducing a large number of stacking faults and superlattice structures into ceramic materials on their mechanical properties is also worthy of study. Research has shown that by preparing a 20 nm thick Ti transition layer under a TiN / AlN coating using magnetron sputtering, the Ti transition layer can generate high-density stacking faults during the preparation process, inducing severe distortion at the interface between the transition layer and the ceramic coating. This results in a sufficiently large distortion energy exceeding the stacking fault energy of the ceramic coating, leading to the generation of stacking faults within the ceramic layer and subsequently inducing the formation of high-density stacking faults. Further research indicates that the mechanical and bonding properties of this coating are significantly better than those of coatings without a transition layer. Therefore, preparing a suitable transition layer is an effective means of introducing high-density stacking faults.

[0003] However, the high-density stacking faults at the interface between the single-structure metal transition layer and the ceramic coating are prone to thermally activated migration or annihilation under high-temperature conditions (above 800℃), disrupting the original defect structure. Furthermore, the high-density stacking fault system has high free energy, which may decrease at high temperatures through stacking fault merging, annihilation, or rearrangement, leading to structural instability. Additionally, the difference in thermal expansion coefficients between the transition layer, the ceramic coating, and the substrate may generate additional stress under thermal loads, forcing the stacking faults to further expand as strain release channels, further damaging the coating's adhesion. Therefore, a single-structure metal transition layer alone cannot solve these problems. To prepare high-density stacking fault ceramic coatings that retain sufficient stacking fault density and good adhesion under high-temperature conditions, new technologies are needed. Summary of the Invention

[0004] This disclosure provides a ceramic coating structure and its preparation method. The core idea of ​​this disclosure is to introduce a specially designed heterogeneous metal multilayer transition layer between the substrate and the ceramic coating. The structure of this transition layer needs to meet specific physical parameter matching rules, thereby synergistically achieving the stabilization of high-density stacking faults in the ceramic layer at high temperatures and the efficient relief of thermal mismatch stress, ultimately obtaining a coating system that combines high temperature, high hardness, and excellent bonding performance.

[0005] Embodiments of this disclosure provide a ceramic coating structure comprising: a substrate; a transition layer disposed on the substrate; and a ceramic coating disposed on the transition layer, wherein the transition layer is formed by alternating deposition of at least one first metal layer and at least one second metal layer, the surface of the substrate is in direct contact with the bottommost layer of the transition layer, the first metal layer, and the topmost layer of the transition layer is in direct contact with the ceramic coating, wherein the ratio of the larger of the stacking fault energies of the first metal layer and the second metal layer to the smaller of the stacking fault energies is greater than 3; the lattice mismatch between the first metal layer and the second metal layer is greater than 2% and less than 15%; and the ratio of the coefficient of thermal expansion of the second metal layer to the coefficient of thermal expansion of the first metal layer is greater than 1.2 and less than 5.

[0006] According to embodiments of this disclosure, both the first metal layer and the second metal layer are single-element metal layers.

[0007] According to embodiments of this disclosure, the single-layer thickness of both the first metal layer and the second metal layer is greater than or equal to 10 nm and greater than three times the corresponding critical thickness, wherein the critical thickness It is obtained from the following formula:

[0008] in, This is the critical thickness. For lattice mismatch, The Burgers vector of the dislocation corresponding to the interface slip system of the corresponding metal is determined based on the crystal structure of the corresponding metal, and the total thickness of the transition layer is 20nm-200nm.

[0009] According to embodiments of this disclosure, the group consisting of the metal forming the first metal layer and the metal forming the second metal layer is one of (Cr, Ti) and (Ni, Ag).

[0010] According to embodiments of this disclosure, the ceramic coating includes TiN and AlN.

[0011] Embodiments of this disclosure provide a method for preparing a ceramic coating structure. The method includes: providing a substrate; selecting a first metal and a second metal; alternately depositing a first metal layer with the first metal and a second metal layer with the second metal on the substrate to form a transition layer, wherein the bottommost first metal layer of the transition layer is in direct contact with the surface of the substrate; and depositing a ceramic coating on the topmost second metal layer of the transition layer. The selection of the first metal and the second metal includes: a ratio of the larger of the stacking fault energies of the first metal and the second metal to a ratio of the smaller of the two stacking fault energies greater than 3; a lattice mismatch between the first metal and the second metal greater than 2% and less than 15%; and a ratio of the thermal expansion coefficient of the second metal layer to the thermal expansion coefficient of the first metal layer greater than 1.2 and less than 5.

[0012] According to embodiments of this disclosure, both the first metal and the second metal are elemental metals, and the group consisting of the first metal and the second metal is one of (Cr, Ti) and (Ni, Ag).

[0013] According to embodiments of this disclosure, the single-layer thickness of both the first metal layer and the second metal layer is greater than or equal to 10 nm and greater than three times the corresponding critical thickness, wherein the critical thickness It is obtained from the following formula:

[0014] in, This is the critical thickness. For lattice mismatch, The Burgers vector of the dislocation corresponding to the interface slip system of the corresponding metal is determined based on the crystal structure of the corresponding metal, and the total thickness of the transition layer is 20nm-200nm.

[0015] According to embodiments of this disclosure, the first metal is Cr and the second metal is Ti. A transition layer is formed by alternately depositing a first metal layer with the first metal and a second metal layer with the second metal. This includes: forming a first metal layer with a substrate bias of -80V and a thickness of 15 nm; and forming a second metal layer with a substrate bias of -100V and a thickness of 15 nm. The deposition environment for forming the transition layer is: target power 400W, target-substrate distance 40 mm, Ar flow rate 20 SCCM, working pressure 0.2 Pa, stage rotation speed 20 r / min, temperature 300°C, and deposition time 30 seconds.

[0016] According to an embodiment of this disclosure, the ceramic coating is TiN. The deposition of the ceramic coating includes: a substrate bias voltage of -80V, a Ti target power of 200W, a target-substrate distance of 40 mm, an Ar flow rate of 20 SCCM, an N2 flow rate of 7 SCCM, a working gas pressure of 0.2 Pa, a stage rotation speed of 20 r / min, a temperature of 300°C, and a deposition time of 3 h. The thickness of the resulting ceramic coating is approximately 2 micrometers.

[0017] According to one or more embodiments of this disclosure, a high-density stacking fault ceramic coating can be prepared by simple means, and the coating still has high-density stacking faults and good adhesion at a high temperature of 800°C, solving the problem that a single metal transition layer is difficult to provide stable high-temperature film-substrate adhesion and high-density stacking fault structure. Attached Figure Description

[0018] The above and other aspects, features, and advantages of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. In the drawings: Figure 1 This is a schematic diagram of a ceramic coating structure according to an embodiment of the present disclosure; Figure 2 This is a schematic diagram of a magnetron sputtering apparatus according to an embodiment of the present disclosure; Figure 3 This is a flowchart of the preparation method for ceramic coating structures; Figure 4 High-resolution transmission electron microscopy (HRTEM) images of ceramic coating structures according to embodiments of the present disclosure after high-temperature annealing at 800°C; and Figure 5 The results are based on the ceramic coating structure according to embodiments of the present disclosure and the nanoindentation mechanical property test results of comparative examples. Detailed Implementation

[0019] The following detailed embodiments are provided to aid the reader in gaining a comprehensive understanding of the methods, apparatus, and / or systems described herein. However, various modifications, variations, and equivalents of the methods, apparatus, and / or systems described herein will be apparent to those skilled in the art. For example, the order of operations described herein is merely illustrative and is not limited to the order set forth herein; changes that will be apparent to those skilled in the art may be made, except for operations that must be performed in a particular order. Furthermore, for clarity and brevity, descriptions of features and structures well-known to those skilled in the art may be omitted. The features described herein may be implemented in different forms and will not be construed as being limited to the examples described herein. Rather, the examples provided herein make this disclosure thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0020] The core idea of ​​this disclosure is to introduce a specially designed heterogeneous metal multilayer transition layer between the substrate and the ceramic coating. The structure of this transition layer needs to meet specific physical parameter matching rules, thereby synergistically achieving high-density stacking faults in the ceramic layer at high temperatures and efficiently alleviating thermal mismatch stress, ultimately obtaining a coating system that combines high temperature, high hardness and excellent bonding performance.

[0021] Figure 1 This is a schematic diagram of a ceramic coating structure according to an embodiment of the present disclosure.

[0022] Reference Figure 1 The ceramic coating structure includes: a substrate; a transition layer disposed on the substrate; and a ceramic coating disposed on the transition layer.

[0023] In an embodiment, the transition layer is formed by alternating deposition of at least one first metal layer and at least one second metal layer. The surface of the substrate is in direct contact with the bottommost first metal layer of the transition layer, and the topmost second metal layer of the transition layer is in direct contact with the ceramic coating.

[0024] In this embodiment, the two metals constituting the heterogeneous multilayer transition layer (i.e., the first metal forming the first metal layer and the second metal forming the second metal layer) are both elemental metals, and they must satisfy the following three quantitative relationships: The ratio of the relatively larger stacking fault energy of the first metal to the relatively smaller stacking fault energy of the second metal is greater than 3. The lattice mismatch between the first metal and the second metal is greater than 2% and less than 15%; and The ratio of the thermal expansion coefficient of the second metal to that of the first metal layer is greater than 1.2 and less than 5.

[0025] The following section will provide a detailed analysis of the selection of these quantitative relationships.

[0026] First, the high stacking fault energy ratio enables energy barrier pinning of dislocations. In this embodiment, a combination of a high stacking fault energy (High SFE) material and a low stacking fault energy (Low SFE) material is selected. When a dislocation slides from the low SFE layer to the high SFE layer interface, the resulting extended dislocation must consume a huge amount of energy to shrink into a total dislocation. The stacking fault energy ratio of the two metals... At this energy level, the energy barrier is sufficient to effectively pin dislocations, greatly hindering their movement and thus stabilizing the defect structure. Molecular dynamics and phase-field simulations confirm that the interaction behavior between dislocations and interfaces has a mechanism transition region determined by the SFE ratio. In systems with low SFE ratios, such as copper / nickel (Cu / Ni), the SFE ratio is approximately 1.1–1.8. ~90 mJ / m 2 vs 50~78 mJ / m 2 Phase-field simulations show that although interfaces hinder dislocations, dislocations still have a considerable probability of contracting and crossing the interface under stress. This contrasts sharply with systems with high SFE ratios. A typical example is the silver / copper (Ag / Cu) system, where... ≈ 25 mJ / m 2 , ≈ 70-78 mJ / m 2 their ratio ≈ 2.8 ~ 3.1. Phase-field simulations clearly show that when a dislocation slides from the Ag layer with a lower SFE to the Ag / Cu interface, it is effectively pinned to the interface due to the large contraction energy barrier, preventing direct passage. Deformation needs to continue through other mechanisms with higher stress (such as activating new dislocation sources at the interface). This directly proves that when the SFE ratio reaches around 3, the interface becomes an effective barrier for dislocations. Therefore, the quantitative relationship of the stacking fault energy ratio is: .

[0027] In the embodiments, taking the Cr / Ti system as an example, Cr is a low SFE metal ( ≈ 40 mJ / m 2 Ti is a high SFE metal ( ≈ 310 mJ / m 2 That is, the first metal is Cr and the second metal is Ti. Their ratio... ≈ 310 / 40 = 7.75, which is much greater than 3, and can form an extremely strong interface pinning effect.

[0028] As another example, taking the Ni / Ag system as an example, For high SFE metals ( Ag is a low SFE metal ( That is, the first metal is Ni and the second metal is Ag. Their ratio... This interface can form an energy barrier and has a strong pinning ability for dislocations.

[0029] In this embodiment, stress pinning can be achieved through lattice mismatch. A significant difference in lattice constants is required between the two metals to form a semi-coherent structure and a high-density network of mismatched dislocations at the interface. This network itself is a periodic nanostress field, further hindering dislocation movement across the interface. However, excessive mismatch leads to interface incoherence and decreased bonding strength. When the lattice mismatch δ is in the range of 2% < δ < 15%, the most effective stress pinning can be achieved while maintaining good interfacial bonding.

[0030] In engineering practice and many experimental studies (such as those on InxGa1-xN / GaN, Ge / Si systems), it is generally considered that when the mismatch is below 1.5-2%, it is difficult to effectively form a high-density mismatch dislocation network in nanoscale thin films. When the mismatch is very large, the spacing between mismatch dislocations at the interface becomes extremely small, the dislocation cores begin to overlap, the interface structure becomes highly disordered, loses its periodicity, and transforms into a non-coherent interface. In multilayer film designs that need to withstand mechanical or thermal stress, in order to ensure the interface has the most basic structural integrity and bonding strength, the upper limit of the mismatch is usually controlled at 10-15%. For example, the mismatch of the InN / GaN system is as high as 11.1%, which is already considered an example of extremely high mismatch. Beyond this range, the sharp decline in interface quality will offset or even outweigh the benefits brought by the pinning effect. Therefore, this disclosure limits the range of lattice mismatch to 2% < δ < 15%.

[0031] In the embodiment, when the {110} plane of Cr (BCC, a=2.88 Å) and the {0001} basal plane of Ti (HCP, a=2.95 Å) are matched, their atomic arrangement mismatch falls within this range, where a is the lattice constant.

[0032] As another example, taking the Ni / Ag system as an example, It has an FCC structure and a lattice constant. , It has an FCC structure and a lattice constant. For FCC / FCC epitaxial growth, the closest-packed plane (111) matching is typically considered. In-plane atomic spacing... .but:

[0033]

[0034] We can see that δ ≈ 14.98%. This value falls within the range of 2% < δ < 15%, which means that a high-density mismatch dislocation network will form at the Ni / Ag interface, generating a large periodic stress field that works in conjunction with the energy barrier.

[0035] On the other hand, the ratio of their coefficients of thermal expansion (CTE) cannot be too small or too large. To alleviate the enormous thermal stress from the substrate to the coating, a significant difference in the CTE between the two metals is required to generate an "internal dissipation" effect in the alternating layers. During cooling, the layer with a larger CTE contracts more (under tension), while the layer with a smaller CTE contracts less (under compression), forming an alternating tensile and compressive stress field. This internal stress field not only decomposes and buffers macroscopic thermal stress, but its local stress gradient can also further hinder the migration of stacking faults and dislocations. When the ratio of their CTEs is... satisfy At the same time, it can provide sufficient thermal stress buffering capacity without causing the transition layer to crack due to excessive internal stress. In addition, the coefficients of thermal expansion of the two metals (metal A and metal B) constituting the transition layer are ( , It should be entirely within the matrix ( ) and ceramic coating ( The coefficients of thermal expansion are determined to ensure that the transition layer, as a whole, can smoothly connect the substrate and the coating, avoiding drastic stress abrupt changes at the macroscopic interface.

[0036] In fields such as microelectronics packaging, to address CTE mismatch, materials with significant CTE differences are typically chosen for graded transitions. A CTE ratio less than 1.2 means the difference between adjacent layers is less than 20%, which offers minimal buffering effect against the stress generated by a large temperature difference of 800°C. While a large CTE difference helps alleviate macroscopic stress between the substrate and coating layers, it introduces mesoscopic / microscopic localized stresses at each pair of first-metal-second-metal interfaces. When the CTE difference between two adjacent layers is too large (a ratio exceeding 5 is generally considered an extreme difference), under a temperature change as large as 800°C, the localized shear stress generated between these two layers alone may exceed the interfacial bond strength or the yield strength of the weaker material. This can cause the transition layer to fail due to delamination or plastic deformation before it can provide protection.

[0037] In the embodiment, Cr ( =6.2×10 -6 / K) and Ti ( =8.6×10 -6 The CTE ratio of / K) is = 8.6 / 6.2 ≈ 1.39.

[0038] As another example, Ni ( ) and Ag (CTE_Ag ≈ 18.9 × 10 -6The CTE ratio of / K is R_CTE = CTE_Ag / CTE_Ni = 18.9 / 13.4 ≈ 1.41.

[0039] Figure 2 This is a schematic diagram of a magnetron sputtering apparatus according to an embodiment of the present disclosure.

[0040] like Figure 2 As shown, the magnetron co-sputtering system consists of a vacuum chamber, multiple targets located above, and a substrate located below. Magnetron sputtering is performed in the vacuum chamber. First, an inert gas (such as Ar and / or Ar and N2) is introduced into the vacuum chamber. Then, in the reaction atmosphere containing the inert gas, a glow discharge confined by a magnetic field generates plasma, Ar... + The target is bombarded, sputtering atoms that then deposit onto the substrate surface under a negative bias. If the inert gas includes N2, the sputtered atoms will also be transported downwards along with the active nitrogen-containing material and deposited onto the substrate surface.

[0041] According to embodiments of this disclosure, a magnetron co-sputtering system includes a Ti target and a Cr target for co-sputtering Ti and Cr. Although not shown, the magnetron co-sputtering system also includes components such as a substrate support, power supply, gas supply port, exhaust port, and vacuum pump to achieve precise control of the deposition environment (such as pressure, gas composition, bias voltage, and target power).

[0042] Figure 3 This is a flowchart of the preparation method for ceramic coating structures; Reference Figure 3 In step S10, a substrate is provided. The substrate is a 0.5 mm thick single-crystal silicon wafer, which is ultrasonically cleaned in acetone and ethanol for 10 minutes. Then, Ar ion etching is performed for 5 minutes. Ion etching requires heating the substrate to 400°C and reducing the gas pressure in the deposition chamber of the magnetron sputtering equipment to 1.5 × 10⁻³ Pa. A constant supply of Ar is then introduced to maintain the total pressure in the chamber at approximately 1.5 Pa. At this point, a constant -1000 V bias voltage is applied to the substrate stage to achieve ion etching of the substrate.

[0043] In step S15, the first metal and the second metal are selected.

[0044] In this embodiment, the first metal is Cr and the second metal is Ti. The elastic modulus of each material is: , , , The selection of Cr and Ti as core materials for the transition layer is mainly based on their high-density stacking fault formation capability, stacking fault energy difference, lattice mismatch, thermal expansion compatibility with the substrate and ceramic layer, chemical compatibility, and fabrication feasibility.

[0045] First, it exhibits excellent high-density stacking fault formation capability. In this embodiment, the stacking faults in the TiN layer to be formed later can reach 1000 mJ / m². 2 Therefore, stacking faults are generally difficult to form in ceramics. However, a metal transition layer with high-density stacking faults can distort the interface between the ceramic layer and the transition layer, resulting in large local strain. To reduce this strain energy, the ceramic coating will form stacking faults at the interface to adapt to the distortion, thereby reducing the strain energy. That is, the formation of high-density stacking faults in the transition layer and their distribution to the interface will cause high-density stacking faults in the ceramic layer. By depositing a TiN coating on a 20 nm thick transition layer, a TiN ceramic coating with high-density stacking faults can be obtained because a large number of stacking faults are formed first in the Ti transition layer. Since the stacking fault energy of Cr is lower than that of Ti, the transition layer constructed of Cr and Ti is conducive to the formation of high-density stacking faults in the TiN ceramic coating.

[0046] Cr (BCC structure) is a low stacking fault energy metal, with a literature SFE value of approximately 40 mJ / m. 2 Ti (HCP structure) is a high-level fault energy metal, with a literature SFE value as high as approximately 310 mJ / m. 2 Their stacking fault energies are:

[0047] The calculated result of 7.75 is much greater than 3. Therefore, the Cr / Ti interface can form an extremely high energy barrier, providing a prerequisite for efficient dislocation pinning and stable defect structures.

[0048] Secondly, Cr and Ti exhibit moderate lattice mismatch. The mismatch must be calculated along specific crystal orientations under specific interface matching conditions. For Cr with a BCC structure and Ti with an HCP structure, the lowest-energy and most common interface matching relationship is that their closest-packed crystal planes are parallel to each other, i.e., Cr{110} || Ti{0001}. Based on this, the atomic arrangement matching of the main crystal orientations at this interface is analyzed.

[0049] For Cr (BCC):

[0050] For Ti (HCP):

[0051] Where 'a' is the lattice constant. For the atomic arrangement at the Cr / Ti interface, on the {0001} basal plane of Ti, the atoms are arranged in a hexagonal close-packed configuration, with the closest packing direction being... Directional group, interatomic spacing along this direction for

[0052] On the {110} plane of Cr, the atoms are arranged in a central rectangular pattern, and there are two main directions of high symmetry, one of which is... Direction, along the edge of the rectangle, interatomic spacing for

[0053] Another one is The direction, along the short diagonal of the rectangle, is also the closest packing direction in the BCC structure, with interatomic spacing. for

[0054] Therefore, the degree of mismatch can be calculated. Since the system spontaneously selects a lower-energy matching mode during growth, we calculate two possible low-exponential orientation relationships (…). as well as degree of mismatch . The calculation is performed using the following relationship:

[0055] Orientation: The closest packing direction on the Ti basal plane needs to be aligned with a principal direction on the Cr{110} plane, thus...

[0056] Orientation: This orientation aligns the closest packing directions of the two crystals, thereby...

[0057] Therefore, the Cr / Ti interface is a semi-coherent interface with significant anisotropy. It exhibits a mismatch direction as low as 2.4%. This falls near the lower limit of the lattice fit criterion 2% < δ < 15%, ensuring that the system can form an epitaxial growth interface and achieve good bonding strength. However, due to the fundamental mismatch in symmetry between the two crystal structures, there is a huge mismatch of up to 17.0% in other directions. This massive mismatch generates a high density of geometrically required dislocations and a strong periodic stress field at the interface, hindering the movement of dislocations across the interface at high temperatures.

[0058] Furthermore, Cr and Ti have good compatibility in terms of thermal expansion. The coefficient of thermal expansion of Cr (… ) between monocrystalline silicon wafer substrate ( ) and TiN coating ( Between ), the coefficient of thermal expansion of the Ti layer ( Similarly, it possesses intermediate transition characteristics. Therefore, through a stepped thermal expansion coefficient design with multiple transition layers, a continuous thermal expansion gradient is constructed from the silicon wafer Cr layer → Ti layer → … → Cr layer → Ti layer → TiN coating. After forming multiple thermal expansion gradients, the overall thermal strain is decomposed into small strain increments between multiple layers, thereby reducing the thermal stress difference. If the silicon wafer directly contacts the ceramic layer, the difference in thermal expansion coefficients at the film-substrate interface is…

[0059] After introducing the Cr / Ti multilayer film, the total thermal mismatch is decomposed across three continuous interfaces: Si to Cr:

[0060] Cr to Ti:

[0061] Ti to TiN:

[0062] The maximum difference in the coefficient of thermal expansion at the interface is calculated to be This represents a 50% reduction compared to direct contact between silicon wafers and TiN. Furthermore, the ratio of the thermal expansion coefficients between Cr and Ti is... This conforms to the requirements of this disclosure. This indicates that while achieving a gradient transition, the Cr / Ti multilayer film still retains a moderate difference in thermal expansion, which can form an alternating tensile / compressive stress field during cooling. This further dissipates and buffers the residual stress transmitted from the matrix through internal micro-deformation, playing a synergistic role of "internal damping".

[0063] Finally, the preparation of Cr and Ti is highly feasible. The sputtering yield difference between Cr and Ti is small (<15%), and the thickness fluctuation of multilayer films can be stably controlled to <5%.

[0064] In step S20, a first metal layer is alternately deposited with a first metal and a second metal layer is alternately deposited with a second metal on the substrate to form a transition layer, wherein the bottommost first metal layer of the transition layer is in direct contact with the surface of the substrate. Alternatingly depositing the first metal layer with a first metal and the second metal layer with a second metal to form the transition layer includes: forming the first metal layer, wherein the substrate bias voltage is -80V and the thickness of the formed first metal layer is 15 nm; forming the second metal layer, wherein the substrate bias voltage is -100V and the thickness of the formed second metal layer is 15 nm. The deposition environment for forming the transition layer is: target power 400 W, target-substrate distance 40 mm, Ar flow rate 20 SCCM, working gas pressure 0.2 Pa, stage rotation speed 20 r / min, temperature 300 °C, and deposition time 30 seconds.

[0065] The structural parameters of the transition layer are as follows: 15 nm nanocrystalline layer per cycle, 4 cycles in total, with a total thickness of 120 nm. These parameters are based on the following: In this disclosure, the selection of the thickness of the transition layer is not a fixed empirical value, but follows a core physical principle related to the specific material: namely, the thickness of the single layer. It must be greater than the Matthews-Blakeslee critical thickness, which is determined by the lattice mismatch δ of the two metals. This is to ensure the formation of a high-density, thermally stable network of mismatch dislocations at the interface, thereby achieving the stress pinning effect described in this disclosure. According to the Matthews-Blakeslee model, the film thickness must exceed a critical value for mismatch dislocations to form. This model reveals the critical thickness. It is directly related to the inherent parameters of the material, such as lattice mismatch δ, among which It is approximately inversely proportional to δ. Therefore, different metal combinations (such as Cr / Ti, Ni / Ag, etc.) have different lattice constants and elastic properties, resulting in varying critical thicknesses. They are also different. The simplified formula for the Matthews-Blakeslee model is:

[0066] in, The lattice mismatch is taken as 0.024; This represents the magnitude of the Burgers vector. The smallest Burgers vector of BCC-Cr is selected. Given that the lattice constant of Cr is a = 2.88 Å, therefore b ≈ 0.25 nm. The Cr / Ti interface of this disclosure exhibits significant anisotropic mismatch, with mismatches ranging from as low as 2.4% to as high as 17.0%. To determine the critical thickness... The calculation, choosing δ ≈ 2.4% as the calculation parameter, is based on the principle of minimizing energy during epitaxial growth. However, for the high misfit (17.0%) case, since the interface is incoherent from the beginning, it easily forms a high density of geometrically required dislocations to match the structure. These dislocations do not only appear after a certain "critical thickness," therefore, only the case of δ ≈ 2.4% is considered. In summary, substituting the parameters into the formula:

[0067] achievable Therefore, the critical thickness of this system is taken as approximately 5 nm in this disclosure. To overcome the kinetic barrier and form a stable dislocation network, the monolayer thickness h should be much greater than... This disclosure preferably adopts... As a design standard. At the same time, thickness. It needs to be large enough (e.g., preferably). >10 nm) to avoid grain boundary slip and ensure the transition layer has excellent mechanical support properties. Therefore, for the Cr / Ti system, its calculated critical thickness is... The thickness is approximately 5 nm, but a single layer thickness of 15 nm was chosen because it simultaneously satisfies... (far exceeding critical thickness) and >10 nm (to ensure mechanical properties) is an optimized value obtained by following the universal design criteria of this disclosure.

[0068] To disperse the thermal stress between the ceramic layer and the substrate, a transition layer is added to reduce the stress difference. Additionally, the transition layer helps to form high-density stacking faults. Therefore, if the thickness is too thin, it will cause thermal stress mismatch and insufficient stacking fault formation. Conversely, if the transition layer is too thick, it will accumulate significant residual stress, inducing failure problems such as cracking and desorption. In this embodiment, for a ceramic layer 1–5 micrometers thick, the transition layer thickness can be 20–200 nm; therefore, 120 nm is chosen as the total thickness of the transition layer.

[0069] a) Ti layer: The bias voltage was -100V, Ti target power was 400W, target-substrate distance was 40 mm, Ar flow rate was 20 SCCM, working pressure was 0.2 Pa, stage rotation speed was 20 r / min, temperature was 300℃, and the deposition time was 30 seconds, resulting in a single layer thickness of approximately 15 nm. Increasing the negative bias voltage resulted in stronger high-energy ion bombardment, improving the mobility of sputtered atoms and stabilizing the nanocrystal size within the 5-15 nm range. High deposition power combined with dynamic deposition (stage rotation) resulted in a film surface roughness Ra < 1.2 nm, reducing high-temperature stress concentration points; simultaneously, the high deposition rate from high power avoided columnar crystal growth caused by low-speed deposition. The increased mean free path of sputtered particles under low pressure (0.2 Pa) enhanced the kinetic energy of sputtered atoms, leading to the formation of dense nanocrystals.

[0070] b) Cr layer: Bias voltage -80V, Cr target power 400W, target-substrate distance 40mm, Ar flow rate 20 SCCM, working gas pressure 0.2Pa, stage rotation speed 20r / min, temperature 300℃, 30 seconds, monolayer thickness approximately 15 nm.

[0071] As another example, in the Ni / Ag system, due to the lattice mismatch of the Ni / Ag system... (14.98%) is relatively high, according to the Matthews-Blakeslee model ( and (inversely proportional), its calculated critical thickness It will be much smaller than 1 nm. In this case, the first part of the design guidelines... This is easily met. Therefore, the actual lower limit of the single-layer thickness will be determined by the second part of the design criteria, namely the lower limit of the dimensions that guarantee excellent mechanical properties (preferred). The thickness is determined by the thickness (>10 nm). Choosing a thickness greater than 10 nm (e.g., 15 nm) ensures that the transition layer exhibits dislocation-dominated mechanical behavior, avoiding softening, thereby meeting the design requirements of this disclosure.

[0072] In step S30, a ceramic coating is deposited on the uppermost second metal layer, which serves as a transition layer.

[0073] According to an embodiment of this disclosure, the ceramic coating is TiN. The deposition of the ceramic coating includes: a substrate bias voltage of -80V, a Ti target power of 200W, a target-substrate distance of 40 mm, an Ar flow rate of 20 SCCM, an N2 flow rate of 7 SCCM, a working gas pressure of 0.2 Pa, a stage rotation speed of 20 r / min, a temperature of 300°C, and a deposition time of 3 h. The thickness of the resulting ceramic coating is approximately 2 micrometers.

[0074] To verify the effectiveness of the technical solution proposed in this disclosure under high-temperature conditions, three samples were prepared according to the preferred embodiments and comparative tests were conducted: S1: TiN coating sample (with stacking faults) prepared using the Cr / Ti multilayer transition layer described in this disclosure.

[0075] S2: Comparative example, TiN coating is deposited directly on the substrate without a transition layer (no stacking faults).

[0076] S3: Sample S1 after annealing at 800℃ (with stacking faults, after annealing).

[0077] The specific steps involved preparing a high-density stacked fault TiN coating (hereinafter referred to as HDSF-TiN) using a Cr / Ti multilayer transition layer, and comparing it with a conventional TiN coating that did not use the transition layer disclosed herein. The key verification step was to anneal both coating samples in a vacuum environment at 800°C for 1 hour to simulate high-temperature conditions, and then characterize their mechanical properties at room temperature.

[0078] Figure 4 High-resolution transmission electron microscopy (HRTEM) images of the HDSF-TiN coating prepared for this disclosure after high-temperature annealing at 800 °C are shown. The HRTEM images clearly reveal numerous straight, linear defects within the TiN grains, which are typical stacking fault structures. Fast Fourier Transform (FFT) analysis of regions a, b, c, and d in the images shows significant elongation and fringe characteristics in the diffraction spots, providing strong evidence of high-density planar defects (stacking faults or nanotwins) within the crystal. These results directly confirm that the transition layer design method proposed in this disclosure can successfully induce high-density stacking fault structures in ceramic coatings with inherently high stacking fault energy.

[0079] Figure 5 The results are based on the ceramic coating structure according to embodiments of the present disclosure and the nanoindentation mechanical property test results of comparative examples.

[0080] Reference Figure 5The mechanical properties of TiN coatings with a special transition layer structure and conventional TiN coatings were tested using nanoindentation technology. The results are shown in the figure below. The left figure is a typical load-displacement curve, and the right figure is a hardness comparison bar chart based on the results of multi-point tests. The hardness bar chart shows that the S1 sample (with stacking faults) has a hardness as high as 26.4 GPa, compared to 20.9 GPa for the S2 sample (without stacking faults), representing an increase of approximately 26.3%. This is reflected in the load-depth curve, where S1 has the shallowest indentation depth under the same load, indicating its strongest resistance to plastic deformation. This demonstrates that the introduction of high-density stacking faults has a significant strengthening effect on the ceramic coating. The S3 sample was obtained by annealing the S1 sample at 800℃, and its hardness is 24.4 GPa. Compared to the unannealed S1, the hardness decreased by only about 7.6%, retaining more than 92% of the strengthening effect. More importantly, the hardness of the annealed S3 sample is still about 16.7% higher than that of the S2 sample without stacking faults. This is reflected in the load-depth curve as curve S3 remaining far to the left of curve S2. This result strongly demonstrates that the heterogeneous multilayer transition layer designed in this disclosure can effectively pin and stabilize stacked fault structures, making them less prone to annihilation at high temperatures, thus solving the problem of structural instability at high temperatures mentioned in the background art.

Claims

1. A ceramic coating structure, characterized in that, The ceramic coating structure includes: Base; A transition layer disposed on the substrate; and A ceramic coating is disposed on the transition layer. The transition layer is formed by alternating deposition of at least one first metal layer and at least one second metal layer. The surface of the substrate is in direct contact with the bottommost first metal layer of the transition layer, and the topmost second metal layer of the transition layer is in direct contact with the ceramic coating. Wherein, the ratio of the larger of the stacking fault energies of the first metal layer and the second metal layer to the smaller of the stacking fault energies is greater than 3; the lattice mismatch between the first metal layer and the second metal layer is greater than 2% and less than 15%; and the ratio of the thermal expansion coefficient of the second metal layer to the thermal expansion coefficient of the first metal layer is greater than 1.2 and less than 5.

2. The ceramic coating structure according to claim 1, characterized in that, Both the first metal layer and the second metal layer are single-element metal layers.

3. The ceramic coating structure according to claim 2, characterized in that, The thickness of both the first and second metal layers is greater than or equal to 10 nm and is greater than three times the corresponding critical thickness. It is obtained from the following formula: in, This is the critical thickness. For lattice mismatch, The Burgers vector of the dislocation corresponding to the interface slip system of the corresponding metal is determined based on the crystal structure of the corresponding metal, and The total thickness of the transition layer is 20nm-200nm.

4. The ceramic coating structure according to claim 2, characterized in that, The group consisting of the metal forming the first metal layer and the metal forming the second metal layer is one of (Cr, Ti) and (Ni, Ag).

5. The ceramic coating structure according to claim 2, characterized in that, The ceramic coating includes TiN and AlN.

6. A method for preparing a ceramic coating structure, the method comprising: Provide a base; Select the first metal and the second metal; On the substrate, a first metal layer is deposited alternately with a first metal and a second metal layer is deposited with a second metal to form a transition layer, wherein the first metal layer, which is the bottommost layer of the transition layer, is in direct contact with the surface of the substrate. A ceramic coating is deposited on the uppermost second metal layer, which serves as the transition layer. The selection of the first metal and the second metal includes: the ratio of the larger of the stacking fault energies of the first metal and the second metal to the smaller of the stacking fault energies of the second metal is greater than 3; the lattice mismatch between the first metal and the second metal is greater than 2% and less than 15%; and the ratio of the thermal expansion coefficient of the second metal layer to the thermal expansion coefficient of the first metal layer is greater than 1.2 and less than 5.

7. The method according to claim 6, characterized in that, Both the first metal and the second metal are elemental metals, and the group consisting of the first metal and the second metal is one of (Cr, Ti) and (Ni, Ag).

8. The method according to claim 7, characterized in that, The thickness of both the first and second metal layers is greater than or equal to 10 nm and is greater than three times the corresponding critical thickness. It is obtained from the following formula: in, This is the critical thickness. For lattice mismatch, The Burgers vector of the dislocation corresponding to the interface slip system of the corresponding metal is determined based on the crystal structure of the corresponding metal, and The total thickness of the transition layer is 20nm-200nm.

9. The method according to claim 7, characterized in that, The first metal is Cr, and the second metal is Ti, wherein a first metal layer is deposited with the first metal and a second metal layer is deposited with the second metal alternately to form a transition layer, including: A first metal layer is formed, wherein the substrate bias voltage is -80V and the thickness of the first metal layer is 15 nm. A second metal layer is formed, wherein the substrate bias voltage is -100V, and the thickness of the second metal layer is 15 nm. The deposition environment for forming the transition layer was as follows: target power 400W, target-substrate distance 40 mm, Ar flow rate 20 SCCM, working gas pressure 0.2 Pa, stage rotation speed 20 r / min, temperature 300℃, and deposition time 30 seconds.

10. The method according to claim 9, characterized in that, The ceramic coating is TiN, wherein the deposition of the ceramic coating includes: The substrate bias was -80V, the Ti target power was 200W, the target-substrate distance was 40 mm, the Ar flow rate was 20 SCCM, the N2 flow rate was 7 SCCM, the working gas pressure was 0.2Pa, the stage rotation speed was 20 r / min, the temperature was 300℃, the deposition time was 3h, and the thickness of the resulting ceramic coating was 2 micrometers.

Images