Multi-component transverse heterogeneous single crystal array based on melting method and preparation method of multi-component transverse heterogeneous single crystal array

Abstract

The invention provides a multi-component transverse heterogeneous single crystal array based on a melting method and a preparation method thereof.The preparation method of the multi-component transverse heterogeneous single crystal array comprises the steps that a silicon column template at least provided with a first silicon column and a second silicon column and a substrate at least provided with a first filling through hole and a second filling through hole are adopted; based on the difference of glass transition temperatures of different semiconductor powder materials, the multi-component transverse heterogeneous single crystal array is formed in a gap between the first silicon column and the substrate and a gap between the second silicon column and the substrate through a melting method. By regulating and controlling the infiltration behavior of the melt in the limited space, the flow and three-dimensional morphology of the micro-area melt are accurately controlled, the directional transmission of the melt is controlled in combination with the periodic structure silicon column template, and the efficient preparation of the multi-component organic semiconductor single crystal array with determined crystal orientation, controllable structure size and accurate positioning is realized. The problems of poor crystallinity, uncontrollable orientation, low alignment precision and the like of a traditional liquid phase processing method are solved, and patterning preparation of the low-solubility material single crystal is realized.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a multi-component lateral heterojunction single crystal array based on the melting method and its preparation method. Background Technology

[0002] Optoelectronic co-integration technology is a key path to improve the computing power density and energy efficiency of semiconductor systems. Its core lies in integrating various electrical and optical functional materials on a single chip at the micro-nano scale, achieving synergistic optimization of logic, memory, and optoelectronic units. Specific applications cover multiple levels: at the circuit level, CMOS technology relies on the coplanar integration of P-type and N-type transistors to construct logic gates; in the field of photodetection, three-color organic photodetectors need to integrate red, green, and blue response units to achieve high-fidelity spectral sensing; in the field of display and light emission, the performance of full-color displays depends on the positioning accuracy and interface quality of RGB light-emitting units; and three-color organic laser resonators require the integration of gain media of different wavelengths in an optical structure with low loss. Furthermore, on-chip optoelectronic systems require the integration of light sources, modulators, waveguides, detectors, and driving circuits on a single substrate. Therefore, achieving monolithic integration of multi-component materials with controllable positions and clear interfaces has become the technological cornerstone for developing high-performance optoelectronic systems.

[0003] Compared to mature inorganic semiconductors, organic semiconductors possess advantages such as designable molecular structures, intrinsic flexibility, low-temperature processing, and large-area, low-cost manufacturing, making them promising candidates for flexible electronics, wearable devices, and optoelectronic neural networks. However, achieving the controllable integration of high-quality single crystals from multi-component organic semiconductor materials remains a challenge.

[0004] Existing processing technologies have significant limitations. For example, while inkjet printing can achieve patterned deposition, its crystallization process is difficult to control, easily leading to polycrystalline structures and introducing grain boundary defects. The fabrication of RGB pixel arrays for full-color displays often relies on multi-step mask evaporation, which is complex, has low material utilization (<5%), and increases costs due to alignment errors. Although transfer printing supports multi-component integration, the process is cumbersome and inefficient, and its multiple pick-and-release operations can easily cause structural damage and positional misalignment. These bottlenecks result in electrical crosstalk, optical interference, and interface defects in devices, severely restricting their uniformity and reliability.

[0005] Therefore, there is a need to provide a simpler and more efficient process for patterning organic semiconductor devices. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the present invention aims to provide a multi-component lateral heterogeneous single crystal array based on a melting method and its preparation method. By controlling the morphology of silicon pillar templates to form a periodic structure, and by realizing the directional transport of different component melts based on the melting method, a multi-component lateral heterogeneous organic semiconductor single crystal array with high density, high crystallinity, controllable position, and clear interface can be obtained.

[0007] To achieve this objective, the present invention adopts the following technical solution:

[0008] In a first aspect, the present invention provides a method for fabricating a multi-component lateral heterojunction single-crystal array based on a melting method. The method includes: providing a silicon pillar template and a substrate; the silicon pillar template having at least a plurality of first silicon pillars and a plurality of second silicon pillars, the first silicon pillars and second silicon pillars being alternately spaced along a first direction and extending independently perpendicular to the first direction; the substrate having at least a plurality of first filling vias and a plurality of second filling vias, the first filling vias and second filling vias being alternately spaced along the first direction at the same end of the substrate; and placing the substrate above the first silicon pillars and second silicon pillars, such that the first filling vias correspond one-to-one with the first silicon pillars, and the second filling vias correspond one-to-one with the second silicon pillars. A one-to-one correspondence is established, followed by pressure to bring the substrate close to the first and second silicon pillars; a first powder is added to the first filling via and then subjected to a heating treatment to melt the first powder and spread it along the surface of the first silicon pillar, followed by a cooling treatment to form a first micron-line single crystal array in the gap between the first silicon pillar and the substrate; a second powder is added to the second filling via and then subjected to a second heating treatment to melt the second powder and spread it along the surface of the second silicon pillar, followed by a second cooling treatment to form a second micron-line single crystal array in the gap between the second silicon pillar and the substrate; then the silicon pillar template is removed to obtain a lateral heterojunction single crystal array; the glass transition temperature of the first powder is greater than that of the second powder; the first direction is the arrangement direction of the first and second silicon pillars.

[0009] This invention designs a silicon pillar template with a periodic structure and an open substrate. Based on the melting point differences of different materials, it achieves directional transport and local crystallization of multi-component melts on the substrate, integrating semiconductor single-crystal arrays with different compositions on the same substrate. The powder bulk is directly melted by a melting method, eliminating the need to introduce other liquid phase raw materials and avoiding the introduction of new contamination or cross-contamination. Furthermore, by controlling the heating and cooling processes, uniform spread and sequential crystallization of the melt are achieved, forming a patterned single-crystal array with consistent orientation, flat interface, low defect density, and the same structure as the silicon pillar array between the silicon pillar template and the substrate.

[0010] It should be noted that the extension direction of the silicon pillar template in this invention refers to the width or length direction of the silicon pillar template, and the extension direction of the substrate is the same as the extension direction of the silicon pillar template.

[0011] As a preferred embodiment of the present invention, the linear lengths of the first silicon pillar and the second silicon pillar in the first direction are independently 1 to 100,000 μm, for example, they can be 1 μm, 5 μm, 10 μm, 50 μm, 100 μm, 500 μm, 1000 μm, 2000 μm, 5000 μm, 8000 μm, 10000 μm, 30000 μm, 50000 μm, 60000 μm, 80000 μm or 100000 μm, but are not limited to the listed values, and other unlisted values ​​within this range are also applicable.

[0012] The distance between the first silicon pillar and the second silicon pillar is 1~100μm, for example, it can be 1μm, 5μm, 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm or 100μm, but it is not limited to the listed values. Other unlisted values ​​within this range are also applicable.

[0013] As a preferred technical solution of the present invention, the provided silicon pillar template is subjected to asymmetric wetting treatment, so that the top surfaces of the first silicon pillar and the second silicon pillar are hydrophilic, while the sidewall surfaces are hydrophobic.

[0014] It should be noted that the top surface mentioned in this invention refers to the surface of the first silicon pillar or the second silicon pillar that is close to the substrate.

[0015] As one embodiment of the present invention, the contact angle of the top surfaces of the first silicon pillar and the second silicon pillar is 5° to 10°, for example, it can be 5°, 6°, 7°, 8°, 9° or 10°, but it is not limited to the listed values. Other unlisted values ​​within this range are also applicable.

[0016] As one embodiment of the present invention, the contact angle of the sidewall surfaces of the first silicon pillar and the second silicon pillar is 80°~100°, for example, it can be 80°, 82°, 85°, 88°, 90°, 93°, 95° or 100°, but it is not limited to the listed values. Other unlisted values ​​within this range are also applicable.

[0017] As a preferred embodiment of the present invention, the substrate material includes at least one of glass, quartz, silicon, or silicon oxide.

[0018] In one embodiment of the present invention, the first filling through hole and the second filling through hole are arranged side by side, or the orthographic projection of the first filling through hole on the vertical plane does not coincide with the orthographic projection of the second filling through hole on the vertical plane, or at least a portion of the orthographic projection of the first filling through hole on the vertical plane coincides with the orthographic projection of the second filling through hole on the vertical plane.

[0019] In one embodiment of the present invention, the diameter of the first filling through hole is smaller than the first length, and the first length is the sum of the linear length of the first silicon pillar in the first direction and the distance between the first silicon pillar and the second silicon pillar.

[0020] The diameter of the second injection via is smaller than the second length, which is the sum of the linear length of the second silicon pillar in the first direction and the distance between the first and second silicon pillars.

[0021] As a preferred technical solution of the present invention, the provided substrate is selectively chemically modified to adjust the wettability of the melt after the first powder and the second powder are fused on the surface of the substrate, so as to obtain a first micron-line single crystal array and a second micron-line single crystal array with different widths.

[0022] As one embodiment of the present invention, the contact angle between the melt of the first powder and the melt of the second powder on the substrate surface is 10° to 80°, for example, it can be 10°, 20°, 30°, 40°, 50°, 60°, 70° or 80°, but is not limited to the listed values. Other unlisted values ​​within this range are also applicable.

[0023] This invention selectively chemically modifies the substrate, enabling continuous adjustment of melt wettability, thereby achieving effective control of the width of the single-crystal array, suppressing cross-contamination between adjacent array liquid bridges, and ensuring the uniformity of the multi-component single-crystal array.

[0024] As a preferred embodiment of the present invention, the glass transition temperature of the first powder is lower than its thermal decomposition temperature, and the glass transition temperature of the second powder is lower than its thermal decomposition temperature.

[0025] The glass transition temperatures of both the first powder and the second powder are lower than the melting point of the substrate, and the glass transition temperatures of both the first powder and the second powder are lower than the melting point of the silicon ingot template.

[0026] As a preferred embodiment of the present invention, the first heating process includes: first heating to a first temperature to melt the first powder, then holding the temperature for a second time, and continuously applying pressure to spread the molten first powder to cover the top surface of the first silicon pillar.

[0027] The secondary heating process includes: first heating the material to a second temperature to melt the second powder, then holding it at the temperature for a second time, and continuously applying pressure to spread the molten second powder to cover the top surface of the second silicon pillar.

[0028] In one embodiment of the present invention, both the primary cooling and the secondary cooling include sequentially performing a first-stage cooling and a second-stage cooling, and the cooling rate of the first-stage cooling is less than the cooling rate of the second-stage cooling.

[0029] As a preferred embodiment of the present invention, the heating rates of the first heating and the second heating are independently 1~20℃ / min, for example, they can be 1℃ / min, 2℃ / min, 3℃ / min, 5℃ / min, 8℃ / min, 10℃ / min, 12℃ / min, 15℃ / min, 16℃ / min, 18℃ / min or 20℃ / min, but are not limited to the listed values, and other unlisted values ​​within this range are also applicable.

[0030] In one embodiment of the present invention, the first temperature is greater than the glass transition temperature of the first powder and less than the thermal decomposition temperature of the first powder. The second temperature is greater than the glass transition temperature of the second powder and less than the thermal decomposition temperature of the second powder, and also less than the glass transition temperature of the first powder.

[0031] As one embodiment of the present invention, the time for the first heat preservation and the second heat preservation are each independently 5 to 60 minutes, for example, 5 minutes, 10 minutes, 15 minutes, 20 minutes, 25 minutes, 30 minutes, 35 minutes, 40 minutes, 45 minutes, 50 minutes, 56 minutes or 60 minutes, but are not limited to the listed values, and other unlisted values ​​within this range are also applicable.

[0032] As one embodiment of the present invention, the cooling rate of the cooling segment is 0.1~1.0℃ / min, for example, it can be 0.1℃ / min, 0.2℃ / min, 0.3℃ / min, 0.4℃ / min, 0.5℃ / min, 0.6℃ / min, 0.7℃ / min, 0.8℃ / min, 0.9℃ / min or 1.0℃ / min, but it is not limited to the listed values. Other unlisted values ​​within this range are also applicable.

[0033] The cooling rate of the two-stage cooling is 1~10℃ / min, for example, it can be 1℃ / min, 2℃ / min, 3℃ / min, 4℃ / min, 5℃ / min, 6℃ / min, 7℃ / min, 8℃ / min, 9℃ / min or 10℃ / min, but it is not limited to the listed values. Other unlisted values ​​within this range are also applicable.

[0034] This invention regulates the crystallization process of the melt by precisely controlling the heating, holding time, and cooling rate, ensuring that the melt spreads evenly and directionally on the surface of the silicon pillar, thus effectively improving the density of the single crystal array.

[0035] As a preferred technical solution of the present invention, the thickness of the lateral heterojunction single crystal array is adjusted by adjusting the applied pressure during the pressure application process.

[0036] In one embodiment of the present invention, during the pressure application process, the distance between the first silicon pillar and the second silicon pillar and the substrate is less than or equal to 1000 nm.

[0037] Secondly, the present invention provides a multi-component lateral heterogeneous single-crystal array based on a melting method. The multi-component lateral heterogeneous single-crystal array is prepared using the melting method described in the first aspect. The multi-component lateral heterogeneous single-crystal array includes a substrate, on which a first micrometer-line single-crystal array and a second micrometer-line single-crystal array are disposed. The first micrometer-line single-crystal array includes a plurality of first micrometer-line single crystals, and the second micrometer-line single-crystal array includes a plurality of second micrometer-line single crystals. The first micrometer-line single crystals and the second micrometer-line single crystals are alternately arranged along a first direction. The glass transition temperature of the first micrometer-line single crystal is higher than that of the second micrometer-line single crystal.

[0038] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0039] (1) The process of the present invention is simple. It uses different silicon pillar arrays with alternating intervals. Based on the melting method, the multi-component organic semiconductor melt is oriented and spread by capillary liquid bridge. It can obtain a high-density, uniform-size, and highly crystalline multi-component organic semiconductor single crystal array without complicated alignment process.

[0040] (2) Based on the difference in melting point of different semiconductor materials, the present invention realizes the monolithic integration of multi-component semiconductor single crystal arrays through melting process, which solves the problem of patterned preparation of low-solubility organic semiconductor single crystals. Compared with the traditional liquid phase processing method, it has a wider range of applications and the process operation is simple, realizing a low-harm preparation process.

[0041] (3) The preparation method provided by the present invention does not require the introduction of liquid solvent, which eliminates the adverse effects of solvent molecules on crystallization, effectively improves the crystallization quality, reduces the defect density of crystals, and avoids environmental pollution, thereby improving the economic and environmental benefits of the process.

[0042] (4) This invention has high precision, strong controllability and universality. It can complete the integration of multi-component materials in one step, providing a new strategy for flexible optoelectronic systems. It is applicable to cutting-edge devices such as three-color lasers, organic PN logic circuits, light-emitting displays and on-chip photonic integration, and has important scientific value and industrial prospects. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the structure of the silicon pillar template and substrate provided in Embodiment 1 of the present invention.

[0044] Figure 2 A fluorescence microscope image of a lateral heterogeneous single-crystal array provided in Embodiment 1 of the present invention.

[0045] Figure 3 This is a schematic diagram of the micro-area fluorescence spectrum of the lateral heterogeneous single crystal array provided in Embodiment 1 of the present invention.

[0046] Figure 4 The XRD pattern of the lateral heterogeneous single crystal array provided in Embodiment 1 of the present invention.

[0047] Figure 5 The SAED spectrum of the lateral heterogeneous single crystal array provided in Embodiment 1 of the present invention.

[0048] Figure 6 This is a fluorescence microscope image of a lateral heterogeneous single-crystal array provided in Embodiment 2 of the present invention.

[0049] Figure 7 This is a fluorescence microscope image of a lateral heterogeneous single-crystal array provided in Embodiment 3 of the present invention.

[0050] Figure 8 This is a schematic diagram of the structure of the OFET device provided in Embodiment 3 of the present invention.

[0051] Figure 9 This is a schematic diagram of the transfer curve of the OFET device provided in Embodiment 3 of the present invention.

[0052] Figure 10 This is a schematic diagram of the complementary logic device provided in Embodiment 4 of the present invention.

[0053] Figure 11a The output curve of the complementary logic device provided in Embodiment 4 of the present invention.

[0054] Figure 11b The gain curve of the complementary logic device provided in Embodiment 4 of the present invention.

[0055] Figure 12 This is a fluorescence microscope image of a lateral heterogeneous single-crystal array provided in Embodiment 5 of the present invention.

[0056] Figure 13This is a fluorescence microscope image of a lateral heterogeneous single-crystal array provided in Embodiment 6 of the present invention.

[0057] Figure 14 This is a schematic diagram of the first and second injection through holes on the substrate surface provided in Embodiment 9 of the present invention.

[0058] Figure 15 This is a schematic diagram of the first and second injection through holes on the substrate surface provided in Embodiment 10 of the present invention.

[0059] Figure 16 This is a schematic diagram of the first and second injection through holes on the substrate surface provided in Embodiment 11 of the present invention.

[0060] Wherein, 1-silicon pillar template; 12-first silicon pillar array; 13-second silicon pillar array; 121-first silicon pillar; 131-second silicon pillar; 2-substrate; 21-substrate body; 22-first injection via; 23-second injection via. Detailed Implementation

[0061] It should be understood that in the description of this invention, the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0062] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0063] In one specific embodiment, the present invention provides a method for preparing a multi-component lateral heterogeneous single crystal array based on a melting method, comprising the following steps.

[0064] S1: Provide a silicon pillar template and a substrate. The silicon pillar template is provided with at least a plurality of first silicon pillars and a plurality of second silicon pillars. The first silicon pillars and the second silicon pillars are arranged alternately and at intervals along a first direction. The substrate is provided with at least a plurality of first injection through holes and a plurality of second injection through holes. The first injection through holes and the second injection through holes are arranged alternately and at intervals along a first direction at the same end of the substrate.

[0065] In this invention, the first direction is the extension direction of the silicon pillar template, and the substrate corresponds to the silicon pillar template, with the extension direction of the substrate being the same as that of the silicon pillar template. In this invention, several first silicon pillars extend independently along a direction perpendicular to the first direction and together form a first silicon pillar array, and several second silicon pillars extend independently along a direction perpendicular to the first direction and together form a second silicon pillar array.

[0066] Specifically, in this invention, the silicon pillar template, the first silicon pillar, and the second silicon pillar all have rectangular cross-sections. Depending on the desired structure of the single crystal array, the first silicon pillar and the second silicon pillar can be spaced apart along the long side of the silicon pillar template and extend along the short side of the silicon pillar template; alternatively, the first silicon pillar and the second silicon pillar can be spaced apart along the short side of the silicon pillar template and extend along both the short and long sides of the silicon pillar template. This invention does not impose any specific limitations on these aspects.

[0067] In the first silicon pillar array, the linear length of the first silicon pillar in the first direction is 1~100000 μm. In the second silicon pillar array, the linear length of the second silicon pillar in the first direction is 1~100 μm. The linear length in the first direction is the straight-line distance connecting the two edges of the first (or second) silicon pillar in the first direction, and usually refers to the width of the first or second silicon pillar. Simultaneously, the spacing between the first and second silicon pillars is 1~100 μm.

[0068] The silicon pillar template described in this invention is prepared by photolithography and plasma etching. The preparation steps include sequential spin-coating of photoresist, pre-baking, exposure, development, rinsing, post-baking, plasma etching, and photoresist removal. This invention does not specifically limit the operation steps and process parameters of the above processes.

[0069] In some embodiments, the preparation method of the present invention further includes: performing an asymmetric wetting treatment on the provided silicon pillar template, such that the top surfaces of the first silicon pillar and the second silicon pillar are hydrophilic, while the sidewall surfaces are hydrophobic. The asymmetric wetting treatment is a wetting process based on the differences in the physical properties of different semiconductor systems, resulting in different regions of the first or second silicon pillar having the same or different wettability, thereby controlling the width of the formed melt to obtain a single-crystal array structure with controllable dimensions and precise positioning. Specifically, the contact angle of the top surfaces of the first and second silicon pillars is 5°~10°, and the contact angle of the sidewall surfaces is 80°~100°.

[0070] In this invention, the top surfaces of the first and second silicon pillars near the substrate are hydrophilic, which facilitates the directional flow of the melt along the silicon pillars until it covers the entire surface. Conversely, the sidewall surfaces of the first and second silicon pillars are hydrophobic, preventing lateral diffusion of the melt and thus avoiding uncontrollable changes in the melt's size and morphology, while also reducing cross-contamination. It should be noted that the sidewall surfaces mentioned in this invention refer to surfaces other than the top surfaces of the first or second silicon pillars near the substrate and the surfaces near the silicon pillar template, specifically including the opposing walls of the first and second silicon pillars.

[0071] The substrate described in this invention includes a substrate body, and the first injection via and the second injection via are formed in the substrate body. The substrate material includes at least one of glass, quartz, silicon, or silicon with a deposited silicon oxide layer.

[0072] When the multi-component lateral heterogeneous single-crystal array of the present invention is used for thin-film transistors, at least one coating layer can be formed on the surface of the substrate, including but not limited to gold, silver, aluminum, silicon oxide, hafnium oxide and aluminum oxide.

[0073] In some embodiments, the present invention ensures that the first filling through hole and the second filling through hole are located at the same end of the substrate, and that the first filling through hole and the second filling through hole are arranged side by side, or that the orthographic projection of the first filling through hole on the vertical plane does not coincide with the orthographic projection of the second filling through hole on the vertical plane, or that at least a portion of the orthographic projection of the first filling through hole on the vertical plane coincides with the orthographic projection of the second filling through hole on the vertical plane, so as to achieve high-density openings.

[0074] When the orthographic projection of the first filling through hole on the vertical plane does not coincide with the orthographic projection of the second filling through hole on the vertical plane, the first filling through hole can be set closer to the edge of the substrate, that is, the second filling through hole is set further forward than the first filling through hole.

[0075] The diameter of the first filling via is smaller than the first length, which is the sum of the linear length of the first silicon pillar in the first direction and the distance between the first and second silicon pillars. The diameter of the second filling via is smaller than the second length, which is the sum of the linear length of the second silicon pillar in the first direction and the distance between the first and second silicon pillars.

[0076] In some embodiments, the preparation method of the present invention further includes: selectively chemically modifying the provided substrate to adjust the wettability of the melt of the first powder and the second powder on the substrate surface, so as to obtain a first micron-line single crystal array and a second micron-line single crystal array with different widths.

[0077] During the melting process, the melt spreads on the top surface of the silicon pillar under the combined drive of Laplace pressure and hydrostatic pressure, and the spreading direction of the melt dynamically changes as the melting process progresses. To precisely control the directional transport of the melt, this invention requires regulation of the wetting properties of the melt. The selective chemical modification is based on the differences in the physical properties of different component melts, modifying the substrate to make the melt exhibit different wetting characteristics on the substrate surface. These wetting characteristics include, but are not limited to, the static contact angle, advance angle, and retreat angle of the melt surface. Furthermore, the contact angle of the melt can be continuously adjusted by controlling the selective chemical modification time. Specifically, the contact angle between the melt of the first powder and the melt of the second powder on the substrate surface is 10°~80°.

[0078] S2: Place the substrate above the first silicon pillar and the second silicon pillar, such that the first injection via corresponds to the first silicon pillar and the second injection via corresponds to the second silicon pillar. Then apply pressure to bring the substrate close to the first silicon pillar and the second silicon pillar.

[0079] After placing the substrate above the silicon pillar template, the first injection via is located directly above the end of the first silicon pillar, and the second injection via is located directly above the end of the second silicon pillar. The first and second silicon pillars have a first end and a second end along their extension direction. The first injection via can correspond to either the first or second end of the first silicon pillar, and the second injection via can correspond to either the first or second end of the second silicon pillar, ensuring that the first and second injection vias are at the same end.

[0080] S3: After adding the first powder to the first filling through-hole, a heating treatment is performed to melt the first powder and spread it along the surface of the first silicon pillar. Then, a cooling treatment is performed to form a first micron-line single crystal array in the gap between the first silicon pillar and the substrate. After adding the second powder to the second filling through-hole, a second heating treatment is performed to melt the second powder and spread it along the surface of the second silicon pillar. Then, a second cooling treatment is performed to form a second micron-line single crystal array in the gap between the second silicon pillar and the substrate. Subsequently, the silicon pillar template is removed to obtain a lateral heterogeneous single crystal array.

[0081] In this invention, the glass transition temperature of the first powder is greater than that of the second powder. Simultaneously, the glass transition temperature of the first powder is lower than its own thermal decomposition temperature, and also lower than the melting point of the silicon ingot template and the substrate; similarly, the glass transition temperature of the second powder is lower than its own thermal decomposition temperature, and also lower than the melting point of the silicon ingot template and the substrate.

[0082] Specifically, the first powder and the second powder include, but are not limited to, at least one of C8-BTBT, C10-BTBT, DPA, C6-DPA, DNTT, C10-DNTT, C8-NTDA, PDI8-CN2 and DFHCO-4T, to ensure that the glass transition temperature of the first powder is greater than that of the second powder.

[0083] In some embodiments, the primary heating process includes: first heating to a first temperature to melt the first powder, then holding the temperature for a second time, and continuously applying pressure to spread the molten first powder all over the top surface of the first silicon pillar. The secondary heating process includes: first heating to a second temperature to melt the second powder, then holding the temperature for a second time, and continuously applying pressure to spread the molten second powder all over the top surface of the second silicon pillar.

[0084] Specifically, the heating rate for the first heating is 1~20℃ / min, and the holding time for the first heating is 5~60min; the heating rate for the second heating is 1~20℃ / min, and the holding time for the second heating is 5~60min. The heating rates for the first and second heating can be the same or different. Similarly, the holding times for the first and second heating can be the same or different. The first temperature range ensures that the first powder is fully melted, but is below the thermal decomposition temperature of the first powder. Similarly, the second temperature range ensures that the second powder is fully melted, but is below the thermal decomposition temperature of the second powder. In addition, both the first and second temperatures are lower than the melting points of the silicon ingot template and the substrate.

[0085] The duration of the first and second heat preservation is 5-60 minutes each.

[0086] In some embodiments, the present invention adjusts the applied pressure during the pressurization process to regulate the height of the molten bridge formed on the surface of the first or second silicon pillar, thereby achieving thickness adjustment of the lateral heterojunction array. Since the single-crystal array is formed between the first or second silicon pillar and the substrate, by regulating the applied pressure, the distance between the surface of the first or second silicon pillar and the substrate can be controlled, thereby obtaining a product of the desired thickness.

[0087] Furthermore, both the primary cooling and the secondary cooling include sequentially performing a first-stage cooling and a second-stage cooling, and the cooling rate of the first-stage cooling is less than the cooling rate of the second-stage cooling.

[0088] Specifically, the cooling rate of the first stage of cooling is 0.1~1℃ / min, and the cooling rate of the second stage of cooling is 1~10℃ / min.

[0089] Furthermore, the types of silicon pillars on the silicon pillar template in this invention are not limited to two; they can be three, four, five, etc., to obtain single-crystal arrays with multiple different semiconductor systems. Those skilled in the art can adapt the array composition according to actual needs. Taking three types of silicon pillars on the silicon pillar template as an example, denoted as the first, second, and third silicon pillars, they are arranged alternately on the surface of the silicon pillar template according to the above-mentioned arrangement. By adjusting the morphology, size, and spacing of the first, second, and third silicon pillars, the desired multi-component patterned single-crystal array can be obtained. Simultaneously, a first, second, and third injection via are formed on the substrate, arranged at the same end of the substrate according to the above-mentioned arrangement, and alternately spaced. The first injection via corresponds one-to-one with the first silicon pillar, the second injection via corresponds one-to-one with the second silicon pillar, and the third injection via corresponds one-to-one with the third silicon pillar. This invention provides three different semiconductor systems—first powder, second powder, and third powder—and can obtain a lateral heterogeneous single-crystal array structure with three components based on a melting method.

[0090] In another specific embodiment, the present invention provides a multi-component lateral heterogeneous single crystal array based on a melting method. The multi-component lateral heterogeneous single crystal array is prepared by the melting method described in a specific embodiment, including a substrate. A first micrometer-line single crystal array and a second micrometer-line single crystal array are disposed on the substrate. The first micrometer-line single crystal array includes a plurality of first micrometer-line single crystals, and the second micrometer-line single crystal array includes a plurality of second micrometer-line single crystals. The first micrometer-line single crystals and the second micrometer-line single crystals are alternately arranged along a first direction. The glass transition temperature of the first micrometer-line single crystal is higher than that of the second micrometer-line single crystal.

[0091] In this invention, the shape of the multi-component lateral heterogeneous single crystal array is the same as the shape of the silicon pillar array on the silicon pillar template. The first single-micron line single crystal and the second single-micron line single crystal have different semiconductor system compositions, and the first micron line single crystal array corresponds to the first silicon pillar array, and the second micron line single crystal array corresponds to the second silicon pillar array.

[0092] Example 1

[0093] This embodiment provides a method for fabricating a multi-component lateral heterojunction single-crystal array based on a melting method, specifically including the following steps:

[0094] (1) Preparation of silicon pillar template 1. After spin-coating photoresist, pre-baking, exposure, development, rinsing, post-baking, plasma etching and photoresist removal on silicon pillar template 1, a silicon pillar template 1 is formed as shown in the figure. Figure 1The diagram shows a first silicon pillar array 12 and a second silicon pillar array 13. The first silicon pillar array 12 includes a plurality of first silicon pillars 121 arranged sequentially along a first direction, and the second silicon pillar array 13 includes a plurality of second silicon pillars 131 arranged sequentially along the first direction, with the first silicon pillars 121 and second silicon pillars 131 alternating at intervals. The silicon pillar template 1, the first silicon pillars 121, and the second silicon pillars 131 all have a cuboid structure, with the first direction being the extension direction of the silicon pillar template 1, i.e., its length direction. The first silicon pillars 121 and the second silicon pillars 131 extend independently along the width direction of the silicon pillar template 1. The first silicon pillars 121 and the second silicon pillars 131 have the same height, and their linear length along the first direction, i.e., their width, is 2 μm. The distance between the first silicon pillars 121 and the second silicon pillars 131 is 2 μm.

[0095] (2) The silicon pillar template 1 is subjected to asymmetric wetting treatment, so that the top surfaces of the first silicon pillar 121 and the second silicon pillar 131 are hydrophilic, while the sidewall surfaces are hydrophobic.

[0096] (3) Provide substrate 2, such as Figure 1 As shown, it includes a quartz substrate 21, on which multiple first filling through holes 22 and multiple second filling through holes 23 are formed. The first filling through holes 22 and the second filling through holes 23 are alternately and alternately arranged at the same end of the substrate 21, and are arranged side by side. Both the first filling through holes 22 and the second filling through holes 23 are circular through holes with a diameter of 3μm, and penetrate through the substrate 21.

[0097] (4) Place the substrate 2 above the silicon pillar template 1, so that the first injection via 22 corresponds one-to-one with the first silicon pillar 121 and is located directly above the first silicon pillar 121. At the same time, the second injection via 23 corresponds one-to-one with the second silicon pillar 131 and is located directly above the second silicon pillar 131. Then apply pressure to bring the substrate body 21 close to the first silicon pillar 121 and the second silicon pillar 131 until the distance between the top surface of the first silicon pillar 121 and the second silicon pillar 131 and the substrate body 21 is less than or equal to 100nm.

[0098] (5) Provide a first powder PDI8-CN2 and a second powder C8-BTBT, wherein the glass transition temperature of the first powder is higher than that of the second powder.

[0099] The molecular structure of PDI8-CN2 is as follows: .

[0100] The molecular structure of C8-BTBT is as follows: .

[0101] (6) After adding the first powder PDI8-CN2 to the first filling through hole 22, the temperature is raised to 280°C at a heating rate of 20°C / min, and then kept at the temperature for 10 min. The pressure is continuously applied to melt the first powder and spread it along the top surface of the first silicon pillar 121. Then, the temperature is slowly lowered at a cooling rate of 1°C / min until the glass transition temperature of the first powder is reached. Then, the temperature is rapidly lowered at a cooling rate of 10°C / min until the room temperature is reached. The first single crystal silicon pillar is formed between the first silicon pillar 121 and the substrate 2 to obtain the first micron-line single crystal array.

[0102] (7) After adding the second powder C8-BTBT to the second filling through hole 23, the temperature is raised to 110°C at a heating rate of 20°C / min, and then kept at the temperature for 5 min. The pressure is continuously applied to melt the second powder and spread it along the top surface of the second silicon pillar 131. Then the temperature is slowly lowered at a cooling rate of 1°C / min until the glass transition temperature of the second powder is reached. Then the temperature is rapidly lowered at a cooling rate of 10°C / min until the room temperature is reached. The second single crystal silicon pillar is formed between the second silicon pillar 131 and the substrate 2 to obtain the second micron-line single crystal array.

[0103] (8) Then the silicon pillar template 1 was removed to obtain a regularly arranged horizontal heterogeneous single crystal array.

[0104] In this embodiment, the shape of the lateral heterojunction single-crystal array is the same as the shape of the silicon pillar array, such as... Figure 2 As shown in the fluorescence microscopy images, under ultraviolet excitation, blue and red fluorescent micrometer lines alternately arrange, indicating that a lateral heterogeneous multi-component organic semiconductor structure has been successfully constructed. Micro-area photoluminescence tests conducted in the micrometer line region between adjacent C8-BTBT and PDI8-CN2 micrometer lines revealed the following... Figure 3 The characteristic emission peaks of the C8-BTBT crystal (467 nm) and the PDI8-CN2 crystal (672 nm) are shown. Figure 4 As shown, the XRD pattern of the lateral heterojunction array also shows characteristic diffraction peaks of both crystals simultaneously. This invention further investigated the crystal properties and orientation of the multicomponent structure using transmission electron microscopy and selected area electron diffraction. No grain boundaries were observed in the TEM images of either material, indicating good single-crystal characteristics. Figure 5 As shown, the diffraction spots in the SAED pattern are sharp. The diffraction spots of the C8-BTBT crystal can be assigned to the

[001] and

[010] zone axes, and the diffraction spots of the PDI8-CN2 crystal can be assigned to the

[001] and

[010] zone axes, indicating that both crystals preferentially grow along the

[001] direction and have excellent crystal quality.

[0105] Example 2

[0106] This embodiment provides a method for fabricating a multi-component lateral heterojunction single-crystal array based on a melting method, specifically including the following steps:

[0107] (1) Preparation of silicon pillar template 1. After spin-coating photoresist, pre-baking, exposure, development, rinsing, post-baking, plasma etching and photoresist removal on silicon pillar template 1, a first silicon pillar array 12 and a second silicon pillar array 13 are formed on silicon pillar template 1. The first silicon pillar array 12 includes a plurality of first silicon pillars 121 arranged sequentially along a first direction, and the second silicon pillar array 13 includes a plurality of second silicon pillars 131 arranged sequentially along the first direction, with the first silicon pillars 121 and the second silicon pillars 131 alternately spaced. Silicon pillar template 1, first silicon pillars 121 and second silicon pillars 131 all have a cuboid structure, and the first direction is the extension direction of silicon pillar template 1, that is, its length direction. First silicon pillars 121 and second silicon pillars 131 extend independently along the width direction of silicon pillar template 1. The first silicon pillar 121 and the second silicon pillar 131 have the same height, and their linear length along the first direction, i.e., their width, is 2μm. The distance between the first silicon pillar 121 and the second silicon pillar 131 is 6μm.

[0108] (2) The silicon pillar template 1 is subjected to asymmetric wetting treatment, so that the top surfaces of the first silicon pillar 121 and the second silicon pillar 131 are hydrophilic, while the sidewall surfaces are hydrophobic.

[0109] (3) A substrate 2 is provided, which includes a substrate body 21 made of quartz material. The substrate body 21 has a plurality of first filling through holes 22 and a plurality of second filling through holes 23. The first filling through holes 22 and the second filling through holes 23 are alternately arranged at intervals along a first direction at the same end of the substrate body 21 and are arranged side by side. The first filling through holes 22 and the plurality of second filling through holes 23 are all circular through holes with a diameter of 3μm and penetrate the substrate body 21.

[0110] (4) Place the substrate 2 above the silicon pillar template 1, so that the first injection via 22 corresponds one-to-one with the first silicon pillar 121 and is located directly above the first silicon pillar 121. At the same time, the second injection via 23 corresponds one-to-one with the second silicon pillar 131 and is located directly above the second silicon pillar 131. Then apply pressure to bring the substrate body 21 close to the first silicon pillar 121 and the second silicon pillar 131 until the distance between the top surface of the first silicon pillar 121 and the second silicon pillar 131 and the substrate body 21 is less than or equal to 100nm.

[0111] (5) Provide a first powder 5,6,11,12-tetraphenyltetraphenyl and a second powder Y6, wherein the glass transition temperature of the first powder is higher than that of the second powder.

[0112] The molecular structure of 5,6,11,12-tetraphenyltetraphenyl is as follows: .

[0113] The molecular structure of Y6 is .

[0114] (6) After adding the first powder to the first filling through hole 22, the temperature is raised to 335°C at a heating rate of 20°C / min, and then kept at the temperature for 20 min. The pressure is continuously applied to melt the first powder and spread it along the top surface of the first silicon pillar 121. Then, the temperature is slowly lowered at a cooling rate of 1°C / min until the glass transition temperature of the first powder is reached. Then, the temperature is rapidly lowered at a cooling rate of 10°C / min until the room temperature is reached. The first single crystal silicon pillar is formed between the first silicon pillar 121 and the substrate 2 to obtain the first micron-line single crystal array.

[0115] (7) After adding the second powder to the second filling through hole 23, the temperature is raised to 300°C at a heating rate of 20°C / min, and then kept at the temperature for 20 min. The pressure is continuously applied to melt the second powder and spread it along the top surface of the second silicon pillar 131. Then the temperature is slowly lowered at a cooling rate of 1°C / min until the glass transition temperature of the second powder is reached. Then the temperature is rapidly lowered at a cooling rate of 10°C / min until the room temperature is reached. The second single crystal silicon pillar is formed between the second silicon pillar 131 and the substrate 2 to obtain the second micron-line single crystal array.

[0116] (8) Then the silicon pillar template 1 was removed to obtain a regularly arranged horizontal heterogeneous single crystal array.

[0117] In this embodiment, the shape of the lateral heterojunction single-crystal array is the same as the shape of the silicon pillar array, such as... Figure 6 As shown in the fluorescence microscope images, under ultraviolet excitation, blue and red fluorescent micrometer lines are arranged alternately, indicating that the multi-component organic semiconductor structure has been successfully constructed.

[0118] Example 3

[0119] This embodiment provides a method for fabricating a multi-component lateral heterojunction single-crystal array based on a melting method, specifically including the following steps:

[0120] (1) Preparation of silicon pillar template 1. After spin-coating photoresist, pre-baking, exposure, development, rinsing, post-baking, plasma etching and photoresist removal on silicon pillar template 1, a first silicon pillar array 12 and a second silicon pillar array 13 are formed on silicon pillar template 1. The first silicon pillar array 12 includes a plurality of first silicon pillars 121 arranged sequentially along a first direction, and the second silicon pillar array 13 includes a plurality of second silicon pillars 131 arranged sequentially along the first direction, with the first silicon pillars 121 and the second silicon pillars 131 alternately spaced. Silicon pillar template 1, first silicon pillars 121 and second silicon pillars 131 all have a cuboid structure, and the first direction is the extension direction of silicon pillar template 1, that is, its length direction. First silicon pillars 121 and second silicon pillars 131 extend independently along the width direction of silicon pillar template 1. The first silicon pillar 121 and the second silicon pillar 131 have the same height, and their linear length along the first direction, i.e., their width, is 2μm. The distance between the first silicon pillar 121 and the second silicon pillar 131 is 6μm.

[0121] (2) The silicon pillar template 1 is subjected to asymmetric wetting treatment, so that the top surfaces of the first silicon pillar 121 and the second silicon pillar 131 are hydrophilic, while the sidewall surfaces are hydrophobic.

[0122] (3) A substrate 2 is provided, comprising a quartz substrate body 21. The substrate body 21 has multiple first filling through-holes 22 and multiple second filling through-holes 23, which are alternately and sequentially arranged at the same end of the substrate body 21 along a first direction, and are arranged side-by-side. The first filling through-holes 22 and the multiple second filling through-holes 23 are all circular through-holes with a diameter of 3 μm, penetrating the substrate body 21. The surface of the substrate 2 is covered with a SiO2 coating.

[0123] (4) Place the substrate 2 above the silicon pillar template 1, so that the first injection via 22 corresponds one-to-one with the first silicon pillar 121 and is located directly above the first silicon pillar 121. At the same time, the second injection via 23 corresponds one-to-one with the second silicon pillar 131 and is located directly above the second silicon pillar 131. Then apply pressure to bring the substrate body 21 close to the first silicon pillar 121 and the second silicon pillar 131 until the distance between the top surface of the first silicon pillar 121 and the second silicon pillar 131 and the substrate body 21 is less than or equal to 100nm.

[0124] (5) Provide a first powder C10-DNTT and a second powder C8-NTDA, wherein the glass transition temperature of the first powder is higher than that of the second powder.

[0125] The molecular structure of C10-DNTT is as follows: .

[0126] The molecular structure of C8-NTDA is as follows: .

[0127] (6) After adding the first powder C10-DNTT to the first filling through hole 22, the temperature is raised to 225°C at a heating rate of 20°C / min, and then kept at the temperature for 20 min. The pressure is continuously applied to melt the first powder and spread it along the top surface of the first silicon pillar 121. Then, the temperature is slowly lowered at a cooling rate of 1°C / min until the glass transition temperature of the first powder is reached. Then, the temperature is rapidly lowered at a cooling rate of 10°C / min until the room temperature is reached. The first single crystal silicon pillar is formed between the first silicon pillar 121 and the substrate 2 to obtain the first micron-line single crystal array.

[0128] (7) After adding the second powder C8-NTDA to the second filling through hole 23, the temperature is raised to 190°C at a heating rate of 20°C / min, and then kept at the temperature for 20 min. The pressure is continuously applied to melt the second powder and spread it along the top surface of the second silicon pillar 131. Then, the temperature is slowly lowered at a cooling rate of 1°C / min until the glass transition temperature of the second powder is reached. Then, the temperature is rapidly lowered at a cooling rate of 10°C / min until the room temperature is reached. The second single crystal silicon pillar is formed between the second silicon pillar 131 and the substrate 2 to obtain the second micron-line single crystal array.

[0129] (8) Then the silicon pillar template 1 was removed to obtain a regularly arranged horizontal heterogeneous single crystal array.

[0130] In this embodiment, the shape of the lateral heterojunction single-crystal array is the same as the shape of the silicon pillar array, such as... Figure 7 As shown in the fluorescence microscope images, under ultraviolet excitation, blue and red fluorescent micrometer lines are arranged alternately, indicating that the multi-component organic semiconductor structure has been successfully constructed.

[0131] In this embodiment, a 5nm Cr coating and a 30nm Au coating were deposited on the surface of a lateral heterogeneous single-crystal array using a metal perforated mask, and then integrated onto a substrate such as... Figure 8 On the same substrate 2, P-type and N-type OFET devices are shown, and the following results are obtained: Figure 9 The graph shows the transfer curves of P-type and N-type OFET devices (the horizontal axis represents the gate voltage, and the vertical axis represents the absolute values ​​of the source and drain currents). An OFET device consists of a stacked gate and dielectric layer. Several sets of drain and source electrodes are disposed on the dielectric layer, with a P-type or N-type organic semiconductor single crystal placed between the drain and source electrodes. The gate is P++Si (heavily doped polycrystalline silicon), the dielectric layer is SiO2, and the first and second micrometer-line single crystal arrays serve as P-type and N-type micrometer-line arrays, respectively.

[0132] Example 4

[0133] This embodiment provides a method for preparing a multi-component lateral heterogeneous single crystal array based on the melting method. The difference from Embodiment 3 is that the substrate 21 is made of silicon wafer and the surface of the substrate 21 is covered with a 30nm HfO2 coating. The remaining steps are the same as in Embodiment 3.

[0134] In this embodiment, the shape of the lateral heterojunction single crystal array is the same as that of the silicon pillar array.

[0135] In this embodiment, a 5nm Cr coating and a 30nm Au coating were deposited on a lateral heterogeneous single-crystal array using a metal cutout mask, and then integrated onto a substrate such as... Figure 10 On the same substrate 2, P-type and N-type complementary logic devices are shown, and the following is obtained: Figure 11a The output curves of the complementary logic devices shown (where the horizontal axis represents input voltage and the vertical axis represents output voltage) are similar to those of the input voltage curves. Figure 11b The gain curve of the complementary logic device is shown below (the horizontal axis represents input voltage, and the vertical axis represents gain). The complementary logic device includes a Vin substrate and a dielectric layer stacked together. Several sets of Vss-Vout-Vdd structures are disposed on the dielectric layer, with a P-type organic semiconductor single crystal disposed between Vss and Vout, and an N-type organic semiconductor single crystal disposed between Vout and Vdd. The Vin substrate is P++Si (heavily doped polycrystalline silicon), the dielectric layer is HfO2, and the first single-crystal silicon pillar and the second micrometer-line single-crystal array serve as the P-type micrometer-line array and the N-type micrometer-line array, respectively.

[0136] Example 5

[0137] This embodiment provides a method for fabricating a multi-component lateral heterojunction single-crystal array based on a melting method, specifically including the following steps:

[0138] (1) Preparation of silicon pillar template 1. After spin-coating photoresist, pre-baking, exposure, development, rinsing, post-baking, plasma etching and photoresist removal on silicon pillar template 1, a first silicon pillar array 12 and a second silicon pillar array 13 are formed on silicon pillar template 1. The first silicon pillar array 12 includes a plurality of first silicon pillars 121 arranged sequentially along a first direction, and the second silicon pillar array 13 includes a plurality of second silicon pillars 131 arranged sequentially along the first direction, with the first silicon pillars 121 and the second silicon pillars 131 alternately spaced. Silicon pillar template 1, first silicon pillars 121 and second silicon pillars 131 all have a cuboid structure, and the first direction is the extension direction of silicon pillar template 1, that is, its length direction. First silicon pillars 121 and second silicon pillars 131 extend independently along the width direction of silicon pillar template 1. First silicon pillars 121 and second silicon pillars 131 have the same height, and their linear length along the first direction, that is, their width, is 2 μm. The distance between first silicon pillars 121 and second silicon pillars 131 is 6 μm.

[0139] (2) The silicon pillar template 1 is subjected to asymmetric wetting treatment, so that the top surfaces of the first silicon pillar 121 and the second silicon pillar 131 are hydrophilic, while the sidewall surfaces are hydrophobic.

[0140] (3) A substrate 2 is provided, which includes a substrate body 21 made of silicon oxide. The substrate body 21 has a plurality of first filling through holes 22 and a plurality of second filling through holes 23. The first filling through holes 22 and the second filling through holes 23 are alternately arranged at the same end of the substrate body 21 along a first direction and are arranged side by side. The first filling through holes 22 and the plurality of second filling through holes 23 are all circular through holes with a diameter of 3μm and penetrate the substrate body 21.

[0141] (4) Place the substrate 2 above the silicon pillar template 1, so that the first injection via 22 corresponds one-to-one with the first silicon pillar 121 and is located directly above the first silicon pillar 121. At the same time, the second injection via 23 corresponds one-to-one with the second silicon pillar 131 and is located directly above the second silicon pillar 131. Then apply pressure to bring the substrate body 21 close to the first silicon pillar 121 and the second silicon pillar 131 until the distance between the top surface of the first silicon pillar 121 and the second silicon pillar 131 and the substrate body 21 is less than or equal to 100nm.

[0142] (5) Provide a first powder C6-DPA and a second powder DFHCO-4T, wherein the glass transition temperature of the first powder is higher than that of the second powder.

[0143] The molecular structure of C6-DPA is as follows: .

[0144] The molecular structure of DFHCO-4T is .

[0145] (6) After adding the first powder C6-DPA to the first filling through hole 22, the temperature is raised to 255°C at a heating rate of 20°C / min, and then kept at the temperature for 20 min. The pressure is continuously applied to melt the first powder and spread it along the top surface of the first silicon pillar 121. Then, the temperature is slowly lowered at a cooling rate of 1°C / min until the glass transition temperature of the first powder is reached. Then, the temperature is rapidly lowered at a cooling rate of 10°C / min until the room temperature is reached. The first single crystal silicon pillar is formed between the first silicon pillar 121 and the substrate 2 to obtain the first micron-line single crystal array.

[0146] (7) After adding the second powder DFHCO-4T to the second filling through hole 23, the temperature is raised to 250°C at a heating rate of 20°C / min, and then kept at the temperature for 20 min. The pressure is continuously applied to melt the second powder and spread it along the top surface of the second silicon pillar 131. Then, the temperature is slowly lowered at a cooling rate of 1°C / min until the glass transition temperature of the second powder is reached. Then, the temperature is rapidly lowered at a cooling rate of 10°C / min until the room temperature is reached. The second single crystal silicon pillar is formed between the second silicon pillar 131 and the substrate 2 to obtain the second micron-line single crystal array.

[0147] (8) Then the silicon pillar template 1 was removed to obtain a regularly arranged horizontal heterogeneous single crystal array.

[0148] In this embodiment, the shape of the lateral heterojunction single-crystal array is the same as the shape of the silicon pillar array, such as... Figure 12 As shown in the fluorescence microscope images, under ultraviolet excitation, green and red fluorescent micrometer lines are arranged alternately, indicating that the multi-component organic semiconductor structure has been successfully constructed.

[0149] Example 6

[0150] This embodiment provides a method for fabricating a multi-component lateral heterojunction single-crystal array based on a melting method, specifically including the following steps:

[0151] (1) Preparation of silicon pillar template. A first silicon pillar array, a second silicon pillar array, and a third silicon pillar array are formed on the silicon pillar template by sequentially spin-coating photoresist, pre-baking, exposure, development, rinsing, post-baking, plasma etching, and photoresist removal. The first silicon pillar array includes multiple first silicon pillars arranged sequentially along a first direction; the second silicon pillar array includes multiple second silicon pillars arranged sequentially along the first direction; and the third silicon pillar array includes multiple third silicon pillars arranged sequentially along the first direction, with the arrangement of the first, second, and third silicon pillars alternating. The silicon pillar template, the first silicon pillars, the second silicon pillars, and the third silicon pillars all have a cuboid structure, with the first direction being the extension direction of the silicon pillar template, i.e., its length direction. The first, second, and third silicon pillars extend independently along the width direction of the silicon pillar template. The first, second, and third silicon pillars have the same height, and their linear length (width) along the first direction is 2 μm. The distance between any two of the first, second, and third silicon pillars is 2 μm.

[0152] (2) The silicon pillar template is subjected to asymmetric wetting treatment, so that the top surface of the first silicon pillar, the second silicon pillar and the third silicon pillar is hydrophilic, while the side wall surface is hydrophobic.

[0153] (3) A substrate is provided, comprising a substrate body, the substrate body being a silicon wafer with a 30nm HfO2 coating on its surface. The substrate body has multiple first filling vias, multiple second filling vias, and multiple third filling vias, arranged alternately at intervals along a first direction at the same end of the substrate body, and side-by-side. The first, second, and third filling vias are all circular vias with a diameter of 3μm, penetrating the substrate body.

[0154] (4) Place the substrate above the silicon pillar template, such that the first injection via corresponds to the first silicon pillar and is located directly above the first silicon pillar, the second injection via corresponds to the second silicon pillar and is located directly above the second silicon pillar, and the third injection via corresponds to the third silicon pillar and is located directly above the third silicon pillar. Then apply pressure to bring the substrate body close to the first silicon pillar, the second silicon pillar and the third silicon pillar until the distance between the top surface of the first silicon pillar, the second silicon pillar and the third silicon pillar and the substrate body is less than or equal to 100 nm.

[0155] (5) Provide the first powder DFHCO-4T, the second powder C8-NTDA and the third powder NSE, and the glass transition temperatures of the three materials are in the following order: first powder DFHCO-4T > second powder C8-NTDA > third powder NSE.

[0156] The molecular structure of DFHCO-4T is .

[0157] The molecular structure of C8-NTDA is as follows: .

[0158] The molecular structure of NSE is .

[0159] (6) After adding the first powder DFHCO-4T to the first filling through hole, the temperature is raised to 250°C at a heating rate of 20°C / min, and then kept at the temperature for 20 min. The pressure is continuously applied to melt the first powder and spread it along the top surface of the first silicon pillar. Then, the temperature is slowly lowered at a cooling rate of 1°C / min until the glass transition temperature of the first powder is reached. Then, the temperature is rapidly lowered at a cooling rate of 10°C / min until the room temperature is reached. The first single crystal silicon pillar is formed between the first silicon pillar and the substrate to obtain the first micron-line single crystal array.

[0160] (7) After adding the second powder C8-NTDA to the second filling through hole, heat it to 195°C at a heating rate of 20°C / min, hold it for 20 min, and continue to apply pressure to melt the second powder and spread it along the top surface of the second silicon pillar. Then, slowly cool it down at a cooling rate of 1°C / min until the glass transition temperature of the second powder is reached, and then rapidly cool it down at a cooling rate of 10°C / min until room temperature is reached. The second single crystal silicon pillar is formed between the second silicon pillar and the substrate to obtain the second micron-line single crystal array.

[0161] (8) After adding the third powder NSE to the third filling through hole, heat it to 130°C at a heating rate of 20°C / min, hold it for 20 min, and continue to apply pressure to melt the third powder and spread it along the top surface of the third silicon pillar. Then, slowly cool it down at a cooling rate of 1°C / min until the glass transition temperature of the third powder is reached. Then, rapidly cool it down at a cooling rate of 10°C / min until room temperature is reached. The third single crystal silicon pillar is formed between the third silicon pillar and the substrate to obtain the third micron-line single crystal array.

[0162] (8) The silicon pillar template was then removed to obtain a regularly arranged horizontal heterogeneous single crystal array.

[0163] In this embodiment, the shape of the lateral heterojunction single-crystal array is the same as the shape of the silicon pillar array, such as... Figure 13 As shown in the fluorescence microscope image, red, blue and green fluorescent micrometer lines are arranged alternately under ultraviolet excitation, confirming that the three-component organic semiconductor structure has been successfully constructed.

[0164] Example 7

[0165] This embodiment provides a method for preparing a multi-component lateral heterogeneous single crystal array based on a melting method. The difference from Embodiment 1 is that the provided substrate is selectively chemically modified to adjust the wettability of the melt after the first powder and the second powder are melted on the substrate surface, so as to obtain a first micron-line single crystal array and a second micron-line single crystal array with different widths. The remaining steps are the same as in Embodiment 1.

[0166] Example 8

[0167] This embodiment provides a method for preparing a multi-component lateral heterogeneous single crystal array based on a melting method. The difference from Embodiment 6 is that the provided substrate is selectively chemically modified to adjust the wettability of the melt after the first powder and the second powder are melted on the substrate surface, so as to obtain a first micron-line single crystal array and a second micron-line single crystal array with different widths. The remaining steps are the same as in Embodiment 6.

[0168] Example 9

[0169] This embodiment provides a method for fabricating a multi-component lateral heterogeneous single-crystal array based on a melting method. The difference from Embodiment 1 lies in the arrangement of the first and second vias 22 on the substrate. For example... Figure 14 As shown, the orthographic projection of the first filling through hole 22 on the vertical plane does not coincide with the orthographic projection of the second filling through hole 23 on the vertical plane, and the first filling through hole 22 is closer to the edge of the substrate. The remaining steps are the same as in Embodiment 1.

[0170] Example 10

[0171] This embodiment provides a method for fabricating a multi-component lateral heterogeneous single-crystal array based on a melting method. The difference from Embodiment 1 lies in the arrangement of the first and second vias 22 on the substrate. For example... Figure 15 As shown, the orthographic projection of the first filling through hole 22 on the vertical plane partially overlaps with the orthographic projection of the second filling through hole 23 on the vertical plane, and the remaining steps are the same as in Embodiment 1.

[0172] Example 11

[0173] This embodiment provides a method for fabricating a multi-component lateral heterogeneous single-crystal array based on a melting method. The difference from Embodiment 1 lies in the arrangement of the first and second vias 22 on the substrate. For example... Figure 16 As shown, the orthographic projection of the first filling through hole 22 on the vertical plane partially overlaps with the orthographic projection of the second filling through hole 23 on the vertical plane, and the remaining steps are the same as in Embodiment 1.

[0174] Comparative Example 1

[0175] This comparative example provides a method for fabricating a multi-component lateral heterogeneous single crystal array. It uses two independent silicon pillar templates with a first silicon pillar array and a second silicon pillar array respectively, combined with a multiple melting method using alignment technology, to fabricate a two-component organic semiconductor single crystal wafer with a complex pattern.

[0176] Comparative Example 2

[0177] This comparative example provides a method for fabricating a multi-component lateral heterogeneous single crystal array. It employs three independent silicon pillar templates, namely a first silicon pillar array, a second silicon pillar array, and a third silicon pillar array, and combines a multi-melting method with alignment technology to fabricate a three-component organic semiconductor single crystal wafer with a complex pattern.

[0178] This invention employs an integrated patterned silicon pillar template. The template's unique morphology and periodic structure control the directional transport of the melt, regulating its wetting behavior within a confined space. This achieves precise control over the flow and three-dimensional morphology of the melt in micro-regions, while simultaneously regulating the wettability of the silicon pillar template and the substrate, avoiding cross-contamination between different melt components. Based on the differences in glass transition temperatures of semiconductor systems, single-crystal arrays are fabricated. By precisely controlling the maximum temperature, heating rate, and cooling rate of the melting process, the slow nucleation and ordered growth of the melt are regulated, thereby achieving multi-component organic semiconductor single-crystal arrays with defined crystal orientation, controllable structural dimensions, and precise positioning. Furthermore, the process flow is simplified, eliminating the need for alignment steps, reducing operational errors, and further improving the uniformity of the single-crystal array.

[0179] The applicant declares that the above description is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention fall within the protection and disclosure scope of the present invention.

Claims

1. A method for fabricating a multi-component lateral heterogeneous single-crystal array based on a melting method, characterized in that, The method for fabricating a multi-component lateral heterogeneous single-crystal array includes: A silicon pillar template and a substrate are provided. The silicon pillar template has at least a plurality of first silicon pillars and a plurality of second silicon pillars. The first silicon pillars and the second silicon pillars are alternately spaced along a first direction and extend independently perpendicular to the first direction. The substrate has at least a plurality of first injection through holes and a plurality of second injection through holes. The first injection through holes and the second injection through holes are alternately spaced along the first direction at the same end of the substrate. The substrate is placed above the first silicon pillar and the second silicon pillar, such that the first injection via corresponds to the first silicon pillar and the second injection via corresponds to the second silicon pillar. Then pressure is applied to bring the substrate close to the first silicon pillar and the second silicon pillar. After adding the first powder to the first filling via, a heating treatment is performed to melt the first powder and spread it along the surface of the first silicon pillar. Then, a cooling treatment is performed to form a first micron-line single crystal array in the gap between the first silicon pillar and the substrate. After adding the second powder to the second filling via, a second heating treatment is performed to melt the second powder and spread it along the surface of the second silicon pillar. Then, a second cooling treatment is performed to form a second micron-line single crystal array in the gap between the second silicon pillar and the substrate. Subsequently, the silicon pillar template is removed to obtain a lateral heterogeneous single crystal array. The glass transition temperature of the first powder is greater than that of the second powder; The first direction is the extension direction of the silicon pillar template.

2. The method for preparing a multi-component lateral heterogeneous single-crystal array based on the melting method according to claim 1, characterized in that, The linear lengths of the first silicon pillar and the second silicon pillar in the first direction are independently 1~100000 μm; And / or, the distance between the first silicon pillar and the second silicon pillar is 1~100μm.

3. The method for preparing a multi-component lateral heterogeneous single-crystal array based on the melting method according to claim 1, characterized in that, The provided silicon pillar template is subjected to an asymmetric wetting treatment, which makes the top surfaces of the first and second silicon pillars hydrophilic, while the sidewall surfaces are hydrophobic. And / or, the contact angle between the top surfaces of the first silicon pillar and the second silicon pillar is 5°~10°; And / or, the contact angle between the sidewall surfaces of the first silicon pillar and the second silicon pillar is 80°~100°.

4. The method for preparing a multi-component lateral heterogeneous single-crystal array based on the melting method according to claim 1, characterized in that, The substrate material includes at least one of glass, quartz, silicon, or silicon with a deposited silicon oxide layer; And / or, the first filling through hole and the second filling through hole are arranged side by side, or the orthographic projection of the first filling through hole on the vertical plane does not coincide with the orthographic projection of the second filling through hole on the vertical plane, or at least part of the orthographic projection of the first filling through hole on the vertical plane coincides with the orthographic projection of the second filling through hole on the vertical plane; And / or, the diameter of the first filling via is less than the first length, the first length being the sum of the linear length of the first silicon pillar in the first direction and the distance between the first silicon pillar and the second silicon pillar; The diameter of the second injection via is smaller than the second length, which is the sum of the linear length of the second silicon pillar in the first direction and the distance between the first and second silicon pillars.

5. The method for preparing a multi-component lateral heterogeneous single-crystal array based on the melting method according to claim 1, characterized in that, The provided substrate is selectively chemically modified to adjust the wettability of the melt after the first powder and the second powder are fused on the surface of the substrate, so as to obtain a first micron-line single crystal array and a second micron-line single crystal array with different widths. And / or, the contact angle between the melt of the first powder and the melt of the second powder on the substrate surface is 10°~80°.

6. The method for preparing a multi-component lateral heterogeneous single-crystal array based on the melting method according to claim 1, characterized in that, The glass transition temperature of the first powder is lower than its thermal decomposition temperature, and the glass transition temperature of the second powder is lower than its thermal decomposition temperature. The glass transition temperatures of both the first powder and the second powder are lower than the melting point of the substrate, and the glass transition temperatures of both the first powder and the second powder are lower than the melting point of the silicon ingot template.

7. The method for preparing a multi-component lateral heterogeneous single-crystal array based on the melting method according to any one of claims 1-6, characterized in that, The first heating process includes: first heating to a first temperature to melt the first powder, then holding the temperature, and continuously applying pressure to spread the molten first powder to cover the top surface of the first silicon pillar. The secondary heating process includes: first heating the material to a second temperature to melt the second powder, then holding it at the temperature for a second time, and continuously applying pressure to spread the molten second powder to cover the top surface of the second silicon pillar. And / or, both the primary cooling and the secondary cooling include sequentially performing a first-stage cooling and a second-stage cooling, and the cooling rate of the first-stage cooling is less than the cooling rate of the second-stage cooling.

8. The method for fabricating a multi-component lateral heterogeneous single-crystal array based on the melting method according to claim 7, characterized in that, The heating rates for the first heating and the second heating are independent, each ranging from 1 to 20 °C / min. And / or, the first temperature is greater than the glass transition temperature of the first powder and less than the thermal decomposition temperature of the first powder; The second temperature is greater than the glass transition temperature of the second powder and less than the thermal decomposition temperature of the second powder, and is also less than the glass transition temperature of the first powder. And / or, the duration of the first heat preservation and the duration of the second heat preservation are each 5~60 min independently; And / or, the cooling rate of the first stage of cooling is 0.1~1.0℃ / min, and the cooling rate of the second stage of cooling is 1~10℃ / min.

9. The method for preparing a multi-component lateral heterogeneous single-crystal array based on the melting method according to claim 7, characterized in that, Adjusting the applied pressure during the pressure application process allows for the thickness adjustment of the lateral heterojunction single crystal array. And / or, during the pressure application process, the distance between the first silicon pillar and the second silicon pillar and the substrate is less than or equal to 1000 nm.

10. A multi-component lateral heterojunction single-crystal array based on a melting method, characterized in that, The multi-component lateral heterogeneous single crystal array is prepared by the melting method of any one of claims 1-9. The multi-component lateral heterogeneous single crystal array includes a substrate, on which a first micrometer-line single crystal array and a second micrometer-line single crystal array are disposed. The first micrometer-line single crystal array includes a plurality of first micrometer-line single crystals, and the second micrometer-line single crystal array includes a plurality of second micrometer-line single crystals. The first micrometer-line single crystals and the second micrometer-line single crystals are arranged alternately along a first direction. The glass transition temperature of the first micrometer-line single crystal is higher than that of the second micrometer-line single crystal.

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