Current sharing test tool and method
By designing current sharing test fixtures and methods, the problem of insufficient accuracy of general surge arrester testing equipment in low-voltage resistor group testing was solved, achieving higher testing accuracy and matching efficiency, and reducing the impact of temperature rise on test results.
Patent Information
- Application Number
- CN202511665169.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-13
- Publication Date
- 2026-02-06
AI Technical Summary
Existing general-purpose surge arrester current sharing testing equipment lacks accuracy when testing low-voltage metal oxide resistor arrays. Temperature rise increases uncertainty, which cannot meet the needs of mass production and affects product performance and cost.
Design a current sharing test fixture, including a current sharing test platform, a resistor array, and a fixture aluminum plate. The resistor array is connected in parallel with an impulse current sharing generator through multiple test channels. A loop current transformer is used to eliminate the influence of temperature and optimize current differences. Screening and grouping methods are adopted to improve the detection accuracy.
It improves the data correlation and accuracy of low-voltage, high-current resistor array testing, shortens the matching cycle, reduces the impact of errors and temperature rise on test results, and enhances the effectiveness and precision of the testing equipment.
Smart Images
Figure CN121476775A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of surge arrester testing technology, specifically relating to a current sharing test fixture and method. Background Technology
[0002] Currently, general-purpose surge arrester current sharing testing equipment has a large measurement range, which is insufficient for testing the current sharing performance of relatively low-voltage metal oxide resistor arrays. Even with the addition of matching resistor arrays, increased uncertainty due to temperature rise makes it unsuitable for mass production. The critical performance of core components cannot be guaranteed, potentially leading to a reduced lifespan of the metal oxide voltage limiter (MOV), wasted materials and labor, and increased operating and maintenance costs. Designing a test fixture that alters the position of the matching test elements, allowing the large-range current sharing testing equipment to measure low-voltage resistor arrays within its relatively accurate operating range, while eliminating the original errors between matching test elements and the impact of increased batch testing temperature on the test results, ensuring the accuracy of the test performance of each detection channel, and improving matching efficiency and accuracy through the detection and analysis of differences in the detection currents, is an urgent need for industry development. Summary of the Invention
[0003] To address the shortcomings of the existing technology, the present invention aims to provide a current sharing test fixture and method that can improve the correlation, accuracy, and effectiveness of data from testing equipment when operating on low-voltage, high-current resistive sheet arrays.
[0004] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A current sharing test fixture includes: a current sharing test platform, a resistor array, and a fixture aluminum plate; the current sharing test platform provides multiple current sharing test channels, and the fixture aluminum plate is suspended on an upper electrode plate using an insulating rod; there are multiple resistor arrays arranged on the upper surface of the fixture aluminum plate, and each resistor array is connected in parallel with an impulse current sharing generator; Conductive contact blocks are provided on the lower surface of the tooling aluminum plate at positions corresponding to each test channel. Each test channel includes a conductive rod connected in series, a lifting base, and a loop current transformer. The lifting base is used to place the current sharing core group under test. Each test channel is connected in parallel and then connected to a grounding device.
[0005] Furthermore, the longitudinal section of the conductive rod is I-shaped, and the circuit is connected when its upper and lower ends are in contact with the conductive contact block and the current equalization core assembly being measured, respectively.
[0006] The lifting base has a T-shaped longitudinal section, with the current equalization core assembly to be tested placed at the top and the tail end connected to form a current path.
[0007] The tooling aluminum plate is circular, and there are 8 flow equalization test channels arranged in a circular and uniform manner.
[0008] A current sharing test method, using the above-mentioned test fixture, includes the following steps: S1. Material preparation: Prepare spare resistors according to the requirement that DC reference voltage ≤ standard thickness × standard gradient ±3%. The number of spare resistors is A times the estimated number of resistors required for testing, and A≥3. S2. Selection of reference: Select 20 resistors that meet the requirement of DC reference voltage ≤ standard thickness × standard gradient ±1%. Place 8 resistors in a group into the test channel, apply a 1000A operating wave impact current, observe the data deviation value, keep the 2 resistors that are closest to the median current value, replace the other 6 resistors, and measure 3 groups in a row. Calculate the current value for each group, and remove resistors with current deviation value >0.5%. Perform one or more rounds of screening until the 4 resistors with the closest discharge current are selected and named reference resistors B1, B2, B3, and B4. Mark the remaining resistors sequentially from 1 to N as the markers for selecting the groups. S3. Batch Testing: Place the reference piece B1 in test channel one, and test the remaining positions. Place a spare resistor at the test position, keep the charging voltage and discharge waveform constant, apply a 1000A operating current surge, and record the resistor label number, absolute current value, and absolute current value of the reference plate for each round until all spare resistors have been tested; measure the surface temperature of the reference plate every 5-6 rounds, and replace it with reference plate B2 if the temperature rise exceeds 10℃. Rotate the reference plates to avoid data distortion caused by excessive temperature rise; S4. Data Filtering: Based on the test records of S3, organize the data and calculate the discharge current value of each spare resistor in each round / discharge current value of the reference resistor × 100%, and record it in a table; sort the data in ascending order according to the discharge current value / discharge current value of the reference resistor × 100%, and define them as C1 to C2. N This yields a statistical table showing that each resistor chip has both a marking order and a screening mark. S5. Simulation Grouping: Based on the number of surge arrester columns M, select numbers C1-C1. M Group Z1; if any resistor in group Z1 has a value greater than ±1% (single resistor current deviation percentage - group current deviation percentage) / group current deviation percentage × 100%, then that resistor is removed and C is selected. M+1 Replace the chips to ensure that the percentage of single-chip current deviation within a group (percentage of current deviation within the group) / percentage of current deviation within the group × 100% is within ±1%; the rejected chips can be kept as spare chips, and Z2 to Z2 chips can be selected using the same method. N / M Group them, and according to the resistors marked 1 to N, select them from the analog grouping table and rearrange them into Z1 to Z2 groups. N / M Group; S6, (1) When the surge arrester consists of only one piece, each simulated group can be directly used as the final group. The group that passes the test is a qualified group. The steps are as follows: (a) Directly take group Z1 for current sharing test. If the absolute value of the current deviation within the group is ≤3%, then group Z1 is qualified; otherwise, group Z1 is unqualified. (b) Test each simulated group in turn and select all simulated groups that meet the flow equalization screening criteria; (2) When a single column of the surge arrester is composed of D-plates, the simulated group needs to be configured as a simulated core group for parameter testing. The steps are as follows: (c) Z1-Z N / M The simulated groups are roughly divided into D segments, which are defined as segments 1 to D. A group is drawn from each segment. (d) The first segment is extracted and grouped to form the first layer of each column, and the second segment is extracted and grouped to form the second layer of each column, until the group extracted from the D segment is placed at the bottom layer. At this point, the M columns are connected in parallel, and the core group of the single column D sheet completes the grouping of the first core group. (e) Repeat step cd to mix and configure all analog groups to create the required analog core group; (f) Perform current sharing tests on each of the final simulated core groups in sequence. If the absolute value of the current deviation between each column is ≤3%, the core group is completed; otherwise, the core group is unqualified. Select all simulated core groups that meet the current sharing screening criteria.
[0009] The percentage of single-chip current deviation = (single-chip current value - reference chip current value) / reference chip current value × 100%; the percentage of group current deviation = (single-chip current value - group average current value) / group average current value × 100%.
[0010] Compared with existing technologies, the beneficial effects of this invention are as follows: This invention calculates the voltage of the current-sharing core group under test and the normal operating voltage of the equipment, configures appropriate resistor groups, and connects each resistor group in parallel with the impulse current-sharing generator. Simultaneously, the resistor groups are placed on a tooling aluminum plate, connected in parallel as a whole, and then connected in series with the test circuit. The current is connected to the next circuit node in a bundle manner, eliminating the inaccuracy of test results caused by temperature changes after repeated testing of the resistor groups. The loop current transformer is installed on the loop output line of each test channel, and each test current-sharing core group is located between the same discharge positive and negative poles, ensuring the consistency of the discharge residual voltage. This optimizes the current difference between resistor groups under the same residual voltage to within 1.5%, and its residual voltage limitation level can also be verified through similar testing equipment, demonstrating high practical application value. Compared with the original grouping and layering method, the matching cycle is greatly shortened, and the accuracy is more scientific, reasonable, intuitive, and effective. Attached Figure Description
[0011] Figure 1 This is a schematic diagram of the structure of a flow equalization test fixture according to the present invention. Detailed Implementation
[0012] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings and specific embodiments.
[0013] See Figure 1 A current sharing test fixture includes: a current sharing test platform, resistor arrays 12, and a fixture aluminum plate 4. The current sharing test platform provides multiple current sharing test channels, and the fixture aluminum plate is suspended on an upper electrode plate 2 using insulating rods 3. Multiple resistor arrays 12 are arranged on the upper surface of the fixture aluminum plate 4, and each resistor array 12 is connected in parallel with an impulse current sharing generator via an impulse current input bus 2.
[0014] Conductive contact blocks 11 are installed on the lower surface of the tooling aluminum plate 4 at positions corresponding to each test channel. The test channel includes a series-connected conductive rod 10, a lifting base 8, and a loop current transformer 5. The lifting base 8 is used to place the current-sharing core group 9 under test. The test channels are connected in parallel and then connected to the grounding device 7.
[0015] The longitudinal section of the conductive rod 10 is I-shaped. When its upper and lower ends are in contact with the conductive contact block 11 and the current equalization core group 9 being measured, respectively, the circuit is connected.
[0016] The lifting base 8 has a T-shaped longitudinal section. The current equalization core to be tested is placed at the top, and the tail end is connected to the output line 6 to form a current path.
[0017] The tooling aluminum plate 4 is circular, and there are 8 flow equalization test channels, which are evenly arranged in a circle.
[0018] A current sharing test method, using the above-mentioned test fixture, includes the following steps: S1. Material preparation: Prepare spare resistors according to the requirement that DC reference voltage ≤ standard thickness × standard gradient ±3%. The number of spare resistors is A times the estimated number of resistors required for testing, and A≥3. S2. Selection of reference: Select 20 resistors that meet the requirement of DC reference voltage ≤ standard thickness × standard gradient ±1%. Place 8 resistors in a group into the test channel, apply a 1000A operating wave impact current, observe the data deviation value, keep the 2 resistors that are closest to the median current value, replace the other 6 resistors, and measure 3 groups in a row. Calculate the current value for each group, and remove resistors with current deviation value >0.5%. Perform one or more rounds of screening until the 4 resistors with the closest discharge current are selected and named reference resistors B1, B2, B3, and B4. Mark the remaining resistors sequentially from 1 to N as the markers for selecting the groups. S3. Batch Testing: Place the reference piece B1 in test channel one, and test the remaining positions. Place a spare resistor at the test position, keep the charging voltage and discharge waveform constant, apply a 1000A operating current surge, and record the resistor label number, absolute current value, and absolute current value of the reference plate for each round until all spare resistors have been tested; measure the surface temperature of the reference plate every 5-6 rounds, and replace it with reference plate B2 if the temperature rise exceeds 10℃. Rotate the reference plates to avoid data distortion caused by excessive temperature rise; S4. Data Filtering: Based on the test records of S3, organize the data and calculate the discharge current value of each spare resistor in each round / discharge current value of the reference resistor × 100%, and record it in a table; sort the data in ascending order according to the discharge current value / discharge current value of the reference resistor × 100%, and define them as C1 to C2. N This yields a statistical table showing that each resistor chip has both a marking order and a screening mark. S5. Simulation Grouping: Based on the number of surge arrester columns M, select numbers C1-C1. M Group Z1; if any resistor in group Z1 has a value greater than ±1% (single resistor current deviation percentage - group current deviation percentage) / group current deviation percentage × 100%, then that resistor is removed and C is selected. M+1 Replace the chips to ensure that the percentage of single-chip current deviation within a group (percentage of current deviation within the group) / percentage of current deviation within the group × 100% is within ±1%; the rejected chips can be kept as spare chips, and Z2 to Z2 chips can be selected using the same method. N / M Group them, and according to the resistors marked 1 to N, select them from the analog grouping table and rearrange them into Z1 to Z2 groups. N / M Group; S6, (1) When the surge arrester consists of only one piece, each simulated group can be directly used as the final group. The group that passes the test is a qualified group. The steps are as follows: (a) Directly take group Z1 for current sharing test. If the absolute value of the current deviation within the group is ≤3%, then group Z1 is qualified; otherwise, group Z1 is unqualified. (b) Test each simulated group in turn and select all simulated groups that meet the flow equalization screening criteria; (2) When a single column of the surge arrester is composed of D-plates, the simulated group needs to be configured as a simulated core group for parameter testing. The steps are as follows: (c) Z1-Z N / M The simulated groups are roughly divided into D segments, which are defined as segments 1 to D. A group is drawn from each segment. (d) The first segment is extracted and grouped to form the first layer of each column, and the second segment is extracted and grouped to form the second layer of each column, until the group extracted from the D segment is placed at the bottom layer. At this point, the M columns are connected in parallel, and the core group of the single column D sheet completes the grouping of the first core group. (e) Repeat step cd to mix and configure all analog groups to create the required analog core group; (f) Perform current sharing tests on each of the final simulated core groups in sequence. If the absolute value of the current deviation between each column is ≤3%, the core group is completed; otherwise, the core group is unqualified. Select all simulated core groups that meet the current sharing screening criteria.
[0019] The percentage of current deviation for a single chip is calculated as follows: (Current value of a single chip - Current value of a reference chip) / Current value of a reference chip × 100%; the percentage of current deviation within a group is calculated as follows: (Current value of a single chip - Average current value within a group) / Average current value within a group × 100%. The percentage of current deviation is used as the main indicator for current equalization screening; the smaller the difference, the smaller the non-uniformity coefficient.
Claims
1. A current sharing test fixture, characterized in that, include: Current sharing test bench, resistor array and tooling aluminum plate; The current sharing test bench provides multiple current sharing test channels, and the tooling aluminum plate is suspended on the upper electrode plate using an insulated hanger rod; The resistor groups are multiple and arranged on the upper surface of the tooling aluminum plate, and each resistor group is connected in parallel with the impact current sharing generator; Conductive contact blocks are provided on the lower surface of the tooling aluminum plate at positions corresponding to each test channel. Each test channel includes a conductive rod connected in series, a lifting base, and a loop current transformer. The lifting base is used to place the current sharing core group under test. Each test channel is connected in parallel and then connected to a grounding device.
2. The current sharing test fixture according to claim 1, characterized in that, The conductive rod has an I-shaped longitudinal section. When its upper and lower ends are in contact with the conductive contact block and the current equalization core assembly being measured, respectively, the circuit is turned on.
3. The current sharing test fixture according to claim 1, characterized in that, The lifting base has a T-shaped longitudinal section, with the current equalization core assembly to be tested placed at the top and the tail end connected to form a current path.
4. The current sharing test fixture according to claim 1, characterized in that, The tooling aluminum plate is circular, and there are 8 flow equalization test channels arranged in a circular and uniform manner.
5. A current sharing test method, using the test fixture described in any one of claims 1-4, characterized in that, Includes the following steps: S1. Material preparation: Prepare spare resistors according to the requirement that DC reference voltage ≤ standard thickness × standard gradient ±3%. The number of spare resistors is A times the estimated number of resistors required for testing, and A≥3. S2. Selection of reference: Select 20 resistors that meet the requirement of DC reference voltage ≤ standard thickness × standard gradient ±1%. Place 8 resistors in a group into the test channel, apply a 1000A operating wave impact current, observe the data deviation value, keep the 2 resistors that are closest to the median current value, replace the other 6 resistors, and measure 3 groups in a row. Calculate the current value for each group, and remove resistors with current deviation value >0.5%. Perform one or more rounds of screening until the 4 resistors with the closest discharge current are selected and named reference resistors B1, B2, B3, and B4. Mark the remaining resistors sequentially from 1 to N as the markers for selecting the groups. S3. Batch Testing: Place the reference piece B1 in test channel one, and test the remaining positions. Place a spare resistor at the test position, keep the charging voltage and discharge waveform constant, apply a 1000A operating current surge, and record the resistor label number, absolute current value, and absolute current value of the reference plate for each round until all spare resistors have been tested; measure the surface temperature of the reference plate every 5-6 rounds, and replace it with reference plate B2 if the temperature rise exceeds 10℃. Rotate the reference plates to avoid data distortion caused by excessive temperature rise; S4. Data Filtering: Based on the test records of S3, organize the data and calculate the discharge current value of each spare resistor in each round / discharge current value of the reference resistor × 100%, and record it in a table; sort the data in ascending order according to the discharge current value / discharge current value of the reference resistor × 100%, and define them as C1 to C2. N This yields a statistical table showing that each resistor chip has both a marking order and a screening mark. S5. Simulation Grouping: Based on the number of surge arrester columns M, select numbers C1-C1. M Group Z1; if any resistor in group Z1 has a value greater than ±1% (single resistor current deviation percentage - group current deviation percentage) / group current deviation percentage × 100%, then that resistor is removed and C is selected. M+1 Replace the chips to ensure that the percentage of single-chip current deviation within a group (percentage of current deviation within the group) / percentage of current deviation within the group × 100% is within ±1%; the rejected chips can be kept as spare chips, and Z2 to Z2 chips can be selected using the same method. N / M Group them, and according to the resistors marked 1 to N, select them from the analog grouping table and rearrange them into Z1 to Z2 groups. N / M Group; S6, (1) When the surge arrester consists of only one piece, each simulated group can be directly used as the final group. The group that passes the test is a qualified group. The steps are as follows: (a) Directly take group Z1 for current sharing test. If the absolute value of the current deviation within the group is ≤3%, then group Z1 is qualified; otherwise, group Z1 is unqualified. (b) Test each simulated group in turn and select all simulated groups that meet the flow equalization screening criteria; (2) When a single column of the surge arrester is composed of D-plates, the simulated group needs to be configured as a simulated core group for parameter testing. The steps are as follows: (c) Z1-Z N / M The simulated groups are roughly divided into D segments, which are defined as segments 1 to D. A group is drawn from each segment. (d) The first segment is extracted and grouped to form the first layer of each column, and the second segment is extracted and grouped to form the second layer of each column, until the group extracted from the D segment is placed at the bottom layer. At this point, the M columns are connected in parallel, and the core group of the single column D sheet completes the grouping of the first core group. (e) Repeat step cd to mix and configure all analog groups to create the required analog core group; (f) Perform current sharing tests on each of the final simulated core groups in sequence. If the absolute value of the current deviation between each column is ≤3%, the core group is completed; otherwise, the core group is unqualified. Select all simulated core groups that meet the current sharing screening criteria.
6. The current sharing test method according to claim 5, characterized in that, The percentage of single-chip current deviation = (single-chip current value - reference chip current value) / reference chip current value × 100%; the percentage of group current deviation = (single-chip current value - group average current value) / group average current value × 100%.