System memory test method, device and storage medium

Abstract

The application discloses a system memory test method, equipment and a storage medium, relates to the technical field of testing, and discloses a system memory test method, which comprises the following steps: mapping CXL memory to a high address space of memory; copying a basic input output system (BIOS) program in a system memory space to the CXL memory; copying a global descriptor table, a local descriptor table and an interrupt descriptor table in the system memory space to the CXL memory respectively; establishing peripheral component interconnect (PCI) device data in the CXL memory, and pointing to an address space of the CXL memory to a device base address corresponding to the PCI device data; setting the system memory space as a testable area, and testing the system memory space based on a memory test program. According to the application, data in the system memory space is copied to the CXL memory, the whole space of the memory can be tested, and the test efficiency of the memory is improved.

Description

Technical Field

[0001] This application relates to the field of testing technology, and in particular to a system memory testing method, apparatus, device and storage medium. Background Technology

[0002] Electronic products have permeated every aspect of life, and almost all electronic products use memory. Before electronic devices / memory leave the factory, the memory needs to undergo functional and reliability testing.

[0003] However, most SLT (System Level Test) tests are currently conducted in a UEFI (Unified Extensible Firmware Interface) shell environment. Consequently, the system memory occupied by memory test programs, BIOS (Basic Input / Output System) programs, and hardware-related register mapping memory spaces is difficult to test, which reduces testable memory and lowers test efficiency.

[0004] CN118427024A adds preset boot parameters to the host system's bootloader command line, mounts the CXL expansion card's memory through a non-uniform memory access node, uses a memory access control tool to specify access, and performs batch memory tests to ensure that only CXL memory is tested. However, it does not solve the problem of testing system memory space.

[0005] US20220222009A1 can only solve the problem of testing the memory space occupied by the program itself, and it requires entering the BIOS and operating system. However, the memory space occupied by the BIOS and operating system itself cannot be moved, so it is impossible to achieve full coverage testing of the memory space.

[0006] Therefore, how to perform full-space testing of memory and improve memory testing efficiency is a problem that urgently needs to be solved.

[0007] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0008] The main purpose of this application is to provide a system memory testing method, device and storage medium, which aims to solve the technical problem of how to perform memory testing on the entire memory space and improve the testing efficiency of memory.

[0009] To achieve the above objectives, this application proposes a system memory testing method, which includes:

[0010] Map CXL memory to the high address space of memory;

[0011] Copy the Basic Input / Output System BIOS program from the system memory space to the CXL memory;

[0012] Copy the global descriptor table, local descriptor table, and interrupt descriptor table from the system memory space to CXL memory respectively;

[0013] Establish peripheral component interconnect PCI device data in CXL memory, and point the device base address corresponding to the PCI device data to the address space of CXL memory;

[0014] Set the system memory space as a testable area and test the system memory space based on the memory testing program.

[0015] In one embodiment, the step of copying the Basic Input / Output System BIOS program from the system memory space to the CXL memory includes:

[0016] Copy the data corresponding to the program area of ​​the BIOS program in the system memory space to the address space of the CXL memory;

[0017] Copy the data corresponding to the data area of ​​the BIOS program in the system memory space to the address space of the CXL memory;

[0018] Copy the data corresponding to the reserved area of ​​the BIOS program in the system memory space to the address space of the CXL memory.

[0019] In one embodiment, the step of copying the global descriptor table, local descriptor table, and interrupt descriptor table from the system memory space to CXL memory includes:

[0020] Disable interrupts, copy the global descriptor table to the CXL memory, and set the global descriptor table register GDTR to point to the new address of the global descriptor table in the CXL memory;

[0021] Copy the local descriptor table to the CXL memory, and set the local descriptor table register LDTR to point to the new address of the local descriptor table in the CXL memory;

[0022] Copy the interrupt descriptor table to CXL memory and enable interrupts.

[0023] In one embodiment, the step of copying the interrupt descriptor table to CXL memory includes:

[0024] Copy the interrupt descriptor table to the CXL memory;

[0025] Copy the interrupt service routine from the system memory space to the CXL memory;

[0026] Set the Interrupt Descriptor Table Register IDTR to the new address of the Interrupt Descriptor Table in the CXL memory.

[0027] In one embodiment, the step of establishing peripheral component interconnect (PCI) device data in CXL memory and pointing the device base address corresponding to the PCI device data to the address space of CXL memory includes:

[0028] Disable interrupts and allocate memory-mapped input / output (MMIO) memory space in the address space of CXL memory;

[0029] In the CXL memory, a PCI device tree corresponding to the PCI device data is established. The device base address corresponding to each PCI device data in the PCI device tree is pointed to the MMIO memory space, and interrupts are enabled.

[0030] In one embodiment, the steps of setting the system memory space as a testable region, loading the memory test program into CXL memory, and starting the memory test program to test the system memory space include:

[0031] Modify the segment attributes of the system memory space to make the system memory space a testable region;

[0032] Load the memory test program into the CXL memory and start the memory test program to test the system memory space.

[0033] In one embodiment, the step of mapping CXL memory to the high address space of memory includes:

[0034] During system initialization, a memory mapping table is established to divide memory into segments;

[0035] Based on the memory mapping table, CXL memory is mapped to the high address space of memory.

[0036] In one embodiment, the system memory testing method further includes:

[0037] Determine the target memory region within the free memory region of the system memory space;

[0038] Copy the BIOS program from the system memory space to the target memory area;

[0039] Copy the global descriptor table, local descriptor table, and interrupt descriptor table from the system memory space to the target memory region respectively;

[0040] Establish peripheral component interconnect PCI device data in the target memory region, and point the device base address corresponding to the PCI device data to the address space of the target memory region;

[0041] The memory regions in the system memory space other than the target memory region are taken as the test regions, and the test regions are tested based on the memory test program;

[0042] If the test area is completed, the test area is used as the target memory area, and the process returns to the step of copying the BIOS program from the system memory space to the target memory area.

[0043] In addition, to achieve the above objectives, this application also proposes a system memory testing device, the device comprising: a memory, a processor, and a computer program stored on the memory and executable on the processor, the computer program being configured to implement the steps of the aforementioned system memory testing method.

[0044] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and which, when executed by a processor, implements the steps of the aforementioned system memory testing method.

[0045] One or more technical solutions proposed in this application have at least the following technical effects:

[0046] The process involves mapping CXL memory to the high address space of memory; then copying the Basic Input / Output System BIOS program from the system memory space to the CXL memory; subsequently copying the Global Descriptor Table, Local Descriptor Table, and Interrupt Descriptor Table from the system memory space to the CXL memory; establishing Peripheral Component Interconnect (PCI) device data in the CXL memory and pointing the device base address corresponding to the PCI device data to the address space of the CXL memory; finally, setting the system memory space as a testable area and testing it based on a memory testing program. By copying the BIOS program, Global Descriptor Table, Local Descriptor Table, and Interrupt Descriptor Table to the CXL memory, and by copying data from the system memory space to the CXL memory, the system memory space becomes a free storage area. By setting the system memory space as a testable area, memory testing can be performed on the system memory space, thereby enabling memory testing of the entire memory space and improving memory testing efficiency. Attached Figure Description

[0047] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0048] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a flowchart illustrating an embodiment of the system memory testing method of this application.

[0050] Figure 2 This is a schematic diagram of the module structure of the system memory testing device according to an embodiment of this application;

[0051] Figure 3 This is a schematic diagram of the hardware operating environment involved in the system memory testing method in this application embodiment.

[0052] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0053] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0054] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0055] The main solution of this application embodiment is as follows: mapping CXL memory to the high address space of memory; copying the Basic Input / Output System BIOS program in the system memory space to the CXL memory; copying the global descriptor table, local descriptor table and interrupt descriptor table in the system memory space to the CXL memory respectively; establishing peripheral component interconnect PCI device data in the CXL memory, and pointing the device base address corresponding to the PCI device data to the address space of the CXL memory; setting the system memory space as a testable area, and testing the system memory space based on the memory test program.

[0056] In this embodiment, for ease of description, the following description will focus on the identification system memory testing device as the execution subject.

[0057] Electronic products have permeated every aspect of life, and almost all electronic products use memory. Before electronic devices / memory leave the factory, the memory needs to undergo functional and reliability testing.

[0058] However, most current memory SLT tests are conducted in a UEFI shell environment. The system memory occupied by memory test programs, BIOS (Basic Input / Output System) programs, and hardware-related registers is difficult to test, which reduces the testable memory and lowers test efficiency.

[0059] Therefore, how to perform memory testing on the entire memory space and improve memory testing efficiency is a problem that urgently needs to be solved.

[0060] This application provides a solution that copies the BIOS program, global descriptor table, local descriptor table, and interrupt descriptor table to CXL memory, copies data from the system memory space to CXL memory to make the system memory space a free storage area, and sets the system memory space as a testable area to perform memory testing on the system memory space. In this way, memory testing of the entire memory space can be achieved, thus improving the efficiency of memory testing.

[0061] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device or system memory testing device capable of performing the above functions. The following description uses a system memory testing device as an example to illustrate this embodiment and the subsequent embodiments.

[0062] Based on this, embodiments of this application provide a system memory testing method, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the system memory testing method of this application.

[0063] In this embodiment, the system memory testing method includes steps S110~S150:

[0064] Step S110: Map the CXL memory to the high address space of memory;

[0065] In this embodiment of the application, memory may include system memory space and other memory spaces besides system memory space. When performing SLT (System Level Test) on memory, memory test can be performed on system memory space after memory test of other memory spaces is completed. At this time, CXL memory can be mapped to the high address space of memory first.

[0066] Specifically, in one feasible implementation, step S110 may include steps S111 to S112:

[0067] Step S111: During system initialization, a memory mapping table is established to divide the memory into segments.

[0068] Step S112: Based on the memory mapping table, map the CXL memory to the high address space of memory.

[0069] Among them, CXL (Compute Express Link) memory is a memory extension based on the CXL open interconnect protocol. Through the CXL protocol, CXL memory can achieve high-speed, low-latency, cache-consistent memory sharing and expansion between CPUs and accelerators (such as GPUs and FPGAs) and between memory modules, which can effectively solve the bottlenecks of memory walls and I / O walls.

[0070] In this embodiment, a memory map is established during system initialization to divide the memory into segments, that is, the memory space is divided into segments, and each segment is labeled with attributes according to its purpose.

[0071] After establishing the memory mapping table, the CXL memory is mapped to the high address space of memory based on the memory mapping table, as shown in Table 1. The CXL memory is treated as an independent memory space with the attribute of "Available".

[0072] Table 1. Type and Description of Memory Space in the Memory Map Table

[0073]

[0074] In Table 1, the memory regions above the CXL memory-mapped region are all system memory spaces.

[0075] Step S120: Copy the Basic Input / Output System BIOS program from the system memory space to the CXL memory;

[0076] In this embodiment, after mapping the CXL memory to the high address space of the memory, the BIOS program in the system memory space is copied to the CXL memory. The copied content includes the program area, data area and reserved area of ​​the BIOS program.

[0077] Specifically, in one feasible implementation, step S120 may include steps S121 to S123:

[0078] Step S121: Copy the data corresponding to the program area of ​​the BIOS program in the system memory space to the address space of the CXL memory;

[0079] Step S122: Copy the data corresponding to the data area of ​​the BIOS program in the system memory space to the address space of the CXL memory;

[0080] Step S123: Copy the data corresponding to the reserved area of ​​the BIOS program in the system memory space to the address space of the CXL memory.

[0081] In this embodiment, when copying the BIOS program, the data corresponding to the program area of ​​the BIOS program in the system memory space is copied to the address space of CXL memory, the data corresponding to the data area of ​​the BIOS program in the system memory space is copied to the address space of CXL memory, and the data corresponding to the reserved area of ​​the BIOS program in the system memory space is copied to the address space of CXL memory. After copying, the program area, data area, and reserved area of ​​the BIOS program are all different in the address space of CXL memory, that is, the three are in different address spaces in CXL memory.

[0082] Step S130: Copy the global descriptor table, local descriptor table and interrupt descriptor table in the system memory space to CXL memory respectively;

[0083] In this embodiment, after copying the BIOS program to CXL memory, the global descriptor table, local descriptor table, and interrupt descriptor table in the system memory space are copied to CXL memory respectively.

[0084] Specifically, in one feasible implementation, step S130 may include steps S131 to S133:

[0085] Step S131: Disable interrupts, copy the global descriptor table to the CXL memory, and set the global descriptor table register GDTR to point to the new address of the global descriptor table in the CXL memory;

[0086] Step S132: Copy the local descriptor table to the CXL memory, and set the local descriptor table register LDTR to point to the new address of the local descriptor table in the CXL memory;

[0087] Step S133: Copy the interrupt descriptor table to CXL memory and enable interrupts.

[0088] It's important to note that the GDTR (Global Descriptor Table Register) is a dedicated hardware register used to store the location information of the global descriptor table. It provides the CPU with the base address (the starting location of the global descriptor table in memory) and table limits (the size of the global descriptor table), acting as a crucial bridge between the CPU and the global descriptor table. This ensures the CPU can accurately access segment descriptors within the global descriptor table, thereby protecting and isolating memory segments. The LDTR (Local Descriptor Table Register) is a critical register in protected mode used to manage task-private memory segments. It stores the segment selector of the LDT (Local Descriptor Table), using this selector to locate the LDT descriptor in the global descriptor table. This allows for the dynamic loading of the task-private segment base address, limits, and access permissions, achieving memory isolation and privilege level protection between tasks. The IDTR (InterruptDescriptor Table Register) is a crucial register used to locate the Interrupt Descriptor Table (IDT). It stores the base address (starting location in memory) and table limits (size of the IDT), ensuring that the CPU can quickly locate the corresponding handler entry address when an interrupt or exception occurs.

[0089] In this embodiment, when copying the global descriptor table, local descriptor table, and interrupt descriptor table, interrupts are first disabled. Then, the global descriptor table is copied to CXL memory, and the global descriptor table register GDTR is set to point to the new address of the global descriptor table in CXL memory, so as to establish a mapping relationship between the GDTR register and the new address of the global descriptor table in CXL memory.

[0090] Next, the local descriptor table is copied to the CXL memory, and the local descriptor table register LDTR is set to point to the new address of the local descriptor table in the CXL memory, so as to establish a mapping relationship between the LDTR register and the new address of the local descriptor table in the CXL memory.

[0091] In this embodiment, the interrupt descriptor table is copied to CXL memory and interrupts are enabled to achieve the copying of the interrupt descriptor table. Specifically, in a feasible implementation, step S133 may include steps S1331 to S1333:

[0092] Step S1331: Copy the interrupt descriptor table to the CXL memory;

[0093] Step S1332: Copy the interrupt service routine in the system memory space to the CXL memory;

[0094] Step S1333: Set the Interrupt Descriptor Table Register IDTR to point to the new address of the Interrupt Descriptor Table in the CXL memory.

[0095] In this embodiment, when copying the interrupt descriptor table, the interrupt descriptor table is first copied to the CXL memory. Then, the interrupt service routine in the system memory space is copied to the CXL memory, and the interrupt descriptor table register IDTR is set to point to the new address of the interrupt descriptor table in the CXL memory, so as to establish a mapping relationship between the IDTR register and the new address of the interrupt descriptor table in the CXL memory.

[0096] In this embodiment, interrupts are enabled when copying the global descriptor table, local descriptor table, and interrupt descriptor table is completed.

[0097] Step S140: Establish peripheral component interconnect PCI device data in CXL memory, and point the device base address corresponding to the PCI device data to the address space of CXL memory;

[0098] It's important to note that PCI (Peripheral Component Interconnect) devices are computer hardware components based on the PCI bus standard, used to enable high-speed data transfer between the motherboard and external devices (such as network cards, sound cards, and graphics cards). MMIO (Memory-Mapped I / O) is a key technology in computer systems for accessing peripheral registers through the memory address space. It maps the control registers and data registers of hardware devices (such as graphics cards, network cards, and memory controllers) to the processor's physical / virtual memory address space, allowing the CPU to directly operate peripherals through standard memory access instructions without the need for dedicated I / O instructions.

[0099] In this embodiment, after the global descriptor table, local descriptor table, and interrupt descriptor table are copied, peripheral component interconnect (PCI) device data is established in the CXL memory, and the device base address corresponding to the PCI device data is pointed to the address space of the CXL memory.

[0100] Specifically, in one feasible implementation, step S140 may include steps S141-S142:

[0101] Step S141: Disable interrupts and allocate memory-mapped input / output (MMIO) memory space in the address space of CXL memory;

[0102] Step S142: Establish a PCI device tree corresponding to the PCI device data in the CXL memory, point the device base address corresponding to each PCI device data in the PCI device tree to the MMIO memory space, and enable interrupts.

[0103] In this embodiment, when establishing PCI device data, interrupts are first disabled, and a memory-mapped I / O (MMIO) memory space is allocated in the address space of CXL memory. Then, a PCI device tree corresponding to the PCI device data is established in CXL memory, and the device base address corresponding to each PCI device data in the PCI device tree is pointed to the MMIO memory space. That is, the device base address is pointed to the MMIO memory space by rewriting the device base address. After that, interrupts are enabled.

[0104] Step S150: Set the system memory space as a testable area and test the system memory space based on the memory test program.

[0105] In this embodiment, after copying the system memory space is complete, all data in the system memory space can be deleted, making the system memory space a free memory area. The system memory space is then set as a testable area, and the system memory space can be tested using a memory testing program.

[0106] In one feasible implementation, step S150 may include steps S151-S152:

[0107] Step S151: Modify the segment attributes of the system memory space to make the system memory space a testable region;

[0108] Step S152: Load the memory test program into the CXL memory and start the memory test program to test the system memory space.

[0109] In this embodiment, after copying the system memory space, all data in the system memory space is deleted, making the system memory space a free memory area. Then, the segment attribute of the system memory space can be modified to "Available", making the system memory space a testable area.

[0110] Once the system memory space becomes a testable area, a memory test program can be loaded into the CXL memory and started to test the system memory space.

[0111] It should be noted that in this embodiment, the order of steps S120, S130 and S140 can be arbitrarily changed, or they can be executed simultaneously.

[0112] As shown in Table 2, Table 2 includes the Attribute and corresponding Content of each memory region in the memory after the CXL memory is created. By creating CXL memory with the Segment Attribute Available, it is possible to copy data from the system memory space to the CXL memory. During the copying process, the data can be copied sequentially according to the address order in the system memory space.

[0113] Table 2, memory after CXL memory mapping;

[0114]

[0115] As shown in Table 3, Table 3 includes the attributes and corresponding storage contents of each memory region in memory after the memory test program is loaded. After the system memory space is copied, the system memory space is in an idle state, and the memory test program in CXL memory can be used to test the system memory space.

[0116] Table 3 shows the memory usage after the memory test program has finished loading.

[0117]

[0118] This embodiment provides a system memory testing method. The method involves mapping the CXL memory to the high address space of the main memory; then copying the Basic Input / Output System (BIOS) program from the system memory space to the CXL memory; subsequently, copying the Global Descriptor Table (GDS), Local Descriptor Table (LDTable), and Interrupt Descriptor Table (IDTable) from the system memory space to the CXL memory; establishing Peripheral Component Interconnect (PCI) device data in the CXL memory and pointing the device base address corresponding to the PCI device data to the address space of the CXL memory; finally, setting the system memory space as a testable area and testing it based on a memory testing program. By copying the BIOS program, GDS, LTable, and ITable to the CXL memory, and by copying data from the system memory space to the CXL memory, the system memory space becomes a free storage area. By setting the system memory space as a testable area, memory testing can be performed on the system memory space, thereby enabling full-space memory testing and improving memory testing efficiency.

[0119] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the system memory testing method of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0120] In another feasible implementation, the system memory testing method may further include steps S210 to S260:

[0121] Step S210: Determine the target memory region in the free memory region of the system memory space;

[0122] Step S220: Copy the BIOS program from the system memory space to the target memory area;

[0123] Step S230: Copy the global descriptor table, local descriptor table and interrupt descriptor table in the system memory space to the target memory area respectively;

[0124] Step S240: Establish peripheral component interconnect PCI device data in the target memory region, and point the device base address corresponding to the PCI device data to the address space of the target memory region;

[0125] Step S250: The memory region in the system memory space other than the target memory region is taken as the test region, and the test region is tested based on the memory test program;

[0126] Step S260: If the test of the area to be tested is completed, the area to be tested is taken as the target memory area, and the process returns to the step of copying the BIOS program in the system memory space to the target memory area.

[0127] In this embodiment, during system initialization, the free memory region of the system memory space is obtained, and a target memory region is determined within the free memory region. The target memory region may have storage space for storing all data in the system memory space. The free memory region is a memory region in the system memory space with the segment attribute of Available. The target memory region can be selected from the memory region with the segment attribute of Available.

[0128] Table 4. Type and Description of Each Memory Region in the System Memory Space

[0129]

[0130] Generally, the address space with the "Available" segment in the high address space of the system memory space has enough storage space to store all the data in the system memory space. Therefore, the address space with the "Available" segment in the high address space of the system memory space can be used as the target memory region. As shown in Table 4, the last available memory region with the "Available" segment in Table 4 is the high address space of the system memory space, and thus this available memory region can be used as the first memory region.

[0131] After determining the first memory region, it is mapped to the high address space of memory. Then, the BIOS program in the system memory space is copied to the first memory region. The copied content includes the program area, data area, and reserved area of ​​the BIOS program. Specifically, the data corresponding to the program area of ​​the BIOS program in the system memory space is copied to the address space of the first memory region, the data corresponding to the data area of ​​the BIOS program in the system memory space is copied to the address space of the first memory region, and the data corresponding to the reserved area of ​​the BIOS program in the system memory space is copied to the address space of the first memory region. After the copying, the address spaces of the program area, data area, and reserved area of ​​the BIOS program in the first memory region are all different, that is, the three are in different address spaces in the first memory region.

[0132] In this embodiment, after copying the BIOS program to the first memory region, the global descriptor table, local descriptor table, and interrupt descriptor table in the system memory space are copied to the first memory region respectively. Specifically, interrupts are first disabled, then the global descriptor table is copied to the first memory region, and the global descriptor table register GDTR is set to point to the new address of the global descriptor table in the first memory region to establish a mapping relationship between the GDTR register and the new address of the global descriptor table in the first memory region. Next, the local descriptor table is copied to the first memory region, and the local descriptor table register LDTR is set to point to the new address of the local descriptor table in the first memory region to establish a mapping relationship between the LDTR register and the new address of the local descriptor table in the first memory region. After that, the interrupt descriptor table is copied to the first memory region, and then the interrupt service routine in the system memory space is copied to the first memory region, and the interrupt descriptor table register IDTR is set to point to the new address of the interrupt descriptor table in the first memory region to establish a mapping relationship between the IDTR register and the new address of the interrupt descriptor table in the first memory region.

[0133] In this embodiment, interrupts are enabled when copying the global descriptor table, local descriptor table, and interrupt descriptor table is completed.

[0134] Then, peripheral component interconnect (PCI) device data is established in the first memory region, and the device base address corresponding to the PCI device data is pointed to the address space of the first memory region. Specifically, when establishing the PCI device data, interrupts are first disabled, and memory-mapped input / output (MMIO) memory space is allocated in the address space of the first memory region. Then, the PCI device tree corresponding to the PCI device data is established in the first memory region, and the device base address corresponding to each PCI device data in the PCI device tree is pointed to the MMIO memory space. That is, the device base address is pointed to the MMIO memory space by rewriting the device base address. After that, interrupts are enabled.

[0135] In this embodiment, after the data copying of memory regions other than the target memory region in the system memory space is completed, the memory regions other than the target memory region in the system memory space are designated as test regions. Specifically, the data in the memory regions other than the target memory region in the system memory space is deleted to make them free memory regions. Then, the segment attributes of each memory space corresponding to the memory regions other than the target memory region in the system memory space are modified to "Available", so that the memory regions other than the target memory region in the system memory space become test regions.

[0136] After determining the area to be tested, a memory test program can be loaded into the target memory area and started to test the area to be tested.

[0137] When the test area is completed, in order to perform memory testing on the target memory area, the test area is taken as the target memory area, and the process returns to step S220 to perform memory testing on the untested memory space in the system memory space, thereby realizing full-space memory testing of the system memory space and improving memory testing efficiency.

[0138] It should be noted that in this embodiment, the order of steps S220, S230 and S240 can be arbitrarily changed, or they can be executed simultaneously.

[0139] Once the system memory space becomes a testable area, a memory test program can be loaded into the CXL memory and started to test the system memory space.

[0140] It should be noted that in this embodiment, the order of steps S120, S130 and S140 can be arbitrarily changed, or they can be executed simultaneously.

[0141] This embodiment provides a system memory testing method. The method involves: determining a target memory region within the free memory area of ​​the system memory space; copying the BIOS program from the system memory space to the target memory region; copying the global descriptor table, local descriptor table, and interrupt descriptor table from the system memory space to the target memory region; establishing peripheral component interconnect (PCI) device data in the target memory region and pointing the device base address corresponding to the PCI device data to the address space of the target memory region; designating the memory region in the system memory space other than the target memory region as the test region and testing the test region based on the memory testing program; if the test region is successfully tested, designating it as the target memory region and returning to the step of copying the BIOS program from the system memory space to the target memory region. By performing step-by-step testing of the system memory space, a full-space memory test of the system memory space can be achieved, thereby improving memory testing efficiency.

[0142] This application also provides a system memory testing device; please refer to... Figure 2 The system memory testing device includes:

[0143] Mapping module 10 is used to map CXL memory to the high address space of memory;

[0144] The first copy module 20 is used to copy the Basic Input / Output System BIOS program in the system memory space to the CXL memory.

[0145] The second copy module 30 is used to copy the global descriptor table, local descriptor table and interrupt descriptor table in the system memory space to CXL memory respectively.

[0146] Module 40 is used to establish peripheral component interconnect PCI device data in CXL memory and point the device base address corresponding to the PCI device data to the address space of CXL memory;

[0147] The configuration module 50 is used to set the system memory space as a testable area and to test the system memory space based on a memory testing program.

[0148] The system memory testing apparatus provided in this application, employing the system memory testing method described in the above embodiments, can solve the technical problem of how to perform memory testing on the entire memory space and improve memory testing efficiency. Compared with the prior art, the beneficial effects of the system memory testing apparatus provided in this application are the same as those of the system memory testing method described in the above embodiments, and other technical features in the system memory testing apparatus are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0149] This application provides a system memory testing device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the system memory testing method in Embodiment 1 above.

[0150] The following is for reference. Figure 3 The diagram illustrates a structural schematic of a system memory testing device suitable for implementing embodiments of this application. The system memory testing device in embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 3 The system memory testing device shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0151] like Figure 3As shown, the system memory testing device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the system memory testing device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, a touchscreen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 1003 including, for example, magnetic tape, hard disk, etc.; and communication devices 1009. Communication device 1009 allows the system memory testing equipment to communicate wirelessly or wiredly with other devices to exchange data. Although the figure shows a system memory testing equipment with various systems, it should be understood that it is not required to implement or have all of the systems shown. More or fewer systems may be implemented alternatively.

[0152] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0153] The system memory testing device provided in this application, employing the system memory testing method described in the above embodiments, can solve the technical problem of how to perform memory testing on the entire memory space and improve memory testing efficiency. Compared with the prior art, the beneficial effects of the system memory testing device provided in this application are the same as those of the system memory testing method provided in the above embodiments, and other technical features of this system memory testing device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0154] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0155] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0156] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, which are used to execute the system memory testing method described in the above embodiments.

[0157] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0158] The aforementioned computer-readable storage medium may be included in the system memory testing equipment; or it may exist independently and not be assembled into the system memory testing equipment.

[0159] The aforementioned computer-readable storage medium carries one or more programs. When these programs are executed by the system memory testing device, the system memory testing device causes the following: it maps the CXL memory to the high address space of the memory; it copies the Basic Input / Output System BIOS program from the system memory space to the CXL memory; it copies the Global Descriptor Table, Local Descriptor Table, and Interrupt Descriptor Table from the system memory space to the CXL memory; it establishes Peripheral Component Interconnect (PCI) device data in the CXL memory and points the device base address corresponding to the PCI device data to the address space of the CXL memory; it sets the system memory space as a testable area and tests the system memory space based on the memory testing program.

[0160] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0161] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0162] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0163] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described system memory testing method. This solves the technical problem of how to perform memory testing on the entire memory space and improve memory testing efficiency. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the system memory testing method provided in the above embodiments, and will not be repeated here.

[0164] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the system memory testing method described above.

[0165] The computer program product provided in this application solves the technical problem of how to perform memory testing on the entire memory space and improve memory testing efficiency. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as those of the system memory testing method provided in the above embodiments, and will not be repeated here.

[0166] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A system memory testing method, characterized in that, The system memory testing method includes: Map CXL memory to the high address space of memory; Copy the Basic Input / Output System BIOS program from the system memory space to the CXL memory; Copy the global descriptor table, local descriptor table, and interrupt descriptor table from the system memory space to CXL memory respectively; Establish peripheral component interconnect PCI device data in CXL memory, and point the device base address corresponding to the PCI device data to the address space of CXL memory; Set the system memory space as a testable area and test the system memory space based on the memory test program; The step of copying the global descriptor table, local descriptor table, and interrupt descriptor table from the system memory space to CXL memory includes: Disable interrupts, copy the global descriptor table to the CXL memory, and set the global descriptor table register GDTR to point to the new address of the global descriptor table in the CXL memory; Copy the local descriptor table to the CXL memory, and set the local descriptor table register LDTR to point to the new address of the local descriptor table in the CXL memory; Copy the interrupt descriptor table to CXL memory and enable interrupts.

2. The system memory testing method as described in claim 1, characterized in that, The step of copying the Basic Input / Output System BIOS program from the system memory space to the CXL memory includes: Copy the data corresponding to the program area of ​​the BIOS program in the system memory space to the address space of the CXL memory; Copy the data corresponding to the data area of ​​the BIOS program in the system memory space to the address space of the CXL memory; Copy the data corresponding to the reserved area of ​​the BIOS program in the system memory space to the address space of the CXL memory.

3. The system memory testing method as described in claim 1, characterized in that, The step of copying the interrupt descriptor table to CXL memory includes: Copy the interrupt descriptor table to the CXL memory; Copy the interrupt service routine from the system memory space to the CXL memory; Set the Interrupt Descriptor Table Register IDTR to the new address of the Interrupt Descriptor Table in the CXL memory.

4. The system memory testing method as described in claim 1, characterized in that, The step of establishing peripheral component interconnect (PCI) device data in CXL memory and pointing the device base address corresponding to the PCI device data to the address space of CXL memory includes: Disable interrupts and allocate memory-mapped input / output (MMIO) memory space in the address space of CXL memory; In the CXL memory, a PCI device tree corresponding to the PCI device data is established. The device base address corresponding to each PCI device data in the PCI device tree is pointed to the MMIO memory space, and interrupts are enabled.

5. The system memory testing method as described in claim 1, characterized in that, The steps of setting the system memory space as a testable area, loading the memory test program into CXL memory, and starting the memory test program to test the system memory space include: Modify the segment attributes of the system memory space to make the system memory space a testable region; Load the memory test program into the CXL memory and start the memory test program to test the system memory space.

6. The system memory testing method as described in claim 1, characterized in that, The step of mapping CXL memory to the high address space of memory includes: During system initialization, a memory mapping table is established to divide memory into segments; Based on the memory mapping table, CXL memory is mapped to the high address space of memory.

7. The system memory testing method according to any one of claims 1 to 6, characterized in that, The system memory testing method also includes: Determine the target memory region within the free memory region of the system memory space; Copy the BIOS program from the system memory space to the target memory area; Copy the global descriptor table, local descriptor table, and interrupt descriptor table from the system memory space to the target memory region respectively; Establish peripheral component interconnect PCI device data in the target memory region, and point the device base address corresponding to the PCI device data to the address space of the target memory region; The memory regions in the system memory space other than the target memory region are taken as the test regions, and the test regions are tested based on the memory test program; If the test area is completed, the test area is used as the target memory area, and the process returns to the step of copying the BIOS program from the system memory space to the target memory area.

8. A system memory testing device, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the system memory testing method as described in any one of claims 1 to 7.

9. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the system memory testing method as described in any one of claims 1 to 7.

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