Operation method of memory, memory and memory system

Abstract

The invention provides an operation method of a memory, the memory and a memory system, and relates to the technical field of semiconductor chips. The operating method includes applying a first program voltage to a first word line coupled to a first memory cell in a first program operation stage. In a first program operation stage, a first pass voltage is applied to a second word line coupled to a second memory cell, a difference between a threshold voltage of the second memory cell and a target threshold voltage being less than a first error value. Wherein the second word line is adjacent to the first word line, and the first programming voltage is greater than the first pass voltage. According to the embodiment of the invention, the coupling voltage of the first pass voltage on the second word line is utilized to enable the second storage unit to generate slight charge injection. Compared with the direct programming of the second memory cell, the threshold voltage change caused by the coupling voltage of the first pass voltage on the second word line is much smaller, so that the accurate adjustment of the threshold voltage of the second memory cell can be realized in a smaller range.

Description

Technical Field

[0001] This application belongs to the field of semiconductor chip technology, and in particular relates to a method for operating a memory, a memory, and a memory system. Background Technology

[0002] Flash memory is a type of storage device characterized by non-volatile data, fast read / write speeds, low power consumption, and long lifespan. It is widely used in various electronic products, such as mobile phones, computers, smart sensors, and positioning devices. With the development of computing in memory (CIM) technology, memory needs to ensure the accuracy of weighted data writing (also known as programming) to guarantee the accuracy of CIM calculations. Summary of the Invention

[0003] In a first aspect, this application provides a method for operating a memory. The method includes: during a first programming operation phase, applying a first programming voltage to a first word line coupled to a first memory cell; during the first programming operation phase, applying a first pass voltage to a second word line coupled to a second memory cell, wherein the difference between a threshold voltage of the second memory cell and a target threshold voltage is less than a first error value. Wherein, the second word line is adjacent to the first word line, and the first programming voltage is greater than the first pass voltage.

[0004] In some possible implementations, the coupling voltage on the second word line is greater than the first pass voltage.

[0005] In some possible implementations, the method further includes: during the first programming operation phase, applying a second pass voltage to a third word line, wherein the third word line is not adjacent to the first word line. The first programming voltage is greater than the second pass voltage.

[0006] In some possible implementations, the method further includes: during the first programming operation phase, verifying the threshold voltage of the second memory cell. In response to the difference between the threshold voltage of the second memory cell and the target threshold voltage being less than a second error value, applying a second pass voltage to the second word line. The second error value is less than a first error value.

[0007] In some possible implementations, the method further includes: during the second programming operation phase, applying a second programming voltage to the second word line and applying a second pass voltage to the first word line. The second programming operation phase occurs before the first programming operation phase.

[0008] In some possible implementations, the first through voltage is not less than the second through voltage.

[0009] In some possible implementations, the second programming voltage includes a plurality of pulse voltages that increase in sequence, wherein any pulse voltage in the second programming voltage is greater than the second pass voltage.

[0010] In some possible implementations, the method further includes: during the second programming operation phase, verifying the threshold voltage of the second memory cell. In response to the difference between the threshold voltage of the second memory cell and the target threshold voltage being less than a first error value, applying a second programming voltage to the first word line and applying a second pass voltage to the second word line.

[0011] In some possible implementations, the method further includes: during the second programming operation phase, verifying the threshold voltage of the second memory cell. In response to the difference between the threshold voltage of the second memory cell and the target threshold voltage being less than a first error value, applying a first programming voltage to the first word line and applying a first pass voltage to the second word line.

[0012] In some possible implementations, the first programming voltage includes a plurality of pulse voltages that increase in sequence, any one of the pulse voltages in the first programming voltage being greater than the second pass voltage.

[0013] In some possible implementations, the first programming voltage comprises a plurality of pulse voltages of the same voltage, wherein any pulse voltage in the first programming voltage is greater than the second pass voltage.

[0014] Secondly, this application provides a memory. The memory includes: a memory array comprising a plurality of memory cells, the plurality of memory cells including first memory cells and second memory cells; a plurality of word lines coupled to the plurality of memory cells, including first word lines and second word lines, the second word lines being adjacent to the first word lines, the first memory cells being coupled to the first word lines, and the second memory cells being coupled to the second word lines; and peripheral circuitry coupled to the plurality of word lines; the peripheral circuitry is configured to: during a first programming operation phase, apply a first programming voltage to the first word line and apply a first pass voltage to the second word line. Wherein, the difference between a threshold voltage of the second memory cell and a target threshold voltage is less than a first error value, and the first programming voltage is greater than the first pass voltage.

[0015] In some possible implementations, the coupling voltage on the second word line is greater than the first pass voltage.

[0016] In some possible implementations, the peripheral circuitry is further configured to apply a second pass voltage to a third word line during the first programming operation phase, wherein the third word line is not adjacent to the first word line. The first programming voltage is greater than the second pass voltage.

[0017] In some possible implementations, the peripheral circuitry is further configured to: verify the threshold voltage of the second memory cell during the first programming operation phase; and apply a second pass voltage to the second word line in response to the difference between the threshold voltage of the second memory cell and the target threshold voltage being less than a second error value, wherein the second error value is less than a first error value.

[0018] In some possible implementations, the peripheral circuitry is further configured to: apply a second programming voltage to the second word line and apply a second pass voltage to the first word line during the second programming operation phase. The second programming operation phase occurs before the first programming operation phase.

[0019] In some possible implementations, the first through voltage is not less than the second through voltage.

[0020] In some possible implementations, the second programming voltage includes a plurality of pulse voltages that increase in sequence, wherein any pulse voltage in the second programming voltage is greater than the second pass voltage.

[0021] In some possible implementations, the peripheral circuitry is further configured to: verify the threshold voltage of the second memory cell during the second programming operation phase. In response to the difference between the threshold voltage of the second memory cell and the target threshold voltage being less than a first error value, a second programming voltage is applied to the first word line, and a second pass voltage is applied to the second word line.

[0022] In some possible implementations, the peripheral circuitry is further configured to: verify the threshold voltage of the second memory cell during the second programming operation phase. In response to the difference between the threshold voltage of the second memory cell and the target threshold voltage being less than a first error value, a first programming voltage is applied to the first word line, and a first pass voltage is applied to the second word line.

[0023] In some possible implementations, the first programming voltage includes a plurality of pulse voltages that increase in sequence, any one of the pulse voltages in the first programming voltage being greater than the second pass voltage.

[0024] In some possible implementations, the first programming voltage comprises a plurality of pulse voltages of the same voltage, wherein any pulse voltage in the first programming voltage is greater than the second pass voltage.

[0025] Thirdly, this application provides a memory system. The memory system includes a memory controller and a memory according to any one of the second aspects described above, the memory controller being coupled to the memory and configured to control the memory. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this application.

[0027] Figure 1 This is a schematic diagram of the memory structure provided in an embodiment of this application;

[0028] Figure 2 This is a schematic diagram of the structure of a storage block provided in an embodiment of this application;

[0029] Figure 3 A partial cross-sectional schematic diagram of the storage string provided in an embodiment of this application;

[0030] Figure 4 This is a schematic diagram of the memory and peripheral circuitry provided in an embodiment of this application;

[0031] Figure 5 A schematic diagram illustrating the principle of in-memory computation provided in an embodiment of this application;

[0032] Figure 6 A flowchart illustrating the memory operation method provided in an embodiment of this application;

[0033] Figure 7 A schematic diagram of word line voltage application during the first programming operation stage provided in an embodiment of this application;

[0034] Figure 8 A schematic diagram of word line voltage application during the second programming operation stage provided in an embodiment of this application;

[0035] Figure 9 A schematic diagram of a voltage waveform applied to a word line by a peripheral circuit provided in an embodiment of this application;

[0036] Figure 10 This is a waveform diagram illustrating one method of sequentially fine-programming all memory cells in a continuous first programming operation phase, as provided in an embodiment of this application.

[0037] Figure 11 This is another waveform diagram illustrating the sequential fine programming of all memory cells during the first programming operation phase, as provided in an embodiment of this application.

[0038] Figure 12 A schematic diagram of another voltage waveform applied to the word line by the peripheral circuit provided in an embodiment of this application;

[0039] Figure 13 A schematic diagram of word line voltage application provided for an embodiment of this application, in which the first programming operation stage is hidden in the next adjacent second programming operation stage;

[0040] Figure 14 This is a schematic diagram of the memory system provided in an embodiment of this application.

[0041] Reference numerals: 100, Memory; 110, Memory array; 120, Peripheral circuit; 121, Control logic circuit; 122, I / O interface; 123, Voltage generator; 124, Column decoder; 125, Row decoder; 126, Page buffer; 127, Data bus; 128, Register; 200, Memory block; 210, Memory string; 211, Top select transistor; 212, Memory cell; 213, Bottom select transistor; 310, Semiconductor layer; 320, Stacked structure; 321, Gate conductive layer; 322, Dielectric layer; 410, Bit line; 420, Source line; 430, Top select line; 440, Word line; 450, Bottom select line; 400, Memory system; 500, Memory controller. Detailed Implementation

[0042] The following will combine Figures 1-14 The technical solutions in some embodiments of this application are clearly and completely described. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments provided in this application, all other embodiments obtained by those skilled in the art are within the scope of protection of this application.

[0043] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, a particular feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0044] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0045] In describing some embodiments, the term "coupled" and its derivative expressions may be used. For example, in describing some embodiments, the term "coupled" may be used to indicate that two or more components have direct physical or electrical contact; in this case, "coupled" can also be described as "connected." Furthermore, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0046] The use of “configured as” in this article implies an open and inclusive language that does not exclude the applicability to or configuration of devices to perform additional tasks or steps.

[0047] Figure 1 A schematic diagram of the structure of a memory provided in an embodiment of this application is shown. For example... Figure 1 As shown, the memory 100 may include a memory array 110 and peripheral circuits 120, with the memory array 110 coupled to the peripheral circuits 120. In some embodiments, the peripheral circuits 120 and the memory array 110 may be independently formed on two separate wafers using different semiconductor manufacturing processes. In some examples, the memory array 110 may be formed using mature process technologies (e.g., any process technology of 22nm, 28nm, and above) to ensure the stability of stored data. The peripheral circuits 120 may be formed using advanced process technologies (e.g., any process technology of 14nm, 10nm, and below) to help improve the speed of data reading / writing in the memory 100. The wafer on which the memory array 110 is formed (which may be called an array wafer) and the wafer on which the peripheral circuits 120 are formed (which may be called a CMOS wafer) are then bonded together using a bonding process, thereby coupling the peripheral circuits 120 to the memory array 110.

[0048] Storage array 110 may include memory blocks. For example... Figure 2As shown, in some embodiments, the memory block 200 may include multiple memory strings 210, one end of which is coupled to a bit line (BL) 410, and the other end of which is coupled to a source line (SL) 420. Each memory string 210 may include a top select gate (TSG), multiple memory cells 212, and a bottom select gate (BSG) stacked in series. In some embodiments, the memory cells 212 may be devices capable of storing charge, such as floating gate transistors or charge trap field-effect transistors.

[0049] Figure 3 A partial cross-sectional schematic diagram of a possible memory string is shown. The memory string 210 may extend vertically above the semiconductor layer 310. The semiconductor layer 310 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0050] The memory string 210 may include a channel structure extending through the stacked structure 320, which may include alternating gate conductive layers 321 and dielectric layers 322. The number of gate conductive layers 321 and dielectric layers 322 in the stacked structure 320 is related to the number of memory cells 212 in the memory string 210.

[0051] The gate conductive layer 321 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 321 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 321 includes a doped polysilicon layer. Each gate conductive layer 321 may include a control gate surrounding the memory cell 212, and the gate conductive layer 321 at the top of the stacked structure 320 may extend laterally and be coupled to the top select line (TSL) 430; the gate conductive layer 321 at the bottom of the stacked structure 320 may extend laterally and be coupled to the bottom select line (BSL) 450; or the gate conductive layer 321 between the top select line 430 and the bottom select line 450 may extend laterally and be coupled to the word line (WL) 440.

[0052] It should be understood that, despite Figure 3 Additional components, not shown, can form the memory string 210. These additional components include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0053] Please continue to refer to Figure 2 The memory strings 210 can be arranged in a row along a first direction, and multiple rows of memory strings 210 can be arranged in a second direction perpendicular to the first direction to form a memory block 200. In some embodiments, in the same row of memory strings 210, the gate of the top select transistor 211 of each memory string 210 can be coupled to the same top select line 430; in some embodiments, the gates of the top select transistors 211 of some rows of memory strings 210 can be coupled to the same top select line 430; memory strings 210 whose gates of the top select transistors 211 are coupled to the same top select line 430 can constitute a memory chip. The gate of the bottom select transistor 213 in each memory string 210 can be coupled to the same bottom select line 450. In some embodiments, the selected memory string 210 can be activated during read operations, programming operations, and erase operations via the top select line 430 and the bottom select line 450.

[0054] Each memory string 210 is coupled to the peripheral circuit 120 via a corresponding bit line 410. For example, the drain of the top selection transistor 211 in the memory string 210 is coupled to the bit line 410. In order to reduce the number of bit lines 410, the memory string 210 in any memory chip can be coupled to the same bit line 410 with the corresponding memory string 210 in other memory chips.

[0055] For multiple memory strings 210 in memory block 200, the control gate of memory cell 212 in any memory string 210 and the control gate of memory cell 212 at the corresponding position in other memory strings 210 can be coupled to the same word line 440. The source of the bottom select transistor 213 in memory string 210 can be coupled to the source line 420 (or, the common select line (CSL)).

[0056] It should be noted that the accompanying drawings of this application only exemplarily illustrate the structure of the storage block 200 in some embodiments, but in practice, the structure of the storage block 200 may also be in other ways.

[0057] like Figure 4As shown, in some embodiments, the peripheral circuitry 120 includes control logic circuitry 121, I / O interface 122, voltage generator 123, column decoder 124, row decoder 125, page buffer 126, data bus 127, and register 128. It should be understood that in some examples, it may also include... Figure 4 Additional circuitry not shown.

[0058] The control logic circuit 121 can be coupled to the voltage generator 123, page buffer 126, column decoder 124, row decoder 125, and I / O interface 122, and is configured to control the operation of each peripheral circuit. The control logic circuit 121 can generate operation signals in response to commands (CMDs) or control signals received from the I / O interface 122 to control the operation of the row decoder 125, column decoder 124, page buffer 126, and voltage generator 123; wherein the command can be a programming command, a read command, etc.

[0059] I / O interface 122 can be coupled to control logic circuitry 121 and act as a control buffer to buffer received control commands and relay them to control logic circuitry 121, as well as to buffer status information received from control logic circuitry 121 and relay it to the host. I / O interface 122 can also be coupled to page buffer 126 via data bus 127 and act as data I / O interface 122 and data buffer to buffer data and relay it to or from memory array 110.

[0060] Voltage generator 123 can use external or internal power supply voltages to generate various voltages for performing operations such as erasing, programming, reading, and verifying on memory array 110; for example, programming voltage Vpgm applied to word line 440, erase voltage Vera, and ground voltage Vss, as well as combinations thereof.

[0061] The column decoder 124 can be controlled by the control logic circuit 121 and can select one or more memory strings 210 in the memory array 110 by applying a voltage to the bit line 410 generated from the voltage generator 123.

[0062] The row decoder 125 can, in response to control of the control logic circuit 121, supply the word line 440 voltage generated from the voltage generator 123 to the selected word lines and non-selected word lines of the memory array 110. As described in detail below, the row decoder 125 is configured to perform programming operations on memory cells 100 coupled to one or more select word lines in the memory array 110.

[0063] Page buffer 126 is coupled to memory array 110 via bit line 410. In some examples, page buffer 126 can read data from memory array 110 and program (write) data to memory array 110 according to control signals from control logic circuitry 121. In other examples, page buffer 126 can store programming data to be programmed into memory array 110 (write data). In still other examples, page buffer 126 can also perform programming verification operations to ensure that data has been correctly programmed into memory cells 212 coupled to select word lines.

[0064] Register 128 can be coupled to control logic circuit 121 and includes a status register, a command register and an address register for storing status information, command opcode (OP code) and command address for controlling the operation of each peripheral circuit 120.

[0065] Those skilled in the art will understand that the operations performed by the line decoder 125, page buffer 126, control logic circuit 121, and voltage generator 123 described in this application can be performed by a processing circuit. This processing circuit may include, but is not limited to, hardware of logic circuits or a hardware / software combination of a processor executing software.

[0066] The peripheral circuit 120 is used to control the memory array 110. In some examples, the peripheral circuit 120 can perform a programming operation on the memory cells 212 in the memory array 110 to store charge in the memory cells 212, thereby writing data "0". In some examples, the peripheral circuit 120 can perform an erase operation on the memory cells 212 to remove (or neutralize) the charge stored in the memory cells 212, thereby writing data "1". The charge stored in the memory cells 212 can generate an electric field, which in turn affects the threshold voltage (Vt) of the memory cells 212; in some examples, the more charge (e.g., electrons) stored in the memory cells 212, the higher the threshold voltage of the memory cells 212. The peripheral circuit 120 can perform a read operation on the memory cells 212 in the memory array 110 to determine the threshold voltage distribution range in which the threshold voltage of the memory cells 212 falls, thereby reading the data stored in the memory cells 212.

[0067] In some implementations, computing functions can be embedded in the memory 100 to enable in-memory computing, thereby reducing unnecessary data movement. In particular, for artificial intelligence (AI) applications that require matrix operations on large amounts of data (e.g., large models), in-memory computing can significantly reduce data transmission power consumption and latency. Figure 5 As shown, in some examples, the voltage value V used to indicate the input data will be... in (For example Figure 5 Vin shown <1> and Vin <2> ) is applied to bit line 410 coupled to memory array 110 and to select word line (e.g. Figure 5 A voltage V1 is applied to WL1, thereby using the conductance value of the memory cell 212 coupled to the select word line as weight data; wherein, the weight data μ is the charge mobility, C ox V is the gate oxide capacitance of memory cell 212, W is the channel width of memory cell 212, L is the channel length of memory cell 212, and V is the gate oxide capacitance of memory cell 212. GS V is the gate-source voltage of memory cell 212. TH This is the threshold voltage for memory cell 212. Simultaneously, it applies voltage to the non-select word line (e.g., ...). Figure 5 A voltage V2 is applied to WL1 and WL2 in the memory string 210, thereby turning on the memory cell 212 coupled to the non-select word line. Based on Kirchhoff's laws and Ohm's law, the currents on each memory string 210 can be added together on the source line 420 to obtain the output current (i.e., ...). Figure 5 The I shown out <ij>< / ij> ); where I out＜ij＞ =Σω ＜ij＞ ×V in＜i＞ This enables the multiplication and addition of weighted data and input data.

[0068] As can be seen, the weight data (i.e., conductance value) of storage cell 212 is related to the threshold voltage of storage cell 212. By adjusting the threshold voltage of storage cell 212 through programming operations, the weight data (i.e., conductance value) of storage cell 212 can be adjusted. Since the accuracy of adjusting the weight data (i.e., conductance value) of storage cell 212 is a key factor affecting the accuracy of in-memory computing, simply reducing the programming voltage in the programming operation is insufficient to achieve a more refined adjustment of the weight data (i.e., conductance value). A more precise adjustment of the threshold voltage of storage cell 212 is required to ensure the accuracy of in-memory computing. It should be understood that the embodiments of this application are not limited to in-memory computing technology; the embodiments of this application are still applicable in other scenarios where precise adjustment of the threshold voltage of storage cell 212 through programming operations is required.

[0069] This application provides a method for operating a memory. For example... Figure 6 As shown, the operation method includes S110-S130, as follows:

[0070] S110. In the first programming operation phase, the peripheral circuit applies a first programming voltage to the first word line coupled to the first memory cell, and applies a first pass voltage to the second word line coupled to the second memory cell.

[0071] In some embodiments, the programming operation of the storage unit 212 can include multiple programming cycles. In some examples, a single programming cycle can include a channel preparation phase (may also be referred to as a pre-charge phase) and a program phase. In other examples, a single programming cycle can include a channel preparation phase, a program phase, and a verify phase.

[0072] In the program phase, a program voltage Vpgm is applied to the selected WL, and a pass voltage Vpass is applied to the unselected WLs. The program voltage Vpgm causes a large voltage difference between the gate and the channel of the storage unit 212, which enables the injection of charges into the floating gate layer (or, charge trap) of the storage unit 212 to achieve programming of the storage unit 212. Although the pass voltage Vpass loaded on the unselected WLs is lower than the program voltage Vpgm, due to the capacitive coupling effect between adjacent WLs, the coupled voltage on the unselected WLs adjacent to the selected WL will be greater than the pass voltage in the above-mentioned program phase, which can cause slight charge injection to the storage units 212 coupled to the unselected WLs adjacent to the selected WL, thereby achieving fine adjustment of the threshold voltage of the storage units 212.

[0073] In the first programming operation phase, the difference between the threshold voltage of the second storage unit and the target threshold voltage is already less than the first error value in the embodiments of the present application. The first programming operation phase is used to finely adjust the threshold voltage of the second storage unit, as shown in Figure 7 In some examples, in the program phase of the first programming operation phase, the peripheral circuit 120 applies a first program voltage Vpgm1 to the first word line (e.g., WL2 in Figure 7 In some examples, in the program phase of the first programming operation phase, the peripheral circuit 120 applies a first program voltage Vpgm1 to the first word line (e.g., WL2 in Figure 7 Due to the capacitive coupling effect, the coupled voltage on the second word line will be greater than the first pass voltage Vpass1. In some embodiments, the peripheral circuit can apply the first pass voltage Vpass1 or a second pass voltage Vpass2 to the fourth word line (e.g., WL3 in Figure 7 In some embodiments, the peripheral circuit 120 also applies a third pass voltage Vpass3 to the third word line (e.g., WL0 in Figure 7 The second pass voltage Vpass2 is applied to the second word line WL6 in the second memory cell 212. In the programming phase of the first programming operation phase, the coupling voltage of the first pass voltage Vpass1 on the second word line causes slight charge injection of the second memory cell. Compared with directly programming the second memory cell (i.e., applying a programming voltage to the second word line), the threshold voltage change caused by the coupling voltage of the first pass voltage Vpass1 on the second word line is much smaller, so that the threshold voltage of the second memory cell can be precisely adjusted in a smaller range, which can better guarantee the accuracy of in-memory computing.

[0074] In some embodiments, the first programming voltage Vpgm1 can include a plurality of pulse voltages with sequentially stepped increases. That is, the first programming operation phase adopts incremental step pulse programming (ISPP), and the programming voltage of each programming cycle in the first programming operation phase is stepped and increased. In other embodiments, the first programming voltage Vpgm2 includes a plurality of pulse voltages with the same voltage, that is, the programming voltage of each programming cycle in the first programming operation phase is the same.

[0075] In some embodiments, the first pass voltage Vpass1 is not less than the second pass voltage Vpass2. By appropriately increasing the pass voltage, the charge injection of the second memory cell in the first programming operation phase can be appropriately enhanced, so that the time required for precisely adjusting the threshold voltage of the memory cell 212 can be optimized.

[0076] S120, in the first programming operation phase, the peripheral circuit verifies the threshold voltage of the second memory cell.

[0077] In some embodiments, each programming cycle of the first programming operation phase includes a programming phase and a verification phase. In the same programming cycle, the verification phase is after the programming phase. In the verification phase of the first programming operation phase, the peripheral circuit 120 applies a verification voltage Vvfy to the second word line to verify the threshold voltage of the second memory cell. If the threshold voltage of the second memory cell is less than the verification voltage Vvfy, the discharge rate of the sensing node SO in the page buffer 126 coupled with the second memory cell is larger. Moreover, the greater the difference between the verification voltage Vvfy and the threshold voltage of the second memory cell, the greater the discharge rate of the sensing node (SO), and the smaller the sensing node voltage V SO after the sensing development duration. If the threshold voltage of the second memory cell is greater than the verification voltage Vvfy, the discharge rate of the sensing node SO in the page buffer 126 coupled with the second memory cell is small, and the sensing node voltage V SO after the sensing development duration is larger.

[0078] S130, in response to the threshold voltage of the second storage unit satisfying the condition of successful programming, the peripheral circuit applies a second pass voltage to the second word line.

[0079] In some embodiments, the setting of the verification voltage Vvfy is related to the target threshold voltage. After the sensing development time elapses, if the sensing node voltage V SO is less than the threshold voltage Vtrip, it indicates that the difference between the threshold voltage of the second storage unit and the verification voltage Vvfy is large. At this time, it can be considered that the difference between the threshold voltage of the second storage unit and the target threshold voltage is not less than the second error value. The peripheral circuit 120 keeps applying the first pass voltage Vpass1 to the second word line, so as to continue adjusting the threshold voltage of the second storage unit in the direction of reducing the difference between the threshold voltage of the second storage unit and the target threshold voltage. After the sensing development time elapses, if the sensing node voltage V SO is greater than the threshold voltage Vtrip, it indicates that the difference between the threshold voltage of the second storage unit and the verification voltage Vvfy is small. At this time, it can be considered that the difference between the threshold voltage of the second storage unit and the target threshold voltage is less than the second error value.

[0080] In some embodiments, when the difference between the threshold voltage of the second storage unit and the target threshold voltage is less than the second error value, the pass voltage applied to the second word line can be appropriately reduced; for example, from the first pass voltage Vpass1 to the second pass voltage Vpass2, so as to weaken or even overcome the pass voltage interference on the second storage unit.

[0081] In some embodiments, the verification of the threshold voltage of the second storage unit can also be verification of whether the second storage unit is successfully programmed, for example, it can be verified whether the number of second storage units whose threshold voltage reaches the target threshold voltage is less than or equal to a threshold value, if yes, it can be indicated that the second storage unit is successfully programmed, and the pass voltage applied to the second word line can be appropriately reduced to weaken or even overcome the pass voltage interference on the second storage unit; if not, it can be indicated that the second storage unit is not successfully programmed, and the adjustment of the threshold voltage of the second storage unit needs to be continued.

[0082] Please continue to refer to Figure 6 In some embodiments, in order to make the difference between the threshold voltage of the second storage unit and the target threshold voltage less than the first error value, before the first programming operation (which can be referred to as fine programming) stage, the operation method provided by the embodiments of the present application further includes S210-S220, as follows:

[0083] S210, in the second programming operation stage, the peripheral circuit applies a second programming voltage to the second word line and a second pass voltage to the first word line.

[0084] In some implementations, the second programming voltage Vpgm2 comprises a plurality of pulse voltages that increase sequentially in steps, where any pulse voltage in the second programming voltage Vpgm2 is greater than the second pass voltage. That is, the second programming operation stage precedes the first programming operation stage, and the second programming operation stage employs incremental steppulse programming (ISPP). In the second programming operation (which can be called coarse programming), the threshold voltage of the second memory cell can be rapidly brought close to the target threshold voltage. Figure 8 As shown, in some examples, during the programming phase of the second programming operation, the peripheral circuit 120, in addition to directing input to the second word line (e.g., ...), Figure 8 Apply a second programming voltage Vpgm2 to WL1 in the first word line (e.g., WL1) to the first word line (e.g., WL1). Figure 8 In addition to applying a second pass voltage Vpass2 to WL2, a third word line (e.g., ...) is also applied to the third word line. Figure 8 WL4-WL6) and the fourth letter line (e.g.) Figure 8 Apply a second pass voltage Vpass2 to WL3.

[0085] In some implementations, the voltage value of any pulse voltage in the first programming voltage Vpgm1 is less than the voltage value of the first pulse voltage in the second programming voltage Vpgm2; or, less than the voltage value of the Mth pulse voltage in the second programming voltage Vpgm2.

[0086] S220. In the second programming operation stage, the peripheral circuit verifies the threshold voltage of the second memory cell.

[0087] Similar to S120, each programming cycle of the second programming operation phase includes a programming phase and a verification phase. Within the same programming cycle, the verification phase follows the programming phase. During the verification phase of the second programming operation phase, the peripheral circuit 120 also applies a verification voltage Vvfy to the second word line to verify the threshold voltage of the second memory cell. If the threshold voltage of the second memory cell is less than the verification voltage Vvfy, the discharge rate of the sensing node SO in the page buffer 126 coupled to the second memory cell is greater. Furthermore, the greater the difference between the verification voltage Vvfy and the threshold voltage of the second memory cell, the greater the discharge rate of the sensing node SO, and the greater the discharge rate of the sensing node voltage Vvfy after the sensing development time. SO The smaller the value. If the threshold voltage of the second memory cell is greater than the verification voltage Vvfy, then the discharge rate of the sensing node SO in the page buffer 126 coupled to the second memory cell is small, and the sensing node voltage Vvfy after the sensing development time is small. SO The larger.

[0088] Unlike S120, the sensing development duration for discharging the sensing node SO in the verification phase of the second programming operation stage can be different from that in the verification phase of the first programming operation stage; or, the verification voltage Vvfy applied to the second word line can be different. In some examples, the sensing development duration for discharging the sensing node SO in the verification phase of the first programming operation stage is a first duration; and the sensing development duration for discharging the sensing node SO in the verification phase of the second programming operation stage is a second duration. The first duration is longer than the second duration. In some examples, the verification voltage Vvfy applied to the second word line in the verification phase of the first programming operation stage is a first verification voltage; and the verification voltage Vvfy applied to the second word line in the verification phase of the second programming operation stage is a second verification voltage. The difference between the target threshold voltage and the first verification voltage is less than the difference between the target threshold voltage and the second verification voltage.

[0089] Figure 9 This diagram illustrates a voltage waveform applied to a word line by an external circuit. For example... Figure 9 As shown, in the programming stage of the first second programming operation, the peripheral circuit 120 applies a second programming voltage Vpgm2 to the word line WLn and a second pass voltage Vpass2 to the word lines WLn+1, WLn+2, and other word lines WLs. This is to perform coarse programming on the memory cell 212 coupled to the word line WLn, so that the threshold voltage of the memory cell 212 coupled to the word line WLn can quickly approach the target threshold voltage. In the verification stage of the first second programming operation, the peripheral circuit 120 applies a verification voltage Vvfy to the word line WLn and a pass voltage Vpass to the word lines WLn+1, WLn+2, and other word lines WLs. This is to verify whether the difference between the threshold voltage of the memory cell 212 coupled to the word line WLn and the target threshold voltage is less than a first error value.

[0090] In the programming phase of the second programming operation, the peripheral circuit 120 applies a second programming voltage Vpgm2 to word line WLn+1 and a second pass voltage Vpass2 to word lines WLn, WLn+2, and other word lines WLs. This is to perform coarse programming on the memory cell 212 coupled to word line WLn+1, allowing the threshold voltage of the memory cell 212 coupled to word line WLn+1 to quickly approach the target threshold voltage. In the verification phase of the second programming operation, the peripheral circuit 120 applies a verification voltage Vvfy to word line WLn+1 and a pass voltage Vpass to word lines WLn, WLn+2, and other word lines WLs. This is to verify whether the difference between the threshold voltage of the memory cell 212 coupled to word line WLn+1 and the target threshold voltage is less than a first error value.

[0091] In the programming phase of the first programming operation, the peripheral circuit 120 applies a first programming voltage Vpgm1 to word line WLn+1, a first pass voltage Vpass1 to word line WLn, and a second pass voltage Vpass2 to word line WLn+2 and other word lines WLs. This is to fine-program the memory cell 212 coupled to word line WLn, finely adjusting the threshold voltage of the memory cell 212 coupled to word line WLn. In the verification phase of the first programming operation, the peripheral circuit 120 applies a verification voltage Vvfy to word line WLn, and a pass voltage Vpass to word lines WLn+1, WLn+2, and other word lines WLs. This is to verify whether the difference between the threshold voltage of the memory cell 212 coupled to word line WLn and the target threshold voltage is less than a second error value.

[0092] As described above, the first programming voltage Vpgm1 may include multiple pulse voltages that increase sequentially in steps; or, the first programming voltage Vpgm2 may include multiple pulse voltages with the same voltage. Furthermore, the voltage value of any pulse voltage in the first programming voltage Vpgm1 is less than the voltage value of the first pulse voltage in the second programming voltage Vpgm2; or, less than the voltage value of the Mth pulse voltage in the second programming voltage Vpgm2. In other words, the first programming voltage Vpgm1 and the second programming voltage Vpgm2 are different; the first programming voltage Vpgm1 is not the programming voltage used in conventional programming operations.

[0093] In the programming phase of the second first programming operation, the peripheral circuit 120 applies a first programming voltage Vpgm1 to word line WLn+2, a first pass voltage Vpass1 to word line WLn+1, and a second pass voltage Vpass2 to word line WLn and other word lines WLs. This is to fine-program the memory cell 212 coupled to word line WLn, finely adjusting the threshold voltage of the memory cell 212 coupled to word line WLn+1. In the verification phase of the second first programming operation, the peripheral circuit 120 applies a verification voltage Vvfy to word line WLn+1, and a pass voltage Vpass to word lines WLn, WLn+2, and other word lines WLs. This is to verify whether the difference between the threshold voltage of the memory cell 212 coupled to word line WLn+1 and the target threshold voltage is less than a second error value.

[0094] Please continue to refer to Figure 9 The first second programming operation stage is consecutive to the second second programming operation stage, and the first first programming operation stage is consecutive to the second first programming operation stage. That is to say, the peripheral circuit 120 can first complete the coarse programming of all memory cells 212 in the order of word lines 440, and then perform fine programming of all memory cells 212 in the order of word lines 440.

[0095] In the case of multiple consecutive first programming operation stages, the waveform of this application performing fine programming on all memory cells 212 sequentially according to word line 440 can also be as follows: Figure 10 and Figure 11 As shown.

[0096] like Figure 10 As shown, in the programming stage of the first programming operation, the peripheral circuit 120 applies a first programming voltage Vpgm1 to word line WLn+1, a first pass voltage Vpass1 to word lines adjacent to word line WLn+1 (i.e., word lines WLn and WLn+2), and a second pass voltage Vpass2 to word lines not adjacent to word line WLn+1 (i.e., word lines WLn+3, WLn+4, WLn+5, and other word lines WLs). At this time, the coupling voltage on word lines WLn and WLn+2 is greater than the first pass voltage Vpass1, and a slight charge injection occurs in the memory cells coupled to word lines WLn and WLn+2, thereby finely adjusting the threshold voltage of the memory cells 212 coupled to word lines WLn and WLn+2; that is, fine programming is performed on the memory cells 212 coupled to word lines WLn and WLn+2 simultaneously. Accordingly, during the verification phase of the first programming operation, the peripheral circuit 120 applies a verification voltage Vvfy to the word line WLn to verify whether the difference between the threshold voltage and the target threshold voltage of the memory cell 212 coupled to the word line WLn is less than a second error value. Similarly, a verification voltage Vvfy is applied to the word line WLn+2 to verify whether the difference between the threshold voltage and the target threshold voltage of the memory cell 212 coupled to the word line WLn+2 is less than the second error value. It should be understood that the application of the verification voltage Vvfy to the word line WLn and the application of the verification voltage Vvfy to the word line WLn+2 by the peripheral circuit 120 can be performed separately at different time points during the verification phase.

[0097] In the programming phase of the second first programming operation, the peripheral circuit 120 applies a first programming voltage Vpgm1 to the word line adjacent to word line WLn+1 (e.g., word line WLn+2), applies a first pass voltage Vpass1 to word line WLn+1, and applies a second pass voltage Vpass2 to word line WLn and word lines not adjacent to word line WLn+1 (i.e., word lines WLn+3, WLn+4, WLn+5, and other word lines WLs). This is to fine-program the memory cell 212 coupled to word line WLn+1, finely adjusting the threshold voltage of the memory cell 212 coupled to word line WLn+1. In the verification phase of the second first programming operation, the peripheral circuit 120 applies a verification voltage Vvfy to word line WLn+1 and applies pass voltage Vpass to word lines WLn, WLn+2, and other word lines WLs. This is to verify whether the difference between the threshold voltage of the memory cell 212 coupled to the word line WLn and the target threshold voltage is less than the second error value.

[0098] For detailed programming of word lines WLn+3, WLn+4, and WLn+5, please refer to [reference needed]. Figure 10 The above descriptions regarding the fine programming of word lines WLn, WLn+1, and WLn+2 will not be repeated here.

[0099] like Figure 11 As shown, in the programming stage of the first programming operation, the peripheral circuit 120 applies a first programming voltage Vpgm1 to word line WLn+1, a first pass voltage Vpass1 to word line WLn, a third pass voltage Vpass3 to word line WLn+2, and a second pass voltage Vpass2 to word lines WLn+3, WLn+4, and other word lines WLs. The third pass voltage Vpass3 is located between the second pass voltage Vpass2 and the first pass voltage Vpass1. This is to fine-program the memory cell 212 coupled to word line WLn, finely adjusting the threshold voltage of the memory cell 212 coupled to word line WLn. In the verification stage of the first programming operation, the peripheral circuit 120 applies a verification voltage Vvfy to word line WLn, and a pass voltage Vpass to word lines WLn+1, WLn+2, WLn+3, WLn+4, and other word lines WLs. This is to verify whether the difference between the threshold voltage of the memory cell 212 coupled to the word line WLn and the target threshold voltage is less than the second error value.

[0100] In the programming phase of the second first programming operation, the peripheral circuit 120 applies a first programming voltage Vpgm1 to word line WLn+2, a first pass voltage Vpass1 to word line WLn+1, a third pass voltage Vpass3 to word line WLn+3, and a second pass voltage Vpass2 to word lines WLn, WLn+4, and other word lines WLs. This is to fine-program the memory cell 212 coupled to word line WLn, finely adjusting the threshold voltage of the memory cell 212 coupled to word line WLn. In the verification phase of the second first programming operation, the peripheral circuit 120 applies a verification voltage Vvfy to word line WLn+1, and a pass voltage Vpass to word lines WLn, WLn+2, WLn+3, WLn+4, and other word lines WLs. This is to verify whether the difference between the threshold voltage of the memory cell 212 coupled to word line WLn+1 and the target threshold voltage is less than a second error value.

[0101] Figure 12 This diagram illustrates another voltage waveform applied to the word line by the peripheral circuitry. (Compared to...) Figure 9 The difference is that, in Figure 12 In the waveform diagram shown, the first second programming operation stage is consecutive to the first first programming operation stage, and the second second programming operation stage is consecutive to the second first programming operation stage. That is, the peripheral circuit 120 can perform coarse programming on the memory cell 212 coupled to one word line, and then fine programming on the memory cell 212 coupled to that word line. Then, coarse programming and fine programming are performed sequentially on the memory cell 212 coupled to the next word line.

[0102] like Figure 13 As shown, in some embodiments, the peripheral circuit 120 may first perform a second programming operation on the memory cell 212 coupled to the word line WLn (i.e., apply a second programming voltage Vpgm2 to the word line WLn), and then perform a second programming operation on the memory cell 212 coupled to the word line WLn+1 (i.e., apply a second programming voltage Vpgm2 to the word line WLn+1). In some examples, the voltage pulses in the first programming voltage Vpgm1 may be the first few voltage pulses in the second programming voltage Vpgm2. Thus, while performing the second programming operation on the memory cell 212 coupled to the word line WLn+1, the first programming operation is performed on the memory cell 212 coupled to the word line WLn using the coupling voltage Vcoup on the word line WLn. In other words, the embodiments of this application can use the first few voltage pulses of the second programming voltage Vpgm2 to fine program the memory cell 212 coupled to the adjacent word line, thereby hiding the first programming operation stage (i.e., fine programming) in the next adjacent second programming operation stage (i.e., coarse programming) to reduce programming time.

[0103] It should be understood that the second programming voltage Vpgm2 comprises multiple voltage pulses with progressively increasing voltage values. Each time a voltage pulse of the second programming voltage Vpgm2 is applied to word line 440, a verification voltage is applied to the corresponding word line to verify whether the memory cell 212 coupled to that word line has passed coarse programming. Similarly, the first programming voltage Vpgm1 also comprises multiple voltage pulses. Each time a voltage pulse of the first programming voltage Vpgm1 is applied to word line 440, a verification voltage is applied to the corresponding adjacent word line to verify whether the memory cell 212 coupled to the adjacent word line has passed fine programming.

[0104] like Figure 14 As shown, this application provides a memory system 400, which includes a memory controller 500 and a memory controller 500. Figure 1 The memory 100 is shown. A memory controller 500 is coupled to the memory 100. In some embodiments, the memory controller 500 can send various commands (e.g., programming commands, read commands, and erase commands) to the memory 100 based on instructions received from the host to control the operation of the memory 100 (e.g., programming operations, read operations, and erase operations). Specifically, when the memory 100 performs a programming operation, the memory 100 can perform operations such as... Figure 6 The operating method is shown.

[0105] It should be understood that the memory controller 500 can also be configured to manage various functions related to data stored or to be stored in the storage device, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. Of course, the memory controller 500 can also perform any other suitable functions (e.g., formatting the memory 100), which will not be elaborated here.

[0106] In some implementations, the memory controller 500 and one or more memories 100 can be packaged into different types of electronic products. In some examples, the memory controller 500 and a single memory 100 can be integrated into a memory card. The memory card can include a PCMCIA card, a compact flash (CF) card, a smart media (SM) card, a memory stick, a multi-media card (MMC), and a secure digital (SD) card, etc. The memory card may further include a memory card connector that couples the memory card to a host. In other examples, the memory controller 500 and multiple memories 100 can be integrated into a solid state disk (SSD). The SSD may further include a solid state disk connector that couples the SSD to a host. In some implementations, the storage capacity and / or operating speed of the SSD is greater than the storage capacity and / or operating speed of the memory card.

[0107] The memory controller 500 can communicate with external devices (e.g., a host) via at least one of various interface protocols. The interface protocol can be at least one of the following: Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-E protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, and Integrated Drive Electronics (IDE) protocol.

[0108] In some implementations, the memory system 400 can be applied to different types of electronic devices, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, and any other electronic device capable of storing data.

[0109] This application provides an operation method, memory, and memory system for a memory. The operation method includes: in a first programming operation phase, applying a first programming voltage to a first word line coupled to a first memory cell; in the first programming operation phase, applying a first through voltage to a second word line coupled to a second memory cell, wherein the difference between a threshold voltage of the second memory cell and a target threshold voltage is less than a first error value; wherein the second word line is adjacent to the first word line, and the first programming voltage is greater than the first through voltage. In the programming phase of the first programming operation phase, the coupling voltage of the first through voltage on the second word line causes a slight charge injection into the second memory cell. Compared to directly programming the second memory cell, the threshold voltage change caused by the coupling voltage of the first through voltage on the second word line is much smaller, thus allowing for precise adjustment of the threshold voltage of the second memory cell within a smaller range, and better ensuring the accuracy of in-memory calculations.

[0110] This application provides a computer-readable storage medium storing computer-executable instructions; when executed, the computer-executable instructions can achieve the following: Figure 6 The method shown.

[0111] This application provides a computer device including a processor and a readable storage medium coupled to the processor. The readable storage medium stores executable instructions, which, when executed by the processor, can achieve the following: Figure 6 The method shown.

[0112] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the descriptions of each embodiment in the above embodiments have different focuses. For parts not described in detail in a certain embodiment, refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0113] In the embodiments provided in this application, it should be understood that the provided memory, memory operation method, and memory system can be implemented in other ways. For example, the division of a certain module is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0114] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0115] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for operating a memory, characterized in that, The operation method includes: During the first programming operation phase, a first programming voltage is applied to the first word line coupled to the first memory cell; During the first programming operation phase, a first pass voltage is applied to the second word line coupled to the second memory cell, and the difference between the threshold voltage of the second memory cell and the target threshold voltage is less than a first error value. Wherein, the second word line is adjacent to the first word line, and the first programming voltage is greater than the first pass voltage.

2. The operating method according to claim 1, characterized in that, The coupling voltage on the second word line is greater than the first pass voltage.

3. The operating method according to claim 1, characterized in that, Also includes: During the first programming operation phase, a second pass voltage is applied to the third word line, which is not adjacent to the first word line; Wherein, the first programming voltage is greater than the second pass voltage.

4. The operating method according to claim 1, characterized in that, Also includes: During the first programming operation phase, the threshold voltage of the second memory cell is verified; In response to the difference between the threshold voltage of the second memory cell and the target threshold voltage being less than a second error value, a second pass voltage is applied to the second word line; The second error value is smaller than the first error value.

5. The operating method according to claim 1, characterized in that, Also includes: In the second programming operation phase, a second programming voltage is applied to the second word line, and a second pass voltage is applied to the first word line; The second programming operation stage occurs before the first programming operation stage.

6. The operating method according to any one of claims 3-5, characterized in that, The first through voltage is not less than the second through voltage.

7. The operating method according to claim 5, characterized in that, The second programming voltage includes a plurality of pulse voltages that increase in sequence, wherein any pulse voltage in the second programming voltage is greater than the second pass voltage.

8. The operating method according to claim 5, characterized in that, Also includes: During the second programming operation phase, the threshold voltage of the second memory cell is verified; In response to the difference between the threshold voltage of the second memory cell and the target threshold voltage being less than the first error value, the second programming voltage is applied to the first word line, and the second pass voltage is applied to the second word line.

9. The operating method according to claim 5, characterized in that, Also includes: During the second programming operation phase, the threshold voltage of the second memory cell is verified; In response to the difference between the threshold voltage of the second memory cell and the target threshold voltage being less than the first error value, the first programming voltage is applied to the first word line and the first pass voltage is applied to the second word line.

10. The operating method according to claim 9, characterized in that, The first programming voltage includes a plurality of pulse voltages that increase in sequence, and any pulse voltage in the first programming voltage is greater than the second pass voltage.

11. The operating method according to claim 8 or 9, characterized in that, The first programming voltage includes multiple pulse voltages of the same voltage, and any pulse voltage in the first programming voltage is greater than the second pass voltage.

12. A memory, characterized in that, include: A storage array, the storage array comprising a plurality of storage units, the plurality of storage units including a first storage unit and a second storage unit; Multiple word lines are coupled to multiple memory cells, and include a first word line and a second word line, wherein the second word line is adjacent to the first word line, the first memory cell is coupled to the first word line, and the second memory cell is coupled to the second word line; as well as Peripheral circuitry, coupled to the plurality of word lines; the peripheral circuitry is configured to: In the first programming operation phase, a first programming voltage is applied to the first word line, and a first pass voltage is applied to the second word line; Wherein, the difference between the threshold voltage of the second storage cell and the target threshold voltage is less than the first error value, and the first programming voltage is greater than the first pass voltage.

13. The memory according to claim 12, characterized in that, The coupling voltage on the second word line is greater than the first pass voltage.

14. The memory according to claim 12, characterized in that, The peripheral circuit is also configured to: During the first programming operation phase, a second pass voltage is applied to the third word line, which is not adjacent to the first word line; Wherein, the first programming voltage is greater than the second pass voltage.

15. The memory according to claim 12, characterized in that, The peripheral circuit is also configured to: During the first programming operation phase, the threshold voltage of the second memory cell is verified; In response to the difference between the threshold voltage of the second memory cell and the target threshold voltage being less than a second error value, a second pass voltage is applied to the second word line; The second error value is smaller than the first error value.

16. The memory according to claim 12, characterized in that, The peripheral circuit is also configured to: In the second programming operation phase, a second programming voltage is applied to the second word line, and a second pass voltage is applied to the first word line; The second programming operation stage occurs before the first programming operation stage.

17. The memory according to any one of claims 14-16, characterized in that, The first through voltage is not less than the second through voltage.

18. The memory according to claim 16, characterized in that, The second programming voltage includes a plurality of pulse voltages that increase in sequence, wherein any pulse voltage in the second programming voltage is greater than the second pass voltage.

19. The memory according to claim 16, characterized in that, The peripheral circuit is also configured to: During the second programming operation phase, the threshold voltage of the second memory cell is verified; In response to the difference between the threshold voltage of the second memory cell and the target threshold voltage being less than the first error value, the second programming voltage is applied to the first word line, and the second pass voltage is applied to the second word line.

20. The memory according to claim 16, characterized in that, The peripheral circuit is also configured to: During the second programming operation phase, the threshold voltage of the second memory cell is verified; In response to the difference between the threshold voltage of the second memory cell and the target threshold voltage being less than the first error value, the first programming voltage is applied to the first word line and the first pass voltage is applied to the second word line.

21. The memory according to claim 20, characterized in that, The first programming voltage includes a plurality of pulse voltages that increase in sequence, and any pulse voltage in the first programming voltage is greater than the second pass voltage.

22. The memory according to claim 19 or 20, characterized in that, The first programming voltage includes multiple pulse voltages of the same voltage, and any pulse voltage in the first programming voltage is greater than the second pass voltage.

23. A memory system, characterized in that, Includes a memory controller and the memory as described in any one of claims 12-22, wherein the memory controller is coupled to the memory and the memory controller is configured to control the memory.

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