Method of manufacturing a semiconductor structure

Abstract

The application provides a preparation method of a semiconductor structure, comprising the following steps: forming a first sacrificial layer on one side of a layer to be etched; forming a mask layer on the side of the first sacrificial layer away from the layer to be etched; forming a first opening and a second opening in the mask layer, the first opening penetrating through the mask layer, and the thickness of the mask layer on the side of the layer to be etched is greater than zero; etching the first sacrificial layer at the bottom of the first opening to form a third opening penetrating through the first sacrificial layer at the bottom of the first opening; etching the mask layer at the bottom of the second opening in the process of forming the third opening, the second opening penetrating through the mask layer, and the bottom wall of the second opening having residual mask material; etching and removing the residual mask material; etching the first sacrificial layer at the bottom of the second opening and the layer to be etched to form a first pattern opening in the layer to be etched; and etching the layer to be etched at the bottom of the third opening in the process of forming the first pattern opening to form a second pattern opening in the layer to be etched.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for preparing a semiconductor structure. Background Technology

[0002] Single-transverse-mode quantum cascade lasers based on photonic crystal surface-emitting semiconductor lasers have important applications in industrial pumping, lidar sensing, laser processing, gas sensing, and quantum sensing. Common photonic crystal surface-emitting semiconductor lasers incorporate two-dimensional photonic crystal micro / nano structures into surface-emitting semiconductor lasers. By utilizing the photonic bandgap in k-space and the optical field confinement in the planar direction of the two-dimensional photonic crystal micro / nano structure, single-transverse-mode output with a large active region volume is achieved, resulting in a high-brightness semiconductor laser that balances beam quality and high power.

[0003] To achieve single-mode output in existing technologies, it is necessary to open the photonic bandgap and reduce mode degeneracy. This requires breaking the symmetry of two-dimensional photonic crystal micro / nano structures, including: using asymmetric patterns in the xy plane to realize dual-lattice or multi-lattice photonic crystals; and etching patterns of different cell elements in multi-lattice photonic crystals to different depths in the z-direction (epitaxical growth direction). However, it is impossible to simultaneously achieve both pattern quality and process cost, preventing the mass production of two-dimensional photonic crystal micro / nano structures. Summary of the Invention

[0004] Therefore, the technical problem to be solved by the present invention is how to overcome the defect that the quality of the pattern and the process cost cannot be balanced in the prior art, thereby providing a method for preparing a semiconductor structure.

[0005] This application provides a method for fabricating a semiconductor structure, comprising: forming a first sacrificial layer on one side of a layer to be etched; forming a mask layer on the side of the first sacrificial layer opposite to the layer to be etched; forming a first opening and a second opening in the mask layer, the first opening penetrating the mask layer, and the thickness of the mask layer on the side of the second opening facing the layer to be etched being greater than zero; etching the first sacrificial layer at the bottom of the first opening, and forming a third opening penetrating the first sacrificial layer at the bottom of the first opening; during the formation of the third opening, etching the mask layer at the bottom of the second opening, such that the second opening penetrates the mask layer, and the bottom wall of the second opening has residual mask material; etching away the residual mask material; after etching away the residual mask material, etching the first sacrificial layer and the layer to be etched at the bottom of the second opening, forming a first patterned opening in the layer to be etched; during the formation of the first patterned opening, etching the layer to be etched at the bottom of the third opening, forming a second patterned opening in the layer to be etched, wherein the depth of the second patterned opening is greater than the depth of the first patterned opening.

[0006] Optionally, the material of the first sacrificial layer is a semiconductor material; during the formation of the first pattern port and the second pattern port, the etching selectivity ratio of the layer to be etched and the first sacrificial layer is 0.1 to 15.

[0007] Optionally, it further includes: forming a second sacrificial layer on one side of the layer to be etched, the second sacrificial layer being made of a semiconductor material; forming the first sacrificial layer on one side of the layer to be etched includes: forming the first sacrificial layer on the side of the second sacrificial layer opposite to the layer to be etched, the first sacrificial layer being made of a dielectric material; the process of forming the mask layer includes: forming the mask layer on the side of the second sacrificial layer opposite to the first sacrificial layer; during the process of etching the first sacrificial layer at the bottom of the second opening and the layer to be etched, forming a fourth opening in the first sacrificial layer; during the process of forming the fourth opening, etching the second sacrificial layer at the bottom of the third opening, forming a fifth opening in the second sacrificial layer; wherein, during the process of etching the first sacrificial layer at the bottom of the second opening and the layer to be etched, the second sacrificial layer at the bottom of the second opening is also etched, forming a sixth opening in the second sacrificial layer.

[0008] Optionally, the bottom wall of the fourth opening has residual dielectric material; the method for fabricating the semiconductor structure further includes: etching away the residual dielectric material before forming the sixth opening.

[0009] Optionally, the layer to be etched is a photonic crystal layer; there are multiple first openings, which are periodically arranged in the lateral direction; there are multiple second openings, which are periodically arranged in the lateral direction; wherein the first openings and the second openings are arranged alternately.

[0010] Optionally, during the formation of the fourth and fifth openings, the etching selectivity ratio of the first sacrificial layer and the second sacrificial layer is greater than 5.

[0011] Optionally, the layer to be etched is an imprint master; the method for fabricating the semiconductor structure further includes: transferring the first pattern opening and the second pattern opening in the imprint master to a sub-plate, wherein the sub-plate has a first protrusion corresponding to the first pattern opening and a second protrusion corresponding to the second pattern opening; the method for fabricating the semiconductor structure further includes: forming a photonic crystal layer on one side of the active layer; forming an imprinting adhesive layer on the side of the photonic crystal layer away from the active layer; imprinting the imprinting adhesive layer using the sub-plate, forming a first groove corresponding to the first protrusion and a second groove corresponding to the second protrusion in the imprinting adhesive layer, wherein the depth of the second groove is greater than the depth of the first groove; etching the photonic crystal layer using the imprinting adhesive layer as a mask, forming a third pattern opening in the photonic crystal layer at the bottom of the first groove, and forming a fourth pattern opening in the photonic crystal layer at the bottom of the second groove.

[0012] The technical solution of this invention has the following beneficial effects:

[0013] The semiconductor structure fabrication method provided by this invention requires only one exposure process to form a first opening and a second opening in a mask layer. The first opening penetrates the mask layer, while the thickness of the mask layer facing the etchable layer at the second opening is greater than zero, creating a height difference between the first and second openings. Combined with etching processes on the mask layer, the first sacrificial layer, and the etchable layer at the bottom of the first and second openings, the height difference between the first and second openings is transferred to the first and second pattern openings within the etchable layer. This results in the second pattern opening having a greater depth than the first pattern opening, improving the relative positional accuracy of the first and second pattern openings in the lateral direction and thus enhancing the pattern quality. Furthermore, this method eliminates the need for overlay alignment marks and overlay etching processes, reducing process steps and increasing production capacity. It also eliminates the need for expensive high-precision lithography equipment, simplifying the exposure process and reducing costs. A first sacrificial layer is formed on one side of the layer to be etched. The first sacrificial layer and the layer to be etched have a high etch selectivity ratio. On the one hand, this reduces the unevenness on the bottom surfaces of the first and second pattern openings during the transfer of the first opening to the first pattern opening in the layer to be etched, and the second opening to the second pattern opening in the layer to be etched, thus improving pattern quality and yield. On the other hand, it allows for precise control of the etching depth of the first and second pattern openings, providing good process scalability. In the semiconductor structure fabrication method, removing residual mask material through etching—that is, completely consuming the residual mask material on the bottom wall of the second opening—improves the uniformity and smoothness of the bottom surface of the second opening, thereby improving the flatness of the bottom wall of the first pattern opening and reducing the relative positional accuracy between the first and second pattern openings in the longitudinal direction. In summary, this method can balance the need to improve pattern quality and reduce process costs, thus enabling mass production. Attached Figure Description

[0014] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0015] Figures 1 to 3 This is a schematic diagram of the fabrication process of a semiconductor structure in the prior art;

[0016] Figures 4 to 7 This is a schematic diagram illustrating the fabrication process of another semiconductor structure in the prior art.

[0017] Figures 8 to 10 This is a schematic diagram illustrating the fabrication process of another semiconductor structure in the prior art.

[0018] Figure 11 A schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application;

[0019] Figures 12 to 20 This is a schematic diagram of the fabrication process of a semiconductor structure provided in an embodiment of this application;

[0020] Figures 21 to 31 This is a schematic diagram of the fabrication process of a semiconductor structure provided in another embodiment of this application;

[0021] Figures 32 to 38 This is a schematic diagram of the semiconductor structure fabrication process provided in another embodiment of this application. Detailed Implementation

[0022] Currently, in order to achieve different etching depths for patterns of different unit cell elements in multi-lattice photonic crystals and break the symmetry in the z-direction, conventional methods include:

[0023] refer to Figures 1 to 3 The related technology provides a method for fabricating a semiconductor structure, including: making alignment marks in a layer 100 to be etched; forming a first mask layer 110 on one side of the layer 100 to be etched; using the alignment marks for positioning, and combining with photolithography, forming a first opening 120 in the first mask layer 110; etching the layer 100 to be etched at the bottom of the first opening 120 to form a first patterned opening 130 in the layer 100 to be etched (see reference). Figure 1); then, the first mask layer 110 is removed; a second mask layer 140 is formed on one side of the layer to be etched 100 and the first pattern opening 130, and a second opening 150 is formed in the second mask layer 140 using alignment marks and photolithography; the layer to be etched at the bottom of the second opening 150 is etched to form the second pattern opening 160 in the layer to be etched (see reference). Figure 2 ); then, the second mask layer 140 is removed; wherein the depth of the second pattern opening 160 is greater than the depth of the first pattern opening 130 (see reference). Figure 3 In the above method, the distance error between the second pattern port 160 and the first pattern port 130 is required to be less than or equal to 0.5 nm. Since the most advanced deep ultraviolet lithography (DUV) machines and electron beam lithography machines currently available have an overlay accuracy of over 2 nm, it is difficult to meet the relative positional accuracy of the first and second pattern ports between two lithography processes. Therefore, it is difficult to achieve high-quality patterns in the layer to be etched.

[0024] refer to Figures 4 to 6 The related technology also provides a method for fabricating a semiconductor structure, including: providing a layer 10 to be etched (refer to...) Figure 4 ); Make alignment marks in the layer 10 to be etched; form a dielectric mask layer 11 on one side of the layer 10 to be etched; use the alignment marks for positioning, and combine with photolithography to form a first opening 12 and a second opening 13 in the dielectric mask layer 11 (refer to...). Figure 5 A mask adhesive layer 14 is formed on one side of the dielectric mask layer 11, the first opening 12, and the second opening 13. Positioning is achieved using alignment marks, and combined with photolithography, the mask adhesive layer 14 exposes the first opening 12 and covers the second opening 13. The mask adhesive layer covering the second opening 13 is distributed in strips. The layer to be etched at the bottom of the first opening 12 is etched. A first initial pattern opening 15a (see reference) is formed in the layer to be etched 10. Figure 6 ); then, the mask adhesive layer 14 is removed, and the layer 10 to be etched is etched using the dielectric mask layer 11 as a mask, forming a first pattern aperture 15 and a second pattern aperture 16 in the layer 10 to be etched; wherein, the depth of the second pattern aperture 16 is less than the depth of the first pattern aperture 15 (see reference). Figure 7In the above method, since the first opening 12 and the second opening 13 are completed in the same photolithography process, the relative position and periodic accuracy of the first patterned opening 15 and the second patterned opening 16 are guaranteed. To achieve the difference in depth between the first patterned opening 15 and the second patterned opening 16, it is only necessary to control the overlay accuracy of the mask adhesive layer 14, controlling it within the range of the distance difference between the first patterned opening 15 and the second patterned opening 16, ensuring that only the first opening 12 is exposed and the second opening 13 is protected. Thus, the overlay accuracy requirement is about half of the distance difference between the first patterned opening 15 and the second patterned opening 16. That is, if the lateral distance difference between the edges of the first patterned opening 15 and the second patterned opening 16 is greater than 20nm, the overlay accuracy is controlled at about 10nm; or, if the lateral distance difference between the edges of the first patterned opening 15 and the second patterned opening 16 is 20nm~50nm, the overlay accuracy is controlled at 10nm~25nm. Current deep ultraviolet lithography (DUV) machines and electron beam lithography machines achieve overlay precision of 2nm or higher, which can meet the relative positional accuracy requirements of the first pattern aperture 15 and the second pattern aperture 16, enabling high-quality patterns to be achieved in the etched layer. However, the fabrication method of the aforementioned semiconductor structure still requires relatively precise lithography machines with high overlay precision, which are expensive. Furthermore, the overlay process requires additional alignment marks, as well as etching and lithography steps to form the first initial pattern aperture 15a. These numerous process steps can easily reduce yield and increase cost, hindering the high-yield mass production of two-dimensional photonic crystal micro / nano structures.

[0025] refer to Figures 8 to 10 The related technology also provides a method for fabricating a semiconductor structure, including: forming a mask layer 210 on one side of the layer to be etched 200; forming a first opening 220 and a second opening 230 in the mask layer 210, the first opening 220 penetrating the mask layer 210, and the thickness of the mask layer 210 on the side of the second opening 230 facing the layer to be etched 200 being greater than zero (see reference). Figure 8 The mask layer 210 and the layer to be etched 200 at the bottom of the second opening 230 are etched, forming a first patterned opening 240 in the layer to be etched 200. During the formation of the first patterned opening 240, the layer to be etched 200 at the bottom of the first opening 220 is etched, forming a second patterned opening 250 in the layer to be etched 200. The depth of the second patterned opening 250 is greater than the depth of the first patterned opening 240 (see reference). Figure 9 ); then, remove mask layer 210 (refer to...). Figure 10 Assume the difference between the depth of the second graphic port 250 and the depth of the first graphic port 240 is h0'. Figure 8The thickness of the mask layer 210 on the side of the second opening 230 facing the layer 200 to be etched is h1'. The relationship between h1' and h0' satisfies: h1' = h0' / etch selectivity, where etch selectivity = etch rate of the material of the layer 200 to be etched / etch rate of the material of the mask layer 210. In a specific embodiment, the value of the etch selectivity is 1 to 5. Therefore, according to the formula h1' = h0' / etch selectivity, the value of h1' can be determined according to the requirements of h0', thereby determining the exposure dose required to form the second opening 230 and the first opening 220 respectively. The above method requires only one exposure process to simultaneously form the first opening 220 and the second opening 230 in the mask layer. Combined with the etching process of the mask layer 210 and the layer to be etched 200 at the bottom of the first opening 220 and the second opening 230, the height difference between the first opening 220 and the second opening 230 is transferred to the area between the first pattern opening 240 and the second pattern opening 250 in the layer to be etched. No overlay etching is required, resulting in fewer process steps. However, in the above method, the bottom surface of the first opening 220 formed in the mask layer 210 using the exposure process... The topography of the first opening 220 and the bottom surface of the second opening 230 are uneven. In particular, residual mask material is easily formed on the bottom surface of the second opening 230, and the etching selectivity is not large enough. This will cause the unevenness of the first opening 220 and the second opening 230 to be transmitted to the etched layer 200 during the etching process, resulting in uneven topography of the bottom surface of the first pattern opening 240 and the bottom surface of the second pattern opening 250. The relative positional accuracy of the first pattern opening 240 and the second pattern opening 250 in the longitudinal direction is poor.

[0026] Based on this, the embodiments of this application provide a method for fabricating a semiconductor structure that balances the need to improve pattern quality and reduce process costs, thereby enabling mass production.

[0027] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0029] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0030] Example 1

[0031] refer to Figure 11 An embodiment of the present invention provides a method for preparing a semiconductor structure, comprising:

[0032] Step S1: Form a first sacrificial layer on one side of the layer to be etched;

[0033] Step S2: Form a mask layer on the side of the first sacrificial layer opposite to the layer to be etched;

[0034] Step S3: Form a first opening and a second opening in the mask layer. The first opening penetrates the mask layer, and the thickness of the mask layer facing the side of the second opening toward the layer to be etched is greater than zero.

[0035] Step S4: Etch the first sacrificial layer at the bottom of the first opening to form a third opening penetrating the first sacrificial layer at the bottom of the first opening;

[0036] Step S5: During the formation of the third opening, the mask layer at the bottom of the second opening is etched so that the second opening penetrates the mask layer and the bottom wall of the second opening has residual mask material.

[0037] Step S6: Etch away residual mask material;

[0038] Step S7: After etching away the residual mask material, etch the first sacrificial layer and the layer to be etched at the bottom of the second opening to form the first patterned opening in the layer to be etched;

[0039] Step S8: During the formation of the first pattern opening, the layer to be etched at the bottom of the third opening is etched to form a second pattern opening in the layer to be etched, wherein the depth of the second pattern opening is greater than the depth of the first pattern opening.

[0040] In this embodiment, only one exposure process is needed to form the first and second openings in the mask layer. The first opening penetrates the mask layer, and the thickness of the mask layer facing the etchable layer with the second opening is greater than zero, creating a height difference between the first and second openings. Combined with the etching processes of the mask layer, the first sacrificial layer, and the etchable layer at the bottom of the first and second openings, the height difference between the first and second openings is transferred to the first and second pattern openings in the etchable layer. This results in the second pattern opening having a greater depth than the first pattern opening, improving the relative positional accuracy of the first and second pattern openings in the lateral direction, thereby improving the pattern quality. Simultaneously, this method eliminates the need for overlay alignment marks and overlay etching processes, reducing process steps and increasing production capacity. Furthermore, it eliminates the need for expensive lithography equipment with high overlay precision, simplifying the exposure process and reducing costs. A first sacrificial layer is formed on one side of the layer to be etched. The first sacrificial layer and the layer to be etched have a high etch selectivity ratio. On the one hand, this reduces the unevenness on the bottom surfaces of the first and second pattern openings during the transfer of the first opening to the first pattern opening in the layer to be etched, and the second opening to the second pattern opening in the layer to be etched, thus improving pattern quality and yield. On the other hand, it allows for precise control of the etching depth of the first and second pattern openings, providing good process scalability. In the semiconductor structure fabrication method, removing residual mask material through etching—that is, completely consuming the residual mask material on the bottom wall of the second opening—improves the uniformity and smoothness of the bottom wall of the second opening, thereby improving the flatness of the bottom wall of the first pattern opening and reducing the relative positional accuracy between the first and second pattern openings in the longitudinal direction. In summary, this method can balance the need to improve pattern quality and reduce process costs, thus enabling mass production.

[0041] The lateral direction refers to the direction parallel to the surface of the layer to be etched. The longitudinal direction refers to the direction perpendicular to the surface of the layer to be etched.

[0042] In one embodiment, there are multiple first openings arranged periodically in the horizontal direction; there are also multiple second openings arranged periodically in the horizontal direction; wherein the first and second openings are staggered in the horizontal direction. That is, there are multiple first graphic openings arranged periodically in the horizontal direction; there are also multiple second graphic openings arranged periodically in the horizontal direction; wherein the first and second graphic openings are staggered in the horizontal direction.

[0043] In this embodiment, the layer to be etched is a photonic crystal layer. To ensure the overall periodicity of the pattern remains consistent and stable, the periodicity of the first and second pattern apertures is stable, and the distance between the centers of the first and second pattern apertures, and the distance between the edges of the first and second pattern apertures, are stable. In one embodiment, for example, the lateral distance between the centers of the first and second pattern apertures is 90nm~110nm, such as 90nm, 100nm, or 110nm; the lateral distance between the edges of the first and second pattern apertures is 30nm~50nm, such as 30nm, 40nm, or 50nm. In other embodiments, the distance between the centers of the first and second pattern apertures and the distance between the edges of the first and second pattern apertures are not limited to these.

[0044] In one embodiment, the lateral distance between the edge of the first pattern port facing the second pattern port and the edge of the second pattern port facing the first pattern port is 30nm~50nm.

[0045] In this embodiment, the distance error between the first graphic port and the second graphic port in the lateral direction is less than or equal to 0.5 nm. The depth difference between the first graphic port and the second graphic port in the longitudinal direction is less than 0.5 nm.

[0046] The following is for reference. Figures 12 to 20 This section details a process for fabricating semiconductor structures. Figures 12 to 20 The photonic crystal layer to be etched is used as an example for illustration.

[0047] refer to Figure 12 , forming the layer to be etched 1.

[0048] In one embodiment, the step of forming the etchable layer 1 includes: forming the etchable layer 1 on one side of a semiconductor substrate.

[0049] Continue to refer to Figure 12 It also includes: before forming the etchable layer 1 on one side of the semiconductor substrate, forming a carrier transport layer 2 and an active layer 3 stacked sequentially on one side of the semiconductor substrate; the etchable layer 1 is located on the surface of the active layer 3 facing away from the carrier transport layer 2.

[0050] In one embodiment, the material of the layer to be etched 1 includes, but is not limited to, gallium arsenide (GaAs) doped with conductive ions. In one embodiment, the material of the semiconductor substrate layer includes, but is not limited to, gallium arsenide (GaAs) doped with conductive ions. In one embodiment, the material of the carrier transport layer 2 includes, but is not limited to, Al₂O₃ doped with conductive ions. x1 Ga 1- x1 As.

[0051] refer to Figure 13 A first sacrificial layer 4 is formed on one side of the layer to be etched 1.

[0052] In this embodiment, a first sacrificial layer 4 is formed on the side of the layer 1 to be etched that is away from the active layer 3. In this embodiment, the material of the first sacrificial layer 4 is a semiconductor material; for example, the material of the first sacrificial layer 4 is InGaAsP, AlGaInP, or InGaP. By utilizing the high etching selectivity ratio between the first sacrificial layer 4 and the layer 1 to be etched, the depth difference between the first pattern aperture 7 and the second pattern aperture 8 in the layer 1 to be etched can be improved.

[0053] The materials of the first sacrificial layer 4 and the layer to be etched 1 are different.

[0054] In other embodiments, the material of the first sacrificial layer is other semiconductor materials formed from groups III to V.

[0055] In this embodiment, the thickness of the first sacrificial layer 4 is H2. The thickness of the first sacrificial layer 4 is the dimension of the first sacrificial layer 4 in the longitudinal direction.

[0056] refer to Figure 14 A mask layer 5 is formed on the side of the first sacrificial layer 4 away from the layer 1 to be etched; and a first opening 5a and a second opening 5b are formed in the mask layer 5, the first opening 5a penetrating the mask layer 5, and the thickness of the mask layer 5 on the side of the second opening 5b facing the layer 1 to be etched is greater than zero.

[0057] In one embodiment, the process of forming the mask layer 5 on the side of the first sacrificial layer 4 opposite to the layer 1 to be etched includes a spin coating process. The material of the mask layer 5 is photoresist.

[0058] In one embodiment, the step of forming a first opening 5a and a second opening 5b in the mask layer 5 includes: sequentially exposing and developing the mask layer 5 to form the first opening 5a and the second opening 5b in the mask layer 5; during the exposure process of the mask layer 5, the exposure doses used to form the first opening 5a and the second opening 5b are different.

[0059] The exposure process for the mask layer 5 includes electron beam exposure or laser direct writing exposure; and combined with grayscale exposure, a first opening 5a and a second opening 5b of different depths are simultaneously formed in the mask layer 5.

[0060] It is understood that the first opening 5a penetrates the mask layer 5, and the thickness of the mask layer 5 on the side of the first opening 5a facing the layer 1 to be etched is zero; the thickness of the mask layer 5 on the side of the second opening 5b facing the layer 1 to be etched is greater than zero, that is, the depth of the first opening 5a is greater than the depth of the second opening 5b. Therefore, the exposure dose used to form the first opening 5a is greater than the exposure dose used to form the second opening 5b. If the exposure dose used to form the first opening 5a is a, and the exposure dose used to form the second opening 5b is b, then a is greater than b. In one specific embodiment, b is equal to 0.8a or 0.9a. In other embodiments, the relationship between b and a is set according to the actual thickness of the mask layer 5 on the side of the second opening 5b facing the layer 1 to be etched. The depths of the first opening 5a and the second opening 5b both refer to the dimensions in the longitudinal direction.

[0061] The thickness of the mask layer 5 on the side of the second opening 5b facing the layer 1 to be etched is inversely linearly related to the exposure dose used to form the second opening 5b. The thickness of the mask layer 5 on the side of the second opening 5b facing the layer 1 to be etched can be adjusted by increasing or decreasing the exposure dose used to form the second opening 5b.

[0062] In this embodiment, the thickness of the mask layer 5 on the side of the second opening 5b facing the layer 1 to be etched is h1. When the first opening 5a penetrates the mask layer 5 and the thickness of the mask layer 5 on the side of the second opening 5b facing the layer 1 to be etched is greater than zero, the relationship between h1 and H2 is satisfied as follows:

[0063] h1 = H2 / first etch selectivity, where the first etch selectivity = etch rate of the material of the first sacrificial layer 4 / etch rate of the material of the mask layer 5.

[0064] refer to Figure 15 The first sacrificial layer 4 at the bottom of the first opening 5a is etched, and a third opening 6 penetrating the first sacrificial layer 4 is formed at the bottom of the first opening 5a. During the formation of the third opening 6, the mask layer 5 at the bottom of the second opening 5b is etched, so that the second opening 5b penetrates the mask layer 5, and the bottom wall of the second opening 5b has residual mask material 5c.

[0065] That is, in this embodiment, the thickness of the first sacrificial layer 4 at the bottom of the first opening 5a and the depth of the third opening 6 are both h2_1, h2_1=H2; since the bottom wall of the second opening 5b has residual mask material 5c, the thickness of the remaining mask layer 5 at the bottom of the second opening 5b after etching the mask layer 5 at the bottom of the second opening 5b is h2_2, h2_2=H2-h1×first etching selectivity.

[0066] In one embodiment, the process of etching the first sacrificial layer 4 at the bottom of the first opening 5a and the mask layer 5 at the bottom of the second opening 5b is a dry etching process.

[0067] In one embodiment, the gas that can be selected for etching the first sacrificial layer 4 at the bottom of the first opening 5a includes one or more of methane (CH4), hydrogen (H2), chlorine (Cl2), boron trichloride (BCl3), hydrogen chloride (HCl), silicon tetrachloride (SiCl4), trifluoromethane (CHF3), and carbon tetrachloride (CCl4); or, the gas that can be selected for etching the first sacrificial layer 4 at the bottom of the first opening 5a includes one or more of methane (CH4), hydrogen (H2), chlorine (Cl2), boron trichloride (BCl3), hydrogen chloride (HCl), silicon tetrachloride (SiCl4), trifluoromethane (CHF3), and carbon tetrachloride (CCl4) combined with any one of argon (Ar2), nitrogen (N2), and helium (HE). For example, when the gas selected for etching the first sacrificial layer 4 at the bottom of the first opening 5a and the mask layer 5 at the bottom of the second opening 5b is a combination of methane, hydrogen and argon, the flow rate ratio of methane to hydrogen is 2 to 20, for example, 2, 4, 8, 10, 15 or 20; the flow rate ratio of methane to argon is 2 to 10, for example, 2, 4, 8, 10, 15 or 20.

[0068] refer to Figure 16 The residual mask material 5c is etched away, and the residual mask material 5c on the bottom wall of the second opening 5b is completely consumed, thereby achieving uniformity and smoothness of the bottom wall of the second opening 5b.

[0069] In one embodiment, the process of etching away residual mask material 5c employs a dry etching process. The gas selected for etching away residual mask material 5c may include one or a combination of methane (CH4) and hydrogen (H2); alternatively, the gas selected for the dry etching process may include one or a combination of methane (CH4) and hydrogen (H2) with any one of argon (Ar2) and oxygen (O2). For example, the gas selected in the dry etching process is a combination of methane, hydrogen, and argon.

[0070] In one embodiment, the gas selected for etching away residual mask material 5c satisfies a second etch selectivity greater than 5, such as 6, 7, or 8. The second etch selectivity is equal to the etch rate of the mask layer 5 material divided by the etch rate of the layer 1 to be etched. Removing residual mask material 5c from the bottom wall of the second opening 5b improves the uniformity and smoothness of the bottom wall of the second opening 5b.

[0071] Reference Figures 17 to 18After etching away the residual mask material 5c, the first sacrificial layer 4 and the layer to be etched 1 at the bottom of the second opening 5b are etched to form a first patterned opening 7 in the layer to be etched 1. During the formation of the first patterned opening 7, the layer to be etched 1 at the bottom of the third opening 6 is etched to form a second patterned opening 8 in the layer to be etched 1, wherein the depth of the second patterned opening 8 is greater than the depth of the first patterned opening 7.

[0072] In this embodiment, the difference between the depth of the second graphic port 8 and the depth of the first graphic port 7 is h0.

[0073] refer to Figure 17 The first sacrificial layer 4 at the bottom of the second opening 5b is etched to expose the layer 1 to be etched; during the etching of the first sacrificial layer 4 at the bottom of the second opening 5b, the layer 1 to be etched at the bottom of the third opening 6 is etched, and an initial second pattern 8a is formed in the layer 1 to be etched.

[0074] In one embodiment, when the thickness of the layer 1 to be etched at the bottom of the third opening 6, which is the initial depth of the second pattern opening 8a, is h3_1, assuming the thickness of the layer 1 to be etched at the bottom of the second opening 5b is h3_2, h3_2 = h3_1 - H2 × third etch selectivity. When the etching of the first sacrificial layer 4 at the bottom of the second opening 5b just stops at the layer 1 to be etched, without etching the layer 1 to be etched at the bottom of the second opening 5b, then h3_2 = 0. Wherein, when the material of the first sacrificial layer 4 is a semiconductor material, the third etch selectivity is the etch selectivity ratio between the layer 1 to be etched and the first sacrificial layer 4, that is, the third etch selectivity is equal to the etching rate of the material of the layer 1 to be etched / the etching rate of the material of the first sacrificial layer 4.

[0075] In this embodiment, h0 = H2 × third etch selectivity, that is, H2 = h0 / third etch selectivity.

[0076] In a specific embodiment, the etching selectivity ratio of the layer to be etched 1 and the first sacrificial layer 4 is 0.1 to 15, that is, the value of the third etching selectivity ratio is between 0.1 and 15, for example, 0.1, 3, 5, 7, 10, or 15. Preferably, the value of the third etching selectivity ratio is between 0.5 and 15, for example, 0.5, 3, 5, 7, 10, or 15. By adjusting the value of the third etching selectivity ratio within the above range, the difference h0 between the depth of the second pattern port 8 and the depth of the first pattern port 7 can be precisely controlled by using the thickness H2 of the first sacrificial layer 4 × the third etching selectivity ratio; and the thickness of the first sacrificial layer 4 is more adjustable when the difference between the depth of the second pattern port 8 and the depth of the first pattern port 7 is large. For example, when the value of the third etching selectivity ratio is 10, and the thickness H2 of the first sacrificial layer 4 is 10 nm, the difference h0 between the depth of the second pattern port 8 and the depth of the first pattern port 7 is 100 nm.

[0077] Therefore, according to the formula h0=H2×third etching selectivity, the value of H2 can be determined according to the requirements of h0, and then the thickness h1 of the mask layer 5 on the side of the second opening 5b facing the layer 1 to be etched can be determined according to h1=H2 / first etching selectivity, and then the size of the exposure dose a can be determined.

[0078] In one embodiment, the process of etching both the first sacrificial layer 4 at the bottom of the second opening 5b and the layer 1 to be etched includes a dry etching process. The gas selected for etching the first sacrificial layer 4 at the bottom of the second opening 5b includes one or more of methane (CH4), hydrogen (H2), chlorine (Cl2), boron trichloride (BCl3), hydrogen chloride (HCl), silicon tetrachloride (SiCl4), and carbon tetrachloride (CCl4); or, the gas selected for etching the first sacrificial layer 4 at the bottom of the second opening 5b includes one or more of methane (CH4), hydrogen (H2), chlorine (Cl2), boron trichloride (BCl3), hydrogen chloride (HCl), silicon tetrachloride (SiCl4), and carbon tetrachloride (CCl4) combined with any one of argon (Ar2), nitrogen (N2), and helium (HE). The gas selected for etching the layer to be etched 1 includes one or more of chlorine (Cl2), boron trichloride (BCl3), hydrogen chloride (HCl), silicon tetrachloride (SiCl4), and methane (CH4); or, the gas selected for etching the layer to be etched 1 includes one or more of chlorine (Cl2), boron trichloride (BCl3), hydrogen chloride (HCl), silicon tetrachloride (SiCl4), and methane (CH4) combined with any one of argon (Ar2), nitrogen (N2), and helium (HE). For example, when both the first sacrificial layer 4 at the bottom of the second opening 5b and the layer to be etched 1 are selected from a combination of chlorine, boron trichloride, and argon, the flow rate ratio of chlorine to argon is 2~30, for example, 2, 4, 8, 10, 15, 20, 25, or 30; the flow rate ratio of boron trichloride to argon is 2~50, for example, 2, 4, 8, 10, 15, 20, 25, 30, 40, or 50.

[0079] refer to Figure 18 The etched layer 1 is exposed, forming a first patterned opening 7 within it. During the formation of the first patterned opening 7, the bottom of the initial second patterned opening 8a of the etched layer 1 is etched, forming a second patterned opening 8 within the etched layer 1. The second patterned opening 8 includes the initial second patterned opening 8a and the opening formed by etching the bottom of the initial second patterned opening 8a of the etched layer 1.

[0080] In this embodiment, the thickness of the etched layer 1 is h0_1, which means the depth of the first pattern opening 7 is h0_1, and the thickness of the second pattern opening 8 is h0_2, where h0_2 = h0_1 + h0.

[0081] The etching process for the exposed layer 1 to be etched, and the etching process for the bottom of the initial second pattern opening 8a of the layer 1 to be etched, includes a dry etching process. The gas selected for the dry etching process has the same gas parameters as those selected for etching the first sacrificial layer 4 at the bottom of the second opening 5b and the layer 1 to be etched.

[0082] refer to Figure 19 Remove the mask layer 5.

[0083] The process for removing mask layer 5 includes a combination of dry etching and wet etching.

[0084] refer to Figure 20 Remove the first sacrificial layer 4.

[0085] In this embodiment, the process for removing the first sacrificial layer 4 includes a wet etching process. This removes plasma and etching damage to the surface of the first sacrificial layer 4 caused by the removal of the mask layer 5, and provides a clean epitaxial interface, improving the quality of secondary epitaxial growth or subsequent film deposition processes and reducing defects. The secondary epitaxial growth process includes novel vapor phase epitaxy (MOCVD), hydride vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE).

[0086] In one embodiment, the solution selected for removing the first sacrificial layer 4 includes a mixed solution of phosphoric acid, hydrochloric acid, and water; a mixed solution of sulfuric acid, hydrochloric acid, and water; or a mixed solution of hydrochloric acid and water. In one embodiment, during the removal of the first sacrificial layer 4, the first corrosion selectivity ratio between the first sacrificial layer 4 and the layer 1 to be etched is greater than 1000, for example, 1000, 1200, or 1300. The solution selected for removing the first sacrificial layer 4 has selective corrosion characteristics, and since the first corrosion selectivity ratio is in the range of greater than 1000, it corrodes the first sacrificial layer 4 while essentially not corroding the layer 1 to be etched.

[0087] The first corrosion selectivity ratio is defined as: corrosion rate of the first sacrificial layer 4 / corrosion rate of the layer 1 to be etched.

[0088] In this embodiment, the layer to be etched 1 is a photonic crystal layer, and the method further includes: after removing the first sacrificial layer 4, forming a semiconductor cladding layer on the side of the photonic crystal layer away from the active layer. A first portion of the semiconductor cladding layer is located in a first patterned opening 7, a second portion of the semiconductor cladding layer is located in a second patterned opening 8, the first portion has a first void inside, the second portion has a second void inside, and a third portion of the semiconductor cladding layer is located on the side of the photonic crystal layer away from the active layer between the first patterned opening 7 and the second patterned opening 8; a Bragg reflector is formed on the side of the semiconductor cladding layer away from the photonic crystal layer. The refractive index of the photonic crystal layer and the refractive index of the semiconductor cladding layer are different.

[0089] Example 2

[0090] Another embodiment of the present invention also provides a method for fabricating a semiconductor structure, which differs from the aforementioned embodiment 1 in that: the method for fabricating the semiconductor structure further includes: forming a second sacrificial layer 9 on one side of the layer to be etched 1, wherein the material of the second sacrificial layer 9 is a semiconductor material; forming a first sacrificial layer 4 on one side of the layer to be etched 1 includes: forming a first sacrificial layer 4 on the side of the second sacrificial layer 9 opposite to the layer to be etched 1, wherein the first sacrificial layer 4 is a dielectric material. Exemplarily, the material of the first sacrificial layer 4 is silicon dioxide or silicon nitride. In other embodiments, the material of the first sacrificial layer is other dielectric materials. Exemplarily, the material of the second sacrificial layer 9 is InGaAsP, AlGaInP, or InGaP. In other embodiments, the material of the second sacrificial layer is other semiconductor materials formed from Group III to Group V. Forming a second sacrificial layer 9 on one side of the layer to be etched 1 is beneficial for achieving planarization of one side of the layer to be etched 1, and also improves the conformability of the pattern in the dry etching process, thereby improving the morphological quality of the first pattern aperture 7 and the second pattern aperture 8.

[0091] The process of forming the mask layer 5 includes: forming the mask layer 5 on the side of the second sacrificial layer 9 opposite to the first sacrificial layer 4; during the etching of the first sacrificial layer 4 at the bottom of the second opening 5b and the layer 1 to be etched, forming a fourth opening 4a in the first sacrificial layer 4; during the formation of the fourth opening 4a, etching the second sacrificial layer 9 at the bottom of the third opening 6, forming a fifth opening 9a in the second sacrificial layer 9; wherein, during the etching of the first sacrificial layer 4 at the bottom of the second opening 5b and the layer 1 to be etched, the second sacrificial layer 9 at the bottom of the second opening 5b is also etched, forming a sixth opening 9b in the second sacrificial layer 9.

[0092] In one embodiment, during the formation of the fourth opening 4a and the fifth opening 9a, the etching selectivity ratio of the first sacrificial layer 4 and the second sacrificial layer 9 is greater than 5, for example, 5, 6, 7, or 8. By utilizing an etching selectivity ratio of the first sacrificial layer 4 and the second sacrificial layer 9 greater than 5, it is easier to control the depth difference between the first pattern opening 7 and the second pattern opening 8. Especially when the depth difference between the first pattern opening 7 and the second pattern opening 8 is large, it is easier to control and adjust the relative position of the first pattern opening 7 and the second pattern opening 8 in the lateral direction, thus enhancing the accuracy of the relative position of the first pattern opening 7 and the second pattern opening 8 in the lateral direction.

[0093] In one embodiment, the bottom wall of the fourth opening 4a has residual dielectric material 4c; the method for fabricating the semiconductor structure further includes etching away the residual dielectric material 4c before forming the sixth opening 9b. This minimizes the impact of the residual dielectric material 4c on the flatness of the underlying second sacrificial layer 9 during subsequent etching, thereby improving the uniformity and smoothness of the bottom wall of the fourth opening 4a.

[0094] The following is for reference. Figures 21 to 31 This section details another process for fabricating semiconductor structures. Figures 21 to 31 The photonic crystal layer to be etched is used as an example for illustration.

[0095] refer to Figure 21 , Figure 21 In order to be in Figure 12 A schematic diagram based on the above. A second sacrificial layer 9 is formed on one side of the layer to be etched 1; and a first sacrificial layer 4 is formed on the side of the second sacrificial layer 9 opposite to the layer to be etched 1.

[0096] The second sacrificial layer 9 is made of a semiconductor material, and the first sacrificial layer 4 is made of a dielectric material. For a description of the materials of the second sacrificial layer 9 and the first sacrificial layer 4, please refer to the preceding description of this embodiment.

[0097] In this embodiment, the thickness of the second sacrificial layer 9 is H2', and the thickness of the first sacrificial layer 4 is H3. H3 = H2' / fourth etch selectivity, where the fourth etch selectivity is the etching rate of the material of the second sacrificial layer 9 / the etching rate of the material of the first sacrificial layer 4.

[0098] refer to Figure 22 , Figure 22 In order to be in Figure 21 A schematic diagram based on the above. A mask layer 5 is formed on the side of the first sacrificial layer 4 away from the layer 1 to be etched; and a first opening 5a and a second opening 5b are formed in the mask layer 5, the first opening 5a penetrating the mask layer 5, and the thickness of the mask layer 5 on the side of the second opening 5b facing the layer 1 to be etched is greater than zero.

[0099] The process description of forming a mask layer 5 on the side of the first sacrificial layer 4 opposite to the layer 1 to be etched, the material description of the mask layer 5, the step description of forming the first opening 5a and the second opening 5b in the mask layer 5, and the process description of sequentially exposing the mask layer 5 are all the same as those described in the foregoing embodiments.

[0100] In this embodiment, Figure 22 The thickness of the mask layer 5 on the side of the second opening 5b facing the layer 1 to be etched is h1. When the first opening 5a penetrates the mask layer 5 and the thickness of the mask layer 5 on the side of the second opening 5b facing the layer 1 to be etched is greater than zero, the relationship between h1 and H3 is:

[0101] h1 = H3 / fifth etch selectivity, where the fifth etch selectivity = etch rate of the material of the first sacrificial layer 4 / etch rate of the material of the mask layer 5.

[0102] refer to Figure 23 , Figure 23 In order to be in Figure 22 A schematic diagram based on the above. The first sacrificial layer 4 at the bottom of the first opening 5a is etched, and a third opening 6 penetrating the first sacrificial layer 4 is formed at the bottom of the first opening 5a. During the formation of the third opening 6, the mask layer 5 at the bottom of the second opening 5b is etched, so that the second opening 5b penetrates the mask layer 5, and the bottom wall of the second opening 5b has residual mask material 5c.

[0103] That is, in this embodiment, the thickness of the first sacrificial layer 4 at the bottom of the first opening 5a and the depth of the third opening 6 are both h4_1, h4_1=H3; since the bottom wall of the second opening 5b has residual mask material 5c, the thickness of the remaining mask layer 5 at the bottom of the second opening 5b after etching the mask layer 5 at the bottom of the second opening 5b is h4_2, h4_2=H3-h1×fifth etching selectivity.

[0104] The process of etching the first sacrificial layer 4 at the bottom of the first opening 5a and the mask layer 5 at the bottom of the second opening 5b adopts a dry etching process.

[0105] The gases that can be selected for etching the first sacrificial layer 4 at the bottom of the first opening 5a and the mask layer 5 at the bottom of the second opening 5b are described in the foregoing embodiments.

[0106] In this embodiment, the gases selected for etching the first sacrificial layer 4 at the bottom of the first opening 5a and the mask layer 5 at the bottom of the second opening 5b are trifluoromethane, methane, oxygen, and argon. The flow rate ratio of trifluoromethane to methane is 0.2 to 5, for example, 0.2, 1.3, 1.5, 3.2, or 5; the flow rate ratio of trifluoromethane to oxygen is 5 to 100, for example, 5, 20, 50, 70, or 100; and the mass percentage of trifluoromethane to argon is 5 to 50, for example, 5, 20, 35, 40, or 50.

[0107] refer to Figure 24 , Figure 24 In order to be in Figure 23 A schematic diagram based on the basic structure. Residual mask material 5c is etched away. The residual mask material 5c on the bottom wall of the second opening 5b is completely consumed, thereby achieving uniformity and smoothness of the bottom wall of the second opening 5b.

[0108] In one embodiment, the etching process for removing residual mask material 5c employs a dry etching process. The gases that can be selected in the dry etching process include, but are not limited to, a combination of carbon tetrafluoride (CF4), oxygen, and argon.

[0109] In one embodiment, during the etching process to remove residual mask material 5c, the etching selectivity ratio for the mask layer 5 and the first sacrificial layer 4 is a sixth etching selectivity ratio, and the etching selectivity ratio for the mask layer 5 and the second sacrificial layer 9 is a seventh etching selectivity ratio. The seventh etching selectivity ratio is greater than 10, for example, 10, 12, or 13, and the sixth etching selectivity ratio is greater than 5, for example, 6, 7, or 8. This minimizes the impact of the bottom wall of the second opening 5b on the flatness of the underlying first sacrificial layer 4 during subsequent etching processes. Therefore, removing the residual mask material 5c from the bottom wall of the second opening 5b achieves better uniformity and smoothness of the bottom wall of the second opening 5b.

[0110] The etching selectivity ratio for mask layer 5 and first sacrificial layer 4 is equal to the etching rate of the material of mask layer 5 / the etching rate of the material of first sacrificial layer 4; the etching selectivity ratio for mask layer 5 and second sacrificial layer 9 is equal to the etching rate of the material of mask layer 5 / the etching rate of the material of second sacrificial layer 9.

[0111] refer to Figure 25 , Figure 25 In order to be in Figure 24 A schematic diagram based on the above. The first sacrificial layer 4 at the bottom of the second opening 5b is etched to form a fourth opening 4a in the first sacrificial layer 4. The fourth opening 4a penetrates the first sacrificial layer 4, and the bottom wall of the fourth opening 4a has residual dielectric material 4c. During the formation of the fourth opening 4a, the second sacrificial layer 9 at the bottom of the third opening 6 is etched. A fifth opening 9a is formed in the second sacrificial layer 9, and the fifth opening 9a penetrates the second sacrificial layer 9.

[0112] In one embodiment, the thickness of the second sacrificial layer 9 at the bottom of the third opening 6 and the thickness of the fifth opening 9a are both h5_1=H2', and the thickness of the remaining first sacrificial layer 4 at the bottom of the second opening 5b after etching the first sacrificial layer 4 is both h5_2, where h5_2=H2'-H3×fourth etching selectivity.

[0113] In one embodiment, the process of etching the second sacrificial layer 9 at the bottom of the third opening 6 and the first sacrificial layer 4 at the bottom of the second opening 5b is a dry etching process. The gas that can be used to etch the first sacrificial layer 4 at the bottom of the second opening 5b is described in the foregoing embodiments.

[0114] In one embodiment, the gas that can be selected for etching the first sacrificial layer 4 at the bottom of the second opening 5b includes one or a combination of several of carbon tetrafluoride (CF4), trifluoromethane (CHF3), nitrogen trifluoride (NHF3), hexafluoroethane (C2F6), octafluorocyclobutane (C4F8), and oxygen; or, the gas that can be selected for etching the second sacrificial layer 9 at the bottom of the third opening 6 includes one or a combination of several of carbon tetrafluoride (CF4), trifluoromethane (CHF3), nitrogen trifluoride (NHF3), hexafluoroethane (C2F6), octafluorocyclobutane (C4F8), and oxygen with any one of argon (Ar2), nitrogen (N2), and helium (HE). When the gas that can be selected for etching the second sacrificial layer 9 at the bottom of the third opening 6 is a combination of methane, hydrogen, and argon, the flow rate ratio of methane to hydrogen is 2 to 10, for example, 2, 4, 8, or 10; the flow rate ratio of methane to argon is 5 to 20, for example, 5, 10, 15, or 20.

[0115] refer to Figure 26 , Figure 26 In order to be in Figure 25 A schematic diagram based on the basic structure. Residual dielectric material 4c is etched away. The residual dielectric material 4c on the bottom wall of the fourth opening 4a is completely consumed, thereby achieving uniformity and smoothness of the bottom wall of the fourth opening 4a.

[0116] In one embodiment, the process of etching away the residual dielectric material 4c employs a dry etching process.

[0117] For example, the gas selected for etching to remove residual dielectric material 4c may include, but is not limited to, a combination of trifluoromethane, methane, argon and oxygen.

[0118] In one embodiment, the eighth etch selectivity of the gas selected for etching away the residual dielectric material 4c is greater than 5, for example, 6, 7, or 8. The eighth etch selectivity is the etch selectivity of the first sacrificial layer 4 and the second sacrificial layer 9 during the formation of the fourth opening 4a and the fifth opening 9a. The eighth etch selectivity is equal to the etch rate of the material of the first sacrificial layer 4 divided by the etch rate of the material of the second sacrificial layer 9.

[0119] During the etching process to remove residual dielectric material 4c, the second sacrificial layer 9 serves as an etching barrier layer.

[0120] refer to Figures 27 to 28 , Figure 27 In order to be in Figure 26 A basic diagram. Figure 28 In order to be in Figure 27 A schematic diagram based on the above. After etching away the residual dielectric material 4c, the second sacrificial layer 9 and the layer to be etched 1 at the bottom of the second opening 5b are etched, forming a first patterned opening 7 in the layer to be etched 1; during the formation of the first patterned opening 7, the layer to be etched 1 at the bottom of the fifth opening 9a is etched, forming a second patterned opening 8 in the layer to be etched 1, wherein the depth of the second patterned opening 8 is greater than the depth of the first patterned opening 7.

[0121] In this embodiment, the difference between the depth of the second graphic port 8 and the depth of the first graphic port 7 is h0.

[0122] refer to Figure 27 The second sacrificial layer 9 at the bottom of the second opening 5b is etched to form the sixth opening 9b in the second sacrificial layer 9; during the process of etching the second sacrificial layer 9 at the bottom of the second opening 5b, the layer 1 to be etched at the bottom of the fifth opening 9a is etched to form the initial second pattern 8a in the layer 1 to be etched.

[0123] In one embodiment, when the depth of etching the layer 1 to be etched at the bottom of the fifth opening 9a, i.e., the initial second pattern opening 8a, is h6_1, assuming the thickness of etching the layer 1 to be etched at the bottom of the second opening 5b is h6_2, h6_2 = h6_1 - H2' × the ninth etch selectivity ratio. When the etching of the second sacrificial layer 9 at the bottom of the second opening 5b just stops at the layer 1 to be etched, that is, no etching is performed on the layer 1 to be etched at the bottom of the second opening 5b, h6_2 = 0. The ninth etch selectivity ratio is the etch selectivity ratio between the layer 1 to be etched and the second sacrificial layer 9. That is, the ninth etch selectivity ratio is equal to the etching rate of the material of the layer 1 to be etched / the etching rate of the material of the second sacrificial layer 9.

[0124] In this embodiment, h0 = H2' × eighth etch selectivity, that is, H2' = h0 / ninth etch selectivity.

[0125] In a specific embodiment, the etching selectivity ratio of the layer to be etched 1 and the second sacrificial layer 9 is 0.1 to 15, that is, the value of the ninth etching selectivity ratio is between 0.1 and 15, for example, 0.1, 3, 5, 7, 10, or 15. By adjusting the value of the ninth etching selectivity ratio within the above range, the difference h0 between the depth of the second pattern port 8 and the depth of the first pattern port 7 can be precisely controlled by the thickness H2' of the second sacrificial layer 9 × the ninth etching selectivity ratio; and when the difference between the depth of the second pattern port 8 and the depth of the first pattern port 7 is large, a large depth difference between the second pattern port 8 and the first pattern port 7 can be achieved by adjusting the thickness of the second sacrificial layer 9, thereby improving the depth difference capability that the process can achieve. For example, when the value of the ninth etching selectivity ratio is 10, and the thickness H2' of the second sacrificial layer 9 is 10 nm, the difference h0 between the depth of the second pattern port 8 and the depth of the first pattern port 7 is 100 nm.

[0126] Therefore, according to the formula h0=H2'×ninth etch selectivity, the value of H2' can be determined according to the requirements of h0. Then, the value of H3 can be determined according to H3=H2' / fourth etch selectivity. Then, the thickness h1 of the mask layer 5 on the side of the second opening 5b facing the layer 1 to be etched can be determined according to h1=H3 / fifth etch selectivity. Finally, the size of the exposure dose a can be determined.

[0127] In one embodiment, the processes for etching the second sacrificial layer 9 at the bottom of the second opening 5b and the process for etching the layer 1 to be etched at the bottom of the fifth opening 9a both include dry etching. The description of the selectable gas for etching the second sacrificial layer 9 at the bottom of the second opening 5b refers to the description of the selectable gas for etching the second sacrificial layer 9 at the bottom of the third opening 6 described above. The description of the selectable gas for etching the layer 1 to be etched at the bottom of the fifth opening 9a refers to the description of the gas selected for etching the layer 1 to be etched in the previous embodiment.

[0128] In this embodiment, for example, when the gases selected for etching the second sacrificial layer 9 at the bottom of the second opening 5b and the etchable layer 1 at the bottom of the fifth opening 9a are both a combination of chlorine, boron trichloride and argon, the flow rate ratio of chlorine to hydrogen is 0.2 to 10, for example, 2, 4, 8 or 10; the flow rate ratio of chlorine to argon is 2 to 50, for example, 5, 10, 15 or 20.

[0129] refer to Figure 28 The bottom of the sixth opening 9b is etched to form the first patterned opening 7 in the etched layer 1. During the formation of the first patterned opening 7, the bottom of the initial second patterned opening 8a is etched to form the second patterned opening 8 in the etched layer 1. The second patterned opening 8 includes the initial second patterned opening 8a and the opening formed by etching the bottom of the initial second patterned opening 8a of the etched layer 1.

[0130] In this embodiment, the thickness of the layer 1 to be etched at the bottom of the sixth opening 9b is h0_1, which means the depth of the first pattern opening 7 is h0_1, and the thickness of the second pattern opening 8 is h0_2, where h0_2 = h0_1 + h0.

[0131] refer to Figure 29 Remove the mask layer 5.

[0132] The process for removing mask layer 5 includes a combination of dry etching and wet etching.

[0133] refer to Figure 30 Remove the first sacrificial layer 4.

[0134] In this embodiment, the process for removing the first sacrificial layer 4 includes a wet etching process.

[0135] In one embodiment, the solution selected for removing the first sacrificial layer 4 includes one or a combination of two of buffered oxide etchant (BOE) and hydrofluoric acid. In one embodiment, during the removal of the first sacrificial layer 4, the second corrosion selectivity ratio for the first sacrificial layer 4, the second sacrificial layer 9, and the layer to be etched 1 is greater than 1000, for example, 1000, 1200, or 1300. The solution selected for removing the first sacrificial layer 4 exhibits selective corrosion characteristics, and with a second corrosion selectivity ratio greater than 1000, it corrodes the first sacrificial layer 4 while essentially not corroding the second sacrificial layer 9 and the layer to be etched 1.

[0136] The second corrosion selectivity ratio is defined as: corrosion rate of the first sacrificial layer 4 / corrosion rate of the second sacrificial layer 9, and corrosion rate of the first sacrificial layer 4 / corrosion rate of the layer 1 to be etched.

[0137] refer to Figure 31 Remove the second sacrificial layer 9.

[0138] In this embodiment, the process for removing the second sacrificial layer 9 includes a wet etching process. This removes plasma and etching damage to the surface of the second sacrificial layer 9 caused during the growth or etching of the first sacrificial layer 4; it also provides a clean epitaxial interface, improving the quality of secondary epitaxial growth or subsequent film deposition processes and reducing defects. The secondary epitaxial growth process includes novel vapor phase epitaxy (MOCVD), hydride vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE).

[0139] In one embodiment, the solution selected for removing the second sacrificial layer 9 includes a mixed solution of phosphoric acid, hydrochloric acid, and water; a mixed solution of sulfuric acid, hydrochloric acid, and water; or a mixed solution of hydrochloric acid and water. In one embodiment, during the removal of the second sacrificial layer 9, the third corrosion selectivity ratio between the second sacrificial layer 9 and the layer 1 to be etched is greater than 1000, for example, 1000, 1200, or 1300. The solution selected for removing the second sacrificial layer 9 exhibits selective corrosion characteristics, and since the third corrosion selectivity ratio is in the range greater than 1000, it corrodes the second sacrificial layer 9 while essentially not corroding the layer 1 to be etched.

[0140] The third corrosion selectivity ratio is defined as: corrosion rate of the second sacrificial layer 9 / corrosion rate of the layer to be etched 1.

[0141] Other aspects of this embodiment that are the same as those in the previous embodiments will not be described in detail.

[0142] In this embodiment, the layer to be etched 1 is a photonic crystal layer, and the method further includes: after removing the second sacrificial layer 9, forming a semiconductor cladding layer on the side of the photonic crystal layer away from the active layer. A first portion of the semiconductor cladding layer is located in a first patterned opening 7, a second portion of the semiconductor cladding layer is located in a second patterned opening 8, the first portion has a first void inside, the second portion has a second void inside, and a third portion of the semiconductor cladding layer is located on the side of the photonic crystal layer away from the active layer between the first patterned opening 7 and the second patterned opening 8; a Bragg reflector is formed on the side of the semiconductor cladding layer away from the photonic crystal layer. The refractive index of the semiconductor cladding layer is different from that of the photonic crystal layer.

[0143] Example 3

[0144] Another embodiment of the present invention also provides a method for preparing a semiconductor structure, which differs from the aforementioned Embodiments 1 and 2 in that: the layer to be etched 1 is an imprint master. The material of the imprint master is silicon.

[0145] In this embodiment, the semiconductor structure fabrication method further includes: transferring the first and second patterned openings in the imprinting master to a sub-plate, wherein the sub-plate has a first protrusion corresponding to the first patterned opening and a second protrusion corresponding to the second patterned opening; the semiconductor structure fabrication method further includes: forming a photonic crystal layer on one side of the active layer; forming an imprinting adhesive layer on the side of the photonic crystal layer away from the active layer; imprinting the imprinting adhesive layer using the sub-plate to form a first groove corresponding to the first protrusion and a second groove corresponding to the second protrusion in the imprinting adhesive layer, wherein the depth of the second groove is greater than the depth of the first groove; etching the photonic crystal layer using the imprinting adhesive layer as a mask to form a third patterned opening in the photonic crystal layer at the bottom of the first groove and a fourth patterned opening in the photonic crystal layer at the bottom of the second groove. By using exposure and etching processes during the creation of the embossing master, first and second patterned openings with different depth differences can be formed in the embossing master. Subsequently, nanoimprinting can be used to transfer the first and second patterned openings with different depth differences to the photonic crystal layer, forming third and fourth patterned openings in the photonic crystal layer. The duration of one nanoimprinting process is usually 2-3 minutes, while the duration of one exposure process is at least 6 hours. Using nanoimprinting can greatly shorten the pattern preparation time, improve production efficiency, and thus achieve mass production.

[0146] The following is for reference. Figures 32 to 38 This section details a process for fabricating semiconductor structures. Figures 31 to 38 The layer to be etched is used as an example to illustrate the process.

[0147] refer to Figure 32 A first pattern opening 7 and a second pattern opening 8 are formed in the layer to be etched 1, wherein the depth of the second pattern opening 8 is greater than the depth of the first pattern opening 7.

[0148] That is, the first graphic aperture 7 and the second graphic aperture 8 are formed in the printing master.

[0149] The steps for forming the first graphic aperture 7 and the second graphic aperture 8 in the printing master are described with reference to the description in the foregoing embodiment.

[0150] refer to Figure 33 The first pattern opening 7 and the second pattern opening 8 in the layer to be etched 1 are transferred to the sub-plate 300, that is, the first pattern opening 7 and the second pattern opening 8 in the imprinting master are transferred to the sub-plate 300. The sub-plate 300 has a first protrusion 300a corresponding to the first pattern opening 7 and a second protrusion 300b corresponding to the second pattern opening 8.

[0151] refer to Figure 34 A photonic crystal layer 500 is formed on one side of the active layer 3; an imprinting adhesive layer 400 is formed on the side of the photonic crystal layer 500 opposite to the active layer 3.

[0152] In this embodiment, the thickness of the imprinting adhesive layer 400 is H5. The thickness of the imprinting adhesive layer 400 is less than half the thickness of the second pattern opening 8.

[0153] In one embodiment, before forming a photonic crystal layer 500 on one side of the active layer 3, a carrier transport layer 2 is formed on one side of a semiconductor substrate (not shown); then, an active layer 3 is formed on the side of the carrier transport layer 2 facing away from the semiconductor substrate. Forming a photonic crystal layer 500 on one side of the active layer 3 includes forming a photonic crystal layer 500 on the side of the active layer 3 facing away from the carrier transport layer 2.

[0154] Reference Figure 35 and Figure 36 The printing plate 300 is used to imprint the printing adhesive layer 400, forming a first groove 400a corresponding to the first protrusion 300a and a second groove 400b corresponding to the second protrusion 300b in the printing adhesive layer 400. The depth of the second groove 400b is greater than the depth of the first groove 400a.

[0155] For details, please refer to Figure 35 The printing plate 300 is used to imprint the printing adhesive layer 400.

[0156] refer to Figure 36 Remove the sub-plate 300, and form a first groove 400a corresponding to the first protrusion 300a and a second groove 400b corresponding to the second protrusion 300b in the printing adhesive layer 400. The depth of the second groove 400b is greater than the depth of the first groove 400a.

[0157] In this embodiment, the second groove 400b penetrates the imprinting adhesive layer 400, and the thickness of the imprinting adhesive layer 400 on the side of the first groove 400a facing the photonic crystal layer 500 is greater than zero.

[0158] In other embodiments, after imprinting the adhesive layer using a sub-plate, residual adhesive layer material remains at the bottom of the second trench. The semiconductor structure fabrication method further includes etching to remove the residual adhesive layer material at the bottom of the second trench, so that the second trench penetrates the adhesive layer. This achieves uniformity and smoothness at the bottom of the second trench. The etching process for removing the residual adhesive layer material at the bottom of the second trench includes inductively coupled plasma etching, reactive ion etching, or plasma cleaning.

[0159] refer to Figure 37 Using the imprinting adhesive layer 400 as a mask, the photonic crystal layer 500 is etched to form a third patterned aperture 500a in the photonic crystal layer 500 at the bottom of the first trench 400a, and a fourth patterned aperture 500b in the photonic crystal layer 500 at the bottom of the second trench 400b. The depth of the fourth patterned aperture 500b is greater than the depth of the third patterned aperture 500a.

[0160] The depth difference between the fourth pattern port 500b and the third pattern port 500a = the depth difference between the second trench 400b and the first trench 400a in the imprinted resist layer 400 / the tenth etch selectivity. The tenth etch selectivity = the etching rate of the imprinted resist layer 400 material / the etching rate of the photonic crystal layer 500.

[0161] The process of etching the photonic crystal layer 500 using the imprinted adhesive layer 400 as a mask includes dry etching.

[0162] refer to Figure 38 Remove the embossing adhesive layer 400.

[0163] In this embodiment, the method further includes: after removing the imprint adhesive layer 400, forming a semiconductor cladding layer on the side of the photonic crystal layer facing away from the active layer. A first portion of the semiconductor cladding layer is located in a third pattern port 500a, and a second portion is located in a fourth pattern port 500b. The first portion has a first void, and the second portion has a second void. A third portion of the semiconductor cladding layer is located on the side of the photonic crystal layer 500 facing away from the active layer between the third pattern port 500a and the fourth pattern port 500b. A Bragg reflector is formed on the side of the semiconductor cladding layer facing away from the photonic crystal layer. The refractive index of the semiconductor cladding layer is different from that of the photonic crystal layer.

[0164] Other aspects of this embodiment that are the same as those in the previous embodiments will not be described in detail.

[0165] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A first sacrificial layer is formed on one side of the layer to be etched; A mask layer is formed on the side of the first sacrificial layer opposite to the layer to be etched; A first opening and a second opening are formed in the mask layer, the first opening penetrating the mask layer, and the thickness of the mask layer is greater than zero on the side of the second opening facing the layer to be etched. The first sacrificial layer at the bottom of the first opening is etched to form a third opening penetrating the first sacrificial layer at the bottom of the first opening; During the formation of the third opening, the mask layer at the bottom of the second opening is etched so that the second opening penetrates the mask layer and the bottom wall of the second opening has residual mask material. Etching removes the residual mask material; After etching away the residual mask material, the first sacrificial layer and the layer to be etched at the bottom of the second opening are etched to form a first patterned opening in the layer to be etched. During the formation of the first patterned opening, the layer to be etched at the bottom of the third opening is etched to form a second patterned opening, wherein the depth of the second patterned opening is greater than the depth of the first patterned opening.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The material of the first sacrificial layer is a semiconductor material; during the formation of the first pattern port and the second pattern port, the etching selectivity ratio of the layer to be etched and the first sacrificial layer is 0.1~15.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, Also includes: A second sacrificial layer is formed on one side of the layer to be etched, and the material of the second sacrificial layer is a semiconductor material; Forming the first sacrificial layer on one side of the layer to be etched includes: forming the first sacrificial layer on the side of the second sacrificial layer opposite to the layer to be etched, wherein the first sacrificial layer is a dielectric material; The process of forming the mask layer includes: forming the mask layer on the side of the second sacrificial layer opposite to the first sacrificial layer; During the etching process of the first sacrificial layer and the layer to be etched at the bottom of the second opening, a fourth opening is formed in the first sacrificial layer; during the formation of the fourth opening, the second sacrificial layer at the bottom of the third opening is etched, and a fifth opening is formed in the second sacrificial layer. During the process of etching the first sacrificial layer and the layer to be etched at the bottom of the second opening, the second sacrificial layer at the bottom of the second opening is also etched, forming a sixth opening in the second sacrificial layer.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The bottom wall of the fourth opening has residual dielectric material; The method for fabricating the semiconductor structure further includes etching away the residual dielectric material before forming the sixth opening.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, The layer to be etched is a photonic crystal layer; there are multiple first openings, which are periodically arranged in the lateral direction; there are multiple second openings, which are periodically arranged in the lateral direction; wherein the first openings and the second openings are arranged alternately.

6. The method for preparing a semiconductor structure according to claim 3, characterized in that, During the formation of the fourth and fifth openings, the etching selectivity ratio of the first sacrificial layer and the second sacrificial layer is greater than 5.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, The layer to be etched is an imprint master; the method for preparing the semiconductor structure further includes: transferring the first pattern opening and the second pattern opening in the imprint master to a sub-plate, wherein the sub-plate has a first protrusion corresponding to the first pattern opening and a second protrusion corresponding to the second pattern opening; The method for fabricating a semiconductor structure further includes: forming a photonic crystal layer on one side of an active layer; forming an imprinting adhesive layer on the side of the photonic crystal layer away from the active layer; imprinting the imprinting adhesive layer using the sub-plate to form a first groove corresponding to the first protrusion and a second groove corresponding to the second protrusion in the imprinting adhesive layer, wherein the depth of the second groove is greater than the depth of the first groove; etching the photonic crystal layer using the imprinting adhesive layer as a mask to form a third patterned opening in the photonic crystal layer at the bottom of the first groove and a fourth patterned opening in the photonic crystal layer at the bottom of the second groove.

Images