Infrared image sensor and pixel-level reading circuit thereof

Abstract

The invention provides an infrared image sensor and a pixel-level reading circuit thereof, and relates to the field of infrared image sensors. The pixel-level reading circuit is integrated in a single pixel unit, and comprises a direct injection input-level circuit used for converting an infrared light-generated current generated by an infrared image sensor into an analog voltage signal; the pulse frequency modulation analog-to-digital converter is connected with the direct injection input stage circuit and is used for converting the analog voltage signal into a pulse signal; the SR latch is electrically connected with the pulse frequency modulation analog-to-digital converter and is used for carrying out accumulative counting on the pulse signals so as to form digital code words reflecting the infrared light intensity; and the digital logic control unit is electrically connected with the SR latch and is used for transmitting the digital code word to a reading bus of the infrared image sensor, so that the output of a digital signal is realized, and the reading rate of the image sensor is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to an infrared image sensor, in particular to an infrared image sensor and a pixel-level readout circuit thereof. BACKGROUND

[0002] In the readout circuit of the infrared image sensor, since the result of the readout circuit is the direct source of the sensor output result. Therefore, the structure of the readout circuit and its readout mode play a key role in the accuracy and speed of the image sensor output signal.

[0003] At present, the image sensor can be divided into chip-level, column (or row) level and pixel-level according to the integration mode of the readout circuit. In the chip-level readout circuit architecture, the entire pixel array is processed by only one readout circuit, and the output signal of each pixel is read out through the readout circuit. A frame of image can be obtained only after the completion of the entire infrared focal plane pixel. However, this method is only suitable for low-resolution image sensors with low readout speed requirements, and has high requirements on the working speed of the readout circuit.

[0004] The column (or row) level readout circuit architecture only needs to be responsible for one column or several columns of pixels. Compared with the chip-level readout circuit architecture, the power consumption of this structure is lower, and when the resolution is increased or the frame rate requirement is high, it will also bring pressure to the design of the analog-to-digital converter.

[0005] At the same time, in the working environment of high-speed photography, due to the requirement of high frame rate, the readout circuit requires more advanced process. The decrease of the working voltage swing in the readout circuit caused by the advanced process leads to the decrease of the working voltage range. SUMMARY

[0006] Therefore, the present application provides an infrared image sensor and a pixel-level readout circuit thereof, which can break through the dynamic range limitation of the advanced process, improve the speed of the readout circuit, and reduce the influence of the decrease of the working voltage on the dynamic range under the condition of ensuring high frame rate.

[0007] The first aspect of the present application provides a pixel-level readout circuit of an infrared image sensor, integrated in a single pixel unit, which comprises: a direct injection input stage circuit, used for converting the infrared light-generated current generated by the infrared image sensor into an analog voltage signal; a pulse frequency modulation analog-to-digital converter connected with the direct injection input stage circuit, used for converting the analog voltage signal into a pulse signal; an SR latch electrically connected with the pulse frequency modulation analog-to-digital converter, used for accumulating and counting the pulse signal to form a digital code reflecting the intensity of the infrared light; and a digital logic control unit electrically connected with the SR latch, used for transmitting the digital code to the readout bus of the infrared image sensor to realize the output of the digital signal.

[0008] Further, the direct injection input stage circuit comprises an injection tube and a metal-oxide semiconductor capacitor; a gate of the injection tube is connected to an external bias voltage, a source of the injection tube is connected to an output terminal of the infrared detector, and a drain of the injection tube is electrically connected to a source of the metal-oxide semiconductor capacitor; a voltage value of the external bias voltage is lower than a voltage of the output terminal of the infrared detector, so as to control the injection tube to be in a critical conduction state, and make the injection tube present a stable high conduction resistance, thereby ensuring the stability of the injection of the infrared photo-generated current into the metal-oxide semiconductor capacitor.

[0009] Further, the pulse frequency modulation analog-to-digital converter comprises a reset tube, a comparator, and an OR gate; a non-inverting input terminal of the comparator is connected to an output voltage node to receive an analog voltage signal, an inverting input terminal of the comparator is connected to a reference voltage, and an output terminal of the comparator is an output node of a pulse signal; the analog voltage signal is converted into a discrete pulse signal by comparing the size between the output voltage node and the reference voltage, and the discrete pulse signal is output to the output node of the pulse signal; a drain of the reset tube is electrically connected to the output voltage node, a source of the reset tube is connected to ground, and a gate of the reset tube is electrically connected to an external reset signal, so as to pull the output voltage node to the ground potential when the reset tube is turned on, thereby realizing the discharge of the metal-oxide semiconductor capacitor.

[0010] Further, the pulse signal is accumulated and counted to form a digital code word reflecting the intensity of the infrared light, which comprises: an SR latch, which latches the pulse signal into a digital signal of logic value 0 or 1, and temporarily stores the digital signal in an output node of the SR latch.

[0011] Further, the working stages of the pixel-level readout circuit include a reset stage, an integration stage, and a readout stage in sequence.

[0012] Further, in the reset stage, an external reset control signal connected to a reset terminal of the SR latch is set to a reset state, and the output node of the SR latch is discharged to 0 potential.

[0013] Further, in the integration stage, a source of the reset tube in the pulse frequency modulation analog-to-digital converter is connected to ground, and a drain of the reset tube is connected to the output voltage node; a first input terminal of the OR gate in the pulse frequency modulation analog-to-digital converter is connected to the output node of the pulse signal, a second input terminal of the OR gate is connected to a reset enable signal, and an output terminal of the OR gate is connected to a gate of the reset tube; when the output node of the pulse signal is at a high level or the reset enable signal is at a high level, the OR gate outputs a high level, thereby triggering the reset tube to be turned on, a path is formed between the source and the drain of the reset tube, so that the output voltage node is connected to ground, to realize the discharge and reset of the metal-oxide semiconductor capacitor, and then the metal-oxide semiconductor capacitor starts to integrate again.

[0014] Further, in the readout stage, the digital code word is output through the digital logic control unit, which includes NAND gate, NOR gate, NOT gate and inverter; wherein the level of the external readout control signal is set to high, and enters the digital logic control unit in two ways, one of which is connected with the P-type transfer tube in the inverter through the NAND gate, and the other is connected with the N-type transfer tube through the NOT gate after being inverted to low and input into the NOR gate; the external readout control signal outputs low level through the NAND gate and high level through the NOR gate to trigger the synchronous conduction of the P-type transfer tube and the N-type transfer tube, so that the digital code word of the output node of the SR latch is output through the single pixel output port.

[0015] Further, the pixel-level readout circuit further comprises a pulse accumulation counting function module cooperating with the SR latch; the pulse accumulation counting function module is used for receiving the pulse signal latched through the SR latch, and adjusting the number of counting bits of the pulse signal through external regulation and control of the counting configuration of the pulse accumulation counting function module; wherein the number of counting bits is positively correlated with the dynamic range of the infrared image sensor and negatively correlated with the imaging frame rate of the infrared image sensor.

[0016] The second aspect of the present application provides an infrared image sensor, comprising: a digital output module connected with the pixel-level readout circuit, used for receiving the digital signal of the pixel-level readout circuit and outputting; a digital scanning module connected with the pixel-level readout circuit, used for receiving external control parameters and generating control signals for the pixel-level readout circuit; a row driving module connected with the digital scanning module, used for driving the row-level reading of the pixel array in the infrared image sensor in response to the control signals of the digital scanning module; an external analog auxiliary module connected with the pixel-level readout circuit and the row driving module respectively, used for outputting bias voltage and clock signals to the pixel-level readout circuit and the row driving module; wherein the pixel-level readout circuit is any one of the pixel-level readout circuits in the above.

[0017] Compared with the prior art, the infrared image sensor and the pixel-level readout circuit thereof provided by the embodiments of the present application have at least the following beneficial effects:

[0018] (1) The pulse readout mode of the pixel-level readout circuit of the present application ensures the accumulation of readout data, and is compatible with image sensors of both high dynamic range and high sensitivity, and the dynamic adjustment of sensitivity is realized by adjusting the threshold voltage.

[0019] (2) The mode of the pixel-level readout circuit of the present application ensures that each pixel has a separate readout circuit, thereby improving the readout rate of the image sensor.

[0020] (3) The model of the pixel-level readout circuit of the present application ensures that the output of the pixel is a digital code word, thereby avoiding the problems of loss and noise caused by long distance. BRIEF DESCRIPTION OF DRAWINGS

[0021] The embodiments of the present application will be described below with reference to the accompanying drawings. In the drawings:

[0022] Figure 1 A circuit diagram of a pixel-level readout circuit according to an embodiment of the present application is schematically shown;

[0023] Figure 2 A chip block diagram of an infrared image sensor according to an embodiment of the present application is schematically shown;

[0024] Figure 3a A timing diagram of an infrared image sensor according to an embodiment of the present application is schematically shown;

[0025] Figure 3b A timing diagram of a single pixel of an infrared image sensor according to an embodiment of the present application is schematically shown.

[0026] REFERENCE NUMERALS

[0027] MP1 - injection transistor; MP2 - metal oxide semiconductor capacitor; VDE - external bias voltage; MN1 - reset transistor; RST - external reset signal; Vin - output voltage node; COMP - comparator; clear - reset enable signal; Vref - reference voltage; V_pulse - pulse signal output node; SR_OUT - output node of latch; RST_SR - external reset control signal; READ - external read control signal; MP3 - P-type transfer transistor; MN2 - N-type transfer transistor; Pixel_out - single pixel output port. DETAILED DESCRIPTION

[0028] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. It is to be understood, however, that the description is merely exemplary of the present application, and is not intended to limit the scope of the present application. In the following detailed description of the embodiments of the present application, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without these specific details. In other instances, well-known structures and functions have not been described in detail in order to avoid obscuring aspects of the present application.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the term "including" as well as other forms such as "include", "includes", and "including", are intended to mean the inclusion of one or more elements, steps, operations, and / or components, but not the exclusion of any other elements, steps, operations, and / or components.

[0030] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0031] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0032] In the infrared image sensor circuit, this application employs a pixel-level readout circuit design method, which directly performs analog-to-digital conversion of the light signal within the pixel and outputs it in the form of digital codewords. On the one hand, this eliminates the loss and noise caused by long-distance signal transmission; on the other hand, the pixel-level readout circuit avoids multiple pixels sharing a single analog-to-digital converter, thus improving the readout circuit speed. By modifying the cumulative number of digital codewords, the dynamic range of the circuit's operating voltage can be adjusted.

[0033] Figure 1 A schematic diagram of a pixel-level readout circuit according to an embodiment of this application is shown.

[0034] like Figure 1 The pixel-level readout circuit of the infrared image sensor shown is integrated inside a single pixel unit. The pixel-level readout circuit includes: a directly injected input stage circuit for converting the infrared photocurrent generated by the infrared image sensor into an analog voltage signal; a pulse frequency modulation analog-to-digital converter connected to the directly injected input stage circuit for converting the analog voltage signal into a pulse signal; an SR latch electrically connected to the pulse frequency modulation analog-to-digital converter for accumulating and counting the pulse signal to form a digital codeword reflecting the infrared light intensity; and a digital logic control unit electrically connected to the SR latch for transmitting the digital codeword to the readout bus of the infrared image sensor to realize the output of the digital signal.

[0035] For example, all the core functional modules of the pixel-level readout circuit are integrated into the smallest independent unit in the pixel array of the infrared image sensor. The integrated pixel-level readout circuit only processes the infrared photocurrent generated by the corresponding single pixel and does not participate in the signal conversion of other pixels, realizing a dedicated architecture of one readout circuit for one pixel, so as to realize complete functions such as signal conversion and output within a limited pixel space.

[0036] In the embodiment, the direct injection input stage circuit includes an injection tube MP1 and a metal oxide semiconductor capacitor MP2; a gate of the injection tube MP1 is connected to an external bias voltage VDE, a source is connected to an output end of the infrared detector, and a drain is electrically connected to a source of the metal oxide semiconductor capacitor MP2; a voltage value of the external bias voltage VDE is lower than a voltage of the output end of the infrared detector, so as to control the injection tube MP1 to be in a critical conduction state, so that the injection tube MP1 presents a stable high conduction resistance, and the stable infrared light-generated current is injected into the metal oxide semiconductor capacitor MP2.

[0037] For example, when the gate voltage is less than the source voltage, the P-type MOS tube MP1 is turned on. In the application, the gate voltage is slightly less than the source voltage, so that the injection tube MP1 is in a critical conduction state, which can ensure that the current is continuously injected and the current speed is slowed down through the high resistance.

[0038] The stability of the resistance of the injection tube MP1 can ensure that the current changes synchronously with the light intensity without introducing additional fluctuations. The uniform and stable current injection process provides key support for the core performances of the signal accuracy, dynamic range, and anti-interference ability of the entire pixel-level readout circuit.

[0039] In the embodiment, the pulse frequency modulation analog-to-digital converter includes a reset tube MN1, a comparator, and an OR gate; a noninverting input end of the comparator is connected to an output voltage node Vin to receive an analog voltage signal, an inverting input end is connected to a reference voltage Vref, and an output end is a pulse signal output node V_pulse; the analog voltage signal is converted into a discrete pulse signal and output to the pulse signal output node V_pulse by comparing the size between the output voltage node Vin and the reference voltage Vref; a drain of the reset tube MN1 is electrically connected to the output voltage node Vin, a source is connected to the ground, and a gate is electrically connected to an external reset signal RST, which is used to pull the output voltage node Vin to the ground potential to discharge the metal oxide semiconductor capacitor MP2 when turned on.

[0040] For example, the comparator is a five-tube OTA composed of MN3, MN4, MN5, MP4, and MP5, and the output end is a drain of MP5; wherein the drain of MP5 and the gate of MP6 are connected, MN6, the drain of MP6 and MN7 are connected, and the gate of MP7 is connected; the drain of MN7 and the gate of MN8, MP8 are connected; the drains of MN8 and MP8 are connected to the pulse signal output node V_pulse. The comparator converts the analog voltage signal into a discrete pulse signal by comparing the size between the voltage of the output voltage node Vin and the reference voltage Vref.

[0041] Furthermore, as photocurrent is injected, the voltage at the voltage node Vin gradually increases. When the voltage at the voltage node Vin and the reference voltage Vref are close, if the comparator gain is low, it cannot amplify this small difference, resulting in the inability to output the correct pulse and causing misjudgment. Therefore, the high gain of the five-transistor OTA in this application can amplify the small voltage difference to several volts, ensuring that even with weak light intensity, the voltage at the output voltage node Vin can be accurately detected to be greater than the reference voltage Vref.

[0042] In this embodiment of the application, the cumulative counting of pulse signals to form a digital codeword reflecting the intensity of infrared light includes: the SR latch latches the pulse signal as a digital signal with a logic value of 0 or 1, and temporarily stores it in the output node SR_OUT of the SR latch.

[0043] For example, the SR latch, as the signal conversion and temporary storage hub between the pulse frequency modulation analog-to-digital converter and the digital logic control unit, converts the discrete pulse signal (V_pulse) output by the pulse frequency modulation analog-to-digital converter into a stable and storeable logic value (0 or 1), and provides a basis for subsequent multi-pulse cumulative counting and digital codeword output through the temporary storage function, ensuring the reliable conversion of infrared light intensity signal from pulse form to digital form.

[0044] In this embodiment, the operation stages of the pixel-level readout circuit include a reset stage, an integration stage, and a readout stage in sequence.

[0045] In the embodiments of this application, during the reset phase, the external reset control signal RST_SR connected to the reset terminal R of the SR latch is set to the reset state, and the output node SR_OUT of the SR latch is discharged to 0 potential.

[0046] The external reset control signal RST_SR is in a high-level state.

[0047] By triggering the SR latch to reset via the external reset control signal RST_SR and forcing its output node SR_OUT to discharge to 0 potential, the pulse digital signals (logic value 1 or residual noise level) temporarily stored in the SR latch in the previous working cycle can be cleared. This ensures that the SR latch is in a zero initial state at the beginning of the integration phase of the current cycle, avoiding interference from historical digital signals with the latching and counting of subsequent pulses, and providing a basis for the accurate conversion of subsequent pulse signals to digital codewords.

[0048] In the embodiment of the present application, during the integration stage, the source of the reset transistor MN1 in the pulse frequency modulation analog-to-digital converter is grounded, and the drain is connected to the output voltage node Vin; the first input of the OR gate in the pulse frequency modulation analog-to-digital converter is connected to the pulse signal output node V_pulse, the second input of the OR gate is connected to the reset enable signal clear, and the output of the OR gate is connected to the gate of the reset transistor MN1; when the pulse signal output node V_pulse is at a high level or the reset enable signal clear is at a high level, the OR gate outputs a high level, thereby triggering the reset transistor MN1 to conduct, a path is formed between the source and the drain of the reset transistor MN1, so that the output voltage node Vin is grounded, the metal oxide semiconductor capacitor MP2 is discharged and reset, and the metal oxide semiconductor capacitor MP2 starts to integrate again.

[0049] Specifically, the automatic discharge cycle includes the following steps:

[0050] Initial integration start: after the reset stage, the RST signal returns to a low level, and the initial state of the reset transistor MN1 is cut off; the photo-generated current generated by the infrared detector is uniformly injected into the metal oxide semiconductor capacitor MP2 through the injection transistor MP1 (critical conduction), the MP2 starts to charge, and the voltage of the output voltage node Vin linearly rises with the charging time.

[0051] Pulse signal trigger: when the voltage of the output voltage node Vin is greater than the reference voltage (Vref), the output end V_pulse of the comparator jumps to a high level instantaneously, and the high level is input to the first input end of the OR gate as an automatic reset signal.

[0052] OR gate logic judgment and conduction of the reset transistor MN1: according to the logic of the OR gate, the first input end is at a high level at this time, and the OR gate outputs a high level regardless of the state of the second input end reset enable signal (clear); the high level is input to the gate of the reset transistor MN1, and since the reset transistor MN1 is an N-type MOS transistor, the high level of the gate triggers the reset transistor MN1 to conduct.

[0053] Discharge and reset of the metal oxide semiconductor capacitor MP2: after the reset transistor MN1 conducts, a low-resistance path is formed between the drain (connected to Vin) and the source (grounded) of the reset transistor MN1, the voltage of the output voltage node Vin is forced to ground potential (0V), and the charge stored in the MP2 is completely discharged (discharge and reset) through the reset transistor MN1; subsequently, the comparator detects that the voltage of the output voltage node Vin is less than the reference voltage Vref, the pulse signal output node V_pulse returns to a low level, the output of the OR gate changes to a low level, the reset transistor MN1 is cut off, the MP2 stops discharging, and the next round of integration starts again by receiving the photo-generated current, thereby completing one integration and discharge cycle.

[0054] On the other hand, the reset transistor MN1 is triggered to conduct by an externally input reset enable signal clear.

[0055] Specifically, the external control unit (such as a digital scanning module) sets the reset permission signal clear to high level, which is input to the second input end of the or gate; at this time, the or gate still outputs high level regardless of the state of the pulse signal output node V_pulse.

[0056] For example, the reset permission signal clear is a dedicated start trigger signal for the first frame of the infrared image sensor, and the start behavior marks that the chip is formally switched from the initialization ready state to the normal imaging working mode, and a complete timing cycle and imaging process are started.

[0057] Specifically, after the basic initialization of the chip is completed, the working start of the first frame is triggered by the clear signal: the clear signal is first set to high, and cooperates with the external reset signal RST to make the metal oxide semiconductor capacitor MP2 complete initial discharge and zero, so as to prepare for signal collection of the first frame; then the clear signal is set to 0 in time sequence, triggering the metal oxide semiconductor capacitors MP2 in each pixel row in the pixel array to start integration in turn, ensuring that the integration time of all pixel rows in the first frame is strictly consistent, and avoiding uneven imaging in the frame caused by differences in start timing. In the readout stage, the digital code is output by the digital logic control unit, which includes NAND gate, NOR gate, NOR gate and inverter; wherein the level of the external readout control signal READ is set to high, and is input into the digital logic control unit in two ways, one of which is connected with the P-type transistor MP3 in the inverter through the NAND gate, and the other is input into the NOR gate after being inverted to low by the NAND gate and connected with the N-type transistor MN2; the external readout control signal READ outputs low through the NAND gate and high through the NOR gate to realize the synchronous conduction of the P-type transistor MP3 and the N-type transistor MN2, so that the digital code of the output node SR_OUT of the SR latch is output through the single pixel output port Pixel_out.

[0058] For example, through the complementary synchronous conduction of the P-type transistor MP3 and the N-type transistor MN2, the digital code (logic 0 / 1) is matched with the SR latch output (SR_OUT) without deviation. At the same time, only when the external readout control signal READ is high, the logic gate and the transistor produce dynamic power consumption; when the external readout control signal READ is low, all elements are in the off or static state, without static power consumption, which is suitable for the low power design requirement of the million-pixel-level infrared image sensor.

[0059] In the embodiment, the pixel-level readout circuit further comprises a pulse accumulation counting function module cooperating with the SR latch; the pulse accumulation counting function module is configured to receive the pulse signal after being latched by the SR latch, and to adjust the number of accumulated counting bits of the pulse signal by externally regulating the counting configuration of the pulse accumulation counting function module; wherein the number of counting bits is positively correlated with the dynamic range of the infrared image sensor and negatively correlated with the imaging frame rate of the infrared image sensor.

[0060] The pulse accumulation counting function module is configured to accurately count the total number of pulse signals corresponding to the infrared light intensity, and specifically comprises the following stages:

[0061] Preparation stage (when resetting): the pulse accumulation counting function module and the SR latch are synchronized to be cleared, an external reset signal RST_SR triggers the counting register to be level 0, and an external control code (such as a 4-bit configuration signal) is configured to set the number of counting bits (8 / 10 / 12 bits, etc.) to determine the effective bit number of the register.

[0062] Pulse receiving stage: the logic value (1 or 0) output by the SR latch is received in the integration stage, and the counting action is triggered only when a logic 1 is detected.

[0063] Accumulation counting stage: the counting register accumulates the number of pulses (such as 10 times for weak light and 100 times for strong light) under the synchronization of the integration clock, and only counts in the integration stage to avoid noise interference in the readout / reset stage.

[0064] Result output stage: a multi-bit digital code word is generated and output by the digital logic control unit.

[0065] More counting bits can distinguish finer light intensity gradients (larger dynamic range), but the data processing time is longer (lower frame rate); fewer bits can have a higher frame rate, but the dynamic range is smaller, so that the imaging accuracy and speed can be flexibly adapted to the needs of different scenes.

[0066] Figure 2 A chip block diagram of an infrared image sensor according to an embodiment of the application is schematically shown.

[0067] As Figure 2The infrared image sensor comprises: a digital output module connected with the pixel-level readout circuit, configured to receive a digital signal of the pixel-level readout circuit and output; a digital scanning module connected with the pixel-level readout circuit, configured to receive an external control parameter and generate a control signal for the pixel-level readout circuit; a row driving module connected with the digital scanning module, configured to drive a row-level reading of a pixel array in the infrared image sensor in response to the control signal of the digital scanning module; and an external analog auxiliary module connected with the pixel-level readout circuit and the row driving module respectively, configured to output a bias voltage and a clock signal to the pixel-level readout circuit and the row driving module; wherein the pixel-level readout circuit is the pixel-level readout circuit of any one of the above circuits.

[0068] The digital scanning module is the core of coordinating the work of each module, responsible for converting external control parameters into precise timing control signals, and the main functions include receiving external control parameters, generating control signals and timing synchronization.

[0069] Specifically, for receiving external control parameters, external instructions are received through an interface, including imaging frame rate, integration time, etc.; control signals in the form of 16-bit digital codes (such as clear, RST, READ, HSYNC) are generated according to parameter analysis results, and the frequency, pulse width and delay time of the signals are defined. Timing synchronization, synchronize the control signal with the clock signal provided by the external analog auxiliary module, ensure that all modules work according to the unified timing, and avoid signal collision.

[0070] The row driving module responds to the instructions of the digital scanning module to realize the orderly work of the pixel array row by row.

[0071] Specifically, the row driving module obtains the row selection signal from the digital scanning module, activates the pixel-level readout circuit row by row in the order from top to bottom or from left to right; for the currently activated row, the corresponding control signal RST_SR or external readout control signal READ is issued, triggering the row of pixels to enter the reset, integration or readout stage.

[0072] For example, when the first row performs readout, the second row is in the integration stage, and the third row is in the reset stage, realizing parallel pipeline operation among multiple rows. By driving row by row, it is ensured that only one row (or a few rows) of pixels transmits data to the digital output module at the same time, greatly reducing the transmission pressure of the readout bus and avoiding signal collision and distortion.

[0073] The external analog auxiliary module provides stable energy supply and timing reference for the entire system to ensure the working accuracy of the circuit.

[0074] Specifically, the external analog auxiliary module is configured to provide an external bias voltage VDE, a reference voltage Vref, etc., which can be fine-tuned by an external potentiometer according to an application scenario, so as to adjust the threshold of the pulse signal, thereby providing a function that the image sensor can normally shoot under a certain range of light intensity.

[0075] The external analog auxiliary module also provides a system clock and a control clock signal, and is configured to isolate the analog voltage and the digital voltage, so as to avoid the switching noise of the digital circuit from being coupled to the analog circuit.

[0076] The digital output module is configured to convert the discrete digital code word of the pixel-level readout circuit into a signal format recognizable by an external device.

[0077] Specifically, the digital code word (for example, a 10-bit binary code) transmitted row by row is received from a single pixel output port Pixel_out of the pixel-level readout circuit array, and the row synchronization signal of the row driving module is synchronously received; the conversion from the parallel signal to the serial signal is completed, and the data format is regularized according to the requirement of the external device and is outputted externally.

[0078] Figure 3a The timing diagram of the infrared image sensor according to the embodiment of the application is schematically shown; Figure 3b The timing diagram of a single pixel of the infrared image sensor according to the embodiment of the application is schematically shown.

[0079] In the embodiment, the readout of the pixel-level readout circuit is in a rolling readout mode, and a reset permission signal clear is added in the first frame, so that the integration time of each row is the same.

[0080] When the reset permission signal clear is set to a high level, the external reset signal RST is at a high level, the capacitor is in a discharging state, the reset permission signal clear signal is set to 0 row by row, and the capacitor starts to integrate row by row, so as to ensure that the integration time of each row in the first frame is the same. After the pixel array is exposed, the photoelectric current is injected into the metal-oxide semiconductor capacitor MP2, and the voltage of the output voltage node Vin is accumulated to the threshold reference voltage Vref. When the voltage of the output voltage node Vin reaches the threshold reference voltage Vref, the pulse signal output node V_pulse is flipped from 0 to 1, the external reset signal RST is set to 1, the capacitor is discharged to 0V, and the comparator output high level is sent to the SR latch. When the readout time of the first frame is reached, the external readout control signal READ signal is set to a high level, the output signal stored in the SR latch is sent to the signal bus, and then the control signal RST_SR is set to a high level to reset the SR, and the readout work of a new frame is started. At the same time, the row synchronization signal HYSNC is set to a high level, and the single pixel output port Pixel_out is read into the register of the digital logic. In this process, since the chip is in a rolling readout mode, the control signal RST_SR and the external readout control signal READ signal of each row are set to a high level row by row.

[0081] Those skilled in the art will appreciate that features recited in the various embodiments of the present disclosure can be combined and / or incorporated in various combinations, even if such combinations have not been recited in the present disclosure. In particular, features recited in the various embodiments of the present disclosure can be combined and / or incorporated in various combinations without departing from the spirit and teachings of the present disclosure. All such combinations are within the scope of the present disclosure.

[0082] The above describes embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes, and are not intended to limit the scope of the present disclosure. Although each embodiment is described above separately, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and these substitutions and modifications shall all fall within the scope of the present disclosure.

Claims

1. A pixel-level readout circuit for an infrared image sensor, characterized in that, Integrated within a single pixel unit, the pixel-level readout circuit includes: The directly injected input stage circuit is used to convert the infrared photocurrent generated by the infrared image sensor into an analog voltage signal; A pulse frequency modulation analog-to-digital converter connected to the directly injected input stage circuit is used to convert the analog voltage signal into a pulse signal; An SR latch electrically connected to the pulse frequency modulation analog-to-digital converter is used to accumulate and count the pulse signal to form a digital codeword reflecting the intensity of infrared light. The digital logic control unit, which is electrically connected to the SR latch, is used to transmit the digital codeword to the readout bus of the infrared image sensor to realize the output of digital signals.

2. The pixel-level readout circuit of the infrared image sensor according to claim 1, characterized in that, The direct injection input stage circuit includes an injection tube (MP1) and a metal-oxide-semiconductor capacitor (MP2). The gate of the injection tube (MP1) is connected to an external bias voltage (VDE), the source is connected to the output terminal of the infrared detector, and the drain is electrically connected to the source of the metal oxide semiconductor capacitor (MP2). The external bias voltage (VDE) is lower than the output voltage of the infrared detector to control the injection tube (MP1) to be in a critical conduction state, so that the injection tube (MP1) presents a stable high on-resistance, ensuring the stability of the infrared photogenerated current injected into the metal oxide semiconductor capacitor (MP2).

3. The pixel-level readout circuit of the infrared image sensor according to claim 1, characterized in that, The pulse frequency modulation analog-to-digital converter includes: a reset transistor (MN1), a comparator, and an OR gate; The non-inverting input of the comparator is connected to the output voltage node (Vin) to receive the analog voltage signal, the inverting input is connected to the reference voltage (Vref), and the output is the pulse signal output node (V_pulse). By comparing the magnitude between the output voltage node (Vin) and the reference voltage (Vref), the analog voltage signal is converted into a discrete pulse signal and output to the pulse signal output node (V_pulse). The drain of the reset transistor (MN1) is electrically connected to the output voltage node (Vin), the source is grounded, and the gate is electrically connected to the external reset signal (RST). It is used to pull the output voltage node (Vin) to ground potential when it is turned on so as to discharge the metal oxide semiconductor capacitor (MP2).

4. The pixel-level readout circuit of the infrared image sensor according to claim 1, characterized in that, Accumulating and counting the pulse signals to form a digital codeword reflecting the infrared light intensity includes: The SR latch latches the pulse signal as a digital signal with a logic value of 0 or 1, and temporarily stores it in the output node (SR_OUT) of the SR latch.

5. The pixel-level readout circuit of the infrared image sensor according to claim 1, characterized in that, The operation of the pixel-level readout circuit includes, in sequence, a reset stage, an integration stage, and a readout stage.

6. The pixel-level readout circuit of the infrared image sensor according to claim 5, characterized in that, During the reset phase, the external reset control signal (RST_SR) connected to the reset terminal (R) of the SR latch is set to the reset state, and the output node (SR_OUT) of the SR latch is discharged to 0 potential.

7. The pixel-level readout circuit of the infrared image sensor according to claim 5, characterized in that, During the integration phase, the source of the reset transistor (MN1) in the pulse frequency modulation analog-to-digital converter is grounded, and its drain is connected to the output voltage node (Vin); the first input of the OR gate in the pulse frequency modulation analog-to-digital converter is connected to the pulse signal output node (V_pulse), the second input of the OR gate is connected to the reset enable signal (clear), and the output of the OR gate is connected to the gate of the reset transistor (MN1); When the pulse signal output node (V_pulse) is high or the reset enable signal (clear) is high, the OR gate outputs a high level, thereby triggering the reset transistor (MN1) to conduct. A path is formed between the source and drain of the reset transistor (MN1) to ground the output voltage node (Vin), thereby clearing the metal oxide semiconductor capacitor (MP2) and allowing the metal oxide semiconductor capacitor (MP2) to start integrating again.

8. The pixel-level readout circuit of the infrared image sensor according to claim 5, characterized in that, During the readout phase, the digital codeword is output by the digital logic control unit, which includes NOT gates, NAND gates, NOR gates, and inverters. The external read control signal (READ) is set to a high level and enters the digital logic control unit in two paths. One path is connected to the P-type transmission tube (MP3) in the inverter via the NAND gate, and the other path is inverted to a low level by the NOT gate, input to the NOR gate and connected to the N-type transmission tube (MN2). The external readout control signal (READ) triggers the synchronous conduction of the P-type transmission tube (MP3) and the N-type transmission tube (MN2) by the NAND gate outputting a low level and the NOR gate outputting a high level, so that the digital codeword of the output node (SR_OUT) of the SR latch is output through a single pixel output port (Pixel_out).

9. The pixel-level readout circuit of the infrared image sensor according to claim 1, characterized in that, The pixel-level readout circuit also includes a pulse accumulation and counting function module that works in conjunction with the SR latch; The pulse cumulative counting function module is used to receive the pulse signal latched by the SR latch, and to adjust the cumulative count bits of the pulse signal by externally controlling the counting configuration of the pulse cumulative counting function module; The number of bits counted is positively correlated with the dynamic range of the infrared image sensor and negatively correlated with the imaging frame rate of the infrared image sensor.

10. An infrared image sensor, characterized in that, include: A digital output module connected to the pixel-level readout circuit is used to receive and output digital signals from the pixel-level readout circuit. The digital scanning module connected to the pixel-level readout circuit is used to receive external control parameters and generate control signals for the pixel-level readout circuit. The row driving module connected to the digital scanning module is used to respond to the control signal of the digital scanning module to drive the row-level reading of the pixel array in the infrared image sensor; An external analog auxiliary module, which is connected to the pixel-level readout circuit and the row driving module respectively, is used to output bias voltage and clock signal to the pixel-level readout circuit and the row driving module. The pixel-level readout circuit is the pixel-level readout circuit according to any one of claims 1 to 9.

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