Local copper-exposed structure for PCB (Printed Circuit Board) positioning hole and optimization design method of local copper-exposed structure

Abstract

The invention relates to integrated circuit manufacturing, in particular to the field of manufacturing of special equipment for producing semiconductor devices such as a special photoetching machine and an etching machine, and provides a local copper-exposed structure for a PCB (printed circuit board) positioning hole and an optimization design method of the local copper-exposed structure. The PCB positioning hole comprises a front face and a back face and is provided with a base material drill hole and an encapsulation window covering the periphery of the base material drill hole, and the aperture of the encapsulation window is larger than that of the base material drill hole. The method comprises the following steps: determining that the front surface of the PCB positioning hole is an element surface and the back surface of the PCB positioning hole is a welding surface, and obtaining the drilling hole diameter of the base material drilling hole and the windowing hole diameter of the packaging windowing; performing copper extraction treatment on the encapsulation windowing area on the front surface, and reserving a copper exposure area meeting the minimum electrical connection or mechanical positioning requirement in the encapsulation windowing area on the front surface; a copper exposing area reserved on the front face is optimized to be a latticed copper layer, and the latticed copper layer is used for reducing the use area of copper while enough adhesive force or electrical performance is guaranteed.

Description

TECHNICAL FIELD

[0001] The present application relates to integrated circuit manufacturing, especially in the technical field of manufacturing special-purpose equipment for semiconductor devices such as special-purpose photolithography machines, etching machines, etc., and in particular to a partial copper exposure structure for PCB positioning holes and an optimization design method thereof. BACKGROUND

[0002] In the field of integrated circuit manufacturing, especially in the field of manufacturing special-purpose equipment for semiconductor devices such as special-purpose photolithography machines, etching machines, etc., positioning holes are key structures for realizing mechanical positioning (such as insertion, mounting, detection) and partial electrical connection (such as grounding, signal transmission) of PCB boards. The traditional design of positioning holes usually adopts a "double-sided full open window copper exposure" structure: that is, a peripheral encapsulated open window (such as a hole diameter of 2.5 mm) is arranged outside the substrate drilling (such as a hole diameter of 2.0 mm), and the front surface (component surface) and back surface (soldering surface) of the encapsulated open window area are both kept intact copper foil, forming a "double-sided copper exposure" structure. However, the above traditional design has the following significant defects: 1. Serious copper material waste: double-sided full open window leads to large copper exposure area, high copper material usage, and increased PCB manufacturing cost; 2. Poor back surface soldering reliability: the copper exposure area on the back surface (soldering surface) is prone to oxidation, tin contamination, and other problems affecting soldering quality, for example, the soldering tin may accidentally touch the copper exposure area of the positioning hole during soldering, causing short circuit or false soldering; 3. Insufficient adhesion of solder resist: the large-area solid copper exposure area on the front surface (component surface) has limited contact area with the solder resist, and the difference in thermal expansion coefficient between the copper layer and the substrate is large, which easily leads to the peeling off of the solder resist, affecting the moisture-proof and oxidation-proof performance of the PCB; 4. Lack of design flexibility: if the encapsulated open window diameter is simply reduced to reduce the copper exposure area, it will cause the positioning pin to be unable to be inserted smoothly (the encapsulated open window needs to be at least 0.2 mm larger than the substrate drilling to meet the positioning accuracy requirement), which will affect the mechanical positioning function; if only single-sided copper exposure is used, the electrical connection requirements on the front surface (such as some positioning holes needing to be used as grounding terminals) cannot be met.

[0003] Therefore, there is an urgent need for a method to solve at least one of the above problems. SUMMARY

[0004] The application relates to integrated circuit manufacturing, in particular to a local copper exposure structure of a PCB positioning hole and an optimization design method thereof in the field of manufacturing special-purpose equipment such as special-purpose photoetching machines and etching machines for semiconductor devices, and aims to solve the problem that a traditional positioning hole design usually adopts a "double-face full-open window copper exposure" structure, that is, a base material drilling hole (such as a hole diameter of 2.0 mm) is provided with a package window (such as a hole diameter of 2.5 mm) in the periphery, and the front surface (component surface) and the back surface (soldering surface) of the package window area are both kept intact copper foil, forming a "double-face copper exposure" structure. However, the traditional design has the problems of serious copper material waste, poor back surface soldering reliability, insufficient solder resist adhesion and insufficient design flexibility.

[0005] In a first aspect, the embodiments of the application provide an optimization design method of a local copper exposure structure of a PCB positioning hole, the PCB positioning hole comprising a front surface and a back surface, having a base material drilling hole and a package window covering the periphery of the base material drilling hole, and the hole diameter of the package window being larger than the hole diameter of the base material drilling hole; the method comprising: determining that the front surface of the PCB positioning hole is a component surface and the back surface is a soldering surface, obtaining the drilling hole diameter of the base material drilling hole and the window hole diameter of the package window; performing copper digging processing on the package window area of the front surface, and keeping a copper exposure area meeting the minimum electrical connection or mechanical positioning requirement in the package window area of the front surface, comprising: calculating the minimum diameter of the copper exposure area needed to be kept in the package window area of the front surface according to the mechanical positioning tolerance requirement of the PCB positioning hole; in a PCB design software, taking the center coordinates of the base material drilling hole as the center of a circle, and drawing a circular or annular reserved area equal to the minimum diameter; using a copper foil trimming tool of the design software, selecting all copper foil objects in the package window area of the front surface except the reserved area, and performing a deletion operation to form a copper foil structure after copper digging of the front surface; performing full etching processing on the package window area of the back surface to completely remove the copper foil in the package window area of the back surface, and only keeping the base material; optimizing the copper exposure area kept on the front surface into a grid-shaped copper layer, the grid-shaped copper layer being used to reduce the use area of copper while ensuring sufficient adhesion or electrical performance.

[0006] In some embodiments, the obtaining of the drilling hole diameter of the base material drilling hole and the window hole diameter of the package window comprises: reading the labeled hole diameter value of the base material drilling hole layer from the CAD design file of the PCB, and taking the labeled hole diameter value as the drilling hole diameter of the base material drilling hole; performing pixel scanning on the solder resist layer corresponding to the package window through an image recognition tool, extracting the maximum outer diameter size of the package window, and taking the maximum outer diameter size as the window hole diameter of the package window; inputting the drilling hole diameter and the window hole diameter into a PCB process verification module to verify whether the window hole diameter meets the preset minimum gap requirement of the package window and the base material drilling hole, and if not, generating hole diameter adjustment prompt information.

[0007] In some embodiments, the process of performing full etching on the back-side encapsulation window area to completely remove the copper foil within the back-side encapsulation window area, leaving only the substrate, includes: selecting all copper foil objects within the encapsulation window area in the back-side copper foil layer of the PCB design software and adding etching removal attribute markers to the copper foil objects; generating an etching instruction file containing coordinate information of the marked areas corresponding to the attribute markers, wherein the coordinate information is based on the absolute coordinate system of the PCB; sending the etching instruction file to a chemical etching device and controlling the device to etch the marked areas according to preset etching process parameters; the etching process parameters include 30°C, 60 seconds, and a 15% concentration etching solution; after etching, taking an image of the back-side encapsulation window area using an automatic optical inspection device, comparing the taken image with a reference image of the substrate without copper foil using an image comparison algorithm to verify whether the copper foil has been completely removed; if there is any residue, resending an extended etching instruction to the device until verification is successful.

[0008] In some embodiments, optimizing the exposed copper area retained on the front side into a grid-like copper layer includes: determining the minimum linewidth and maximum grid spacing of the grid-like copper layer according to the solder resist adhesion test standard; using the grid generation tool of PCB design software, generating a square or rhomboid grid pattern that conforms to the minimum linewidth and maximum grid spacing within the exposed copper area retained on the front side, with the center of the substrate drill hole as the origin; aligning the grid pattern with the boundary of the encapsulation opening area to ensure that the grid pattern is completely located within the encapsulation opening area; simulating the bonding strength between the grid-like copper layer and the substrate using finite element analysis software; if the simulation result reaches a preset adhesion threshold, retaining the corresponding grid design; if not, increasing the grid linewidth or decreasing the grid spacing, regenerating the grid pattern and simulating again until the threshold requirement is met.

[0009] In some embodiments, the method further includes: collecting historical mechanical positioning accuracy requirements for PCB positioning holes and traditional fully-open copper exposed area dimensions and corresponding positioning error data to construct a training dataset; training a random forest regression model based on the training dataset, wherein the input of the random forest regression model is the mechanical positioning accuracy requirement, and the output is the minimum diameter of the exposed copper area to be retained within the front encapsulation opening area; inputting the mechanical positioning accuracy requirement corresponding to the PCB positioning hole into the trained random forest regression model to obtain the output minimum diameter prediction value; comparing the minimum diameter prediction value with the encapsulation opening hole diameter to verify whether the encapsulation opening hole diameter is at least 0.5 mm larger than the prediction value; if it meets the requirement, the minimum diameter prediction value is used as the diameter of the front retained area; if it does not meet the requirement, an encapsulation opening hole diameter adjustment suggestion is generated.

[0010] In some embodiments, the method further includes: using the linewidth and grid spacing of the front mesh copper layer as optimization variables, and the copper foil usage area reduction rate and solder resist adhesion compliance rate as optimization objectives; constructing a fitness function using the DEAP genetic algorithm library, wherein the solder resist adhesion compliance rate has a higher weight than the copper foil usage area reduction rate; initializing multiple candidate solutions, each candidate solution containing a set of linewidth and spacing parameters, performing multiple iterations, and retaining a preset number of candidate solutions in each generation based on fitness; simulating the adhesion of the mesh copper layer using finite element analysis software for the candidate solutions retained in each generation, and selecting the candidate solutions that simultaneously satisfy the two optimization objectives as the target solutions; if there are multiple target solutions, selecting the target solution with the highest copper foil usage area reduction rate as the final parameters of the front mesh copper layer.

[0011] In some embodiments, the method further includes: collecting multiple sets of etching process parameters and corresponding residual copper foil area data to construct a training dataset; the etching process parameters include etching time, temperature, and solution concentration; training a convolutional neural network model using the training dataset, wherein the input of the convolutional neural network model is etching time, temperature, and solution concentration, and the output is a predicted value of the residual copper foil area; during the back-side etching process, an automatic optical inspection device takes an image of the back-side sealed window area at a preset interval and extracts the area value of the residual copper foil; inputting the current etching process parameters and the extracted residual copper foil area value into the trained convolutional neural network model to obtain the optimized etching process parameters output by the convolutional neural network model; sending the optimized etching process parameters to the etching equipment, and controlling the equipment to adjust according to the etching process parameters and continue to execute the etching steps until the residual copper foil area is 0.

[0012] In some embodiments, the method further includes: collecting multiple sets of size and shape data of the exposed copper area on the front side and corresponding positioning error data to construct a training dataset, wherein the size includes a diameter of 2mm-3mm and the shape includes circles and rings; training a classification model using a support vector machine, wherein the input of the classification model is the size and shape of the exposed copper area on the front side, and the output is a judgment result indicating whether the positioning error meets the standard; after the copper removal process on the front side is completed, the size and shape of the retained exposed copper area are input into the trained classification model to obtain the judgment result output by the classification model; if the judgment result is negative, the size or shape of the exposed copper area on the front side is automatically adjusted or changed, and the copper removal process on the front side is re-executed until the judgment result output by the model is positive.

[0013] In some embodiments, the method further includes: inputting the copper foil structure parameters after copper removal on the front side, the copper foil structure parameters after full etching on the back side, and the parameters of the front grid-like copper layer into an intelligent design integration module; the intelligent design integration module matches each parameter with PCB manufacturing process rules through a rule engine, and if parameter conflicts are found, automatically adjusts the parameters to eliminate the conflicts; based on the integrated parameters, automatically generates a manufacturing file containing a front copper foil layer, a back copper foil layer, a substrate drilling layer, and an encapsulation window layer; converting the manufacturing file into instructions that can be recognized by the production equipment, and starting the processing flow of the positioning holes.

[0014] Secondly, this application provides a partially exposed copper structure for PCB positioning holes, which is optimized based on the method provided in any embodiment of this application.

[0015] This application reduces copper foil exposure by removing copper foil through full etching on the back and removing copper from the front, resulting in a reduction of copper material usage per hole by approximately 50%, significantly lowering copper material costs. The absence of exposed copper on the back soldering surface avoids issues such as solder mis-contact and oxidation during soldering, improving soldering yield. The grid-like copper layer on the front increases the contact area with the solder resist (more than 30% larger than a solid copper layer), and the grid structure mitigates thermal expansion differences, reducing solder resist peeling. The minimal exposed copper area retained on the front meets mechanical positioning (encapsulation opening is still 0.5mm larger than the substrate drill hole) and electrical connection requirements (e.g., grounding resistance ≤0.1Ω) without sacrificing core functionality. The shape of the exposed copper area can be adjusted according to front requirements (e.g., ring-shaped, partially solid), making it suitable for different types of PCBs (e.g., consumer electronics, industrial control).

[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic flowchart illustrating the steps of an optimized design method for a partially exposed copper structure for PCB positioning holes, provided in an embodiment of this application. Figure 2 This is a schematic block diagram of an optimized design system for a partial exposed copper structure of a PCB positioning hole, provided in one embodiment of this application. Figure 3 This is a schematic block diagram of the structure of a computer device provided in an embodiment of this application.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0022] It should be understood that, in order to clearly describe the technical solutions of the embodiments of the present invention, the terms "first" and "second" are used in the embodiments of the present invention to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and the terms "first" and "second" are not necessarily different.

[0023] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0024] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0025] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0026] In PCB manufacturing, positioning holes are crucial structures for achieving mechanical positioning of the PCB board (such as component insertion, mounting, and testing) and some electrical connections (such as grounding and signal transmission). Traditional positioning hole designs typically employ a "double-sided fully exposed copper" structure: a hole in the substrate (e.g., 2.0mm diameter) is surrounded by an encapsulated window (e.g., 2.5mm diameter), and both the front (component side) and back (soldering side) of the encapsulated window area retain complete copper foil, forming a "double-sided exposed copper" structure. However, the above traditional design has the following significant drawbacks: 1. Significant copper waste: Double-sided full-window design results in a large exposed copper area, leading to high copper consumption and increased PCB manufacturing costs; 2. Poor reliability of back-side soldering: The exposed copper area on the back side (soldering surface) is prone to problems such as oxidation and solder contamination, which can affect the soldering quality. For example, during the soldering process, the solder may accidentally touch the exposed copper area of ​​the positioning hole, resulting in a short circuit or poor soldering. 3. Insufficient adhesion of solder resist: The contact area between the large solid exposed copper area on the front side (component side) and the solder resist is limited, and the thermal expansion coefficients of the copper layer and the substrate are significantly different, which can easily lead to the solder resist peeling off and affect the PCB's moisture-proof and oxidation-proof performance. 4. Insufficient design flexibility: If the exposed copper area is reduced simply by shrinking the diameter of the encapsulation opening, the positioning pin will not be able to be inserted smoothly (the positioning accuracy requires the encapsulation opening to be at least 0.2mm larger than the base material drilling hole), which will affect the mechanical positioning function. If only single-sided copper exposure is changed, the electrical connection requirements on the front side cannot be taken into account (such as some positioning holes needing to be used as grounding terminals).

[0027] Therefore, a method is urgently needed to solve at least one of the above problems.

[0028] To solve the above problem, please refer to Figure 1 This application provides an optimized design method for partially exposed copper structures of PCB positioning holes, applicable to computer equipment that can be deployed on a single server or server cluster. It can also be deployed on handheld terminals, laptops, wearable devices, or robots, etc.

[0029] The provided optimized design method for the partial exposed copper structure of PCB positioning holes includes steps S101 to S103. Details are as follows: Step S101. Determine that the front side of the PCB positioning hole is the component side and the back side is the soldering side, obtain the drilling diameter of the substrate hole and the opening diameter of the encapsulation opening; perform copper removal processing on the encapsulation opening area on the front side, and retain an exposed copper area that meets the minimum electrical connection or mechanical positioning requirements within the encapsulation opening area on the front side, including: calculating the minimum diameter of the exposed copper area to be retained within the encapsulation opening area on the front side according to the mechanical positioning tolerance requirements of the PCB positioning hole; in the PCB design software, draw a circular or annular retention area equal to the minimum diameter with the center coordinates of the substrate hole as the center; use the copper foil trimming tool of the design software to select all copper foil objects in the encapsulation opening area on the front side except for the retention area, and perform a deletion operation to form the copper foil structure on the front side after copper removal.

[0030] Specifically, addressing the issues of copper waste and insufficient solder resist adhesion caused by traditional full-opening windows, a "copper removal" operation is used to preserve an exposed copper area within the front-facing window area that meets minimum electrical connection (such as grounding) or mechanical positioning requirements, while simultaneously reducing the exposed copper area (at least 1mm smaller than traditional full-opening windows). The core principle is to reduce the amount of copper foil used on the front while maintaining functionality, and to lay the foundation for subsequent grid optimization.

[0031] Parameter acquisition and minimum diameter calculation: By defining the front side of the PCB positioning holes as the component side, obtain the "drill hole diameter" (e.g., traditional 2.0mm) for the substrate drilling and the "window opening diameter" (e.g., traditional 2.5mm) for the encapsulation opening. Based on the mechanical positioning tolerance requirements of the PCB positioning holes (e.g., the gap for the positioning pin insertion, the minimum contact area for electrical connections), calculate the minimum diameter of the exposed copper area to be retained on the front side—this diameter must be at least 1mm smaller than the diameter of the traditional fully opened exposed copper area (equal to the window opening diameter, e.g., 2.5mm) (e.g., the minimum diameter is set to 1.5mm).

[0032] In PCB design software, a circular or annular area with a diameter equal to the minimum diameter is drawn, with the center coordinates of the drill hole in the substrate as the center. (For example, a circle with a diameter of 1.5mm, or an annular shape with an inner diameter equal to the drill hole diameter and an outer diameter equal to the minimum diameter.)

[0033] The copper removal operation uses the "copper foil trimming tool" in the design software. Select all copper foil objects in the front enclosure area except for the reserved area, and perform the deletion operation. The final result is a front copper foil structure with "a small area of ​​exposed copper in the center and copper removed around the perimeter" (for example, in an area with a window diameter of 2.5mm, only a circular exposed copper with a diameter of 1.5mm in the center is retained).

[0034] Step S102. Perform full etching on the encapsulation window area on the back side to completely remove the copper foil in the encapsulation window area on the back side, leaving only the substrate.

[0035] Specifically, addressing the poor soldering reliability issues (oxidation, solder smudging, short circuits / cold solder joints) caused by traditional back-side fully exposed copper, a "full etching" operation completely removes the copper foil covering the exposed area on the back side, leaving only the substrate. This completely resolves the soldering risks caused by exposed copper on the back side, while further reducing the amount of copper used.

[0036] In PCB design software, select the encapsulation opening area on the back side (soldering side) (i.e., the area with the same opening diameter as the front side, such as 2.5mm), and execute the "Full Etch" setting (or directly delete all copper foil objects in this area). The final result is: there is no copper foil in the back encapsulation opening area, only the substrate (resin or glass fiber) is retained, avoiding solder contact with this area during soldering.

[0037] Step S103. Optimize the exposed copper area retained on the front side into a grid-like copper layer, which is used to reduce the area of ​​copper used while ensuring sufficient adhesion or electrical performance.

[0038] Specifically, addressing the potential issues of insufficient solder resist adhesion (due to the large difference in thermal expansion coefficients between solid copper and the substrate) or wasted copper in the small solid exposed copper area retained in step S101, the solid exposed copper is optimized into a "grid-like copper layer." The grid structure increases the contact area between the copper layer and the solder resist (improving adhesion) while reducing the area of ​​copper used (saving material compared to solid copper), thus balancing electrical performance (such as grounding conductivity) and cost.

[0039] The mesh parameter design is based on the shape of the reserved area (circular or annular), setting the mesh line width (e.g., 0.2mm, to meet the minimum line width requirement for electrical conductivity) and spacing (e.g., 0.5mm, to ensure sufficient mesh density to support the adhesion of the solder resist).

[0040] In PCB design software, select the small exposed copper area (such as a 1.5mm diameter circle) retained in step S101, and use the "Grid Fill Tool" (such as Altium's "Grid Fill" or PADS' "Mesh Tool") to convert the solid copper layer into a grid. For example, converting a 1.5mm circular area into a grid with a "0.2mm line width and 0.5mm spacing" reduces the copper area by approximately 50% compared to solid copper.

[0041] Verify the conductivity of the grid-like copper layer (such as whether the grounding resistance meets the requirements) by using the "Electrical Rule Check (ERC)" in the design software, or verify the thermal expansion matching (whether the grid structure reduces the stress difference between the copper and the substrate) by using the "Thermal Analysis Tool" to ensure that the optimized grid-like copper layer meets the minimum requirements for electrical connection or mechanical positioning.

[0042] In some embodiments, obtaining the bore diameter of the substrate drill and the opening diameter of the encapsulation window includes: reading the marked hole diameter value of the substrate drill layer from the PCB CAD design file, and using the marked hole diameter value as the bore diameter of the substrate drill; performing pixel scanning on the solder mask layer corresponding to the encapsulation window using an image recognition tool, extracting the maximum outer diameter of the encapsulation window, and using the maximum outer diameter as the opening diameter of the encapsulation window; inputting the bore diameter and the opening diameter into the PCB process verification module to verify whether the opening diameter meets the preset minimum gap requirement between the encapsulation window and the substrate drill, and if not, generating a hole diameter adjustment prompt message.

[0043] To address the issues of inaccurate aperture parameter acquisition or substandard gap between the encapsulation opening and the substrate drilling in traditional designs, a solution is proposed that reads the drilling aperture from the CAD file, extracts the opening aperture diameter through image recognition, and ensures the gap meets requirements through a process verification module. The core is to accurately acquire aperture parameters, providing reliable input for subsequent copper extraction and etching steps.

[0044] To read the drill hole diameter, locate the "substrate drill layer" (usually labeled "Drill" or "NPTH") in the PCB CAD design file (such as Gerber or DXF), extract the marked hole diameter value of the drill hole in this layer (such as 2.0mm in the design), and use it as the "drill hole diameter" of the substrate drill hole.

[0045] For the "solder mask layer" (usually marked "Soldermask") corresponding to the encapsulation opening, use an image recognition tool (such as OpenCV) to perform pixel scanning on the layer image, identify the boundary contour of the encapsulation opening, calculate its maximum outer diameter (e.g., 2.5mm obtained from scanning), and use it as the "opening aperture" of the encapsulation opening.

[0046] Input the "drill hole diameter" (e.g., 2.0mm) and "window hole diameter" (e.g., 2.5mm) into the PCB process verification module to verify whether the gap between the window hole diameter and the drill hole diameter (2.5mm-2.0mm=0.5mm) meets the preset minimum gap requirement (e.g., at least 0.2mm). If the gap is insufficient (e.g., window hole diameter is 2.1mm, gap is 0.1mm), the module generates a hole diameter adjustment prompt message (e.g., "It is recommended to increase the window hole diameter to 2.3mm or more") to remind the designer to make the modification.

[0047] In some embodiments, the process of performing full etching on the back-side encapsulation window area to completely remove the copper foil within the back-side encapsulation window area, leaving only the substrate, includes: selecting all copper foil objects within the encapsulation window area in the back-side copper foil layer of the PCB design software and adding etching removal attribute markers to the copper foil objects; generating an etching instruction file containing coordinate information of the marked areas corresponding to the attribute markers, wherein the coordinate information is based on the absolute coordinate system of the PCB; sending the etching instruction file to a chemical etching device and controlling the device to etch the marked areas according to preset etching process parameters; the etching process parameters include 30°C, 60 seconds, and a 15% concentration etching solution; after etching, taking an image of the back-side encapsulation window area using an automatic optical inspection device, comparing the taken image with a reference image of the substrate without copper foil using an image comparison algorithm to verify whether the copper foil has been completely removed; if there is any residue, resending an extended etching instruction to the device until verification is successful.

[0048] To address the poor soldering reliability caused by exposed copper in traditional back-side fully-open windows, a complete etching process of "marking-etching-inspection-feedback" is proposed to ensure complete removal of copper foil from the back-side enclosed window area. The core of this solution is to thoroughly resolve the back-side copper exposure problem through precise control of the etching process (parameters and instructions) and automated verification (AOI + image comparison).

[0049] In the "Bottom Copper" layer of the PCB design software, select all copper foil objects within the encapsulation window area, add an etch removal attribute marker (such as "Etch_Remove"), and specify the range of copper foil to be removed.

[0050] Based on the absolute coordinates of the marked area (e.g., the center coordinates of the drill hole are (100mm, 200mm), and the window area is a circle with a diameter of 2.5mm), generate an etching instruction file (e.g., G-code or XML file) containing coordinate information. The instruction content is "Perform etching removal in the Bottom Copper layer, at coordinates (100,200), in an area with a diameter of 2.5mm".

[0051] The etching instruction file is sent to the chemical etching equipment, and the equipment is controlled to etch the marked area according to the preset process parameters (30°C, 60 seconds, 15% concentration of ferric chloride / ammonium chloride etching solution).

[0052] After etching, an image of the back-side sealed window area is captured using an automated optical inspection (AOI) device. The captured image is then compared with a "copper foil-free substrate reference image" (such as an image of pure resin / glass fiber) using an image comparison algorithm (such as SSIM or MSE). If residual copper foil is found (e.g., the difference in the comparison result exceeds a threshold), an extended etching command is sent to the device (e.g., increasing the etching time by 30 seconds), and etching is repeated until AOI verification is passed (the area of ​​residual copper foil is 0).

[0053] In some embodiments, optimizing the exposed copper area retained on the front side into a grid-like copper layer includes: determining the minimum linewidth and maximum grid spacing of the grid-like copper layer according to the solder resist adhesion test standard; using the grid generation tool of PCB design software, generating a square or rhomboid grid pattern that conforms to the minimum linewidth and maximum grid spacing within the exposed copper area retained on the front side, with the center of the substrate drill hole as the origin; aligning the grid pattern with the boundary of the encapsulation opening area to ensure that the grid pattern is completely located within the encapsulation opening area; simulating the bonding strength between the grid-like copper layer and the substrate using finite element analysis software; if the simulation result reaches a preset adhesion threshold, retaining the corresponding grid design; if not, increasing the grid linewidth or decreasing the grid spacing, regenerating the grid pattern and simulating again until the threshold requirement is met.

[0054] To address the issues of insufficient solder resist adhesion and copper waste caused by exposed solid copper on the front side, a solution is proposed: "Design mesh parameters based on adhesion standards - generate mesh patterns - verify strength using finite element analysis." The core principle is to increase the contact area between the copper layer and the solder resist through the mesh structure (improving adhesion) while reducing the copper area (saving costs).

[0055] According to the solder resist adhesion test standard (such as IPC-SM-840), determine the minimum line width of the grid (such as 0.2 mm, to meet the minimum requirements for electrical conductivity) and the maximum grid spacing (such as 0.5 mm, to ensure that the solder resist can penetrate into the grid gaps and improve adhesion).

[0056] In the PCB design software, select the exposed copper area retained in step S101 (such as a circle with a diameter of 1.5mm), and use a mesh generation tool (such as Altium's "Grid Fill") to generate a square or diamond mesh (such as a square mesh with a line width of 0.2mm and a spacing of 0.5mm) with the center of the drill hole as the origin, and ensure that the mesh pattern is completely within the encapsulation opening area (such as the opening area with a diameter of 2.5mm).

[0057] Input the parameters (line width, spacing, area size) of the mesh-like copper layer into the finite element analysis software to simulate the bonding strength between the mesh copper layer and the substrate (such as stress distribution caused by thermal expansion). If the simulation results reach the preset adhesion threshold (e.g., stress less than 10MPa, meeting the IPC standard), the corresponding mesh design is retained; if not (e.g., stress 15MPa), adjust the parameters (e.g., increase the line width to 0.25mm or decrease the spacing to 0.4mm), regenerate the mesh, and simulate again until the threshold requirement is met.

[0058] In some embodiments, the method further includes: collecting historical mechanical positioning accuracy requirements for PCB positioning holes and traditional fully-open copper exposed area dimensions and corresponding positioning error data to construct a training dataset; training a random forest regression model based on the training dataset, wherein the input of the random forest regression model is the mechanical positioning accuracy requirement, and the output is the minimum diameter of the exposed copper area to be retained within the front encapsulation opening area; inputting the mechanical positioning accuracy requirement corresponding to the PCB positioning hole into the trained random forest regression model to obtain the output minimum diameter prediction value; comparing the minimum diameter prediction value with the encapsulation opening hole diameter to verify whether the encapsulation opening hole diameter is at least 0.5 mm larger than the prediction value; if it meets the requirement, the minimum diameter prediction value is used as the diameter of the front retained area; if it does not meet the requirement, an encapsulation opening hole diameter adjustment suggestion is generated.

[0059] To address the problem of traditional minimum diameter calculations relying on experience, this paper proposes using a random forest regression model to predict the minimum diameter of the frontal reserved area, ensuring that the diameter meets the accuracy requirements for mechanical positioning. The core principle is to train the model using historical data to achieve accurate prediction of the minimum diameter, avoiding errors from manual calculations.

[0060] Collect historical PCB positioning hole mechanical positioning accuracy requirements (e.g. ±0.1mm), traditional fully open copper exposed area size (e.g. diameter 2.5mm), and corresponding positioning error data (e.g. 0.08mm) to construct a training dataset (e.g. 1000 sets of data).

[0061] Using "mechanical positioning accuracy requirements" as input features and "minimum diameter of the front-facing reserved area" as output label, a random forest regression model (e.g., using the Scikit-learn library) is trained. The model predicts the minimum diameter by learning associations in historical data (e.g., higher accuracy requirements correspond to larger minimum diameters).

[0062] Input the current mechanical positioning accuracy requirement of the PCB positioning hole (e.g., ±0.05mm) into the trained model to obtain the minimum diameter prediction value (e.g., 1.2mm). Verify whether the encapsulation opening diameter (e.g., 2.5mm) is at least 0.5mm larger than the predicted value (2.5mm-1.2mm=1.3mm≥0.5mm). If it meets the requirement, then 1.2mm is used as the diameter of the front-side reserved area; if it does not meet the requirement (e.g., the opening diameter is 1.5mm, the predicted value is 1.2mm, and the gap is 0.3mm<0.5mm), then generate an adjustment suggestion for the encapsulation opening diameter (e.g., "It is recommended to increase the opening diameter to 1.8mm or more").

[0063] In some embodiments, the method further includes: using the linewidth and grid spacing of the front mesh copper layer as optimization variables, and the copper foil usage area reduction rate and solder resist adhesion compliance rate as optimization objectives; constructing a fitness function using the DEAP genetic algorithm library, wherein the solder resist adhesion compliance rate has a higher weight than the copper foil usage area reduction rate; initializing multiple candidate solutions, each candidate solution containing a set of linewidth and spacing parameters, performing multiple iterations, and retaining a preset number of candidate solutions in each generation based on fitness; simulating the adhesion of the mesh copper layer using finite element analysis software for the candidate solutions retained in each generation, and selecting the candidate solutions that simultaneously satisfy the two optimization objectives as the target solutions; if there are multiple target solutions, selecting the target solution with the highest copper foil usage area reduction rate as the final parameters of the front mesh copper layer.

[0064] To address the challenge of balancing copper area reduction rate and solder resist adhesion in mesh parameters, a genetic algorithm is proposed to optimize mesh line width and spacing, achieving the goal of "high adhesion + high copper saving." The core principle is to select the optimal mesh parameters through multi-objective optimization (with a higher weighting for adhesion achievement rate).

[0065] The line width (e.g., 0.1mm-0.3mm) and spacing (e.g., 0.3mm-0.7mm) of the grid are used as optimization variables; the copper foil area reduction rate (e.g., target ≥50%) and the solder resist adhesion compliance rate (e.g., target ≥95%) are used as optimization targets, with the adhesion compliance rate having a higher weight (e.g., 0.7) than the copper area reduction rate (e.g., 0.3).

[0066] Constructing the fitness function: Using the DEAP genetic algorithm library, the fitness function is constructed as follows: Fitness = 0.7 × Adhesion compliance rate + 0.3 × Copper area reduction rate; where the adhesion compliance rate is calculated based on the finite element analysis results (e.g., 1 if the stress is less than 10 MPa, otherwise 0), and the copper area reduction rate is calculated as the ratio of the mesh area to the solid area (e.g., mesh area 1.0 mm²). 2 Solid area 2.0mm 2 The reduction rate would be 50%.

[0067] Initialize multiple candidate solutions (e.g., 100 sets of linewidth and spacing parameters) and perform multiple iterations (e.g., 50 generations). In each generation, retain a preset number of candidate solutions (e.g., 20 sets) based on the fitness function, and generate new solutions through crossover and mutation operations. For the candidate solutions retained in each generation, simulate adhesion using finite element analysis software, and select candidate solutions that simultaneously satisfy two optimization objectives (e.g., 100% adhesion achievement rate and 60% copper area reduction rate). If there are multiple objective solutions, select the solution with the highest copper area reduction rate (e.g., 60%) as the final mesh parameters (e.g., linewidth 0.2 mm, spacing 0.6 mm).

[0068] In some embodiments, the method further includes: collecting multiple sets of etching process parameters and corresponding residual copper foil area data to construct a training dataset; the etching process parameters include etching time, temperature, and solution concentration; training a convolutional neural network model using the training dataset, wherein the input of the convolutional neural network model is etching time, temperature, and solution concentration, and the output is a predicted value of the residual copper foil area; during the back-side etching process, an automatic optical inspection device takes an image of the back-side sealed window area at a preset interval and extracts the area value of the residual copper foil; inputting the current etching process parameters and the extracted residual copper foil area value into the trained convolutional neural network model to obtain the optimized etching process parameters output by the convolutional neural network model; sending the optimized etching process parameters to the etching equipment, and controlling the equipment to adjust according to the etching process parameters and continue to execute the etching steps until the residual copper foil area is 0.

[0069] To address the issue of residual copper foil due to experience-dependent etching process parameters, this paper proposes using a convolutional neural network (CNN) to predict the area of ​​residual copper foil, thereby enabling dynamic adjustment of etching process parameters. The core principle is to adjust etching parameters (time, temperature, and concentration) in real time by detecting the residual area, ensuring complete removal of the copper foil.

[0070] Collect multiple sets of etching process parameters (such as etching time 30-120 seconds, temperature 25-35℃, solution concentration 10%-20%) and corresponding residual copper foil area data (such as obtained through AOI detection) to construct a training dataset (such as 500 sets of data).

[0071] Using "etching time, temperature, and solution concentration" as input features and "residual copper foil area" as the output label, a convolutional neural network model (e.g., using the TensorFlow library) is trained. The model predicts the residual area by learning the relationship between process parameters and residual area (e.g., the longer the etching time, the smaller the residual area).

[0072] During the back-side etching process, the AOI equipment takes images of the back-side sealed window area at preset intervals (e.g., every 20 seconds) and extracts the residual copper foil area value (e.g., 1.2 mm). 2The current etching process parameters (e.g., time 60 seconds, temperature 30℃, concentration 15%) and the residual area value are input into the trained CNN model to obtain optimized etching process parameters (e.g., time extended to 90 seconds, temperature maintained at 30℃, concentration 15%). The optimized parameters are sent to the etching equipment, which adjusts the parameters and continues etching. This process is repeated until the residual copper foil area is 0 (AOI verification passed).

[0073] In some embodiments, the method further includes: collecting multiple sets of size and shape data of the exposed copper area on the front side and corresponding positioning error data to construct a training dataset, wherein the size includes a diameter of 2mm-3mm and the shape includes circles and rings; training a classification model using a support vector machine, wherein the input of the classification model is the size and shape of the exposed copper area on the front side, and the output is a judgment result indicating whether the positioning error meets the standard; after the copper removal process on the front side is completed, the size and shape of the retained exposed copper area are input into the trained classification model to obtain the judgment result output by the classification model; if the judgment result is negative, the size or shape of the exposed copper area on the front side is automatically adjusted or changed, and the copper removal process on the front side is re-executed until the judgment result output by the model is positive.

[0074] To address the issue of "the size / shape of the reserved area not meeting positioning error requirements," a Support Vector Machine (SVM) classification model is proposed to determine whether the size and shape of the reserved area meet the standards, enabling automatic adjustment. The core principle is to quickly verify the rationality of the reserved area through machine learning classification, avoiding the lag of manual inspection.

[0075] A training dataset (e.g., 800 sets of data) is constructed by collecting multiple sets of data on the size (e.g., diameter 2mm-3mm), shape (e.g., circular, annular), and corresponding positioning error data (e.g., whether it meets the standard: yes / no) of the frontal preservation area. For example, a circular preservation area with a diameter of 2.0mm has a positioning error of 0.12mm (not meeting the standard); an annular preservation area with a diameter of 2.5mm has a positioning error of 0.07mm (meets the standard).

[0076] The SVM classification model is trained using "size and shape of the preserved region" as input features and "whether the localization error meets the standard" as the output label (binary classification: yes / no). The model learns patterns from historical data (e.g., rings are easier to meet the standard than circles, and larger diameters are easier to meet the standard) to classify the preserved region.

[0077] After copper removal is completed in step S101, the size (e.g., diameter 1.5mm) and shape (e.g., circle) of the retained area are input into the trained SVM model to obtain a judgment result (e.g., "not up to standard"). If the result is "no", the parameters of the retained area are automatically adjusted: for example, the diameter is increased to 1.8mm (size adjustment), or it is changed from a circle to an annular shape (shape adjustment), and the copper removal process in step S101 is re-executed (drawing a new retained area and trimming the copper foil) until the model judgment result is "yes" (up to standard).

[0078] In some embodiments, the method further includes: inputting the copper foil structure parameters after copper removal on the front side, the copper foil structure parameters after full etching on the back side, and the parameters of the front grid-like copper layer into an intelligent design integration module; the intelligent design integration module matches each parameter with PCB manufacturing process rules through a rule engine, and if parameter conflicts are found, automatically adjusts the parameters to eliminate the conflicts; based on the integrated parameters, automatically generates a manufacturing file containing a front copper foil layer, a back copper foil layer, a substrate drilling layer, and an encapsulation window layer; converting the manufacturing file into instructions that can be recognized by the production equipment, and starting the processing flow of the positioning holes.

[0079] To address the issues of "parameter conflicts in steps S101-S103" or "low efficiency in manufacturing document generation," a smart design integration module is proposed to integrate parameters from each step and generate manufacturing documents that conform to process rules. The core principle is to eliminate conflicts through a rule engine, achieving seamless integration from design to manufacturing.

[0080] Input the front copper foil structure parameters of step S101 (such as the diameter of the reserved area is 1.5 mm and the ring shape), the back etching parameters of step S102 (such as the etching area coordinates (100,200) and diameter of 2.5 mm), and the mesh parameters of step S103 (such as the line width of 0.2 mm and the spacing of 0.5 mm) into the intelligent design integration module (such as a custom module based on Python).

[0081] The rule engine in the module (such as using Prolog or Drools) matches the input parameters with PCB manufacturing process rules (such as "grid line width must not be less than 0.1mm" and "etched area must not exceed the encapsulation opening range"). For example, if the grid line width is 0.08mm (less than 0.1mm), the rule engine will automatically adjust the line width to 0.1mm (to meet the minimum line width requirement); if the coordinates of the etched area exceed the encapsulation opening range (e.g., the opening center is (100, 200) and the etched area center is (101, 201)), the etched area coordinates will be automatically corrected to the opening center.

[0082] The generated manufacturing file includes: integrated parameters (such as front grid line width 0.1mm, back etched area coordinates (100,200), diameter 2.5mm), and generates a manufacturing file (such as Gerber X2 file) containing a front copper foil layer (grid-like), a back copper foil layer (no copper), a substrate drill layer (diameter 2.0mm), and an encapsulation window layer (diameter 2.5mm).

[0083] The manufacturing documents are converted into instructions recognizable by the production equipment (such as G-code for drilling equipment and XML instructions for etching equipment), and sent to the corresponding equipment (drilling machine, etching machine, copper foil trimming machine) to initiate the positioning hole processing flow (sequence: drilling → front copper removal → back etching → front mesh processing). After processing, the positioning hole structure (front mesh, no copper on the back) is finally verified using AOI equipment to ensure it meets the design requirements.

[0084] This application provides a partially exposed copper structure for PCB positioning holes, which is optimized based on the method provided in any embodiment of this application.

[0085] Please see Figure 2 As shown, Figure 2 This is a schematic diagram of the structure of an optimization design system 200 for partial exposed copper structures of PCB positioning holes provided in this application embodiment. The optimization design system 200 for partial exposed copper structures of PCB positioning holes is used to execute the steps of the optimization design method for partial exposed copper structures of PCB positioning holes shown in the above embodiments. The optimization design system 200 for partial exposed copper structures of PCB positioning holes can be a single server or a server cluster, or it can be a terminal, such as a handheld terminal, laptop computer, wearable device, or robot.

[0086] like Figure 2 As shown, the optimized design system 200 for partial exposed copper structures of PCB positioning holes includes: The welding determination unit 201 is used to determine that the front side of the PCB positioning hole is the component side and the back side is the welding side, obtain the drilling diameter of the substrate drilling hole and the opening diameter of the encapsulation opening; perform copper removal processing on the encapsulation opening area on the front side, and retain an exposed copper area in the encapsulation opening area on the front side that meets the minimum electrical connection or mechanical positioning requirements. The substrate retention unit 202 is used to perform full etching on the encapsulation window area on the back side, completely removing the copper foil in the encapsulation window area on the back side and retaining only the substrate. The mesh optimization unit 203 is used to optimize the exposed copper area retained on the front side into a mesh-like copper layer, which is used to reduce the area of ​​copper used while ensuring sufficient adhesion or electrical performance.

[0087] It should be noted that those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the optimized design system and each module for the partial exposed copper structure of PCB positioning holes described above can be referred to the corresponding content in the various embodiments of the optimized design method for the partial exposed copper structure of PCB positioning holes described above, and will not be repeated here.

[0088] The aforementioned optimized design method for locally exposed copper structures used for PCB positioning holes can be implemented as a computer program, which can be used in various ways, such as... Figure 2 It runs on the device shown.

[0089] Please see Figure 3 , Figure 3 This is a schematic block diagram of the structure of a computer device provided in an embodiment of this application. The computer device includes a processor, a memory, and a network interface connected via a device bus, wherein the memory may include a storage medium and internal memory.

[0090] The storage medium can store operating devices and computer programs. The computer program includes program instructions that, when executed, cause the processor to perform any optimized design method for the local exposed copper structure of PCB positioning holes.

[0091] The processor provides computing and control capabilities, supporting the operation of the entire computer device.

[0092] The internal memory provides an environment for the execution of computer programs in non-volatile storage media. When the computer program is executed by the processor, it enables the processor to perform any optimization design method for the local exposed copper structure of PCB positioning holes.

[0093] This network interface is used for network communication, such as sending assigned tasks. Those skilled in the art will understand that... Figure 3 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the terminal to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0094] It should be understood that the processor can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among these, a general-purpose processor can be a microprocessor or any conventional processor.

[0095] In one embodiment, the processor is configured to run a computer program stored in memory to perform the following steps: Prepare the PCB substrate and perform pretreatment on the copper surface of the PCB substrate. For the yellow cover film area of ​​the PCB substrate, the yellow cover film is attached to the corresponding position of the PCB substrate. The cover film at the Mark point position is not opened. The color of the yellow cover film itself is used to form a contrast with the background copper surface for SMT equipment to identify. For the black cover film area, the white ink dots are first optimized at the Mark point position of the PCB substrate. The black cover film is then attached to the corresponding position of the PCB substrate to expose the white ink dots. After lamination, the yellow and black cover films are cured. Multiple sensors deployed on the production line collect real-time process parameter data on temperature, pressure, and position. This data is analyzed in real time, and when deviations from preset ranges are detected, an early warning signal is issued, and corresponding production equipment parameters are adjusted to ensure the optimized design quality of the Mark point structure and the stability of the production process. Before optimizing the Mark point design, a machine learning-based intelligent algorithm is used to analyze and train the contrast between the cover film and the background copper surface for different color combinations and the SMT equipment recognition success rate in historical production data. A contrast-recognition success rate prediction model is established. Based on this model, it is predicted whether the contrast between the yellow cover film and the background copper surface, and between the white ink dots and the black cover film in the current design meets the recognition requirements of the SMT equipment. The cover film color parameters or Mark point design parameters are automatically adjusted based on the prediction results.

[0096] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, causes the processor to implement the steps of the optimized design method for a partial exposed copper structure for PCB positioning holes as provided in any embodiment of this application.

[0097] The computer-readable storage medium may be an internal storage unit of the computer device described in the foregoing embodiments, such as the hard disk or memory of the computer device. The computer-readable storage medium may also be an external storage device of the computer device, such as a plug-in hard disk, SmartMedia Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the computer device.

[0098] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An optimized design method for partially exposed copper structures of PCB positioning holes, characterized in that, The PCB positioning hole includes a front side and a back side, has a substrate drill hole and an encapsulation window covering the periphery of the substrate drill hole, and the diameter of the encapsulation window is larger than the diameter of the substrate drill hole; the method includes: The PCB positioning hole is determined to have its front side as the component side and its back side as the soldering side. The drilling diameter of the substrate hole and the opening diameter of the encapsulation window are obtained. Copper removal is performed on the encapsulation window area on the front side, retaining an exposed copper area that meets the minimum electrical connection or mechanical positioning requirements. This includes: calculating the minimum diameter of the exposed copper area to be retained in the encapsulation window area on the front side according to the mechanical positioning tolerance requirements of the PCB positioning hole; in the PCB design software, a circular or annular retention area equal to the minimum diameter is drawn with the center coordinates of the substrate hole as the center; using the copper foil trimming tool of the design software, all copper foil objects in the encapsulation window area on the front side except for the retention area are selected and deleted to form the copper foil structure on the front side after copper removal. The encapsulation window area on the back side is fully etched to completely remove the copper foil in the encapsulation window area on the back side, leaving only the substrate; The exposed copper area on the front is optimized into a grid-like copper layer, which is used to reduce the area of ​​copper used while ensuring sufficient adhesion or electrical performance.

2. The method according to claim 1, characterized in that, The step of obtaining the borehole diameter of the substrate and the opening diameter of the encapsulation opening includes: Read the marked hole diameter value of the substrate drilling layer from the PCB CAD design file, and use the marked hole diameter value as the drilling hole diameter of the substrate. The solder resist layer corresponding to the encapsulation opening is scanned pixel by pixel using an image recognition tool, and the maximum outer diameter of the encapsulation opening is extracted. The maximum outer diameter is then used as the opening diameter of the encapsulation opening. The drill hole diameter and window opening diameter are input into the PCB process verification module to verify whether the window opening diameter meets the preset minimum gap requirement between the encapsulation window and the substrate drill hole. If it does not meet the requirement, a hole diameter adjustment prompt message is generated.

3. The method according to claim 1, characterized in that, The process involves a full etching of the encapsulation window area on the back side, completely removing the copper foil within the encapsulation window area and retaining only the substrate, including: In the back copper foil layer of the PCB design software, select all copper foil objects within the encapsulation window area and add an etch removal attribute mark to the copper foil objects; Generate an etching instruction file, which contains coordinate information of the marked area corresponding to the attribute mark, wherein the coordinate information is based on the absolute coordinate system of the PCB; The etching instruction file is sent to the chemical etching equipment, and the equipment is controlled to etch the marked area according to the preset etching process parameters; the etching process parameters include 30°C, 60 seconds and 15% concentration etching solution. After etching is completed, an image of the back-side sealed window area is captured by an automatic optical inspection device. The captured image is compared with a reference image of the substrate without copper foil using an image comparison algorithm to verify whether the copper foil has been completely removed. If there is any residue, the extended etching command is resent to the device until the verification is successful.

4. The method according to claim 1, characterized in that, The step of optimizing the exposed copper area on the front side into a grid-like copper layer includes: The minimum line width and maximum grid spacing of the grid-like copper layer are determined according to the solder resist adhesion test standard. Using the grid generation tool of PCB design software, a square or diamond grid pattern conforming to the minimum line width and maximum grid spacing is generated in the exposed copper area reserved on the front side, with the center of the substrate drill hole as the origin. Align the grid pattern with the boundary of the encapsulation window area to ensure that the grid pattern is completely within the encapsulation window area; The bonding strength between the mesh-like copper layer and the substrate is simulated using finite element analysis software. If the simulation results reach the preset adhesion threshold, the corresponding mesh design is retained; if not, the mesh line width is increased or the mesh spacing is decreased, the mesh pattern is regenerated, and the simulation is repeated until the threshold requirement is met.

5. The method according to claim 1, characterized in that, The method further includes: Collect historical data on the mechanical positioning accuracy requirements of PCB positioning holes and the dimensions of traditional fully open copper exposed areas and corresponding positioning errors to construct a training dataset; A random forest regression model is trained based on the training dataset. The input of the random forest regression model is the mechanical positioning accuracy requirement, and the output is the minimum diameter of the exposed copper area that needs to be retained within the frontal enclosed window area. Input the mechanical positioning accuracy requirements corresponding to the PCB positioning holes into the trained random forest regression model to obtain the minimum diameter prediction value of the output. The predicted minimum diameter is compared with the encapsulation window diameter to verify whether the encapsulation window diameter is at least 0.5 mm larger than the predicted value. If the condition is met, the predicted minimum diameter is used as the diameter of the front-facing reserved area; otherwise, an adjustment suggestion for the encapsulation window diameter is generated.

6. The method according to claim 1, characterized in that, The method further includes: The line width and grid spacing of the front grid copper layer are used as optimization variables, and the reduction rate of copper foil usage area and the compliance rate of solder resist adhesion are used as optimization targets. The fitness function was constructed using the DEAP genetic algorithm library, where the weight of the solder resist adhesion compliance rate was higher than the weight of the copper foil usage area reduction rate. Multiple candidate solutions are initialized, each containing a set of line width and spacing parameters. Multiple iterations are performed, and a preset number of candidate solutions are retained in each generation based on fitness. For each generation of candidate solutions, the adhesion of the mesh copper layer is simulated using finite element analysis software. The candidate solutions that simultaneously satisfy the two optimization objectives are selected as the target solutions. If there are multiple target solutions, the target solution with the highest reduction rate of copper foil usage area is selected as the final parameters of the front mesh copper layer.

7. The method according to claim 1, characterized in that, The method further includes: Multiple sets of etching process parameters and corresponding residual copper foil area data were collected to construct a training dataset; the etching process parameters included etching time, temperature, and solution concentration. A convolutional neural network model is trained using a training dataset. The inputs to the convolutional neural network model are etching time, temperature, and solution concentration, and the output is a predicted value of the area of ​​the remaining copper foil. During the back-side etching process, an automated optical inspection device takes an image of the back-side sealed window area at preset intervals and extracts the area value of the residual copper foil. Input the current etching process parameters and the extracted residual copper foil area value into the trained convolutional neural network model to obtain the optimized etching process parameters output by the convolutional neural network model. The optimized etching process parameters are sent to the etching equipment. The control equipment adjusts according to the etching process parameters and continues to execute the etching steps until the residual copper foil area is 0.

8. The method according to claim 1, characterized in that, The method further includes: Collect multiple sets of size and shape data of the exposed copper area on the front side, as well as the corresponding positioning error data, to construct a training dataset. The size includes diameters of 2mm-3mm and shapes include circles and rings. A classification model is trained using a support vector machine. The input of the classification model is the size and shape of the exposed copper area on the front side, and the output is the judgment result of whether the positioning error meets the standard. After the copper removal process is completed, the size and shape of the remaining exposed copper area are input into the trained classification model to obtain the judgment result output by the classification model. If the judgment result is negative, the size or shape of the exposed copper area on the front will be automatically adjusted, and the copper removal process on the front will be repeated until the judgment result output by the model is positive.

9. The method according to claim 1, characterized in that, The method further includes: The copper foil structure parameters after copper removal on the front side, the copper foil structure parameters after full etching on the back side, and the parameters of the grid-like copper layer on the front side are input into the intelligent design integration module. The intelligent design integration module matches each parameter with the PCB manufacturing process rules through a rule engine. If a parameter conflict is found, the parameters are automatically adjusted to eliminate the conflict. Based on the integrated parameters, a manufacturing file is automatically generated that includes a front copper foil layer, a back copper foil layer, a substrate drilling layer, and an encapsulation window layer. The manufacturing documents are converted into instructions that the production equipment can recognize, and the machining process for the positioning holes is initiated.

10. A partially exposed copper structure for PCB positioning holes, characterized in that, It is designed based on the method of any one of claims 1-9.

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