Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of manufacturing the same. A semiconductor device includes: a gate structure including a plurality of insulating layers and a plurality of conductive layers alternately stacked; a contact structure extending within the gate structure and electrically connected to one of the conductive layers; a plurality of second supports, each second support including a pillar having a center located within a first distance from the center of the contact structure and a protrusion extending between the pillar and the plurality of conductive layers; and a plurality of first supports, the plurality of first supports being at least partially surrounded by the plurality of protrusions.

Description

TECHNICAL FIELD

[0001] The disclosure relates to an electronic device including, but not limited to, a semiconductor device and a method of manufacturing a semiconductor device. BACKGROUND

[0002] The integration level of a semiconductor device is mainly determined by the area occupied by a unit memory cell. As the integration level of a single layer semiconductor device on a substrate is improved to the limit of forming a memory cell, a three-dimensional semiconductor device in which memory cells are stacked on a substrate is being developed. In order to improve the operation reliability of such a semiconductor device, various structures and manufacturing methods are also being developed. SUMMARY

[0003] In an embodiment, a semiconductor device can include a gate structure including a plurality of insulating layers and a plurality of conductive layers alternately stacked, a contact structure extending within the gate structure and electrically connected to one of the conductive layers, a plurality of second supports each including a pillar having a center within a first distance of the center of the contact structure and a plurality of protrusions extending between the pillar and the conductive layers, and a plurality of first supports at least partially surrounded by the plurality of protrusions.

[0004] In an embodiment, a semiconductor device can include a gate structure including a plurality of insulating layers and a plurality of conductive layers alternately stacked, a contact structure extending within the gate structure and electrically connected to one of the plurality of conductive layers, a plurality of second supports each including a pillar spaced apart from the contact structure by a first distance and including a plurality of protrusions extending between the pillar and the plurality of conductive layers, wherein the pillar extends through the gate structure and the plurality of protrusions extend from a center of the pillar to a second distance, and a plurality of first supports within the second distance of one of the plurality of second supports.

[0005] In an embodiment, a method of manufacturing a semiconductor device can include forming a stack including a plurality of first material layers and a plurality of second material layers alternately stacked, forming a first support at least partially extending through the stack, forming a sacrificial contact structure extending through the stack, forming a first opening extending through the stack, forming a plurality of second openings exposing the first support and the sacrificial contact structure by etching the plurality of first material layers through the first opening, and forming a second support in the first opening and the plurality of second openings.

[0006] In one embodiment, a method of manufacturing a semiconductor device may include: forming a laminate comprising alternating layers of a plurality of first material layers and a plurality of second material layers; forming a plurality of first openings extending through the laminate; forming a plurality of second openings extending through the laminate, wherein the centers of the plurality of second openings are located at a first distance from a point on the laminate, wherein the plurality of second openings are spaced apart; forming a plurality of first supports, one of which is disposed in each of the first openings; forming a sacrificial contact structure that extends at least partially through the laminate and is centered at a point on the laminate; forming a plurality of third openings by etching the plurality of first material layers through the plurality of second openings, the plurality of third openings exposing the plurality of first supports and the sacrificial contact structure; and forming a plurality of second supports, one of which is disposed in each of the second openings and a set of third openings. Attached Figure Description

[0007] Figures 1A-1D This is a diagram illustrating the structure of a semiconductor device according to an embodiment.

[0008] Figure 2A and Figure 2B This is a diagram illustrating the structure of a semiconductor device according to an embodiment.

[0009] Figure 3 This is a diagram illustrating the structure of a semiconductor device according to an embodiment.

[0010] Figure 4 This is a diagram illustrating the structure of a semiconductor device according to an embodiment.

[0011] Figures 5A-5E This is a diagram illustrating a semiconductor device formed according to an embodiment, such as by a method for manufacturing a semiconductor device.

[0012] Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A and Figure 11B This is a diagram illustrating a semiconductor device formed according to an embodiment, such as by a method for manufacturing a semiconductor device.

[0013] Figure 12 This is a configuration diagram of a semiconductor device according to an embodiment.

[0014] Figure 13This is a configuration diagram of a semiconductor device according to an embodiment. Detailed Implementation

[0015] Various embodiments relate to a semiconductor device having a stable structure and improved reliability and other characteristics, as well as a method of manufacturing the semiconductor device.

[0016] By using three-dimensional stacked memory cells, the integration density of semiconductor devices can be improved. This results in semiconductor devices with stable structures and improved reliability.

[0017] Embodiments of this disclosure will be described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided as examples to illustrate the concepts disclosed in this application. Examples or embodiments based on these concepts can be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.

[0018] When one element is labeled "connected" to another element, these elements may be directly connected or connected via an intermediate element between them. When two elements are labeled "directly connected," one element is directly connected to the other without any intermediate element between them. Terms such as "bottom," "below," "above," "upper," "inner," "outer," "upper part," "height," "column," "row," "level," "outermost layer," "vertical," and other terms that suggest relative spatial relationships or orientations are used for descriptive or reference purposes only and are not intended to be limiting in any other way.

[0019] Cross-shading throughout the figures indicates corresponding or similar areas between figures, rather than indicating material associated with those areas.

[0020] Figures 1A-1D This is a diagram illustrating the structure of a semiconductor device according to an embodiment. Figure 1A This is a plan view of the first height LV1 of the contact area CTR. Figure 1B This is a plan view at the second height LV2 of the contact area CTR. Figure 1C It is along Figure 1A The cross-sectional view taken by line A-A', and Figure 1D This is a cross-sectional view of the unit region CR and the contact region CTR.

[0021] Reference Figures 1A-1D The semiconductor device includes a gate structure GST, a contact structure CS, a first support SP1, and a second support SP2. The semiconductor device also includes a channel structure CH.

[0022] The gate structure GST includes alternating layers of insulating layer 12 and conductive layer 11. Conductive layer 11 includes gate lines such as source select lines, word lines, or drain select lines. Conductive layer 11 may include conductive materials such as polysilicon, tungsten, or molybdenum. Insulating layer 12 insulates the continuously stacked conductive layers 11 from each other and may include oxides, nitrides, air gaps, etc.

[0023] The gate structure GST includes a cell region CR and a contact region CTR. The channel structure CH is located in the cell region CR, and the contact structure CS, the first support SP1, and the second support SP2 are located in the contact region CTR.

[0024] exist Figure 1A The diagram illustrates a first pattern or shape F1 and a second pattern or shape F2 located on the upper surface of a gate structure GST to illustrate the positional relationship between a first support SP1, a second support SP2, and a contact structure CS. The first pattern F1 and the second pattern F2 do not form part of the semiconductor device. For example, the first pattern F1 is a two-dimensional shape such as a circle or polygon. The first pattern F1 is a circle with the center of the contact structure CS as its center and a radius equal to a first distance D1. The center of the first pattern F1 can be referred to as a point on the gate structure GST. The center of the second support SP2 is located along the perimeter of the first pattern F1. The second support SP2 includes a pillar SP2A and a protrusion SP2B. The pillar SP2A is located at the perimeter of the first pattern F1 and extends through the gate structure GST, as shown below. Figure 1C As shown in the example, for example, the center of the pillar SP2A is spaced apart from the center of the contact structure CS by a first distance D1. A protrusion SP2B extends between the pillar SP2A and the conductive layer 11. For example, the protrusion SP2B extends from the center of the pillar to a second distance D2. In this example, the first distance D1 is greater than the second distance D2. The second support SP2 may each comprise an insulating material such as an oxide.

[0025] The second shape F2 can be a two-dimensional shape such as a circle or a polygon. The second shape F2 is a circle with the center of the second support SP2 as its center and a radius equal to the second distance D2. In this example, the centers of the second shape F2 are arranged along and spaced apart from the periphery of the first shape F1. The protrusion SP2B can correspond to the second shape F2.

[0026] The center of the support SP2A is located at the center of the second pattern F2. The first support SP1 is primarily located inside the second pattern F2. The center of the first support SP1 is located at a position less than a second distance D2 from the center of the second support SP2. For example, a large portion of the first support SP1 is located inside the second pattern F2. The first support SP1 is at least partially surrounded by the protrusion SP2B and extends through the gate structure GST. Each of the plurality of first supports SP1 is located within a second distance D2 from the center of one of the second supports SP2. For example, the first support SP1 includes a dummy channel structure.

[0027] The contact structure CS is located inside the first pattern F1 and extends through the gate structure GST. For example, as Figure 1A As shown, the center of the contact structure CS is located at the center of the first pattern F1. The contact structure CS is electrically connected to the first conductive layer 11 in the conductive layer 11. The contact structure CS includes a contact plug 16 electrically connected to the first conductive layer 11 and an insulating spacer 17 surrounding the outer sidewall of the contact plug 16. The contact plug 16 includes a barrier layer 16A adjacent to the insulating spacer 17 and a metal layer 16B surrounded by the barrier layer 16A. The barrier layer 16A may include a metal nitride. The semiconductor device includes a plurality of contact structures CS, and one of the contact structures CS is connected to a different conductive layer in the conductive layer 11. The outer periphery of the contact structure CS is located within a second distance D2 from the center of one or more second supports SP2.

[0028] The second pattern F2 is spaced apart and located near the outer periphery of the contact structure CS. The second pattern F2 may overlap with the contact structure CS. The second support SP2 is positioned around the contact structure CS. A subset of the protrusions SP2B extending between the support SP2A and the contact structure CS contacts the contact structure CS. For example, the protrusions SP2B may contact the insulating spacer 17.

[0029] The channel structure CH extends through the gate structure GST in the cell region CR. The channel structure CH includes a channel layer 13, a memory layer 14 surrounding the channel layer 13, and an insulating core 15 located within and surrounded by the channel layer 13. The memory layer 14 includes at least one of a tunneling layer, a data storage layer, and a barrier layer. The data storage layer may include a floating gate, polysilicon, a charge trapping material, a nitride, a phase change material, etc.

[0030] The first support member SP1 includes a dummy channel structure. For example, the first support member SP1 includes a dummy channel layer 13D, a dummy memory layer 14D surrounding the dummy channel layer 13D, and a dummy insulating core 15D located within and surrounded by the dummy channel layer 13D.

[0031] As described above, the first support SP1 and the second support SP2 are positioned on the outer periphery of the contact structure CS. The first support SP1 surrounds the outer periphery of the second support SP2. Therefore, the gate structure GST can be stably supported by the first support SP1 and the second support SP2.

[0032] Figure 2A and Figure 2B This is a plan view showing the structure of a semiconductor device according to an embodiment.

[0033] Reference Figure 2A and Figure 2B The semiconductor device includes a gate structure GST, a contact structure CS, a first support SP1, and a second support SP2. The gate structure GST includes stacked conductive layers 21, and the contact structure CS is electrically connected to one of the conductive layers 21. The second support SP2 includes a pillar SP2A and a protrusion SP2B.

[0034] Reference Figure 2A The first pattern F1 is circular, and the center of the contact structure CS is located at the center of the first pattern F1 or a point on the gate structure GST. The centers of the pillars SP2A are arranged along the periphery of the first pattern F1. For example, in one embodiment, the center of the pillar SP2A is located at the periphery of the first pattern F1. Alternatively, the center of the pillar SP2A may be located inside or outside the periphery of the first pattern F1, and at least a portion of the pillars SP2A is located inside the first pattern F1. For example, the center of the first support SP1 may be located at the periphery of the first pattern F1. Alternatively, the center of the first support SP1 may be located inside or outside the periphery of the first pattern F1, and at least a portion of the first support SP1 is located inside the first pattern F1. In one embodiment, each of the second patterns F2 includes a second support SP2 and two first support SP1s, the second support SP2s and the two first support SP1s being formed such that the centers of the two first support SP1s and the center of the second support SP2 form a line tangent to the outer periphery of the first pattern F1.

[0035] The second shape F2 is circular, and in this example, the center of each support SP2A is located at the center of one of the second shapes F2. First support members SP1 are arranged along the periphery of the second shape F2. For example, the center of the first support member SP1 is located at the periphery of the second shape F2. Alternatively, the center of the first support member SP1 may be located inside or outside the periphery of the second shape F2, and at least a portion of the first support members SP1 may be located inside the second shape F2.

[0036] At least one first support member SP1 is at least partially located inside the second shape F2. For example, two first support members SP1 may be at least partially located inside each second shape F2. Figure 2A In the example, the first support SP1 is symmetrically located inside the second pattern F2 relative to the pillar SP2A. For example, the first of the two first support SP1s is located near the first side of the pillar SP2A, and the second of the two first support SP1s is located near the second side or opposite side of the pillar SP2A. The centers of the first support SP1s and the centers of the pillar SP2A can be arranged in a line. The number of first support SP1s located inside the second pattern F2 can be determined based on the structural stability characteristics or parameters of the semiconductor device. Three or more first support SP1s can be located at least partially inside the second pattern F2.

[0037] Reference Figure 2B In this example, the first support SP1 is entirely located inside the second shape F2. The first support SP1 does not extend beyond the perimeter of the second shape F2, but is positioned close to the support column SP2A. For example, the first support SP1 may contact the support column SP2A inside each second shape F2.

[0038] The number of the first support SP1 and the second support SP2, as well as their arrangement, can be determined based on the structural stability characteristics or parameters of the semiconductor device. Positioning the first support SP1 completely within the second pattern F2 can improve the structural stability of the semiconductor device.

[0039] Figure 3 This is a perspective view showing the structure of a semiconductor device according to an embodiment.

[0040] Reference Figure 3 The semiconductor device includes two first supports SP1 and a second support SP2. The second support SP2 includes a pillar SP2A, a first protrusion SP2B1, and a second protrusion SP2B2. One or more first supports SP1 extend through the first protrusion SP2B1 and the second protrusion SP2B2. The protrusions SP2B1 and SP2B2 can be protrusions or extensions.

[0041] The first protrusion SP2B1 contacts the contact structure CS. A groove G is formed in the first protrusion SP2B1 in the region of contact with the contact structure. The second protrusion SP2B2 is located below the contact structure CS and may not contact the contact structure CS. When the second protrusion SP2B2 does not contact the contact structure CS, the second protrusion SP2B2 does not include the groove G. Therefore, the first protrusion SP2B1 and the second protrusion SP2B2 have different shapes. The second protrusion SP2B2 has a general shape that does not include the groove G. For example, the second protrusion SP2B2 has a symmetrical shape such as a circle. The first protrusion SP2B1 has an anomalous shape that includes the groove G, and may have an asymmetrical or symmetrical shape.

[0042] Figure 4 This is a diagram illustrating the structure of a semiconductor device according to an embodiment.

[0043] Reference Figure 4 The semiconductor device includes peripheral circuitry PC, bonding structure BS, and memory cell array CA. The bonding structure BS is located between the peripheral circuitry PC and the memory cell array CA.

[0044] The memory cell array CA includes a gate structure GST, a contact structure CS, a first support SP1, and a second support SP2. The memory cell array CA includes a channel structure CH, a source structure 39, a first interconnect structure IC1, a first interlayer insulating layer IL1, and a third interlayer insulating layer IL3.

[0045] The gate structure GST includes alternating layers of insulating layer 32 and conductive layer 31. A source structure 39 is located on the gate structure GST, and a third interlayer insulating layer IL3 is located on the source structure 39. A channel structure CH extends through the gate structure GST and into the source structure 39. The channel structure CH includes a channel layer 36, a memory layer 37 surrounding the channel layer 36, and an insulating core 38 surrounded by the channel layer 13. A first interconnect structure IC1 is connected to at least one of the channel structure CH and the contact structure CS. The first interconnect structure IC1 is located within the first interlayer insulating layer IL1.

[0046] The contact structure CS extends through the gate structure GST and connects to the conductive layer 31. Each of the contact structures CS includes a contact plug 33 and an insulating spacer 34.

[0047] The second support SP2 is located on the outer periphery of the contact structure CS and extends through the gate structure GST. Each of the second supports SP2 includes a pillar SP2A and a plurality of protrusions SP2B.

[0048] The first support SP1 is located on the side of the second support SP2 and extends through the protrusion SP2B. The first support SP1 includes a dummy channel structure and may include a dummy channel layer 36D, a dummy memory layer 37D, and a dummy insulating core 38D.

[0049] The peripheral circuit PC includes transistors TR disposed on the substrate 30. For example, the peripheral circuit PC may include page buffers, line decoders, logic circuits, etc. The second interconnect structure IC2 is connected to the peripheral circuit PC and is located in the second interlayer insulating layer IL2.

[0050] The bonding structure BS is located between the first interlayer insulating layer IL1 and the second interlayer insulating layer IL2. The bonding structure BS includes a bonding layer BL and a bonding pad BP. The memory cell array CA is bonded to the peripheral circuit PC through the bonding layer BL. The peripheral circuit PC is electrically connected to the memory cell array CA through the bonding pad BP.

[0051] The peripheral circuitry PC and the memory cell array CA can be formed through separate manufacturing processes and connected via a bonding structure BS. A first support SP1 extends through a protrusion SP2B, thereby improving structural stability during the manufacturing process.

[0052] Figures 5A-5E This is a diagram illustrating a semiconductor device formed according to an embodiment, such as by a method for manufacturing a semiconductor device.

[0053] Reference Figure 5A This forms a laminate ST comprising alternating layers of a first material layer 101 and a second material layer 102. For example, the first material layer 101 forms gate lines. The first material layer 101 comprises a sacrificial material such as a nitride or a conductive material such as polysilicon or metal. The second material layer 102 insulates the continuously stacked gate lines from each other. The second material layer 102 comprises an insulating material such as an oxide, nitride, or air gap.

[0054] A first support member SP1 is formed extending through the laminate ST. The first support member SP1 can be formed as a single layer or multiple layers. The first support member SP1 includes a material with high etch selectivity relative to the etch selectivity of the first material layer 101. When the first support member SP1 has multiple layers, the outermost layer includes a material with high etch selectivity relative to the etch selectivity of the first material layer 101.

[0055] A sacrificial contact structure SCS is formed extending through the laminate ST. For example, multiple sacrificial contact structures SCS are formed, each sacrificial contact structure being connected to a different first material layer in the first material layer 101. The sacrificial contact structure SCS includes at least one sacrificial layer that is replaced with a contact plug in a subsequent process.

[0056] The sacrificial contact structure SCS is formed as a single layer or multiple layers. The sacrificial contact structure SCS comprises a material with high etch selectivity relative to the etch selectivity of the first material layer 101. When the sacrificial contact structure SCS comprises multiple layers, the outermost layer comprises a material with high etch selectivity relative to the etch selectivity of the first material layer 101. The sacrificial contact structure SCS can be formed before or after the formation of the first support SP1. A contact structure including a contact plug can be formed instead of the sacrificial contact structure SCS.

[0057] A first opening OP1 is formed extending through the laminate ST. The first material layer 101 is exposed through the first opening OP1. The first opening OP1 is located near the outer periphery of the sacrificial contact structure SCS. The first support SP1 is located near the outer periphery of the first opening OP1.

[0058] Reference Figure 5B The second opening OP2 is formed by etching the first material layer 101 through the first opening OP1. The first material layer 101 is selectively etched until the first support SP1 and the sacrificial contact structure SCS are exposed. The second opening OP2 is formed to partially expose the sidewalls of the first support SP1. The second opening OP2 is formed to partially expose the sidewalls of the sacrificial contact structure SCS.

[0059] During etching of the first material layer 101, the first support SP1 supports the remaining second material layer 102. As a result, the occurrence of tilting or collapse of the second material layer 102 can be reduced or eliminated. The closer the first support SP1 is positioned to the first opening OP1, the stronger the supporting force. The stronger the supporting force is when there are more first support SP1s located around the first opening OP1.

[0060] Reference Figure 5C A second support member SP2 is formed in the first opening OP1 and the second opening OP2. The second support member SP2 includes a strut SP2A in the first opening OP1 and a protrusion SP2B extending from the strut SP2A into the second opening OP2. The protrusion SP2B partially surrounds the sidewall of the first support member SP1. The protrusion SP2B partially surrounds or extends around the sidewall of the sacrificial contact structure SCS.

[0061] Reference Figure 5D The third opening OP3 is formed by removing the first material layer 101. During the process of removing the first material layer 101, the second support SP2 supports the laminate ST. For example, the support force is increased by the protrusion SP2B of the second support SP2.

[0062] Reference Figure 5EA third material layer 103 is formed in the third opening OP3. The third material layer 103 forms the gate line and is a conductive layer. The alternately stacked second material layer 102 and third material layer 103 form the gate structure GST.

[0063] According to the manufacturing method, when the second opening OP2 is formed, the laminate ST is supported by the first support SP1. When the first material layer 101 is replaced by the third material layer 103, the laminate ST is supported by the second support SP2. Therefore, the occurrence of tilting or collapse of the laminate ST can be reduced or eliminated.

[0064] Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A and Figure 11B This is a diagram illustrating a semiconductor device formed according to an embodiment, such as by a method for manufacturing a semiconductor device. Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A and Figure 11A This is a plan view of the third height LV3 of the contact area CTR, and Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B and Figure 11B It is a cross-sectional view.

[0065] Reference Figure 6A and Figure 6B A stack ST is formed comprising alternating layers of first material layer 41 and second material layer 42. The stack ST includes cell regions CR and contact regions CTR. The first material layer 41 forms gate lines. The first material layer 41 comprises a sacrificial material such as a nitride or a conductive material such as polysilicon or metal. The second material layer 42 insulates the continuously stacked gate lines from each other. The second material layer 42 comprises an insulating material such as an oxide, nitride, or air gap.

[0066] The first opening OP1 is formed in the contact region CTR of the laminate ST. For example, a hard mask pattern 43 is formed on the laminate ST, and the first opening OP1 is formed by etching the laminate ST using the hard mask pattern 43 as an etch stop. For example, in Figure 6AIn this design, a first opening OP1 is located at the periphery of a first graphic F1 with a radius of a first distance D1, such that a portion of the first opening OP1 lies within the first distance D1 from the center of the first graphic F1. The center of the first opening OP1 is located at the periphery of the first graphic F1, or the center of the first opening OP1 is located inside or outside the periphery of the first graphic F1. At least a portion of the first opening OP1 lies inside the first graphic F1. The first opening OP1 may be completely located inside the first graphic F1.

[0067] A second opening OP2 is formed in the contact area CTR of the laminate ST. For example, the second opening OP2 is formed by etching the laminate ST using a hard mask pattern 43 as an etch stop. The second opening OP2 is located inside the first pattern F1. For example, the second opening OP2 is located at the periphery of the first pattern F1. The center of the second opening OP2 is located at the periphery of the first pattern F1, or at a first distance D1 from the center of the first pattern F1, or the center of the second opening OP2 is located inside or outside the periphery of the first pattern F1. For example, each of the second openings OP2 is located within a first distance D1 from the center of the first pattern F1.

[0068] A channel hole CHH is formed in the cell region CR of the laminate ST. For example, the channel hole CHH is formed by etching the laminate ST using a hard mask pattern 43 as an etch stop.

[0069] The first opening OP1, the second opening OP2, and the channel hole CHH can be formed simultaneously, or they can be formed individually or sequentially through separate processes. When the channel hole CHH is formed, the first opening OP1 and the second opening OP2 are formed. The first opening OP1, the second opening OP2, and the channel hole CHH can have substantially the same width and substantially the same depth. Forming the first opening OP1, the second opening OP2, and the channel hole CHH simultaneously can reduce manufacturing costs.

[0070] Reference Figure 7A and Figure 7B A sacrificial layer 47 is formed in the first opening OP1, the second opening OP2, and the channel via CHH. The sacrificial layer 47 comprises a material with high etch selectivity relative to the first material layer 41 and the second material layer 42.

[0071] The first opening OP1 and the channel hole CHH are selectively reopened. For example, a mask pattern covers the second opening OP2, and the sacrificial layer 47 in the first opening OP1 and the channel hole CHH is removed while forming the first opening OP1 and the channel hole CHH.

[0072] A first support member SP1 is formed in the first opening OP1, and a channel structure CH is formed in the channel hole CHH. The first support member SP1 can be formed when the channel structure CH is formed. The channel structure CH includes a channel layer 44, a memory layer 45, and an insulating core 46. The first support member SP1 includes a dummy channel layer 44D, a dummy memory layer 45D, and a dummy insulating core 46D.

[0073] Reference Figure 8A and Figure 8B An insulating layer 48 and a hard mask pattern 49 are formed on the laminate ST. Contact holes CTHs are formed extending through the hard mask pattern 49 and the insulating layer 48 into or within the laminate ST. For example, a plurality of contact holes CTHs are formed to expose a first material layer 41. In this example, the contact holes CTHs are located inside a first pattern F1. For example, the center of the contact hole CTH is located at the center of the first pattern F1, which is referred to as a point on the laminate ST.

[0074] A sacrificial contact structure SCS is formed in the contact hole CTH. For example, an insulating pad 51 is formed in the contact hole CTH, and a sacrificial layer 52 is formed within the insulating pad 51. The sacrificial layer 52 includes a barrier layer 52A and a sacrificial metal layer 52B. The barrier layer 52A may include a metal nitride.

[0075] Reference Figure 9A and Figure 9B The second opening OP2 is reopened. For example, the hard mask pattern 49 is removed and an insulating layer 53 is formed. The insulating layer 53 includes an insulating layer 48. The second opening OP2 is exposed by etching the insulating layer 53, and the sacrificial layer 47 is removed.

[0076] The third opening OP3 is formed by etching the first material layer 41 via the second opening OP2. Relative to Figure 9B The third opening OP3 is spaced apart, for example, in a vertical direction from the first end of the laminate ST to the opposite end of the laminate ST. Figure 9A As shown in the example, a third opening OP3 is arranged along and extends from the second opening OP2, centered on the center of the second opening OP2, and extends between the sacrificial contact structure SCS and the second opening OP2. The outer periphery of the third opening OP3 may correspond to the periphery of the second pattern F2. The first support SP1 and the sacrificial contact structure SCS are exposed through the third opening OP3. The area where the first material layer 41 is removed forms the third opening OP3, which may correspond to the second pattern F2. In this example, the second pattern F2 is spaced apart and arranged along the periphery of the first pattern F1, and the center of the second pattern F2 is located at the periphery of the first pattern F1. A set of third openings OP3 surrounds one of the second openings OP2.

[0077] The second graphic F2 overlaps with the sacrificial contact structure SCS, and the outer periphery of the first support SP1 is located within the second graphic F2, as shown below. Figure 9A As shown in the example, during the process of forming the third opening OP3, the second material layer 42 is supported by the first support SP1, which can improve the structural stability.

[0078] Reference Figure 10A and Figure 10B A second support member SP2 is formed in the second opening OP2 and the third opening OP3. For example, the second support member SP2 is formed by filling the second opening OP2 and the third opening OP3 with an insulating material such as an oxide or nitride and performing a planarization process. The second support member SP2 includes a pillar SP2A in the second opening OP2 and a protrusion SP2B extending from the pillar SP2A in the third opening OP3. Figure 10A As shown in the example, each of the second supports SP2 includes a strut SP2A surrounded by a set of protrusions SP2B, and the different sets of protrusions SP2B are spaced apart or do not overlap. A set of protrusions SP2B at least partially surrounds one or more of the first supports SP1. Therefore, as... Figure 10A As shown in the example, the first support SP1 is located within a second distance D2 from the center of the second support SP2, and the center of the second support SP2 is located at a first distance D1 from the center of the sacrificial contact structure SCS. An insulating layer 54 is formed.

[0079] Reference Figure 11A and Figure 11B The first material layer 41 is replaced with a third material layer 55. For example, a slit is formed in the stack ST, and the first material layer 41 is removed through the slit (not shown). The third material layer 55 is formed in the region where the first material layer 41 has been removed. The third material layer 55 is used to form the gate line and may include a metal such as tungsten or molybdenum. The alternately stacked second material layer 42 and third material layer 55 form the gate structure GST. Alternatively, when the first material layer 41 includes a conductive material, the first material layer 41 does not undergo a replacement process. In this example, the first material layer 41 forms the gate line, and the stack ST is the gate structure GST.

[0080] The sacrificial contact structure SCS is exposed by etching the insulating layer 54, and the sacrificial layer 52 is removed. An insulating spacer 51A is formed by etching the insulating pad 51, and a third material layer 55 is exposed through an opening at the bottom of the insulating spacer 51A. A contact plug 56 can be formed within the insulating spacer 51A. For example, a barrier layer 56A is formed adjacent to the insulating spacer 51A, and a metal layer 56B is formed within the barrier layer 56A. The contact plug 56 is formed by planarizing the metal layer 56B and the barrier layer 56A. During the planarization process, the insulating layer 54 is partially etched, and the second support SP2 is exposed. Figure 11A As shown in the example, the center of the contact structure CS is equidistant from the center of each of the second supports SP2, and the centers of the second supports SP2 are equidistant from the center of the contact structure CS, for example, equiangularly spaced such as at 90-degree intervals.

[0081] When the third opening OP3 is formed, the second material layer 42 is supported by the first support SP1. Therefore, the tilting or collapse of the second material layer 42 is reduced or eliminated during the manufacturing process, and the structural stability can be improved.

[0082] The structure and manufacturing method according to the described embodiments can be applied to semiconductor devices including various structures. Figure 12 and Figure 13 An example configuration of a semiconductor device to which the described implementation methods can be applied is shown.

[0083] Figure 12 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0084] Reference Figure 12 The semiconductor device includes a substrate SUB, peripheral circuitry PC, and a memory cell array CA. In this example, the peripheral circuitry PC and the memory cell array CA are formed on or above the same substrate.

[0085] The substrate SUB can be made of or comprise semiconductor materials. In embodiments, the semiconductor material can include at least one of group IV semiconductors, group III-V compound semiconductors, and group II-VI compound semiconductors. Group IV semiconductors can include single-crystal silicon (Si), polycrystalline silicon, germanium (Ge), or silicon-germanium (SiGe). Group III-V compound semiconductors can include GaAs, GaN, GaP, GaAsP, GaInAsP, AlAs, AlGa, InP, InSb, or InGaAs. Group II-VI compound semiconductors can include ZnS, ZnO, or CdS.

[0086] The substrate SUB may include a dielectric layer. The substrate SUB may be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or a glass substrate. The substrate SUB may include organic materials. In one embodiment, the substrate SUB may include graphene.

[0087] The substrate SUB can be a bulk wafer or an epitaxial layer grown using a selective epitaxial growth (SEG) method. The substrate SUB can be a layer formed using a metal-induced lateral crystallization (MILC) method and may partially comprise a metal. The substrate SUB can be monocrystalline, polycrystalline, or amorphous. The substrate SUB can include group II, III, IV, V, or VI impurities. In an embodiment, the substrate SUB can include an n-well region doped with n-type impurities and / or a p-well region doped with p-type impurities.

[0088] The peripheral circuitry PC is disposed between the substrate SUB and the memory cell array CA. In this example, the peripheral circuitry PC includes row decoders, column decoders, page buffers, logic circuits, control circuits, sense amplifiers, input / output circuits, etc. In implementations, the peripheral circuitry PC may include NMOS transistors, PMOS transistors, resistors, capacitors, etc. The peripheral circuitry PC includes interconnect structures. The interconnect structures include paths for transmitting operating voltages and may include contact plugs, wires, etc.

[0089] The memory cell array CA includes memory cells. In one embodiment, the memory cell array CA includes memory strings connected between source lines and bit lines, and the memory strings may include stacked memory cells. In another embodiment, the memory cell array CA includes memory cells connected between word lines and bit lines. The memory cell array CA includes interconnect structures.

[0090] Figure 13 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0091] Reference Figure 13 The semiconductor device includes a substrate SUB, peripheral circuitry PC, bonding structure BS, and memory cell array CA. The peripheral circuitry PC and memory cell array CA are formed on separate substrates and bonded together. The semiconductor device includes a support substrate SP-B.

[0092] During processes including the formation of peripheral circuitry PC, substrate SUB serves as a support. During processes including the formation of memory cell array CA, support substrate SP-B serves as a support. In an embodiment, after fabricating a first wafer including memory cell array CA and a second wafer including peripheral circuitry PC, the first and second wafers are electrically connected via bonding structure BS. At least a portion of the support substrate SP-B of the first wafer can be removed. The support substrate SP-B can be completely removed or can be partially retained on memory cell array CA.

[0093] The supporting substrate SP-B can be a semiconductor substrate, an insulating substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. The supporting substrate SP-B can be a bulk wafer, an epitaxial layer grown using selective epitaxial growth (SEG), or a layer formed using metal-induced lateral crystallization (MILC). The supporting substrate SP-B can be single-crystal, polycrystalline, or amorphous. The supporting substrate SP-B can include group II, III, IV, V, or VI impurities.

[0094] The bonding structure BS connects the memory cell array CA and the peripheral circuit PC. The memory cell array CA and the peripheral circuit PC can be bonded using wafer-to-wafer bonding, chip-to-wafer bonding, chip-to-chip bonding, etc. The bonding structure BS may include bonding pads, bonding layers, bonding interfaces, etc. Bonding pads may include metals such as copper and aluminum, and / or metal alloys. Bonding interfaces may include non-metal-to-non-metal interfaces, metal-to-metal interfaces, etc. The memory cell array CA and the peripheral circuit PC are electrically connected through the bonding structure BS.

[0095] Interconnect structures included in the memory cell array (CA) and / or peripheral circuitry (PC) can be directly connected without bonding pads. In one embodiment, bonding layers included in the memory cell array (CA) and bonding layers included in the peripheral circuitry (PC) can be bonded to form a bonding interface, and interconnect structures included in the memory cell array (CA) and interconnect structures included in the peripheral circuitry (PC) can be directly connected. As a result, contact plugs, wires, etc., formed on different wafers can be electrically connected without separate bonding pads.

[0096] Can be used and referenced Figure 12 and Figure 13 The configuration described is similar to other configurations.

[0097] Semiconductor devices can have a reference Figure 12 and Figure 13 The described implementation method is a combination of structures, or may have partially modified structures. (Refer to...) Figure 12 and Figure 13In the described implementation, the positions of the memory cell array CA and the peripheral circuit PC can be changed. At least one memory cell array CA and / or at least one peripheral circuit PC can be coupled to a reference. Figure 12 and Figure 13 The configuration described. In this implementation, a portion of the peripheral circuitry PC may be located within the memory cell array CA.

[0098] Although detailed embodiments are described in this disclosure, those skilled in the art will understand that various modifications, additions, and substitutions related to these embodiments are possible without departing from the scope and technical concept of this disclosure. Therefore, the scope of this disclosure should not be limited to the embodiments described above. All variations within the meaning and equivalent scope of the claims are included within its scope.

[0099] Cross-reference to related applications

[0100] This application claims priority to Korean Patent Application No. 10-2024-0103792, filed on August 5, 2024, with the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, the semiconductor device comprising: A gate structure comprising alternating layers of conductive and insulating layers; The second support member includes a pillar and a protrusion, the pillar being located at the periphery of a first pattern defined on the upper surface of the gate structure, and the protrusion extending from the sidewall of the pillar toward the conductive layer. A contact structure that extends through the gate structure within the first pattern and is electrically connected to one of the conductive layers; as well as A first support member penetrates the protrusion.

2. The semiconductor device according to claim 1, wherein, The second pattern is defined by the protrusion on the upper surface of the gate structure, and the pillar is located at the center of each of the second patterns.

3. The semiconductor device according to claim 2, wherein, The second graphic is arranged along the periphery of the first graphic and spaced apart from each other.

4. The semiconductor device according to claim 2, wherein, The first support member is located inside the second shape.

5. The semiconductor device according to claim 2, wherein, In each of the second figures, the first support member is positioned symmetrically to each other relative to the pillar.

6. The semiconductor device according to claim 2, wherein, Each of the second pattern overlaps with the contact structure.

7. The semiconductor device according to claim 1, wherein, The contact structure is located at the center of the first pattern.

8. The semiconductor device according to claim 1, wherein, The contact structure includes: A contact plug electrically connected to one of the conductive layers; and An insulating spacer surrounds the sidewall of the contact plug.

9. The semiconductor device according to claim 1, wherein, The protrusions that extend toward the contact structure make contact with the contact structure.

10. The semiconductor device according to claim 1, wherein, The protrusions arranged along the periphery of the first pattern are spaced apart from each other.

11. The semiconductor device of claim 1, further comprising a channel structure extending through the gate structure.

12. The semiconductor device according to claim 11, wherein, Each of the first support members is a dummy channel structure.

13. A semiconductor device, the semiconductor device comprising: A gate structure comprising alternating layers of conductive and insulating layers; A contact structure that extends through the gate structure and is electrically connected to one of the conductive layers; The second support member includes a pillar and a protrusion, the pillar extending through the gate structure and positioned spaced apart from the contact structure by a first distance, and the protrusion extending from the center of the pillar toward the conductive layer by a second distance. as well as A first support member is located within the second distance from the second support member.

14. The semiconductor device according to claim 13, wherein, The protrusions of adjacent second supports in the second support are spaced apart from each other.

15. The semiconductor device according to claim 13, wherein, The first support penetrates the protrusion.

16. The semiconductor device according to claim 13, wherein, The second support member is arranged along the periphery of a first circle centered on the contact structure and having a radius of the first distance.

17. The semiconductor device according to claim 13, wherein, The first support member is located inside a second circle with a radius centered on each of the second supports member and having the second distance.

18. The semiconductor device according to claim 17, wherein, The second circle overlaps with the contact structure.

19. A semiconductor device, the semiconductor device comprising: A gate structure comprising alternating layers of insulating and conductive layers; A contact structure that extends within the gate structure and is electrically connected to one of the conductive layers; The second support member includes a pillar and a protrusion, the pillar having a center within a first distance from the center of the contact structure, and the protrusion extending between the pillar and the conductive layer. as well as A first support member, which is at least partially surrounded by the protrusion.

20. The semiconductor device of claim 19, wherein, The pillar is located at the center of each of the protrusions.

21. The semiconductor device according to claim 19, wherein, The second support members are spaced apart from each other.

22. The semiconductor device according to claim 19, wherein, Each of the first supports is located within a second distance from the center of one of the second supports, and wherein the first distance is greater than the second distance.

23. The semiconductor device according to claim 19, wherein, The center of the contact structure is positioned equidistant from the center of each of the second supports.

24. A semiconductor device, the semiconductor device comprising: A gate structure comprising alternating layers of insulating and conductive layers; A contact structure that extends within the gate structure and is electrically connected to one of the conductive layers; The second support member includes a pillar spaced apart from the contact structure by a first distance, and includes a protrusion extending between the pillar and the conductive layer, wherein the pillar extends through the gate structure, and the protrusion extends from the center of the pillar to a second distance. as well as A first support member is located within the second distance of one of the second supports members.

25. The semiconductor device according to claim 24, wherein, The protrusions are arranged around the contact structure and spaced apart from each other.

26. The semiconductor device of claim 24, wherein, A group of the protrusions at least partially surrounds one or more of the first support member.

27. A method for manufacturing a semiconductor device, the method comprising the following steps: Forming a laminate comprising alternating layers of first material layers and multiple layers of second material layers; Forming a first support member extending through the laminated member; Forming a sacrificial contact structure that at least partially extends through the laminate; Forming a first opening extending through the laminate; A plurality of second openings are formed by etching the plurality of first material layers through the first opening, the second openings exposing the first support and the sacrificial contact structure; as well as A second support is formed in the first opening and the plurality of second openings.

28. The method of claim 27, further comprising: Forming a channel structure that extends through the laminated member.

29. The method according to claim 28, wherein, The first support member is formed during the formation of the channel structure.

30. The method according to claim 27, wherein, The steps for forming the first support member include the following: An opening is formed in the laminate; A virtual memory layer is formed in the opening; A virtual channel layer is formed within the virtual memory layer; and A virtual insulating core is formed within the virtual channel layer.

31. The method according to claim 27, further comprising: Replace the first material layer with a third material layer.

32. The method according to claim 27, wherein, The steps for forming the sacrificial contact structure include the following: Contact holes are formed in the laminate; An insulating gasket is formed in the contact hole; and A sacrificial layer is formed within the insulating liner.

33. The method according to claim 32, further comprising the following steps: Remove the sacrificial layer; An insulating spacer is formed by etching the insulating pad; as well as A contact plug is formed within the insulating spacer.

34. The method according to claim 27, wherein, The second support member includes: A support pillar, located in the first opening; and A protrusion located in the second opening.

35. A method for manufacturing a semiconductor device, the method comprising the following steps: Forming a laminate comprising alternating layers of first material layers and multiple layers of second material layers; Forming a plurality of first openings extending through the laminate; A plurality of second openings are formed extending through the laminate, wherein the center of the plurality of second openings is located at a first distance from a point on the laminate, and wherein the plurality of second openings are spaced apart; Multiple first support members are formed, and one first support member is provided in each of the first openings; A sacrificial contact structure is formed that at least partially extends through the laminate and is centered at the point on the laminate; A plurality of third openings are formed by etching the plurality of first material layers via the plurality of second openings, the plurality of third openings exposing the plurality of first supports and the sacrificial contact structure; and A plurality of second support members are formed, with one second support member provided in each of the second openings and in a set of third openings among the plurality of third openings.

36. The method according to claim 35, wherein, Each of the plurality of first openings is located within a first distance from the point on the laminate.

37. The method of claim 35, wherein, The plurality of second openings are formed when the plurality of first openings are formed.

38. The method according to claim 35, wherein, Each of the plurality of second openings is positioned at the center of a set of third openings.

39. The method according to claim 35, wherein, The third opening is arranged around the sacrificial contact structure and spaced apart from each other.

40. The method of claim 35, further comprising the step of: Forming channel holes extending through the laminate; and A channel structure is formed in the channel hole.

41. The method according to claim 40, wherein, When the channel hole is formed, the plurality of first openings and the plurality of second openings are formed, and When the channel structure is formed, the plurality of first support members are formed.

42. The method of claim 35, further comprising replacing the first material layer with a third material layer.

43. The method according to claim 35, wherein, The steps for forming the sacrificial contact structure include the following: Forming contact holes that extend through the laminate; An insulating gasket is formed in the contact hole; and A sacrificial layer is formed within the insulating liner.

44. The method according to claim 43, wherein, The contact hole is centered on the point on the laminate.

45. The method according to claim 43, further comprising the following step: Remove the sacrificial layer; An insulating spacer is formed by etching the insulating pad; as well as A contact plug is formed within the insulating spacer.

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