Semiconductor device and preparation method thereof, and storage system

Abstract

The invention discloses a semiconductor device, a preparation method thereof and a storage system. The semiconductor device comprises a stack structure and a connection structure, the stack structure comprises a gate layer, the connection structure extends into the stack structure along a first direction and is connected with the gate layer, and the gate layer comprises two first sub-gate layers oppositely arranged in a second direction and a second sub-gate layer located between the two first sub-gate layers. The first sub-gate layers extend along the third direction, the second sub-gate layers extend along the second direction and are respectively connected with the two first sub-gate layers, and the first direction, the second direction and the third direction intersect in pairs.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor technology, and particularly relate to a semiconductor device and a preparation method thereof, and a storage system. BACKGROUND

[0002] A semiconductor device is a memory device used for storing information in modern information technology, and its main function is to store programs and various data, and can complete the access of programs or data at high speed and automatically during the operation of a computer. Taking a three-dimensional memory as an example, the three-dimensional memory generally includes a stack structure and a channel structure penetrating the stack structure, and the stack structure includes alternatingly stacked dielectric layers and gate layers.

[0003] At present, how to further improve the performance of the semiconductor device is one of the technical problems to be solved by those skilled in the art. SUMMARY

[0004] Embodiments of the present application provide a semiconductor device and a preparation method thereof, and a storage system.

[0005] The first aspect of the present application provides a semiconductor device, which includes a stack structure and a connection structure, the stack structure includes a gate layer, the connection structure extends into the stack structure along a first direction and is connected with the gate layer, the gate layer includes two first sub-gate layers oppositely arranged in a second direction and a second sub-gate layer located between the two first sub-gate layers, the first sub-gate layer extends along a third direction, the second sub-gate layer extends along the second direction and is connected with the two first sub-gate layers respectively, and the first direction, the second direction and the third direction intersect with each other.

[0006] In some embodiments, a plurality of second sub-gate layers are arranged between the two first sub-gate layers and are spaced apart in the third direction.

[0007] In some embodiments, the plurality of second sub-gate layers are equally spaced apart in the third direction.

[0008] In some embodiments, the size of the second sub-gate layer along the third direction is less than or equal to 4um.

[0009] In some embodiments, the connection structure is located between the two first sub-gate layers in the second direction and is connected with one of the first sub-gate layers.

[0010] In some embodiments, the part of the first sub-gate layer in contact with the connection structure has a first size in the second direction, the part of the first sub-gate layer located on one side of the connection structure along the third direction has a second size in the second direction, and the first size is greater than the second size.

[0011] In some embodiments, the gate layer further includes two third sub-gate layers, the first sub-gate layer is located between the two third sub-gate layers along a third direction, and the third sub-gate layers extend along the third direction and are connected with the two first sub-gate layers.

[0012] In some embodiments, the stack structure includes a first dielectric layer arranged in the same layer as the gate layer, the connection structure penetrates the first dielectric layer along the first direction, the first dielectric layer includes a plurality of sub-dielectric layers, the sub-dielectric layers are alternately distributed with the second sub-gate layers along the third direction, and the second sub-gate layers are provided with the sub-dielectric layers on both sides along the third direction.

[0013] In some embodiments, the stack structure has a first region and two second regions, the first region is located between the two second regions along a third direction, the first sub-gate layers, the second sub-gate layers and the sub-dielectric layers are located in the first region, the gate layer further includes third sub-gate layers located in the second regions, the stack structure further includes second dielectric layers alternately stacked with the gate layers and the first dielectric layers along the first direction, the second dielectric layers extend in the first region and the second regions along the third direction, and the connection structure is located in the first region and extends along the first direction.

[0014] In some embodiments, the semiconductor device further includes a first gate line isolation structure and a second gate line isolation structure, the first gate line isolation structure penetrates the stack structure along the first direction and is located on a side of the first sub-gate layers away from the second sub-gate layers along the second direction, the second gate line isolation structure penetrates the stack structure along the first direction, and the second sub-gate layers surround the second gate line isolation structure.

[0015] In some embodiments, the first gate line isolation structure includes a spacing structure and a plurality of sub-isolation structures, the plurality of sub-isolation structures are spaced apart along the third direction, and the spacing structure is located between adjacent sub-isolation structures along the third direction.

[0016] In some embodiments, the spacing structure includes a spacing column and a spacing layer, the spacing column penetrates the stack structure along the first direction, and the spacing layer is arranged in the same layer as the gate layer and surrounds the spacing column.

[0017] In some embodiments, the sub-isolation structure and / or the second gate line isolation structure include a first semiconductor layer, a first adhesive layer and a first isolation layer, the first semiconductor layer penetrates the stack structure along the first direction, the first adhesive layer is located at least on a sidewall of the first semiconductor layer extending along the first direction, and the first isolation layer is located on a side of the first adhesive layer away from the first semiconductor layer.

[0018] In some embodiments, a sidewall of the first gate line isolation structure and / or the second gate line isolation structure extending along the first direction includes a convex surface and / or a concave surface.

[0019] In some embodiments, the connection structure includes a conductive layer, a second adhesive layer, and a second isolation layer, the conductive layer extends along a first direction, a portion of the second adhesive layer is located on a sidewall of the conductive layer extending along the first direction, another portion of the second adhesive layer is located on a side of the conductive layer along the first direction and extends to the gate layer along a second direction, and the second isolation layer is located on a side of the second adhesive layer away from the conductive layer along a direction intersecting the first direction.

[0020] The second aspect of the present application provides a method for manufacturing a semiconductor device, the method comprising: forming a stack structure, the stack structure including a gate layer; and forming a connection structure, the connection structure extending into the stack structure along a first direction and connecting with the gate layer; wherein the gate layer includes two first sub-gate layers oppositely arranged along a second direction and a second sub-gate layer located between the two first sub-gate layers, the first sub-gate layers extend along a third direction, and the second sub-gate layers extend along the second direction and connect with the two first sub-gate layers respectively, the first direction, the second direction, and the third direction intersect with each other pairwise.

[0021] In some embodiments, forming the stack structure includes: forming a layer stack structure, the layer stack structure including a first dielectric layer; forming a first gate line slit and a second gate line slit oppositely arranged along the second direction, the first gate line slit and the second gate line slit both penetrating the layer stack structure along the first direction; and replacing part of the first dielectric layer with the gate layer through the first gate line slit and the second gate line slit.

[0022] In some embodiments, the first gate line slit includes a plurality of sub-isolation slits spaced apart along a third direction and a spacing slit located between adjacent sub-isolation slits along the third direction; and replacing part of the first dielectric layer with the gate layer through the first gate line slit and the second gate line slit includes: replacing part of the first dielectric layer with a spacing layer through the spacing slit; replacing part of the first dielectric layer with a first sub-gate layer through one of the sub-isolation slits and replacing part of the first dielectric layer with a second sub-gate layer through the second gate line slit.

[0023] In some embodiments, replacing part of the first dielectric layer with the first sub-gate layer includes: replacing part of the first dielectric layer with the first sub-gate layer through a first sub-isolation slit; and replacing part of the first dielectric layer with the gate layer through the first gate line slit and the second gate line slit further includes: replacing part of the first dielectric layer with a third sub-gate layer through a second sub-isolation slit, the third sub-gate layer extends along the third direction and connects with the two first sub-gate layers respectively; and the gate layer further includes the third sub-gate layer, and the plurality of sub-isolation slits include the first sub-isolation slit and two second sub-isolation slits respectively located on both sides of the first sub-isolation slit along the third direction.

[0024] In some embodiments, replacing the portion of the first dielectric layer with the spacer layer through the spacer gap comprises: forming a first sacrificial layer filling the first gate line gap and a second sacrificial layer filling the second gate line gap; removing the portion of the first sacrificial layer located in the spacer gap, exposing a portion of the first dielectric layer; removing the exposed portion of the first dielectric layer, forming a first interlayer gap; and forming the spacer layer in the first interlayer gap.

[0025] In some embodiments, the method further comprises: forming a first connection hole extending to the first dielectric layer in the first direction in the stacked structure; removing a portion of the first dielectric layer through the first connection hole, forming a sacrificial gap in communication with the first connection hole; depositing a sacrificial material in the first connection hole and the sacrificial gap, forming a connection sacrificial layer; wherein forming the connection structure comprises: removing the connection sacrificial layer, forming a second connection hole exposing the first sub-gate layer; forming the connection structure in the second connection hole.

[0026] The third aspect of the present application provides a storage system, the storage system comprising a controller and the semiconductor device of the first aspect of the present application, the controller being coupled to the semiconductor device and configured to control the semiconductor device to store data.

[0027] It is to be understood that the details set forth herein do not purport to be exhaustive or limiting the scope of the application. Other features, aspects, and objects of the application will become apparent to those skilled in the art from the following detailed description, which, taken in combination with the drawings, discloses various embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0028] Other features, objects, and advantages of the application will become apparent to those skilled in the art from the following detailed description, which, taken in conjunction with the drawings, discloses various embodiments. Like reference numerals in the various drawings are meant to indicate like elements. In the drawings:

[0029] FIG. 1 is a top view schematic of a semiconductor device according to one embodiment of the present application;

[0030] FIG. 2 is a schematic of a conductive path of a gate layer in a semiconductor device according to one embodiment of the present application;

[0031] FIG. 3 is a top view schematic of a semiconductor device according to another embodiment of the present application;

[0032] FIG. 4 is a schematic of a conductive path of a gate layer in a semiconductor device according to another embodiment of the present application;

[0033] FIG. 5 is a top view schematic of a semiconductor device according to yet another embodiment of the present application;

[0034] FIG. 6 is a top view schematic diagram of a semiconductor device according to one embodiment of the present application;

[0035] FIG. 7 is FIG. 3 is a cross-sectional view schematic diagram at A-A and B-B;

[0036] FIG. 8 is FIG. 3 is a cross-sectional view schematic diagram at C-C and D-D;

[0037] FIG. 9 is FIG. 3 is a cross-sectional view schematic diagram at E-E;

[0038] FIG. 10 is a partial cross-sectional view schematic diagram of a first region of a semiconductor device according to one embodiment of the present application;

[0039] FIG. 11 is a cross-sectional view schematic diagram of a first (second) channel structure according to one embodiment of the present application;

[0040] FIG. 12 is a flow chart schematic diagram of a method of manufacturing a semiconductor device according to one embodiment of the present application;

[0041] FIG. 13A to FIG. 38 is a process schematic diagram of a method of manufacturing a semiconductor device according to one embodiment of the present application;

[0042] FIG. 39 is a block diagram of a system having a semiconductor device according to one embodiment of the present application;

[0043] FIG. 40 is a schematic diagram of a memory card having a semiconductor device according to one embodiment of the present application; and

[0044] FIG. 41 is a schematic diagram of a solid state drive having a semiconductor device according to one embodiment of the present application.

[0045] Reference Signs:

[0046] 100, stack structure; 100', layer stack structure; 101, first region;

[0047] 102, second region; 110, gate layer; 111, first sub-gate layer;

[0048] 112, second sub-gate layer; 113, third sub-gate layer; 114, second interlayer gap;

[0049] 115, third interlayer gap; 116, gate dielectric layer; 117, gate conductive layer;

[0050] 120, first dielectric layer; 121, sub-dielectric layer; 130, second dielectric layer;

[0051] 140, fourth dielectric layer; 150, fifth dielectric layer; 160, sixth dielectric layer;

[0052] 200, connection structure; 201, first connection hole; 202, second connection hole;

[0053] 203, sacrificial gap; 210, conductive layer; 220, second adhesive layer;

[0054] 230, second isolation layer; 240, connection sacrificial layer; 300, first gate line isolation structure;

[0055] 301, first gate line gap; 302, sub-isolation gap; 302-1, first sub-isolation gap;

[0056] 302-2, second sub-isolation gap; 303, interval gap; 310, sub-isolation structure;

[0057] 310-1, first sub-isolation structure; 310-2, second sub-isolation structure;

[0058] 311, semiconductor layer; 312, first adhesive layer; 313, first isolation layer;

[0059] 320, interval structure; 321, interval pillar; 322, interval layer;

[0060] 323, first interlayer gap; 400, second gate line isolation structure;

[0061] 401, second gate line gap; 510, first channel structure; 520, second channel structure;

[0062] 530, functional layer; 531, barrier layer; 532, charge trapping layer; 533, tunneling layer;

[0063] 540, channel layer; 550, filling core layer; 560, channel plug;

[0064] 610, first sacrificial layer; 620, second sacrificial layer; 630, third sacrificial layer;

[0065] 640, fourth sacrificial layer; 700, substrate; 710, second semiconductor layer; 800, system;

[0066] 801, memory system; 802, semiconductor device; 803, memory controller;

[0067] 804, host; 810, memory card; 811, memory card connector; 820, SSD;

[0068] 821, SSD connector. DETAILED DESCRIPTION

[0069] For a better understanding of the present application, various aspects of the present application will be described in more detail below with reference to the accompanying drawings. It is to be noted that these detailed description is merely descriptive of exemplary embodiments of the present application and is not intended in any way to limit the scope of the present application. Throughout the specification, like reference numerals will refer to like elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0070] It should be noted that in this specification and in the claims, the terms first, second, third, etc. are merely used to separate one feature from another, and do not imply any order or sequence, unless explicitly stated otherwise.

[0071] In the drawings, the thickness, size, and shape of components have been slightly adjusted for ease of illustration. The drawings are merely examples and are not strictly to scale.

[0072] It should also be understood that expressions such as "include", "including", "have", "has", "contain" and / or "containing" and the like, are open-ended terms that are intended to mean that the listed components are present, but that other components are not excluded, unless specifically stated otherwise. Furthermore, when expressions such as "at least one of" appear after a list of two or more items, it is meant that any of the listed items can be present, individually or in combination, but not necessarily all of the items. Furthermore, when describing embodiments of the present application, the use of "may" means "one or more embodiments of the present application". Also, the word "exemplary" is intended to mean an example or an illustration.

[0073] Unless otherwise defined, all terms used in this document, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It should also be understood that the words "comprise", "comprising", "comprises", "including", "has", "have", "contains" and / or "containing" when used in this specification are open-ended terms that are intended to mean that the listed components are present, but that other components are not excluded, unless specifically stated otherwise. Furthermore, when expressions such as "at least one of" appear after a list of two or more items, it is meant that any of the listed items can be present, individually or in combination, but not necessarily all of the items. Furthermore, when describing embodiments of the present application, the use of "may" means "one or more embodiments of the present application". Also, the word "exemplary" is intended to mean an example or an illustration.

[0074] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. In addition, unless explicitly limited or contradictory in context, the specific steps contained in the methods described in the present application do not have to be limited to the order described, but can be executed in any order or in parallel. The present application will be described in more detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0075] Furthermore, in this application, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a structure below or above, or may have a range smaller than that of the structure below or above. Additionally, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. Furthermore, in this application, the use of "connection" or "joint" may indicate direct or indirect contact between corresponding components, unless otherwise expressly defined or inferred from the context.

[0076] FIG. 1 A top view schematic diagram of a semiconductor device according to one embodiment of this application is shown. To facilitate a clear view of the gate layer, FIG. 1 The channel structure is omitted. For example... FIG. 1 As shown, this application provides a semiconductor device including a stacked structure, a channel structure (not shown), and a connection structure 200. The stacked structure includes a gate layer 110 and a first dielectric layer 120 disposed on the same layer as the gate layer 110. The channel structure penetrates the gate layer 110 along a first direction, and the connection structure 200 penetrates the first dielectric layer 120 along the first direction and is connected to the gate layer 110. The gate layer 110 includes two first sub-gate layers 111 disposed opposite each other in a second direction. The first dielectric layer 120 is located between the two first sub-gate layers 111 in the second direction. The connection structure 200 is connected to one of the first sub-gate layers 111. The first direction intersects the second direction. As an example, the first direction can be perpendicular to the second direction; for example, the first direction is the z-direction, and the second direction is... FIG. 1 The x-direction in the middle.

[0077] like FIG. 1 As shown, the stacked structure has a first region 101 and two second regions 102. The first region 101 is located between the two second regions 102 in a third direction. Multiple connection structures 200 are disposed in the first region 101, and each connection structure 200 is connected to a different gate layer 110. The channel structure corresponding to a portion of the stacked structure and a portion of the gate layer 110 together constitute a memory cell. Multiple memory cells are connected in series along a first direction to form a memory string. Memory cells located in the same row, i.e., distributed along a third direction, can be connected to the same word line. The remaining portion of the gate layer 110 can serve as the word line for multiple memory cells in the corresponding memory string. The connection structures 200 are connected to the gate layer 110, so that the connection structures 200 can control the corresponding memory cells to perform operations such as programming, reading, or erasing by applying different voltages to the gate layer 110.

[0078] FIG. 2A schematic diagram of the conductive path of the gate layer in a semiconductor device according to one embodiment of this application is shown. (Combined with...) FIG. 1 and FIG. 2 As shown, the connection structure 200 controls... FIG. 2 Taking the storage string in the second region 102 on the left as an example, and... FIG. 2 The connection structure 200 connected to the gate layer 110 shown is located in the middle of the first region 101 in the third direction. Therefore, if the memory string located on the left side needs to be controlled, the connection structure 200 connected to the gate layer 110 will... FIG. 2 The solid arrow indicates the first conductive path, and the dashed arrow indicates the second conductive path, which controls the memory string. The first conductive path includes a portion of one of the first sub-gate layers 111, and the second conductive path includes the remainder of one of the first sub-gate layers 111 and the entirety of the other first sub-gate layer 111. It is evident that the second conductive path needs to bypass the portion of the first dielectric layer 120 located to the right of the connection structure 200. It should be noted that the connection structure 200 is controlled via the gate layer 110. FIG. 2 The principle of storing the string in the second region 102 on the right is similar to that described above, and will not be repeated here.

[0079] FIG. 3 A top view schematic diagram of a semiconductor device according to another embodiment of this application is shown. FIG. 4 A schematic diagram of the conductive path of the gate layer in a semiconductor device according to another embodiment of this application is shown. FIG. 7 It shows FIG. 3 Cross-sectional views at AA and BB. FIG. 8 It shows FIG. 3 Cross-sectional views at CC and DD. FIG. 9 It shows FIG. 3 Cross-sectional view at EE FIG. 10 It shows FIG. 3 Another cross-sectional view at BB. This is to make the gate layer clearer. FIG. 3 and FIG. 4 The channel structure is omitted.

[0080] like FIG. 3 , FIG. 7 to FIG. 10As shown, the semiconductor device provided by the embodiment of the present application includes a stack structure 100 and a connection structure 200, the stack structure 100 includes a gate layer 110, and the connection structure 200 extends into the stack structure 100 along a first direction and is connected with the gate layer 110. The gate layer 110 includes two first sub-gate layers 111 oppositely arranged in a second direction and a second sub-gate layer 112 between the two first sub-gate layers 111, the first sub-gate layers 111 extend along a third direction, and the second sub-gate layer 112 extends along the second direction and is connected with the two first sub-gate layers 111 respectively, the first direction, the second direction and the third direction intersect with each other.

[0081] Since the second sub-gate layer 112 is further arranged between the two first sub-gate layers 111 in the embodiment of the present application, one end of the second sub-gate layer 112 is connected with one of the first sub-gate layers 111, and the other end of the second sub-gate layer 112 is connected with the other first sub-gate layer 111, in other words, the second sub-gate layer 112 is connected in parallel between the two first sub-gate layers 111, therefore, if the storage string on the left side is to be controlled, the connection structure 200 connected with the gate layer 110 can control the storage string through the third conductive path shown by the solid arrow and the fourth conductive path shown by the dashed arrow. FIG. 4 The third conductive path includes a part of one of the first sub-gate layers 111, and the fourth conductive path includes the second sub-gate layer 112 and a part of the other first sub-gate layer 111. Due to the existence of the second sub-gate layer 112, the fourth conductive path does not need to be long, in other words, the fourth conductive path in the embodiment of the present application does not include the remaining part of one of the first sub-gate layers 111, but includes a part of the other first sub-gate layer 111 instead of the whole, so that the path of the fourth conductive path is shorter compared with the second conductive path, thereby not only reducing the resistance of the gate layer 110 as a whole, but also hardly increasing the cost. It should be noted that the principle of the connection structure 200 controlling the storage string on the right side through the gate layer 110 is similar to the above, which will not be described here.

[0082] It should be noted that the semiconductor device provided in the embodiments of this application can be a memory or a part of a memory. For example, the memory may include peripheral circuits and the aforementioned semiconductor device, with the peripheral circuits bonded to the semiconductor device. In this case, the aforementioned semiconductor device is part of the memory. Alternatively, the memory may be a memory array, in which case the memory array is the aforementioned semiconductor device. The intersection of the first direction, the second direction, and the third direction can generally be understood as having an angle between the first direction and the second direction, between the second direction and the third direction, and between the first direction and the third direction. For example, the first direction and the second direction are perpendicular or approximately perpendicular to each other, the second direction and the third direction are perpendicular or approximately perpendicular to each other, and the first direction and the third direction are perpendicular or approximately perpendicular to each other. As an example, in the embodiments of this application, the first direction can be the z-direction in the figures, the second direction can be the x-direction in the figures, and the third direction can also be the y-direction.

[0083] In some embodiments, the stacked structure 100 has a first region 101 and two second regions 102, the first region 101 being located between the two second regions 102 in a third-direction orientation, and a first sub-gate layer 111 and a second sub-gate layer 112 both located in the first region 101. FIG. 3 and FIG. 7 As shown, the stacked structure 100 includes a gate layer 110 and a first dielectric layer 120 disposed on the same layer as the gate layer 110. The first dielectric layer 120 is located in a first region 101 and is situated between two first sub-gate layers 111 in a second direction. The material of the first dielectric layer 120 may include, but is not limited to, silicon oxynitride or silicon nitride. FIG. 3 and FIG. 6 As shown, since a second sub-gate layer 112 is also provided between the two first sub-gate layers 111 in this embodiment, the first dielectric layer 120 is divided into multiple sub-dielectric layers 121 by the second sub-gate layer 112. The sub-dielectric layers 121 and the second sub-gate layers 112 are alternately distributed in the third direction. The second sub-gate layer 112 is provided with sub-dielectric layers 121 on both sides of the third direction. In other words, along the third direction, the second sub-gate layer 112 is located between adjacent sub-dielectric layers 121.

[0084] like FIG. 7 As shown, the stacked structure 100 may further include a second dielectric layer 130 that is alternately stacked with the gate layer 110 and the first dielectric layer 120 along a first direction. The second dielectric layer 130 extends in the first region 101 and the second region 102 along a third direction. The material of the second dielectric layer 130 may include, but is not limited to, silicon oxide, silicon oxynitride, or high-k materials such as hafnium oxide, zirconium oxide, aluminum oxide, and tantalum oxide.

[0085] In some implementations, such as FIG. 6As shown, a plurality of second sub-gate layers 112 is arranged between the two first sub-gate layers 111, and the plurality of second sub-gate layers 112 is spaced apart in the third direction. As an example, the plurality of second sub-gate layers 112 can be equally spaced apart in the third direction.

[0086] According to the above, by connecting the second sub-gate layer 112 in parallel between the two first sub-gate layers 111, the path of the conductive path between the connection structure 200 and the storage string can be shortened, and thus the overall resistance of the gate layer 110 can be reduced. In some embodiments, one second sub-gate layer 112 is arranged between the two first sub-gate layers 111, and the overall resistance of the gate layer 110 is reduced by about 33.3%, and the overall resistance of all the gate layers 110 in the stack structure 100 is reduced by about 9.1%. In some other embodiments, three second sub-gate layers 112 are equally spaced apart between the two first sub-gate layers 111, and the overall resistance of all the gate layers 110 in the stack structure 100 is reduced by about 13.6%.

[0087] In some embodiments, the width of the second sub-gate layer 112, i.e., the size of the second sub-gate in the third direction, is less than or equal to 4 um. As an example, the width of the second sub-gate layer 112 is about 0.5 um to 1.5 um. For example, the width of the second sub-gate layer 112 is 1 um.

[0088] In some embodiments, the gate layer 110 can further include two third sub-gate layers 113, the two first sub-gate layers 111 are located between the two third sub-gate layers 113 in the third direction, and the two first sub-gate layers 111 are oppositely arranged in the second direction. The third sub-gate layer 113 extends along the third direction and is connected with the two first sub-gate layers 111. As shown, FIG. 3 As shown, the first sub-gate layer 111 and the second sub-gate layer 112 are located in the first region 101, and the third sub-gate layer 113 is located in the second region 102. It should be noted that the first sub-gate layer 111, the second sub-gate layer 112, and the third sub-gate layer 113 can be formed in the same process or in different processes. There can be no obvious detectable interface between the first sub-gate layer 111 and the second sub-gate layer 112 and between the first sub-gate layer 111 and the third sub-gate layer 113. The first sub-gate layer 111 and the third sub-gate layer 113 can be distinguished by the size of the gate layer 110 in the second direction and the remaining first dielectric layer 120, and the first sub-gate layer 111 and the second sub-gate layer 112 can be distinguished by the extension direction of the first sub-gate layer 111 and the second sub-gate layer 112 and the remaining first dielectric layer 120.

[0089] In some embodiments, the semiconductor device further includes a plurality of first gate isolation structures 300 spaced apart in a second direction. The first gate isolation structures 300 penetrate the stacked structure 100 along a first direction and extend along a third direction, dividing the stacked structure 100 into multiple blocks. A first sub-gate layer 111 and a second sub-gate layer 112 are located between adjacent first gate isolation structures 300, with the first gate isolation structure 300 located in the second direction on the side of the first sub-gate layer 111 away from the second sub-gate layer 112. The first gate isolation structure 300 can be a single-layer structure or a multi-layer structure; this application does not limit this.

[0090] As an example, such as FIG. 3 , FIG. 7 and FIG. 8 As shown, the first gate isolation structure 300 may include a spacer structure 320 and a plurality of sub-isolation structures 310. The plurality of sub-isolation structures 310 are spaced apart in a third direction, and the spacer structure 320 is located between adjacent sub-isolation structures 310 in the third direction. The dimension of the sub-isolation structure 310 extending in the third direction may be larger than the dimension of the spacer structure 320 extending in the third direction. The plurality of sub-isolation structures 310 may include a first sub-isolation structure 310-1 located in a first region 101 and a second sub-isolation structure 310-2 located in a second region 102.

[0091] As an example, the spacer structure 320 includes a spacer post 321 and a spacer layer 322. The spacer post 321 extends through the stacked structure 100 along a first direction, and the spacer layer 322 is disposed on the same layer as the gate layer 110 and surrounds the spacer post 321. The spacer layer 322 and the spacer post 321 can be made of the same or different materials. The material of the spacer layer 322 can include, but is not limited to, silicon oxide, silicon oxynitride, or high-k materials such as hafnium oxide, zirconium oxide, aluminum oxide, and tantalum oxide. The spacer post 321 and the sub-isolation structure 310 can have the same structure or different structures. For example, both the spacer post 321 and the sub-isolation structure 310 include a first isolation layer 313, a first adhesive layer 312, and a first semiconductor layer 311. The first semiconductor layer 311 extends through the stacked structure 100 along the first direction, the first adhesive layer 312 at least covers the sidewalls of the first semiconductor layer 311 extending along the first direction, and the first isolation layer 313 is located on the side of the first adhesive layer 312 opposite to the first semiconductor layer 311. The material of the first semiconductor layer 311 may include, but is not limited to, semiconductor materials such as polycrystalline silicon; the material of the first adhesive layer 312 may include, but is not limited to, at least one of titanium nitride, tantalum nitride, tungsten carbide, and metal alloys; and the material of the first isolation layer 313 may include, but is not limited to, at least one of silicon carbide, silicon nitride, silicon oxynitride, and organosilicon glass.

[0092] In some embodiments, the semiconductor device further comprises a second gate line isolation structure 400 located between adjacent first gate line isolation structures 300 in the second direction, the second gate line isolation structure 400 extending through the stack structure 100 along the first direction and extending along the second direction, the second sub-gate layer 112 surrounding the second gate line isolation structure 400. The second gate line isolation structure 400 can be a single-layer structure or a multi-layer structure. As an example, the second gate line isolation structure 400 has the same structure as the sub-isolation structure 310. For example, the second gate line isolation structure 400 also comprises a first isolation layer 313, a first adhesive layer 312 and a first semiconductor layer 311.

[0093] It should be noted that the first gate line isolation structure 300 and the second gate line isolation structure 400 can be formed based on etching a groove or based on a hole expansion process. The first gate line isolation structure 300 (the second gate line isolation structure 400) formed by different processes can have different shapes of sidewalls. For example, as shown in FIG. 5 , the sidewall of the first gate line isolation structure 300 and / or the second gate line isolation structure 400 extending along the first direction comprises a convex surface and / or a concave surface; for another example, as shown in FIG. 6 , the sidewall of the first gate line isolation structure 300 and / or the second gate line isolation structure 400 extending along the first direction comprises a plane extending along the third direction.

[0094] In some embodiments, the connection structure 200 is located in the first region 101 and extends in the stack structure 100 along the first direction, the connection structure 200 is located between two first sub-gate layers 111 in the second direction, and the connection structure 200 is connected to one of the first sub-gate layers 111. As an example, as shown in FIG. 7 , the part of the first sub-gate layer 111 in contact with the connection structure 200 has a first size in the second direction, the part of the first sub-gate layer 111 located on one side of the connection structure 200 along the third direction has a second size in the second direction, and the first size is greater than the second size.

[0095] As an example, as shown in FIG. 7As shown, the connection structure 200 can include a conductive layer 210, a second adhesive layer 220, and a second isolation layer 230, the conductive layer 210 extends into the stack structure 100 along a first direction, a portion of the second adhesive layer 220 covers a sidewall of the conductive layer 210 extending along the first direction, another portion of the second adhesive layer 220 is located at one side of the conductive layer 210 along the first direction and connected with the gate layer 110, and the second isolation layer 230 is located at a side of the second adhesive layer 220 away from the conductive layer 210 in a direction intersecting the first direction. The material of the second isolation layer 230 can include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, and organosilicate glass; the material of the conductive layer 210 can include, but is not limited to, at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, and silicide; and the material of the second adhesive layer 220 can include, but is not limited to, at least one of titanium nitride, tantalum nitride, tungsten carbide, and metal alloy. It should be noted that the connection structure 200 can also have other structural forms, which are not limited in the present application. For example, the connection structure 200 can not include the second adhesive layer 220, but only include the second isolation layer 230 and the conductive layer 210, a portion of the conductive layer 210 extends along the first direction, another portion of the conductive layer 210 extends along a second direction and is connected with the gate layer 110, and the second isolation layer 230 covers a sidewall of the conductive layer 210 extending along the first direction.

[0096] In some embodiments, the semiconductor device further includes a first channel structure 510 extending through the stack structure 100 along a first direction, the first channel structure 510 being located in the second region 102 and extending through the third sub-gate layer 113 along the first direction. As an example, as shown in FIG. 5, the first channel structure 510 includes a blocking layer 531, a charge trapping layer 532, a tunneling layer 533, and a channel layer 540, the channel layer 540 extending through the stack structure 100 along the first direction, the tunneling layer 533 being located at a side of the channel layer 540 facing the stack structure 100 in a direction intersecting the first direction, the charge trapping layer 532 being located at a side of the tunneling layer 533 away from the channel layer 540, and the blocking layer 531 being located at a side of the charge trapping layer 532 away from the tunneling layer 533. FIG. 11 As shown, the first channel structure 510 includes a blocking layer 531, a charge trapping layer 532, a tunneling layer 533, and a channel layer 540, the channel layer 540 extending through the stack structure 100 along a first direction, the tunneling layer 533 being located at a side of the channel layer 540 facing the stack structure 100 in a direction intersecting the first direction, the charge trapping layer 532 being located at a side of the tunneling layer 533 away from the channel layer 540, and the blocking layer 531 being located at a side of the charge trapping layer 532 away from the tunneling layer 533. The material of the channel layer 540 can include, but is not limited to, amorphous silicon, polysilicon, or single crystal silicon; the material of the tunneling layer 533 can include, but is not limited to, silicon oxide or silicon nitride; the material of the charge trapping layer 532 can include, but is not limited to, silicon nitride, silicon oxynitride, silicon, or a combination of any of the above; and the material of the blocking layer 531 can include, but is not limited to, silicon oxide, silicon nitride, high-K dielectric material, or a combination of any of the above.

[0097] In addition, the semiconductor device can further include a second channel structure 520 penetrating the stack structure 100 along the first direction, the second channel structure 520 being located in the first region 101 and penetrating the first sub-gate layer 111 or the second sub-gate layer 112 along the first direction. The first channel structure 510 has a storage function, and the second channel structure 520 can serve as a virtual channel structure and play a role of mechanical support and load balancing. The first channel structure 510 and the second channel structure 520 can have the same structure or different structures. In order to simplify the process and reduce the cost, the first channel structure 510 and the second channel structure 520 can be formed in the same process.

[0098] In some embodiments, the semiconductor device can further include a second semiconductor layer 710 located on one side of the stack structure 100, the channel layer 540 of the first channel structure 510 protruding from the stack structure 100 along the first direction, and the second semiconductor layer 710 surrounding the part of the channel layer 540 protruding from the stack structure 100 along the first direction.

[0099] The application also provides a preparation method of a semiconductor device. FIG. 12 A flowchart of a preparation method of a semiconductor device according to an embodiment of the application is shown.

[0100] FIG. 13A to FIG. 38 A process diagram of a preparation method of a semiconductor device according to an embodiment of the application is shown. As shown in the figure, the preparation method 1000 includes: FIG. 12 to FIG. 38

[0101] S100, forming a stack structure 100, the stack structure 100 including a gate layer 110, the gate layer 110 including two first sub-gate layers 111 oppositely arranged along a second direction and a second sub-gate layer 112 located between the two first sub-gate layers 111, the first sub-gate layer 111 extending along a third direction, and the second sub-gate layer 112 extending along the second direction and connected with the two first sub-gate layers 111 respectively;

[0102] S200, forming a connection structure 200 extending into the stack structure 100 along a first direction and connected with the gate layer 110, the first direction, the second direction and the third direction intersecting with each other.

[0103] The following will introduce each step of the preparation method of the semiconductor device in the embodiments of the application.

[0104] Step S100

[0105] ​The stack structure 100 is formed in step S100, and the stack structure 100 includes a gate layer 110. The material of the gate layer 110 can include, but is not limited to, at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, and silicide.

[0106] As an example, the stack structure 100 can be formed by the following way: as shown in FIG. 13A and FIG. 13B , a stack structure 100’ is formed, and the stack structure 100’ includes a first dielectric layer 120; the material of the first dielectric layer 120 can include, but is not limited to, silicon oxynitride or silicon nitride. As shown in FIG. 14A and FIG. 14B , two first gate line gaps 301 and a second gate line gap 401 are formed, the two first gate line gaps 301 are oppositely arranged in a second direction, the second gate line gap 401 is located between the two first gate line gaps 301, the first gate line gap 301 and the second gate line gap 401 both penetrate the stack structure 100’ in a first direction, the first gate line gap 301 extends in a third direction, and the second gate line gap 401 extends in the second direction; as shown in FIG. 36A and FIG. 36B , the first dielectric layer 120 is replaced by the gate layer 110 through the first gate line gap 301 and the second gate line gap 401.

[0107] For example, the first gate line gap 301 includes a plurality of sub-isolation gaps 302 and a spacing gap 303, the plurality of sub-isolation gaps 302 are distributed in the third direction, and the spacing gap 303 is located between adjacent sub-isolation gaps 302 in the third direction. As shown in FIG. 23B , the first dielectric layer 120 can be replaced by a spacing layer 322 through the spacing gap 303; as shown in FIG. 36A and FIG. 36B , the first dielectric layer 120 is replaced by a first sub-gate layer 111 through one of the sub-isolation gaps 302, and the first dielectric layer 120 is replaced by a second sub-gate layer 112 through the second gate line gap 401.

[0108] In some embodiments, the layer stack 100' can be formed by a thin film deposition process, which can be but is not limited to a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a combination of any of the above processes. As an example, the layer stack 100' can be formed on one side of the substrate 700, which includes first dielectric layers 120 and second dielectric layers 130 alternately stacked along a first direction. The first dielectric layers 120 and the second dielectric layers 130 are different in material, and have a high etching selectivity under the same etching condition, so that the second dielectric layers 130 are hardly removed when at least part of the first dielectric layers 120 are removed subsequently. The layer stack 100' can include, but is not limited to, 64 pairs, 128 pairs, or more than 128 pairs of the first dielectric layers 120 and the second dielectric layers 130. The more the number of layers of the first dielectric layers 120 and the second dielectric layers 130, the higher the integration level, and the more the number of memory cells of the final semiconductor device. The number of layers of the first dielectric layers 120 and the second dielectric layers 130 can be designed according to actual requirements, which is not limited in the present application. The first dielectric layers 120 can act as sacrificial layers, and at least part of the first dielectric layers 120 can be replaced by gate layers 110 subsequently. The material of the first dielectric layers 120 can include, but is not limited to, silicon oxynitride or silicon nitride, and the material of the second dielectric layers 130 can include, but is not limited to, silicon oxide, silicon oxynitride, or high-K materials such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, etc. For example, the first dielectric layers 120 are silicon nitride layers, and the second dielectric layers 130 are silicon oxide layers. In some embodiments, the layer stack 100' has a first region 101 and two second regions 102, and the first region 101 is located between the two second regions 102 in a third direction. In subsequent processes, channel structures with a storage function can be formed in the second regions 102, and connection structures 200 connected to the gate layers 110 can be formed in the first region 101. The gate layers 110 can be connected to a peripheral circuit through the connection structures 200.

[0109] In addition, the substrate 700 can be a single-layer structure or a multi-layer structure. For example, the material of the substrate 700 can include, but is not limited to, monocrystalline silicon (Si), monocrystalline germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or group III-V compound such as gallium arsenide, etc. In some embodiments, part of the substrate 700 can be formed with a well region doped with an N-type or P-type dopant. The dopant can include at least one of phosphorus (P), arsenic (As), and antimony (Sb).

[0110] It should be noted that the above mainly relates to the preparation method of a single layer stack structure 100', i.e., for the case of a small number of stacked layers of the layer stack structure 100'. With the continuous increase of the storage capacity of semiconductor devices, the number of stacked layers of the layer stack structure 100' also increases accordingly. In the related art, a dual stack technology or a multi-stack technology is usually used to prepare semiconductor devices, i.e., a plurality of sub-layer stack structures can be sequentially stacked along the first direction on one side of the substrate 700 to form the layer stack structure 100'. Each sub-layer stack structure includes a plurality of first dielectric layers 120 and second dielectric layers 130 which are alternately stacked. The number of layers of each sub-layer stack structure can be the same or different. The content and structure involved in the preparation process of the single layer stack structure 100' mentioned above can be completely or partially applicable to the plurality of sub-layer stack structures herein, and therefore the related or similar content will not be described again.

[0111] As FIG. 14AAs shown, after the formation of the layered structure 100', a first channel structure 510 with a storage function can also be formed in the second region 102 of the layered structure 100', the first channel structure 510 penetrating the layered structure 100' along the first direction. For example, the first channel structure 510 can be formed by forming a first channel hole (not shown) penetrating the layered structure 100' along the first direction from the side of the layered structure 100' away from the substrate 700; wherein, in view of the problem of lateral undercutting in wet etching, the first channel hole can be formed by a dry etching process, a combination of dry and wet etching processes, or a patterning process including photolithography, cleaning, and chemical mechanical polishing process. Wherein, the cross-sectional shape of the first channel hole, i.e. the cross-sectional shape of the first channel hole perpendicular to its extension direction, can be but is not limited to circular, elliptical, or polygonal. The functional layer 530 is formed on the inner wall of the first channel hole, specifically, the blocking layer 531 can be formed on the inner wall of the first channel hole to block the outflow of the charges stored in the subsequently formed charge trapping layer 532. Wherein, the material of the blocking layer 531 can be but is not limited to including silicon oxide, silicon nitride, high-K dielectric material, or a combination of any of the above. The charge trapping layer 532 is formed on the side of the blocking layer 531 away from the first channel hole, to store charges. Wherein, the material of the charge trapping layer 532 can be but is not limited to including silicon nitride, silicon oxynitride, silicon, or a combination of any of the above. The tunneling layer 533 is formed on the side of the charge trapping layer 532 away from the blocking layer 531, the functional layer 530 includes the blocking layer 531, the charge trapping layer 532, and the tunneling layer 533. Wherein, the material of the tunneling layer 533 can be but is not limited to including silicon oxide or silicon nitride. The channel layer 540 is formed on the side of the tunneling layer 533 away from the charge trapping layer 532, the channel layer 540 is used to transport the required charges, i.e. electrons or holes. Wherein, the material of the channel layer 540 can be but is not limited to including amorphous silicon, polycrystalline silicon, or single crystal silicon. In some embodiments, the channel layer 540 does not fill the gap formed around the tunneling layer 533, so that after the formation of the channel layer 540, a filling material can also be deposited in the gap formed around the channel layer 540 to form a filling core layer 550. Wherein, the material of the filling core layer 550 can be but is not limited to including silicon oxide, silicon nitride, silicon oxynitride, spin-on glass, carbon-doped oxide, etc. In addition, in order to alleviate the structural stress, at least one air gap can be formed in the filling core layer 550 by controlling the corresponding parameters in the filling process during the formation of the filling core layer 550.

[0112] In some embodiments, after the filling core layer 550 is formed, a channel plug 560 can be formed in contact with the channel layer 540. Specifically, at least part of the filling core layer 550 can be removed from a side of the filling core layer 550 away from the substrate 700 to form a recess exposing the channel layer 540, and the channel plug 560 can be formed in the recess. For example, only part of the filling core layer 550 can be removed to expose part of the sidewall of the channel layer 540 in the recess. Thus, the channel plug 560 formed in the recess later contacts the exposed sidewall of the channel layer 540, and part of the functional layer 530 is located on one side of the channel plug 560 along a first direction, and another part of the functional layer 530 is located on the periphery of the channel plug 560 along a direction intersecting the first direction. For another example, part of the filling core layer 550, part of the channel layer 540, and part of the functional layer 530 can be removed, and the end surface of the remaining filling core layer 550, channel layer 540, and functional layer 530 is exposed in the recess. Thus, the channel plug 560 formed in the recess later contacts the end surface of the channel layer 540. The material of the channel plug 560 and the material of the channel layer 540 can be the same or different. As an example, the material of the channel plug 560 can include, but is not limited to, polysilicon doped with a dopant, and the dopant can include, but is not limited to, N-type dopants such as phosphorus (P), arsenic (As), and / or antimony (Sb).

[0113] To reduce the risk of the part of the second medium layer 130 located in the first region 101 being bent or collapsed when part of the first medium layer 120 is removed, as shown in FIG. 14A and FIG. 14B After the layer stack structure 100' is formed, a second channel hole (not shown) can be formed in the first region 101 of the layer stack structure 100' to penetrate the layer stack structure 100' along the first direction, and a second channel structure 520 can be formed in the second channel hole. The second channel structure 520 can act as a virtual channel structure to provide mechanical support and load balancing. The second channel structure 520 and the first channel structure 510 can have the same structure or different structures. To simplify the process and reduce costs, the second channel structure 520 and the first channel structure 510 have the same structure, and the second channel structure 520 and the first channel structure 510 are formed in the same process.

[0114] In some embodiments, as shown in FIG. 14A and FIG. 14B After the layer stack structure 100' is formed, two first gate line gaps 301 can be formed in the layer stack structure 100' to be oppositely arranged in the second direction, and a second gate line gap 401 can be formed between the two first gate line gaps 301. The first gate line gap 301 and the second gate line gap 401 can be formed in the same process or different processes, and the first gate line gap 301 and the second gate line gap 401 can be formed by etching a groove or hole expansion.

[0115] For example, the first gate line gap 301 can be formed by forming a first trench extending along the third direction in the first region 101 of the layer stack structure 100' from the side of the layer stack structure 100' away from the substrate 700, forming a second trench extending along the third direction in the second region 102 of the layer stack structure 100', and forming a third trench extending along the third direction between the first trench and the second trench, the first trench, the second trench, and the third trench all penetrating the layer stack structure 100' along the first direction, the third trench having a smaller extension along the third direction than the first trench and the second trench, the first trench being the first sub-isolation gap 302-1, the second trench being the second sub-isolation gap 302-2, and the third trench being the interval gap 303, the first gate line gap 301 comprising the first sub-isolation gap 302-1, the second sub-isolation gap 302-2, and the interval gap 303. The first sub-isolation gap 302-1, the second sub-isolation gap 302-2, and the interval gap 303 can be formed in the same process, thereby not only reducing the number of etching times and reducing costs, but also improving overlay accuracy and reducing overlay errors by using the same mask to form the above-mentioned multiple trenches. The sidewall of the first sub-isolation gap 302-1, the second sub-isolation gap 302-2, and the interval gap 303 formed by etching the trench along the first direction generally comprises a plane extending along the third direction.

[0116] In some other embodiments, the first gate line gap 301 can also be formed by forming a plurality of first holes spaced apart in the third direction in the first region 101 of the layer stack structure 100' from the side of the layer stack structure 100' away from the substrate 700, forming a plurality of second holes spaced apart in the third direction in the second region 102 of the layer stack structure 100', and forming a plurality of interval holes (not shown) between adjacent first holes and second holes in the third direction; wherein the first holes, the second holes, and the interval holes all penetrate the layer stack structure 100' along the first direction; at least removing the portion of the layer stack structure 100' between adjacent interval holes, for example, the plurality of interval holes can be connected together by a hole expansion process to form the interval gap 303; at least removing the portion of the layer stack structure 100' between adjacent first holes, for example, the plurality of first holes can be connected together by a hole expansion process to form the first sub-isolation gap 302-1; and at least removing the portion of the layer stack structure 100' between adjacent second holes, for example, the plurality of second holes can be connected together by a hole expansion process to form the second sub-isolation gap 302-2.

[0117] As an example, the first holes, the second holes and / or the spacer holes can be formed in the same process, and the first holes, the second holes and the spacer holes can be formed by, but not limited to, a dry etching process, a combination of dry and wet etching processes or a patterning process including photolithography, cleaning and chemical mechanical polishing process. The embodiments of the present application can not only reduce the etching times and cost by forming the above-mentioned multiple holes in the same process, but also improve the overlay accuracy and reduce the overlay error by forming the multiple holes through the same mask. It should be noted that the first channel holes and the second channel holes can also be formed in the same process with the first holes, the second holes and the spacer holes.

[0118] After the above-mentioned multiple holes are formed, a sacrificial material can be deposited from the side of the layer stack 100’ away from the substrate 700 to form a sacrificial fill layer filling the above-mentioned multiple holes. The material of the sacrificial fill layer can be a material with a high deposition rate to facilitate fast filling of the above-mentioned multiple holes. The sacrificial fill layer can be a single-layer structure or a multi-layer structure. For example, the sacrificial fill layer can include a sacrificial dielectric layer and a sacrificial core, and the sacrificial dielectric layer covers at least the sidewall of the sacrificial core extending in the first direction. The material of the sacrificial core can include, but is not limited to, carbon, spin-on carbon or polysilicon. Under the same etching conditions, the sacrificial fill layer has a high etching selectivity ratio with the first dielectric layer 120 (the second dielectric layer 130). In order to avoid oxidation of the sacrificial fill layer, a third dielectric layer can be formed on the side of the layer stack 100’ away from the substrate 700 after the sacrificial fill layer is formed, and the third dielectric layer covers the sacrificial fill layer.

[0119] For example, the first channel structure 510 is formed by forming a first mask layer on the side of the third dielectric layer away from the stack structure 100', removing part of the third dielectric layer through the patterned first mask layer to expose part of the sacrificial filling layer in the first channel hole, removing the first mask layer, removing part of the sacrificial filling layer in the first channel hole, and forming the first channel structure 510 in the exposed first channel hole. After forming the above channel structure, a second mask layer can be formed on the side of the third dielectric layer away from the stack structure 100', part of the third dielectric layer is removed through the patterned second mask layer to expose part of the sacrificial filling layer in the spacing hole, the second mask layer is removed, part of the sacrificial filling layer in the spacing hole is removed, and the plurality of spacing holes are connected together by a hole expansion process to form the spacing gap 303. Similarly, the first sub-isolation gap 302-1 can be formed by removing part of the sacrificial filling layer in the first hole and connecting the plurality of first holes by a hole expansion process. The second sub-isolation gap 302-2 can be formed by removing part of the sacrificial filling layer in the second hole and connecting the plurality of second holes by a hole expansion process. The sidewalls of the first sub-isolation gap 302-1, the second sub-isolation gap 302-2, and the spacing gap 303 formed by the hole expansion process along the first direction all include convex and / or concave surfaces.

[0120] Similar to the first gate line gap 301, the second gate line gap 401 can also be formed by etching a groove or a hole expansion process. The formation method of the second gate line gap 401 is similar to that of the first gate line gap 301, which will not be described here.

[0121] After forming the first gate line gap 301 and the second gate line gap 401, part of the first dielectric layer 120 in the first region 101 can be replaced by the first sub-gate layer 111 through the first sub-isolation gap 302-1, another part of the first dielectric layer 120 in the first region 101 can be replaced by the second sub-gate layer 112 through the second gate line gap 401, and all of the first dielectric layer 120 in the second region 102 can be replaced by the third sub-gate layer 113 through the second sub-isolation gap 302-2, thereby forming the stack structure 100.

[0122] Specifically, after forming the first sub-isolation gap 302-1, the second sub-isolation gap 302-2, the spacing gap 303, and the second gate line gap 401, as shown in FIG. 4B, the first dielectric layer 120 in the first region 101 is replaced by the first sub-gate layer 111 through the first sub-isolation gap 302-1, the first dielectric layer 120 in the first region 101 is replaced by the second sub-gate layer 112 through the second gate line gap 401, and the first dielectric layer 120 in the second region 102 is replaced by the third sub-gate layer 113 through the second sub-isolation gap 302-2, thereby forming the stack structure 100. FIG. 14A and FIG. 14BAs shown, a sacrificial material can be deposited from the side of the stack structure 100' away from the substrate 700 to form a first sacrificial layer 610 filling the first sub-isolation gap 302-1, the second sub-isolation gap 302-2 and the spacing gap 303, and a second sacrificial layer 620 filling the second gate line gap 401. The material of the first sacrificial layer 610 and the second sacrificial layer 620 can include, but is not limited to, carbon, spin-on carbon or polysilicon. In order to avoid oxidation of the first sacrificial layer 610 and the second sacrificial layer 620, a fourth dielectric layer 140 can be formed on the side of the stack structure 100' away from the substrate 700 after the formation of the first sacrificial layer 610 and the second sacrificial layer 620, and the fourth dielectric layer 140 covers the first sacrificial layer 610 and the second sacrificial layer 620. A third mask layer is formed on the side of the stack structure 100'; as FIG. 20B As shown, at least part of the fourth dielectric layer 140 is removed through the patterned third mask layer to expose part of the first sacrificial layer 610 located in the spacing gap 303; the third mask layer is removed; as FIG. 21B As shown, part of the first sacrificial layer 610 located in the spacing gap 303 is removed to expose part of the first dielectric layer 120 through the spacing gap 303; as FIG. 22B As shown, part of the first dielectric layer 120 is removed to form a first interlayer gap 323; as FIG. 23B As shown, a spacing layer 322 is formed in the first interlayer gap 323, and the spacing layer 322 is arranged in the same layer as the remaining first dielectric layer 120; as FIG. 24B As shown, a third sacrificial layer 630 is formed by filling a sacrificial material in the remaining space in the spacing gap 303; a fourth mask layer is formed on the side of the fourth dielectric layer 140 away from the stack structure 100'; as FIG. 24B As shown, at least part of the fourth dielectric layer 140 is removed through the patterned fourth mask layer to expose part of the first sacrificial layer 610 located in the first sub-isolation gap 302-1 and part of the second sacrificial layer 620 located in the second gate line gap 401; as FIG. 25A and FIG. 25B As shown, part of the first sacrificial layer 610 located in the first sub-isolation gap 302-1 and part of the second sacrificial layer 620 located in the second gate line gap 401 are removed; as FIG. 26A and FIG. 26B As shown, part of the first dielectric layer 120 located in the first region 101 is removed through the first sub-isolation gap 302-1 and the second gate line gap 401 to form a second interlayer gap 114; as FIG. 28A and FIG. 28BAs shown, a fourth sacrificial layer 640 is formed, filling the second interlayer gap 114, the first sub-isolation gap 302-1, and the second gate line gap 401. If a thin-film deposition process is used to form the fourth sacrificial layer 640, then during the deposition of sacrificial material to form the fourth sacrificial layer 640, the sacrificial material will cover the side of the fourth dielectric layer 140 away from the stacked structure 100', thereby... FIG. 29A and FIG. 29B As shown, after the fourth sacrificial layer 640 is formed, the sacrificial material covering the fourth dielectric layer 140 can be removed by a process such as Chemical Mechanical Polishing (CMP). Considering that the surface planarized after CMP may not be sufficiently smooth, it can be... FIG. 30A and FIG. 30B As shown, a thin sacrificial material can be deposited from the side of the fourth dielectric layer 140 facing away from the substrate 700. FIG. 31A and FIG. 31B As shown, to prevent the sacrificial material from being oxidized, a sixth dielectric layer 160 covering the sacrificial material can be formed on the side of the fourth dielectric layer 140 facing away from the substrate 700. A fifth mask layer is formed on the side of the sixth dielectric layer 160 facing away from the substrate 700; as FIG. 32A and FIG. 32B As shown, at least a portion of the sixth dielectric layer 160, the fifth dielectric layer 150, and the fourth dielectric layer 140 are removed by the patterned fifth mask layer, exposing the portion of the first sacrificial layer 610 located within the second sub-isolation gap 302-2; the fifth mask layer is then removed; as shown... FIG. 33A and FIG. 33B As shown, the portion of the first sacrificial layer 610 located within the second sub-isolation gap 302-2 is removed; the entire first dielectric layer 120 located in the second region 102 is removed through the second sub-isolation gap 302-2, forming a third interlayer gap 115 communicating with the second interlayer gap 114; as FIG. 34A and FIG. 34B As shown, at least the sixth dielectric layer 160, the third sacrificial layer 630 and the fourth sacrificial layer 640 are removed to expose the second interlayer gap 114 and the third interlayer gap 115; a gate layer 110 is formed within the gate gap, the gate gap including the second interlayer gap 114 and the third interlayer gap 115.

[0123] As an example, the first dielectric layer 120 can be removed using a wet etching process in the above procedure. The etchant may include, but is not limited to, a phosphoric acid solution. To improve etching selectivity, an etching inhibitor targeting the second dielectric layer 130 can be added to the phosphoric acid solution.

[0124] like FIG. 3As shown, the gate layer 110 formed by the above method includes two first sub-gate layers 111, a second sub-gate layer 112, and two third sub-gate layers 113. The first sub-gate layers 111 and 112 are located in a first region 101, and the third sub-gate layers 113 are located in a second region 102. The first sub-gate layers 111 extend along a third direction, and the second sub-gate layers 112 extend along a second direction. It should be noted that the first sub-gate layers 111, 112, and 113 can be formed in the same process or in different processes. There may not be a clearly detectable interface between the first sub-gate layer 111 and the second sub-gate layer 112, or between the first sub-gate layer 111 and the third sub-gate layer 113. The first sub-gate layer 111 and the third sub-gate layer 113 can be distinguished by the size of the gate layer 110 in the second direction and the remaining first dielectric layer 120. The size of the third sub-gate layer 113 in the second direction is larger than the size of the first sub-gate layer 111 in the second direction. The third sub-gate layer 113 is located on one side of the first dielectric layer 120 in the third direction, while the first dielectric layer 120 is located between the two first sub-gate layers 111 in the second direction. Similarly, the first sub-gate layer 111 and the second sub-gate layer 112 can be distinguished by the extension directions of the first sub-gate layer 111 and the second sub-gate layer 112 and the remaining first dielectric layer 120. The first sub-gate layer 111 extends along a third direction, the second sub-gate layer 112 extends along a second direction, the first dielectric layer 120 is located between the two first sub-gate layers 111 in the second direction, and the first dielectric layer 120 surrounds the second sub-gate layer 112.

[0125] As an example, such as FIG. 38 As shown, the gate layer 110 may include a gate conductive layer 117. The gate layer 110 may be formed within the gate gap by forming the gate conductive layer 117 on the inner wall of the gate gap; wherein the material of the gate conductive layer 117 may include, but is not limited to, at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, and silicide. To reduce the risk of leakage between adjacent gate layers 110, a gate dielectric layer 116 may be formed on the inner wall of the gate gap before forming the gate conductive layer 117; then the gate conductive layer 117 may be formed in the remaining space of the gate gap, i.e., within the gap formed by the gate dielectric layer 116; wherein the material of the gate dielectric layer 116 may include, but is not limited to, high-k dielectric materials such as alumina, hafnium oxide, or tantalum oxide. In addition, in order to improve the adhesion between the gate conductive layer 117 and the gate dielectric layer 116, a gate adhesive layer (not shown) may be formed on the inner wall of the gap formed in the gate dielectric layer 116 before the gate conductive layer 117 is formed. In other words, the gate layer 110 may also include a gate adhesive layer. The material of the gate adhesive layer may include, but is not limited to, at least one of titanium nitride, tantalum nitride, tungsten carbide and metal alloy.

[0126] Step S200

[0127] In step S200, a connection structure 200 is formed, which extends into the stack structure 100 along the first direction and is connected with the gate layer 110. In this way, the connection structure 200 can control the carriers in the channel layer 540 to enter the charge trapping layer 532 or the carriers in the charge trapping layer 532 to return to the channel layer 540 by applying different voltages to the gate layer 110, so as to make the memory cell in a programmed or erased state.

[0128] In some embodiments, the connection structure 200 can be formed by the following way: after the stack structure 100 is formed, a connection hole (not shown) extending into one of the first dielectric layers 120 along the first direction can be formed in the stack structure 100; part of the first dielectric layer 120 is removed through the connection hole to form a fourth interlayer gap (not shown) exposing the gate layer 110, the fourth interlayer gap being in communication with the connection hole; and the connection structure 200 is formed in the fourth interlayer gap and the connection hole. It should be noted that in the case where the gate layer 110 includes a gate dielectric layer 116 and a gate conductive layer 117, after the fourth interlayer gap is formed, part of the gate dielectric layer 116 is exposed through the fourth interlayer gap, so that before the connection structure 200 is formed, part of the gate dielectric layer 116 exposed through the fourth interlayer gap needs to be removed to expose the gate conductive layer 117.

[0129] In some other embodiments, as shown in FIG. 2B, after the stack structure 100’ is formed, a first connection hole 201 extending into one of the first dielectric layers 120 along the first direction can be formed in the stack structure 100’; as shown in FIG. 2C, part of the first dielectric layer 120 is removed through the first connection hole 201 to form a sacrificial gap 203 in communication with the first connection hole 201; as shown in FIG. 2D, a connection sacrificial layer 240 is formed by depositing a sacrificial material in the first connection hole 201 and the sacrificial gap 203; wherein the material of the connection sacrificial layer 240 can include, but is not limited to, carbon, spin-on carbon or polysilicon. Since the sacrificial material also covers the side of the stack structure 100’ away from the substrate 700 during the process of depositing the sacrificial material, as shown in FIG. 2E and FIG. 2F, after the connection sacrificial layer 240 is formed, the sacrificial material covering the surface of the stack structure 100’ can be removed by a chemical mechanical polishing (CMP) process. In addition, as shown in FIG. 2G and FIG. 2H, the connection structure 200 can be formed by removing the connection sacrificial layer 240 through the first connection hole 201. FIG. 15A FIG. 16A FIG. 17A FIG. 18A FIG. 18B FIG. 19A FIG. 19B ​​​​​​As shown, to prevent the connection sacrificial layer 240 from being oxidized, a fifth dielectric layer 150 covering the connection sacrificial layer 240 can be formed on one side of the stacked structure 100. Based on this, as FIG. 37A As shown, after the stacked structure 100 is formed, the connection structure 200 can be formed in the following manner: the connection sacrificial layer 240 is removed to form a second connection hole 202 that exposes the gate layer 110; and the connection structure 200 is formed in the second connection hole 202.

[0130] It should be noted that, as FIG. 16A As shown, to reduce the risk of other first dielectric layers 120 exposed in the first interconnect 201 being etched during the formation of the sacrificial gap 203, a second isolation layer 230 can be formed on the sidewall extending along the first direction of the first interconnect 201 after the formation of the first interconnect 201 and before the formation of the sacrificial gap 203. The second isolation layer 230 is made of a different material than the first dielectric layer 120, and the material of the second isolation layer 230 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, and organosilicon glass. Furthermore, to increase the contact area between the subsequently formed interconnect structure 200 and the gate layer 110, after removing a portion of the first dielectric layer 120 located in the first region 101 through the first sub-isolation gap 302-1 and the second gate line gap 401 to form the second interlayer gap 114, as shown... FIG. 26A and FIG. 27A As shown, the portion of the connecting sacrificial layer 240 exposed within the second interlayer gap 114 can also be removed.

[0131] like FIG. 38As shown, in the case where the gate layer 110 includes the gate conductive layer 117 and the gate dielectric layer 116, after the removal of the connection sacrificial layer 240, the part of the gate dielectric layer 116 exposed through the second connection hole 202 is removed through the second connection hole 202 to expose the gate conductive layer 117 before forming the connection structure 200. Generally, the first dielectric layer 120 and the gate dielectric layer 116 have a small etching selectivity under the same etching condition, in other words, the etching rate of the first dielectric layer 120 and the gate dielectric layer 116 is not much different, while the connection sacrificial layer 240 and the gate dielectric layer 116 have a high etching selectivity, in other words, the etching rate of the connection sacrificial layer 240 and the gate dielectric layer 116 is greatly different. Therefore, by forming the connection sacrificial layer 240 in the stacked structure 100' before replacing the gate, the present embodiment can reduce the risk of over-etching when removing part of the first dielectric layer 120, i.e., forming the sacrificial gap 203 (the fourth interlayer gap), due to the relatively large etching amount, so that the part of the gate dielectric layer 116 between the gate conductive layer 117 and the second dielectric layer 130 is also etched, causing part of the gate conductive layer 117 to be suspended. Since the connection sacrificial layer 240 and the gate dielectric layer 116 have a large etching selectivity under the same etching condition, after replacing the gate, the loss of the gate dielectric layer 116 is very small when removing the connection sacrificial layer 240, in other words, the gate dielectric layer 116 is almost completely retained, so that only the part of the gate dielectric layer 116 in contact with the connection sacrificial layer 240 needs to be removed subsequently, i.e., only the part of the gate dielectric layer 116 in the second direction located towards the second connection hole 202 of the gate conductive layer 117 needs to be removed. By controlling the etching conditions such as etching time, concentration of etchant, etc., the etching amount can be relatively accurately controlled, thereby reducing the risk of the part of the gate dielectric layer 116 between the gate conductive layer 117 and the second dielectric layer 130 being etched, causing part of the gate conductive layer 117 to be suspended.

[0132] As an example, as FIG. 38As shown, the connection structure 200 can include a second isolation layer 230, a second adhesive layer 220 and a conductive layer 210. Taking the second connection hole 202 as an example, the second connection hole 202 includes a connection interlayer gap arranged in the same layer as the gate layer 110 and a sub-connection hole in communication with the connection interlayer gap, after the second connection hole 202 is formed, an adhesive material can be deposited in the second connection hole 202 to form the second adhesive layer 220 which fills the connection interlayer gap and covers the sidewall of the sub-connection hole extending in the first direction, and the second adhesive layer 220 is in contact with the gate conductive layer 117; wherein the material of the second adhesive layer 220 can include, but is not limited to, at least one of titanium nitride, tantalum nitride, tungsten carbide and metal alloy; the conductive layer 210 is formed on the side of the second adhesive layer 220 away from the inner wall of the sub-connection hole; wherein the material of the conductive layer 210 can include, but is not limited to, at least one of tungsten, cobalt, copper, aluminum, doped polysilicon and silicide. Since the conductive layer 210 is surrounded by the second adhesive layer 220 in the embodiments of the present application, the second adhesive layer 220 can separate the conductive layer 210 from the second dielectric layer 130, thereby reducing the risk of damaging the second dielectric layer 130 due to contact between the conductive layer 210 and the second dielectric layer 130.

[0133] In some other embodiments, if the conductive layer 210 does not fill the remaining space of the sub-connection hole, a connection filling layer (not shown) can be formed in the remaining space of the sub-connection hole, in other words, the connection filling layer can be formed on the side of the conductive layer 210 away from the second adhesive layer 220; wherein the material of the connection filling layer can include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide and organosilicate glass.

[0134] In some embodiments, after the gate layer 110 is formed, the preparation method can further include: forming a first gate line isolation structure 300, that is, forming a sub-isolation structure 310 in the sub-isolation gap 302 and forming a spacing column 321 in the spacing gap 303; wherein the first gate line isolation structure 300 includes the sub-isolation structure 310 and the spacing structure 320, and the spacing structure 320 includes the spacing column 321 and the spacing layer 322; and forming a second gate line isolation structure 400 in the second gate line gap 401. Wherein the sub-isolation structure 310, the spacing column 321 and the second gate line isolation structure 400 can be formed in the same process or in different processes. In addition, the sub-isolation structure 310, the spacing column 321 and the second gate line isolation structure 400 can be a single-layer structure or a multi-layer structure. Taking the second gate line isolation structure 400 as an example, a dielectric material can be deposited in the second gate line gap 401 to form the second gate line isolation structure 400 which fills the second gate line gap 401. Wherein the material of the second gate line isolation structure 400 can include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride and organosilicate glass. For example, as shown in FIG. 4, the second gate line isolation structure 400 can include a second sub-isolation layer 410 and a second spacing layer 420; wherein the material of the second sub-isolation layer 410 can include, but is not limited to, at least one of silicon oxide, silicon nitride and silicon oxynitride; and the material of the second spacing layer 420 can include, but is not limited to, at least one of organosilicate glass. FIG. 35BAs shown, the second gate line isolation structure 400 is a multi-layer structure, and the second gate line isolation structure 400 includes a first isolation layer 313, a first adhesive layer 312, and a first semiconductor layer 311. When forming the second gate line isolation structure 400, the first isolation layer 313 can be formed on the inner wall of the second gate line gap 401; wherein the material of the first isolation layer 313 can include, but is not limited to, at least one of silicon nitride, silicon nitride, silicon oxynitride, and organosilicate glass; the first adhesive layer 312 is formed on the side of the first isolation layer 313 away from the inner wall of the second gate line gap 401; wherein the material of the first adhesive layer 312 can include, but is not limited to, at least one of titanium nitride, tantalum nitride, tungsten carbide, and metal alloy; and the first semiconductor layer 311 is formed on the side of the first adhesive layer 312 away from the first isolation layer 313; wherein the material of the first semiconductor layer 311 can include, but is not limited to, a semiconductor material such as polysilicon.

[0135] In some embodiments, the preparation method can further include: removing the substrate 700 to expose a portion of the first channel structure 510; removing the functional layer 530 of the first channel structure 510 exposed portion to expose a portion of the channel layer 540 of the first channel structure 510; and forming a second semiconductor layer 710 covering the exposed channel layer 540.

[0136] The embodiments of the present application also provide a three-dimensional memory including a peripheral circuit and the semiconductor device described above, and the peripheral circuit is bonded to the semiconductor device. The peripheral circuit can include, but is not limited to, at least one of a high-voltage device, a low-voltage device, and an ultra-low-voltage device. The high-voltage device can include, but is not limited to, at least one of a row decoder, a column decoder, a word line driver, and a bit line driver. The low-voltage device can include, but is not limited to, a page buffer or a logic device. The ultra-low-voltage device can include, but is not limited to, an I / O circuit.

[0137] In addition, the embodiments of the present application also provide a storage system including a controller and the semiconductor device described above, and the controller is coupled to the semiconductor device and used to control the semiconductor device to store data.

[0138] FIG. 39 A block diagram of a system having a semiconductor device according to one embodiment of the present application is shown. The system 800 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle-mounted computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device located therein. As shown, the system 800 includes a processor 810, a memory 820, and a bus 830. The processor 810 can be a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), or any other suitable processor. The memory 820 can include the semiconductor device described above. The bus 830 can be a hardware bus, a software bus, or a combination thereof. The system 800 can further include an input device 840 and an output device 850. The input device 840 can be a keyboard, a mouse, a microphone, a camera, or any other suitable input device. The output device 850 can be a display, a speaker, or any other suitable output device. FIG. 39As shown in the middle, the system 800 can include a host 804 and a memory system 801 having one or more semiconductor devices 802 and a memory controller 803. The host 804 can be a processor of an electronic device, such as a central processing unit (CPU), or can be a system on chip (SoC), such as an application processor (AP). The host 804 can be configured to send or receive data to or from the semiconductor device 802.

[0139] The semiconductor device 802 can be any semiconductor device disclosed in the present application, such as FIG. 3 to FIG. 10 The semiconductor device 802 can be any semiconductor device disclosed in the present application, such as

[0140] In some embodiments, the memory controller 803 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 803 is designed to operate in a high duty cycle environment, such as an SSD or embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays. The memory controller 803 can be configured to control operations of the semiconductor device 802, such as read, erase, and program operations. The memory controller 803 can also be configured to manage various functions related to data stored in or to be stored into the semiconductor device 802, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 803 is further configured to process error correction codes (ECCs) related to data read from or written to the semiconductor device 802. Any other appropriate functions, for example, formatting the semiconductor device 802, can also be performed by the memory controller 803. The memory controller 803 can communicate with external devices (e.g., the host 804) according to a specific communication protocol. For example, the memory controller 803 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a firewire protocol, etc.

[0141] The memory controller 803 and the one or more semiconductor devices 802 can be integrated into various types of memory devices, e.g., contained within the same package, such as a Universal Flash Storage (UFS) package or an eMMC package. That is, the memory system 801 can be implemented and packaged into different types of final electronic products. In one example as shown in FIG. 8A, the memory controller 803 and the single semiconductor device 802 can be integrated into a memory card 810. The memory card 810 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 810 can further include a memory card connector 811 that couples the memory card 810 with a host (e.g., the host 804 in FIG. 8B). In another example as shown in FIG. 8B, the memory controller 803 and the multiple semiconductor devices 802 can be integrated into a solid state drive (SSD) 820. The SSD 820 can further include an SSD connector 821 that couples the SSD 820 with a host (e.g., the host 804 in FIG. 8B). In some embodiments, the storage capacity and / or operating speed of the SSD 820 is higher than that of the memory card 810. FIG. 40 FIG. 39 FIG. 41 FIG. 39

[0142] It should be understood that the various forms of flow shown above can be re-ordered, added to, or have steps deleted, as examples, the steps recited in the present disclosure can be performed in parallel, in series, or in a different order, as long as the desired results of the present disclosure are achieved, which are not limited herein.

[0143] The specific embodiments have been shown and described for purposes of illustrating the applications disclosed herein, and not for purposes of limiting the same. It will be understood by those skilled in the art that various modifications, combinations, sub-combinations, and alternatives can be made to the specific embodiments without departing from the spirit and principles of the disclosure. Any modifications, equivalent substitutions, improvements, and the like which are within the spirit and principles of the disclosure are intended to be included in the disclosure.​​​​

Claims

1. A semiconductor device, comprising: A stacked structure, including a gate layer; and A connection structure extends along a first direction into the stacked structure and is connected to the gate layer; The gate layer includes two first sub-gate layers disposed opposite each other in a second direction and a second sub-gate layer located between the two first sub-gate layers. The first sub-gate layers extend along a third direction, and the second sub-gate layer extends along the second direction and is connected to the two first sub-gate layers respectively. The first direction, the second direction and the third direction intersect each other.

2. The semiconductor device according to claim 1, wherein, A plurality of second sub-gate layers are disposed between the two first sub-gate layers and spaced apart on the third side.

3. The semiconductor device according to claim 2, wherein, Multiple second sub-gate layers are evenly spaced in the third direction.

4. The semiconductor device according to claim 1, wherein, The dimension of the second sub-gate layer along the third direction is less than or equal to 4 μm.

5. The semiconductor device according to claim 1, wherein, The connection structure is located between the two first sub-gate layers in the second direction and is connected to one of the first sub-gate layers.

6. The semiconductor device according to claim 5, wherein, The portion of the first sub-gate layer that contacts the connection structure has a first dimension in the second direction, and the portion of the first sub-gate layer located on one side of the connection structure along the third direction has a second dimension in the second direction, wherein the first dimension is larger than the second dimension.

7. The semiconductor device according to claim 1, wherein, The gate layer further includes two third sub-gate layers, wherein the first sub-gate layer is located between the two third sub-gate layers along the third direction, and the third sub-gate layer extends along the third direction and is connected to the two first sub-gate layers.

8. The semiconductor device according to claim 1, wherein, The stacked structure further includes: A first dielectric layer is disposed on the same layer as the gate layer, and the connection structure penetrates the first dielectric layer along the first direction; The first dielectric layer includes a plurality of sub-dielectric layers, which are alternately distributed with the second sub-gate layer along the third direction, and the second sub-gate layer is provided with the sub-dielectric layer on both sides along the third direction.

9. The semiconductor device according to claim 8, wherein, The stacked structure has a first region and two second regions, the first region being located between the two second regions along the third direction, and the first sub-gate layer, the second sub-gate layer and the sub-dielectric layer being located in the first region; The gate layer further includes a third sub-gate layer located in the second region, and the stacked structure further includes a second dielectric layer that is alternately stacked with the gate layer and the first dielectric layer along the first direction. The second dielectric layer extends in the first region and the second region along the third direction, and the connection structure is located in the first region and extends along the first direction.

10. The semiconductor device according to any one of claims 1 to 9, wherein, The semiconductor device further includes: A first gate isolation structure extends through the stacked structure along the first direction and is located along the second direction on the side of the first sub-gate layer away from the second sub-gate layer; and A second gate line isolation structure extends through the stacked structure along the first direction, and a second sub-gate layer surrounds the second gate line isolation structure.

11. The semiconductor device according to claim 10, wherein, The first gate isolation structure includes: Multiple sub-isolation structures are spaced apart along the third direction; and The spacing structure is located between adjacent sub-spacing structures along the third direction.

12. The semiconductor device according to claim 11, wherein, The spacing structure includes: Spacer posts, penetrating the stacked structure along the first direction; and A spacer layer is disposed in the same layer as the gate layer and surrounds the spacer pillar.

13. The semiconductor device according to claim 11, wherein, The sub-isolation structure and / or the second gate isolation structure includes: A first semiconductor layer extends through the stacked structure along the first direction; A first adhesive layer, at least located on the sidewall of the first semiconductor layer extending along the first direction; and The first isolation layer is located on the side of the first adhesive layer opposite to the first semiconductor layer.

14. The semiconductor device according to claim 10, wherein, The sidewalls of the first gate isolation structure and / or the second gate isolation structure extending along the first direction include convex and / or concave surfaces.

15. The semiconductor device according to any one of claims 1 to 9, wherein, The connection structure includes: A conductive layer extending along the first direction; A second adhesive layer, a portion of which is located on the sidewall of the conductive layer extending along the first direction, and another portion located on one side of the conductive layer along the first direction and extending to the gate layer along the second direction; and The second isolation layer is located on the side of the second adhesive layer opposite to the conductive layer, along a direction intersecting the first direction.

16. A method for fabricating a semiconductor device, comprising: A stacked structure is formed, the stacked structure including a gate layer; and A connection structure is formed, the connection structure extending along a first direction into the stacked structure and connecting to the gate layer; The gate layer includes two first sub-gate layers disposed opposite each other along a second direction and a second sub-gate layer located between the two first sub-gate layers. The first sub-gate layers extend along a third direction, and the second sub-gate layer extends along the second direction and is connected to the two first sub-gate layers respectively. The first direction, the second direction and the third direction intersect each other.

17. The method for fabricating a semiconductor device according to claim 16, wherein, The formation of the stacked structure includes: A layered structure is formed, the layered structure including a first dielectric layer; Two first gate line slots are formed, which are arranged opposite to each other along the second direction, and a second gate line slot is located between the two first gate line slots. Both the first gate line slot and the second gate line slot penetrate the stacked structure along the first direction; and The first dielectric layer is partially replaced with the gate layer through the first gate line gap and the second gate line gap.

18. The method for fabricating a semiconductor device according to claim 17, wherein, The first grid line gap includes a plurality of sub-isolation gaps spaced apart along the third direction, and a gap located between adjacent sub-isolation gaps along the third direction; The process of replacing a portion of the first dielectric layer with the gate layer through the first gate line gap and the second gate line gap includes: The first dielectric layer is partially replaced with a spacer layer through the gap; A portion of the first dielectric layer is replaced with the first sub-gate layer through one of the sub-isolation gaps, and a portion of the first dielectric layer is replaced with the second sub-gate layer through the second gate line gap.

19. The method for fabricating a semiconductor device according to claim 18, wherein, Replacing a portion of the first dielectric layer with the first sub-gate layer includes: The first dielectric layer is partially replaced with the first sub-gate layer through the first sub-isolation gap; The method of replacing part of the first dielectric layer with the gate layer through the first gate line gap and the second gate line gap further includes: A portion of the first dielectric layer is replaced by a third sub-gate layer through a second sub-isolation gap. The third sub-gate layer extends along the third direction and is respectively connected to the two first sub-gate layers. The gate layer further includes the third sub-gate layer, and the plurality of sub-isolation gaps include the first sub-isolation gap and two second sub-isolation gaps located along the third direction and respectively on both sides of the first sub-isolation gap.

20. The method for fabricating a semiconductor device according to claim 18, wherein, Replacing a portion of the first dielectric layer with a spacer layer through the spacer gap includes: A first sacrificial layer is formed to fill the gaps in the first gate lines, and a second sacrificial layer is formed to fill the gaps in the second gate lines; Remove the portion of the first sacrificial layer located in the gap, exposing a portion of the first dielectric layer; Remove the exposed first dielectric layer to form a first interlayer gap; and The spacer layer is formed within the first interlayer gap.

21. The method for fabricating a semiconductor device according to claim 17, wherein, The preparation method further includes: A first connection hole extending along the first direction to the first dielectric layer is formed in the stacked structure; A portion of the first dielectric layer is removed through the first connection hole to form a sacrificial gap communicating with the first connection hole; A sacrificial material is deposited within the first connecting hole and the sacrificial gap to form a connecting sacrificial layer; The connection structure includes: Remove the connection sacrificial layer to form a second connection via that exposes the first sub-gate layer; The connection structure is formed within the second connection hole.

22. A storage system, characterized in that, The storage system includes a controller and a semiconductor device according to any one of claims 1 to 15, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

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