Semiconductor device

Abstract

The invention discloses a semiconductor device. The semiconductor device has a first region. The semiconductor device includes: a substrate; the epitaxial layer is arranged on one side, in the first direction, of the substrate, a groove is formed in the side, away from the substrate, of the epitaxial layer, the groove comprises a first groove located in the first area, the first groove extends in the second direction, and the first direction intersects with the second direction; the resistor structure is arranged in the first groove; the insulating layer is arranged on the side, away from the substrate, of the epitaxial layer; the gate structure is arranged on the side, away from the substrate, of the insulating layer, the gate structure comprises a gate binding structure and a gate wire, the gate wire comprises a first segment located in the first area, the gate binding structure is located in the first area and is spaced from the first segment in the second direction, the insulating layer is provided with a first via hole and a second via hole, and the first via hole is communicated with the second via hole. The grid binding structure is connected with the resistor structure in the first groove through the first via hole, and the first segment is connected with the resistor structure in the first groove through the second via hole.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device. Background Technology

[0002] Semiconductor devices are electronic devices whose conductivity lies between that of a good conductor and an insulator. They utilize the unique electrical properties of semiconductor materials to perform specific functions and are the core of modern electronic technology, with broad application prospects in electronic circuits. However, in semiconductor devices, including JFETs (Junction Field Effect Transistors), gate leakage is prone to occur, which can easily lead to gate drive signal drift and noise, thus hindering the improvement of semiconductor device performance. Summary of the Invention

[0003] This application provides a semiconductor device, which aims to improve the operating performance of the semiconductor device.

[0004] This application provides a semiconductor device having a first region. The semiconductor device includes: a substrate; an epitaxial layer disposed on one side of the substrate in a first direction, with a trench formed on the side of the epitaxial layer away from the substrate, the trench including a first trench located in the first region, the first trench extending along a second direction, the first direction intersecting the second direction; a resistor structure disposed in the first trench; an insulating layer disposed on the side of the epitaxial layer away from the substrate; and a gate structure disposed on the side of the insulating layer away from the substrate, the gate structure including a gate bonding structure and a gate trace, the gate trace including a first segment located in the first region, the gate bonding structure being located in the first region and spaced apart from the first segment in the second direction. The insulating layer has a first via and a second via. The gate bonding structure is connected to the resistor structure in the first trench through the first via, and the first segment is connected to the resistor structure in the first trench through the second via. The orthographic projection of the resistor structure of a single first trench on the substrate overlaps with the orthographic projection of the gate bonding structure and the first segment on the substrate. At least one first via and at least one second via are located on the side of the same resistor structure away from the substrate.

[0005] According to the foregoing embodiments of this application, the trench further includes a second trench located in the first region. The second trench extends along a second direction. The first trench and the second trench are arranged at intervals in a third direction. The first direction, the second direction, and the third direction intersect each other. The semiconductor device further includes a conductive structure and a dielectric structure. The conductive structure is disposed in the second trench. The orthographic projection of the conductive structure in a single second trench onto the substrate overlaps with the orthographic projection of the gate bonding structure and the first segment onto the substrate. The dielectric structure is at least partially disposed in the second trench and between the conductive structure and the epitaxial layer. The epitaxial layer includes a first well region located in the first region and at least adjacent to the second trench. The insulating layer has a third via and a fourth via. The gate bonding structure is connected to the conductive structure in the second trench through the third via. The first segment is connected to the first well region through the fourth via.

[0006] According to any of the foregoing embodiments of this application, the minimum distance between the orthographic projection of the first via on the substrate and the orthographic projection of the first segment on the substrate is the first distance, and the minimum distance between the orthographic projection of the third via on the substrate and the orthographic projection of the first segment on the substrate is the second distance, wherein the first distance is greater than the second distance.

[0007] According to any of the foregoing embodiments of this application, the size of the first via in the second direction is smaller than the size of the third via in the second direction.

[0008] According to any of the foregoing embodiments of this application, there are multiple fourth vias, and the multiple fourth vias are spaced apart in a third direction, with the orthogonal projection of the conductive structure on the substrate located between the orthogonal projections of adjacent fourth vias on the substrate.

[0009] According to any of the foregoing embodiments of this application, there are multiple second grooves, which are respectively disposed on both sides of the first groove in the third direction.

[0010] According to any of the foregoing embodiments of this application, the semiconductor device further includes a second region. The semiconductor device further includes a semiconductor structure disposed on the side of the insulating layer near the substrate, a drain metal disposed on the side of the substrate away from the epitaxial layer, and a source metal disposed on the side of the insulating layer away from the substrate. The gate trace includes a second segment electrically connected to the first segment and located in the second region. The epitaxial layer includes an epitaxial region, a second well region, a channel region, and a source region. The source metal, the semiconductor structure, the second well region, the channel region, and the source region are all located in the second region. The second well region is located on the side of the epitaxial region away from the substrate. The source region is at least partially located on the side of the second well region away from the substrate. The channel region is connected to the source region and located on the side of the second well region near the semiconductor structure. The insulating layer also has a first functional opening and a second functional opening located in the second region. The source metal is connected to the source region through the first functional opening, and the second segment is connected to the semiconductor structure through the second functional opening.

[0011] According to any of the foregoing embodiments of this application, the second region includes a first sub-region and a second sub-region, the second sub-region is located on at least one side of the first sub-region in a second direction, the second segment is located within the second sub-region, and the source metal is located within the first sub-region and is spaced apart from the second segment.

[0012] According to any of the foregoing embodiments of this application, the source metal has a clearance opening on the third-side upward side, and the gate bonding structure and the first segment are at least partially located within the clearance opening.

[0013] According to any of the foregoing embodiments of this application, the semiconductor device further has a third region, which is located on the same side of the second region in a third direction as the first region. The gate trace also includes a third segment located within the third region, and the first segment and the second segment are electrically connected through the third segment.

[0014] The semiconductor device provided in this application embodiment has a first region, and the semiconductor device in the first region can be used to receive a gate drive signal. The semiconductor device includes a substrate, an epitaxial layer, an insulating layer, and a gate structure. The epitaxial layer is disposed on one side of the substrate in a first direction, and a trench is formed on the side of the epitaxial layer away from the substrate. The trench includes a first trench located in the first region, and the first trench extends along a second direction, that is, the first trench can have a large extension dimension in the second direction. A resistor structure is disposed in the first trench, and the resistor structure can have a certain resistance. The insulating layer is disposed on the side of the epitaxial layer away from the substrate, and the insulating layer can protect the underlying film layer.

[0015] The gate structure is disposed on the side of the insulating layer away from the substrate. The gate structure includes a gate bonding structure and a gate trace. The gate bonding structure can be used to receive gate drive signals, and the gate trace can be used to transmit gate drive signals, so as to realize the control of the turn-on and turn-off of the semiconductor device.

[0016] The gate trace includes a first segment located in a first region. The gate bonding structure is located in the first region and spaced apart from the first segment in a second direction, such that there is no direct electrical connection between the first segment in the first region and the gate bonding structure. Even when the gate bonding structure receives a gate drive signal, the gate drive signal will not be directly transmitted from the gate bonding structure to the first segment.

[0017] The insulating layer has a first via and a second via. The gate bonding structure is connected to the resistive structure in the first trench through the first via, and the first segment is connected to the resistive structure in the first trench through the second via. By setting the orthogonal projection of the resistive structure of a single first trench on the substrate to overlap with the orthogonal projections of the gate bonding structure and the first segment on the substrate, and by setting at least one first via and at least one second via located on the side of the same resistive structure away from the substrate, the gate bonding structure can be electrically connected to the first segment through the resistive structure. The setting of the resistive structure is beneficial to improving the input impedance of the semiconductor device and also beneficial to reducing the driving capability requirements of the driving circuit used to provide the gate drive signal, which can effectively reduce the gate leakage current, thereby improving the operating performance of the semiconductor device. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application; Figure 2 This is a partial cross-sectional view of a semiconductor device provided in an embodiment of this application; Figure 3 This is a partial cross-sectional view of a semiconductor device provided in another embodiment of this application; Figure 4 This is an equivalent circuit diagram of a semiconductor device provided in an embodiment of this application; Figure 5 This is a schematic diagram of a gate structure, source metal, and terminal provided in an embodiment of this application; Figure 6 This is a partially enlarged schematic diagram of a semiconductor device provided in an embodiment of this application; Figure 7 This is a partial cross-sectional view of a semiconductor device provided in another embodiment of this application; Figure 8 This is a partial cross-sectional view of a semiconductor device provided in another embodiment of this application; Figure 9 This is a partial cross-sectional view of a semiconductor device provided in another embodiment of this application; Figure 10 This is a partial cross-sectional view of a semiconductor device provided in another embodiment of this application; Figure 11This is a parameter simulation diagram of an RC network circuit provided in an embodiment of this application; Figure 12 This is a parameter simulation diagram of an RC network circuit provided in another embodiment of this application.

[0020] Explanation of reference numerals in the attached figures: 10. Semiconductor devices; 100. Drain metal; 200. Substrate; 300, Epitaxial layer; 301, Trench; 301a, First trench; 301b, Second trench; 301c, Third trench; 310, Epitaxial region; 320, First well region; 321, Fourth functional trench; 330, Second well region; 340, Source region; 350, Channel region; 360, Channel conditioning region; 400. Medium structure; 500, Insulating layer; 501, First via; 502, Second via; 503, Third via; 504, Fourth via; 505, First functional opening; 506, Second functional opening; 510, Passivation protective layer; 520, Isolation layer; 600. Semiconductor structure; 700. Gate structure; 710. Gate bonding structure; 720. Gate trace; 721. First segment; 722. Second segment; 723. Third segment; 800, source metal; 801, clearance opening; 900, Terminal; S1, resistive structure; S1a, first functional slot; S1b, second functional slot; S1c, third functional slot; S2, conductive structure; R, resistive element; C, capacitive element; G1, first spacing; G2, second spacing; A1, First Region; A2, Second Region; A21, First Sub-region; A22, Second Sub-region; A3, Third Region; A4, Fourth Region; D1, First Direction; D2, Second Direction; D3, Third Direction. Detailed Implementation

[0021] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are intended only to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples. In the drawings and the following description, at least some well-known structures and technologies are not shown in order to avoid causing unnecessary ambiguity to this application; and, for clarity, the dimensions of some structures may be exaggerated. Furthermore, the features, structures, or characteristics described below can be combined in any suitable manner in one or more embodiments.

[0022] It should be noted that, unless otherwise stated, "a plurality of" in this document means two or more; the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0023] The directional terms appearing in the following description refer to the directions shown in the figures and are not intended to limit the specific structure of the embodiments of this application. It should also be noted in the description of this application that, unless otherwise explicitly specified and limited, the terms "installation" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0024] Semiconductor devices are electronic devices whose conductivity lies between that of a good conductor and an insulator. They utilize the unique electrical properties of semiconductor materials to perform specific functions and are the core of modern electronic technology, with broad application prospects in electronic circuits. However, in semiconductor devices, including JFET devices, gate leakage is prone to occur, which can easily lead to drift and noise in the gate drive signal, hindering the improvement of the device's operational stability.

[0025] When a semiconductor device has a large gate leakage current in the on state, it is also easy to cause the input impedance to be low, which is not conducive to the drive control of the drive circuit used to provide the gate drive signal, and thus not conducive to improving the working performance of the semiconductor device.

[0026] Optionally, gate drive signal drift and noise refer to the deviation of the gate drive signal voltage from the preset value caused by changes in gate leakage current or parasitic parameters in the semiconductor device (i.e., causing a slow drift in the gate potential), resulting in instability or distortion of the gate drive signal and affecting the device's turn-on and turn-off characteristics. Simultaneously, current fluctuations and parasitic capacitance and inductive coupling (such as EMI coupling, or Electromagnetic Interference Coupling, which refers to the process by which electromagnetic interference energy is transferred from the interference source to the affected target through different paths, mainly including conduction coupling, radiation coupling, capacitive coupling, and inductive coupling. For example, when a semiconductor device generates voltage and current transients during high-frequency switching, energy will be coupled between circuits through electromagnetic fields or parasitic parameters, leading to signal distortion or system malfunction) can easily superimpose to form high-frequency noise, easily causing gate drive signal jitter and gate voltage waveform distortion, thereby affecting the switching stability and electromagnetic compatibility performance of the semiconductor device.

[0027] To address the aforementioned problems, this application provides a semiconductor device, and the embodiments of the semiconductor device will be described below with reference to the accompanying drawings.

[0028] Figure 1 This is a schematic diagram of the structure of a semiconductor device 10 provided in an embodiment of this application. Figure 2 This is a partial cross-sectional view of a semiconductor device 10 provided in an embodiment of this application. Figure 3 This is a partial cross-sectional view of a semiconductor device 10 provided in another embodiment of this application. In the figure, direction D1 can represent a first direction D1, direction D2 can represent a second direction D2, and direction D3 can represent a third direction D3. The first direction D1, the second direction D2, and the third direction D3 can intersect each other; for example, the first direction D1, the second direction D2, and the third direction D3 can be perpendicular to each other. Optionally, for ease of illustration, some of the figures in this application (e.g.) Figure 1 And the following Figure 5 and Figure 6 In the diagram, the schematic of the insulating layer 500 is omitted, and only the location of the through hole in the insulating layer 500 is shown.

[0029] Optional, Figure 2 This can be one embodiment. Figure 1 A partial sectional view at position AA in the middle. Figure 3 This can be one embodiment. Figure 1 A partial sectional view at position BB in the middle.

[0030] like Figures 1 to 3 As shown, this application embodiment provides a semiconductor device 10, which has a first region A1. The semiconductor device 10 includes: a substrate 200; an epitaxial layer 300 disposed on one side of the substrate 200 in a first direction D1, wherein a trench 301 is formed on the side of the epitaxial layer 300 away from the substrate 200, the trench 301 including a first trench 301a located in the first region A1, the first trench 301a extending along a second direction D2, the first direction D1 intersecting the second direction D2; a resistor structure S1 disposed in the first trench 301a; an insulating layer 500 disposed on the side of the epitaxial layer 300 away from the substrate 200; and a gate structure 700 disposed on the side of the insulating layer 500 away from the substrate 200, the gate structure 700 including a gate bonding structure 710 and a gate trace 720. The trace 720 includes a first segment 721 located in the first region A1. The gate bonding structure 710 is located in the first region A1 and spaced from the first segment 721 in the second direction D2. The insulating layer 500 has a first via 501 and a second via 502. The gate bonding structure 710 is connected to the resistor structure S1 in the first trench 301a through the first via 501. The first segment 721 is connected to the resistor structure S1 in the first trench 301a through the second via 502. The orthographic projection of the resistor structure S1 of a single first trench 301a on the substrate 200 overlaps with the orthographic projections of the gate bonding structure 710 and the first segment 721 on the substrate 200. At least one first via 501 and at least one second via 502 are located on the side of the same resistor structure S1 away from the substrate 200.

[0031] The semiconductor device 10 provided in this application embodiment can be a power device. Optionally, the semiconductor device 10 provided in this application embodiment can be a silicon carbide (SiC) power device. Silicon carbide power devices can have higher withstand voltage, lower on-resistance, faster switching characteristics, higher operating temperature, better heat dissipation performance, and good radiation resistance.

[0032] As a further example, the semiconductor device 10 provided in the embodiments of this application may include a JFET (Junction Field Effect Transistor) device.

[0033] Optionally, the JFET can be a three-terminal device. Its operating principle involves adjusting the forward and reverse bias states of the PN junction through a gate drive signal to control the conduction and turn-off of the channel in the semiconductor device 10. JFETs offer advantages such as low noise, small size, and high-frequency response. JFETs fabricated based on silicon carbide material further possess high voltage withstand capability and high power density, which is beneficial for the application of the semiconductor device 10 in high-power scenarios such as new energy vehicles and high-voltage power transmission.

[0034] The semiconductor device 10 provided in this embodiment has a first region A1, and the semiconductor device 10 in the first region A1 can be used to receive a gate drive signal. The semiconductor device 10 includes a substrate 200, an epitaxial layer 300, an insulating layer 500, and a gate structure 700. The epitaxial layer 300 is disposed on one side of the substrate 200 in a first direction D1, and a trench 301 is formed on the side of the epitaxial layer 300 away from the substrate 200. The trench 301 includes a first trench 301a located in the first region A1. The first trench 301a extends along a second direction D2, that is, the first trench 301a can have a large extension dimension in the second direction D2.

[0035] For example, the depth direction of the first groove 301a can be a first direction D1, the length direction of the first groove 301a can be a second direction D2, and the width direction of the first groove 301a can be a third direction D3.

[0036] The resistive structure S1 is disposed within the first trench 301a, and the resistive structure S1 may have a certain resistance. The insulating layer 500 is disposed on the side of the epitaxial layer 300 away from the substrate 200, and the insulating layer 500 can protect the underlying film layer.

[0037] Optionally, the material of the resistor structure S1 can be configured in various ways, and the material of the resistor structure S1 can include any material with a suitable resistance value. For example, the material of the resistor structure S1 can include polycrystalline silicon.

[0038] Optionally, the shape of the resistor structure S1 can be approximately the same as or similar to the shape of the first trench 301a, that is, the first trench 301a can be sufficiently filled with the resistor structure S1. For example, the height direction of the resistor structure S1 can be a first direction D1, the length direction of the resistor structure S1 can be a second direction D2, and the width direction of the resistor structure S1 can be a third direction D3.

[0039] Optionally, the dimensions of the resistor structure S1 can be approximately the same as the dimensions of the second trench 301b.

[0040] The gate structure 700 is disposed on the side of the insulating layer 500 away from the substrate 200. The gate structure 700 includes a gate bonding structure 710 and a gate trace 720. The gate bonding structure 710 can be used to receive gate drive signals, and the gate trace 720 can be used to transmit gate drive signals, so as to realize the control of the turn-on and turn-off of the semiconductor device 10.

[0041] For example, the gate bonding structure 710 can be used to electrically connect with the driving circuit via bonding, and the driving circuit can provide a gate drive signal to the semiconductor device 10 through the gate bonding structure 710. The gate trace 720 can be used to transmit the gate drive signal to the JFET device to control the turn-on and turn-off of the semiconductor device 10.

[0042] Optionally, the gate bonding structure 710 and the gate trace 720 can be set in the same layer and with the same material, so that the gate bonding structure 710 and the gate trace 720 can be fabricated simultaneously during the fabrication of the semiconductor structure 600, which is beneficial to improving the fabrication efficiency of the semiconductor structure 600.

[0043] The gate trace 720 includes a first segment 721 located in the first region A1. The gate bonding structure 710 is located in the first region A1 and is spaced apart from the first segment 721 in the second direction D2, so that there is no direct electrical connection between the first segment 721 in the first region A1 and the gate bonding structure 710. Even when the gate bonding structure 710 receives a gate drive signal, the gate drive signal will not be directly transmitted from the gate bonding structure 710 to the first segment 721.

[0044] Optionally, the gate bonding structure 710 is located in the first region A1 and spaced apart from the first segment 721 in the second direction D2. This can mean that the gate bonding structure 710 is located in the first region A1, the first segment 721 is spaced apart from the gate bonding structure 710, and the first segment 721 is located on at least one side of the gate bonding structure 710 in the second direction D2.

[0045] For example, there may be two first segments 721. The two first segments 721 may be disposed on both sides of the gate bonding structure 710 in the second direction D2, so that the gate trace 720 can transmit the gate drive signal from both sides of the second direction D2 to other structures in the semiconductor device 10, which is beneficial to improving the transmission efficiency and transmission effect of the gate drive signal in the semiconductor device 10.

[0046] Optionally, the size of the gate bonding structure 710 in the second direction D2 can be larger than the size of the first segment 721 in the second direction D2, so that the gate bonding structure 710 can have a larger size, which is beneficial to the bonding of the gate bonding structure 710.

[0047] The insulating layer 500 has a first via 501 and a second via 502. The gate bonding structure 710 is connected to the resistor structure S1 in the first trench 301a through the first via 501, and the first segment 721 is connected to the resistor structure S1 in the first trench 301a through the second via 502.

[0048] Optionally, the orthogonal projection of the first via 501 on the substrate 200 may lie within the orthogonal projection of the gate bonding structure 710 on the substrate 200, and the orthogonal projection of the first via 501 on the substrate 200 may lie within the orthogonal projection of the resistor structure S1 on the substrate 200. This facilitates the connection of the gate bonding structure 710 to the resistor structure S1 in the first trench 301a through the first via 501. The orthogonal projection of the second via 502 on the substrate 200 may lie within the orthogonal projection of the first segment 721 on the substrate 200, and the orthogonal projection of the second via 502 on the substrate 200 may lie within the orthogonal projection of the resistor structure S1 on the substrate 200. This facilitates the connection of the first segment 721 to the resistor structure S1 in the first trench 301a through the second via 502.

[0049] Optionally, a first functional slot S1a communicating with the first via 501 and a second functional slot S1b communicating with the second via 502 may be provided on the side of the resistor structure S1 away from the substrate 200. The provision of the first functional slot S1a is beneficial to increasing the connection area between the gate bonding structure 710 and the resistor structure S1, and the provision of the second functional slot S1b is beneficial to increasing the connection area between the first segment 721 and the resistor structure S1.

[0050] Optionally, the orthogonal projection of the first functional slot S1a on the substrate 200 may lie within the orthogonal projection of the gate bonding structure 710 on the substrate 200, and the orthogonal projection of the first functional slot S1a on the substrate 200 may lie within the orthogonal projection of the resistor structure S1 on the substrate 200. The orthogonal projection of the second functional slot S1b on the substrate 200 may lie within the orthogonal projection of the first segment 721 on the substrate 200, and the orthogonal projection of the first functional slot S1a on the substrate 200 may lie within the orthogonal projection of the resistor structure S1 on the substrate 200.

[0051] By setting the orthographic projection of the resistor structure S1 of a single first trench 301a on the substrate 200 to overlap with the orthographic projections of the gate bonding structure 710 and the first segment 721 on the substrate 200, and setting at least one first via 501 and at least one second via 502 located on the side of the same resistor structure S1 away from the substrate 200, the gate bonding structure 710 can be electrically connected to the first segment 721 through the resistor structure S1. The setting of the resistor structure S1 is beneficial to improving the input impedance of the semiconductor device 10, and also beneficial to reducing the driving capability requirements of the driving circuit used to provide the gate driving signal (for example, it is beneficial to control the charging and discharging rate of the driving circuit to the semiconductor device 10), and can effectively reduce the gate leakage current (for example, the gate leakage current can be reduced from the milliampere level to the microampere level), thereby improving the operating performance of the semiconductor device 10.

[0052] Optionally, the orthographic projection of the resistive structure S1 of a single first trench 301a onto the substrate 200 overlaps with the orthographic projections of the gate bonding structure 710 and the first segment 721 onto the substrate 200. This can mean that both the single first trench 301a and the single first resistive structure S1 can extend below the gate bonding structure 710 and the first segment 721, which is beneficial for the gate bonding structure 710 to achieve electrical connection with the first segment 721 through the resistive structure S1.

[0053] Optionally, the resistor structure S1 used to realize the electrical connection between the gate bonding structure 710 and the first segment 721 can be used as a resistor element R (for example, the portion of resistor structure S1 whose orthogonal projection on the substrate 200 overlaps with the orthogonal projections of the first via 501 and the second via 502 on the substrate 200, and the portion of resistor structure S1 whose orthogonal projection on the substrate 200 lies between the orthogonal projections of the first via 501 and the second via 502 on the substrate 200 can be used as a resistor element R). Through the structural arrangement of the semiconductor device 10 described in the foregoing embodiments, the resistor element R can be better integrated into the semiconductor device 10, so that the semiconductor device 10 has better electrical performance and adaptability, which is beneficial to simplify the driving circuit and reduce design complexity and system cost.

[0054] In the embodiments of this application, there are various ways to adjust the resistance of the resistive element R. As an example, when the material of the resistive structure S1 includes polysilicon, the resistance of the resistive element R can be adjusted by adjusting the doping activation concentration of the polysilicon. As an example, the resistance of the resistive element R can also be adjusted by adjusting the spacing between the first via 501 and the second via 502. That is, when the spacing between the first via 501 and the second via 502 (for example, the spacing between the first via 501 and the second via 502 in the second direction D2) is larger, the resistance of the resistive element R is larger, and when the spacing between the first via 501 and the second via 502 is smaller, the resistance of the resistive element R is smaller.

[0055] Figure 4 This is an equivalent circuit diagram of a semiconductor device 10 provided in an embodiment of this application.

[0056] Please see Figures 1 to 4 In some embodiments, trench 301 further includes a second trench 301b located within the first region A1. The second trench 301b extends along a second direction D2. The first trench 301a and the second trench 301b are spaced apart on a third direction D3. The semiconductor device 10 also includes a conductive structure S2 and a dielectric structure 400. The conductive structure S2 is disposed within the second trench 301b. The orthogonal projection of the conductive structure S2 within a single second trench 301b onto the substrate 200 is perpendicular to the gate bonding structure 710 and the first segment 721 on the substrate 200. The orthographic projection portions overlap, the dielectric structure 400 is at least partially disposed within the second trench 301b and between the conductive structure S2 and the epitaxial layer 300, the epitaxial layer 300 includes a first well region 320 located within the first region A1 and at least adjacent to the second trench 301b, the insulating layer 500 has a third via 503 and a fourth via 504, the gate bonding structure 710 is connected to the conductive structure S2 in the second trench 301b through the third via 503, and the first segment 721 is connected to the first well region 320 through the fourth via 504.

[0057] Optionally, the depth direction of the second groove 301b can be a first direction D1, the length direction of the second groove 301b can be a second direction D2, and the width direction of the second groove 301b can be a third direction D3.

[0058] Optionally, the dimensions of a single first trench 301a and a single second trench 301b may be the same (e.g., the first trench 301a and the second trench 301b may have the same length, the same width and the same depth) or different (e.g., the length of the first trench 301a is different from the length of the second trench 301b, and / or the width of the first trench 301a is different from the width of the second trench 301b, and / or the depth of the first trench 301a is different from the depth of the second trench 301b). This application does not impose specific limitations on them.

[0059] Optionally, the material of the conductive structure S2 can be configured in various ways, and the material of the conductive structure S2 can include any material with conductive properties. For example, the material of the conductive structure S2 can include polycrystalline silicon.

[0060] Optionally, the conductive structure S2 can be made of the same material as the resistive structure S1, so that the conductive structure S2 and the resistive structure S1 can be fabricated in the same fabrication step, which is beneficial to improving the fabrication efficiency of the semiconductor device 10.

[0061] Optionally, the material of the dielectric structure 400 may include an insulating material.

[0062] Optionally, the dielectric structure 400 may also be partially disposed within the first trench 301a and between the resistor structure S1 and the epitaxial layer 300.

[0063] Optionally, a dielectric structure 400 can be provided between the conductive structure S2 and the epitaxial layer 300, meaning that the conductive structure S2 can be separated from the epitaxial layer 300 through the dielectric structure 400. Similarly, a dielectric structure 400 can be provided between the resistive structure S1 and the epitaxial layer 300, meaning that the resistive structure S1 can be separated from the epitaxial layer 300 through the dielectric structure 400.

[0064] Optionally, the shape of the conductive structure S2 can be approximately the same as or similar to the shape of the second trench 301b, meaning that the second trench 301b can be sufficiently filled with the conductive structure S2. For example, the height direction of the conductive structure S2 can be a first direction D1, the length direction of the conductive structure S2 can be a second direction D2, and the width direction of the conductive structure S2 can be a third direction D3.

[0065] Optionally, the dimensions of the conductive structure S2 can be approximately the same as the dimensions of the second trench 301b.

[0066] Optionally, the orthogonal projection of the third via 503 on the substrate 200 may lie within the orthogonal projection of the gate bonding structure 710 on the substrate 200, and the orthogonal projection of the third via 503 on the substrate 200 may lie within the orthogonal projection of the conductive structure S2 on the substrate 200, which is beneficial for the gate bonding structure 710 to connect with the conductive structure S2 in the second trench 301b through the third via 503. The orthogonal projection of the fourth via 504 on the substrate 200 may lie within the orthogonal projection of the first segment 721 on the substrate 200, and the orthogonal projection of the fourth via 504 on the substrate 200 may lie within the orthogonal projection of the first well region 320 on the substrate 200, which is beneficial for the first segment 721 to connect with the first well region 320 through the fourth via 504.

[0067] Optionally, the first well region 320 may be disposed around the second trench 301b. For example, a portion of the first well region 320 may be located on the side of the second trench 301b close to the substrate 200 in the first direction D1, a portion of the first well region 320 may be located on both sides of the second trench 301b in the second direction D2, and a portion of the first well region 320 may be located on both sides of the second trench 301b in the third direction D3.

[0068] Optionally, the first well region 320 may also be disposed around the first trench 301a. For example, a portion of the first well region 320 may be located on the side of the first trench 301a close to the substrate 200 in the first direction D1, a portion of the first well region 320 may be located on both sides of the first trench 301a in the second direction D2, and a portion of the first well region 320 may be located on both sides of the first trench 301a in the third direction D3.

[0069] Optionally, a third functional slot S1c communicating with the third via 503 may be formed on the side of the conductive structure S2 away from the substrate 200, and a fourth functional slot 321 communicating with the fourth via 504 may be formed on the side of the first well region 320 away from the substrate 200. The setting of the third functional slot S1c is beneficial to increasing the connection area between the gate bonding structure 710 and the conductive structure S2, and the setting of the fourth functional slot 321 is beneficial to increasing the connection area between the first segment 721 and the first well region 320.

[0070] Optionally, the orthographic projection of the third functional trench S1c on the substrate 200 may lie within the orthographic projection of the gate bonding structure 710 on the substrate 200, and the orthographic projection of the third functional trench S1c on the substrate 200 may lie within the orthographic projection of the conductive structure S2 on the substrate 200. The orthographic projection of the fourth functional trench 321 on the substrate 200 may lie within the orthographic projection of the first segment 721 on the substrate 200, and the orthographic projection of the fourth functional trench 321 on the substrate 200 may lie within the orthographic projection of the first well region 320 on the substrate 200.

[0071] In the aforementioned embodiments, by providing a conductive structure S2 within the second trench 301b and providing an insulating layer 500 with a third via 503, the gate bonding structure 710 can be electrically connected to the conductive structure S2 within the second trench 301b through the third via 503. By providing an epitaxial layer 300 including a first well region 320 located within the first region A1 and providing an insulating layer 500 with a fourth via 504, the first segment 721 can be electrically connected to the first well region 320 through the fourth via 504. Since the gate bonding structure 710 and the first segment 721 are spaced apart in the second direction D2, by setting the second trench 301b to extend along the second direction D2, it is beneficial to realize that the orthographic projection of the conductive structure S2 in a single second trench 301b on the substrate 200 overlaps with the orthographic projections of the gate bonding structure 710 and the first segment 721 on the substrate 200. That is, it is beneficial to realize that the conductive structure S2 in a single second trench 301b extends through the area below the gate bonding structure 710 and the first segment 721.

[0072] By setting a dielectric structure 400 between the conductive structure S2 and the epitaxial layer 300 in the second trench 301b, and setting the first well region 320 to be at least adjacent to the second trench 301b, a capacitor element C can be formed between the first well region 320 and the conductive structure S2. One plate of the capacitor element C can be connected to the gate bonding structure 710, and the other substrate of the capacitor element C can be connected to the first segment 721. This allows the capacitor element C to be connected in parallel with the resistor element R in the aforementioned embodiment between the gate bonding structure 710 and the first segment 721, forming an RC network circuit (Resistor-Capacitor Network Circuit). RC network circuits can often achieve functions such as delaying, filtering, coupling, decoupling, or damping of electrical signals through the combination of the impedance characteristics of resistors and capacitors. They can be used to adjust the rise and fall speed of electrical signals, suppress high-frequency oscillations, reduce electromagnetic interference (EMI), reduce electromagnetic interference coupling (EMI coupling), and stabilize the circuit operating state. In the embodiments of this application, the RC network circuit formed between the gate bonding structure 710 and the first segment 721 (e.g., between the gate bonding structure 710 and the JFET device) can use the resistor element R to control the charging and discharging rate and use the capacitor to absorb transient charge, thereby reducing the gate leakage current and suppressing parasitic oscillations, signal ringing, high-frequency noise interference and noise coupling (e.g. EMI coupling). This can improve the switching stability and electromagnetic compatibility performance of the semiconductor device 10, so that the semiconductor device 10 can have better driving stability and operating stability.

[0073] Compared with traditional devices, this application integrates the RC network circuit between the gate bonding structure 710 and the gate trace 720 through the aforementioned structural arrangement, which enables the semiconductor device 10 to have better working performance and adaptability. It can not only simplify the driving circuit and reduce the system design complexity and cost, but also improve the working stability and anti-interference capability of the semiconductor device 10.

[0074] In the embodiments of this application, there are various ways to adjust the capacitance of capacitor element C. As an example, the capacitance of capacitor element C can be adjusted by adjusting the thickness of the dielectric layer; that is, the greater the thickness of the dielectric layer, the smaller the capacitance of capacitor element C, and the smaller the thickness of the dielectric layer, the larger the capacitance of capacitor element C.

[0075] In some embodiments, the minimum distance between the orthographic projection of the first via 501 on the substrate 200 and the orthographic projection of the first segment 721 on the substrate 200 is the first distance G1, and the minimum distance between the orthographic projection of the third via 503 on the substrate 200 and the orthographic projection of the first segment 721 on the substrate 200 is the second distance G2, wherein the first distance G1 is greater than the second distance G2.

[0076] For example, the minimum distance between the orthographic projection of the first via 501 on the substrate 200 and the orthographic projection of the first segment 721 on the substrate 200 in the second direction D2 is the first distance G1, and the minimum distance between the orthographic projection of the third via 503 on the substrate 200 and the orthographic projection of the first segment 721 on the substrate 200 in the second direction D2 is the second distance G2.

[0077] By setting the first spacing G1 to be greater than the second spacing G2, the first spacing G1 can be larger, which can better improve the spacing between the first via 501 and the second via 502, so that the resistor element R can have a more suitable resistance. It can also make the second spacing G2 smaller, which can better reduce the resistance when the gate bonding structure 710 is connected to one of the plates of the capacitor element C, thereby enabling the RC network circuit to have better working performance.

[0078] In some embodiments, the size of the first via 501 in the second direction D2 is smaller than the size of the third via 503 in the second direction D2.

[0079] Optionally, the size of the second via 502 in the second direction D2 may be equal to the size of the fourth via 504 in the second direction D2.

[0080] Optionally, the projection of the second via 502 onto the third-direction D3 may overlap with the projection of the fourth via 504 onto the third-direction D3.

[0081] In the above embodiments, by setting the size of the first via 501 in the second direction D2 to be smaller than the size of the third via 503 in the second direction D2, it is beneficial to achieve a first spacing G1 greater than a second spacing G2, which can better improve the spacing between the first via 501 and the second via 502, so that the resistor element R can have a more suitable resistance, and can also better reduce the resistance when the gate bonding structure 710 is connected to one of the plates in the capacitor element C.

[0082] In some embodiments, there are multiple fourth vias 504, and the multiple fourth vias 504 are spaced apart on the third direction D3, and the orthogonal projection of the conductive structure S2 on the substrate 200 is located between the orthogonal projections of adjacent fourth vias 504 on the substrate 200.

[0083] For example, the orthographic projection of the conductive structure S2 on the substrate 200 lies between the orthographic projections of the fourth via 504 adjacent to the third via D3 on the substrate 200.

[0084] Optionally, the orthogonal projection of the resistor structure S1 on the substrate 200 may also be located between the orthogonal projections of adjacent fourth vias 504 on the substrate 200. For example, the orthogonal projection of the resistor structure S1 on the substrate 200 may also be located between the orthogonal projections of adjacent fourth vias 504 on the third-direction D3 on the substrate 200.

[0085] Optionally, the orthographic projection of the second via 502 on the substrate 200 may also be located between the orthographic projections of the adjacent fourth via 504 on the substrate 200. For example, the orthographic projection of the second via 502 on the substrate 200 may also be located between the orthographic projections of the adjacent fourth via 504 on the third-direction D3 on the substrate 200.

[0086] In the above embodiment, by setting the orthogonal projection of the conductive structure S2 on the substrate 200 between the orthogonal projections of the adjacent fourth via 504 on the substrate 200, the first well regions 320 on both sides of the conductive structure S2 in the third direction D3 can be connected to the first segment 721, thereby enabling the conductive structure S2 to form a capacitor element C between it and the first well regions 320 on both sides of the third direction D3, which can improve the working performance of the RC network circuit.

[0087] In some embodiments of this application, the number of first trenches 301a and second trenches 301b can be set in various ways.

[0088] Optionally, the number of first trenches 301a may be one or more, wherein the number of first trenches 301a may be the same as the number of resistor structures S1, and the first trenches 301a and resistor structures S1 may correspond one-to-one. For example, the number of first trenches 301a and resistor structures S1 in the semiconductor device 10 may be only one.

[0089] Optionally, the number of second trenches 301b can be one or more, wherein the number of second trenches 301b can be the same as the number of conductive structures S2, and the number of second trenches 301b can correspond one-to-one with the number of conductive structures S2. For example, the number of second trenches 301b and conductive structures S2 in the semiconductor device 10 can be multiple.

[0090] In some embodiments, there are multiple second grooves 301b, which are respectively disposed on both sides of the first groove 301a on the third direction D3.

[0091] For example, the number of second grooves 301b located on one side of the first groove 301a on the third direction D3 can be the same as the number of second grooves 301b located on the other side of the first groove 301a on the third direction D3.

[0092] In the above embodiment, by distributing multiple second trenches 301b on both sides of the first trench 301a in the third direction D3, the capacitor element C formed in the semiconductor device 10 can be distributed more evenly on both sides of the resistor element R, which is beneficial to improving the electric field effect generated by the RC network circuit, thereby improving the working stability of the RC network circuit.

[0093] Optionally, the first segment 721 may extend along the third direction D3, that is, the length direction of the first segment 721 may be the third direction D3, so that the first segment 721 has a larger size in the third direction D3, which is beneficial for the first segment 721 to connect with the first well region 320 and the resistor structure S1 arranged in the third direction D3.

[0094] Figure 5 This is a schematic diagram of a gate structure 700, a source metal 800, and a terminal 900 provided in an embodiment of this application. Figure 6 This is a partially enlarged schematic diagram of a semiconductor device 10 provided in an embodiment of this application. Figure 7 This is a partial cross-sectional view of a semiconductor device 10 provided in another embodiment of this application. Figure 8 This is a partial cross-sectional view of a semiconductor device 10 provided in another embodiment of this application.

[0095] Optional, Figure 6 This can be one embodiment. Figure 5A partially enlarged schematic diagram of the semiconductor device 10 at position J, as shown in the diagram. Figure 7 This can be one embodiment. Figure 6 A partial sectional view at position CC. Figure 8 This can be one embodiment. Figure 6 A partial sectional view at position DD in the middle.

[0096] like Figures 5 to 8 As shown, in some embodiments, the semiconductor device 10 may also have a second region A2. A JFET device may be disposed in the second region A2, and the JFET device in the second region A2 may receive a gate drive signal through the gate trace 720 to control the turn-on and turn-off of the semiconductor device 10.

[0097] For example, the semiconductor device 10 further includes a second region A2. The semiconductor device 10 also includes a semiconductor structure 600 disposed on the side of the insulating layer 500 near the substrate 200, a drain metal 100 disposed on the side of the substrate 200 away from the epitaxial layer 300, and a source metal 800 disposed on the side of the insulating layer 500 away from the substrate 200. The gate trace 720 includes a second segment 722 electrically connected to the first segment 721 and located within the second region A2. The epitaxial layer 300 includes an epitaxial region 310, a second well region 330, a channel region 350, and a source region 340. The source metal 800, semiconductor structure 600, and second well region 330 are also included. 0. The channel region 350 and the source region 340 are both located in the second region A2. The second well region 330 is located on the side of the epitaxial region 310 away from the substrate 200. The source region 340 is at least partially located on the side of the second well region 330 away from the substrate 200. The channel region 350 is connected to the source region 340 and is located on the side of the second well region 330 close to the semiconductor structure 600. The insulating layer 500 also has a first functional opening 505 and a second functional opening 506 located in the second region A2. The source metal 800 is connected to the source region 340 through the first functional opening 505. The second segment 722 is connected to the semiconductor structure 600 through the second functional opening 506.

[0098] Optionally, the material of the semiconductor structure 600 may include polycrystalline silicon.

[0099] Optionally, the epitaxial region 310 and the drain metal 100 can be located in the first region A1 and the second region A2, that is, the epitaxial region 310 and the drain metal 100 can be provided in both the first region A1 and the second region A2, and the first well region 320 can be located on the side of the epitaxial region 310 away from the substrate 200.

[0100] Optionally, the first well region 320 may be connected to the second well region 330.

[0101] Optionally, the epitaxial layer 300 may also include a channel conditioning region 360 adjacent to the channel region 350.

[0102] Optionally, the substrate 200, epitaxial region 310, channel region 350, channel conditioning region 360, and source region 340 can all be configured with a first doping type, and the first well region 320 and second well region 330 can both be configured with a second doping type. By reasonably setting the first and second doping types, the semiconductor device 10 provided in this application embodiment can be a normally-on device or a normally-off device. For example, one of the first and second doping types can be N-type doping, and the other can be P-type doping.

[0103] Optionally, when the semiconductor device 10 provided in the embodiments of this application is a normally off device, it can better improve the shortcomings of normally open devices in terms of safety control.

[0104] Optionally, the insulating layer 500 may include a passivation protection layer 510 and an isolation layer 520 located on the side of the passivation protection layer 510 away from the substrate 200. The passivation protection layer 510 may be located only in the second region A2. The passivation protection layer 510 is disposed on the side of the epitaxial layer 300 and the semiconductor structure 600 away from the substrate 200. The isolation layer 520 may be located in the first region A1 and the second region A2.

[0105] Optionally, the orthographic projection of the first functional opening 505 on the substrate 200 lies within the orthographic projection of the second segment 722 on the substrate 200, and the orthographic projection of the first functional opening 505 on the substrate 200 at least partially overlaps with the orthographic projection of the semiconductor structure 600 on the substrate 200. The orthographic projection of the second functional opening 506 on the substrate 200 lies within the orthographic projection of the source metal 800 on the substrate 200, and the orthographic projection of the second functional opening 506 on the substrate 200 at least partially overlaps with the orthographic projection of the source region 340 on the substrate 200.

[0106] Optionally, the second functional opening 506 may extend along the second direction D2, that is, the length direction of the second functional opening 506 may be the second direction D2, and the number of second functional openings 506 may be multiple, and multiple second functional openings 506 may be arranged at intervals on the third direction D3.

[0107] Optionally, the orthographic projection of the semiconductor structure 600 onto the substrate 200 may be located between the orthographic projections of adjacent second functional openings 506 onto the substrate 200.

[0108] In the above embodiments, Figure 7 and Figure 8The diagrams illustrate cross-sectional views of a single pitch structure in the semiconductor device 10 at different locations. The pitch structure can be the smallest repeating unit of the semiconductor device 10 in the second region A2. The entire pitch structure can extend along the second direction D2, and multiple pitch structures can be arranged along the third direction D3. Under the action of the gate drive signal transmitted from the gate trace 720 to the semiconductor structure 600, the source metal 800 can be turned on via the source region 340, channel region 350, channel adjustment region 360, epitaxial region 310, substrate 200, and drain metal 100, thereby turning on the semiconductor device 10; or, under the action of the gate drive signal transmitted from the gate trace 720 to the semiconductor structure 600, the source metal 800 and drain metal 100 can be de-conductive, thereby turning off the semiconductor device 10.

[0109] In the embodiments of this application, there are various ways to arrange the structure of the semiconductor device 10 located in the second region A2.

[0110] As an example, such as Figure 7 and Figure 8 As shown, in a single unit cell structure, there can be two source regions 340, channel conditioning regions 360, and second well regions 330. The two second well regions 330 can be spaced apart on the third direction D3. The epitaxial region 310 extends partially between adjacent second well regions 330. A single source region 340 and a single channel conditioning region 360 can be disposed above a single second well region 330. The channel region 350 can be located between adjacent channel conditioning regions 360 and extends partially to the side of the well region away from the substrate 200. The source region 340 can be located on the side of the channel conditioning region 360 away from the channel region 350. The semiconductor structure 600 can be disposed on the side of the channel region 350 away from the substrate 200.

[0111] Figure 9 This is a partial cross-sectional view of a semiconductor device 10 provided in another embodiment of this application. Figure 10 This is a partial cross-sectional view of a semiconductor device 10 provided in another embodiment of this application. Optionally, Figure 9 This could be in another embodiment. Figure 5 A partial sectional view at position C in the middle. Figure 10 This could be in another embodiment. Figure 5 A partial sectional view at position D in the middle.

[0112] As an example, such as Figure 9 and Figure 10As shown, trench 301 also includes a third trench 301c located within the second region A2. The semiconductor structure 600 is located within the third trench 301c. Both the third trench 301c and the semiconductor structure 600 can extend in the second direction D2. There can be multiple third trenches 301c, which can be arranged at intervals in the third direction D3. A single third trench 301c can correspond to a single unit cell structure. In a single unit cell structure, there can be two source regions 340, two channel regions 350, two channel adjustment regions 360, and two second well regions 330. The two second well regions 330 can be disposed on both sides of the third trench 301c in the third direction D3. The two channel regions 350 can be disposed on both sides of the third trench 301c in the third direction D3. The two channel adjustment regions 360 can be disposed on both sides of the third trench 301c in the third direction D3. The channel regions 350 and 360 can be located between the second well regions 330 and the third trench 301c. The channel region 350 can be located on the side of the channel adjustment region 360 away from the substrate 200. The two source regions 340 can be disposed on both sides of the third trench 301c in the third direction D3. The source regions 340 can be located on the side of the channel regions 350 and the second well regions 330 away from the substrate 200.

[0113] Optionally, the depth direction of the third groove 301c can be the first direction D1, the length direction of the third groove 301c can be the second direction D2, and the width direction of the third groove 301c can be the third direction D3.

[0114] Optionally, the first trench 301a, the second trench 301b, and the third trench 301c may not be interconnected, making it less likely for the structures within the first trench 301a, the second trench 301b, and the third trench 301c to short-circuit, which is beneficial to improving the working stability of the semiconductor device 10.

[0115] In some embodiments, the second region A2 includes a first sub-region A21 and a second sub-region A22. The second sub-region A22 is located on at least one side of the first sub-region A21 in the second direction D2. The second segment 722 is located within the second sub-region A22. The source metal 800 is located within the first sub-region A21 and is spaced apart from the second segment 722.

[0116] Optionally, the orthographic projection of the semiconductor structure 600 within a single third trench 301c onto the substrate 200 may overlap with the orthographic projection of the source metal 800 and the second segment 722 onto the substrate 200, meaning that the semiconductor structure 600 within a single third trench 301c may extend below the source metal 800 and the second segment 722.

[0117] Optionally, the second segment 722 may extend along the third direction D3, that is, the length direction of the second segment 722 may be the third direction D3, so that the second segment 722 has a larger size in the third direction D3, which is beneficial for the third segment 723 to be connected to the semiconductor structure 600 with multiple unit cell structures arranged in the third direction D3.

[0118] In the above embodiments, by setting the source metal 800 to be located in the first sub-region A21 and spaced apart from the second segment 722, the source metal 800 is less likely to be short-circuited with the gate trace 720, and the gate trace 720 can provide a gate drive signal to the unit cell structure from at least one side of the source metal 800 in the second direction D2, so as to control the conduction and turn-off of the source metal 800 and the drain metal 100 in the first sub-region A21.

[0119] In some embodiments, the source metal 800 has a clearance opening 801 on one side of the third-direction D3, and the gate bonding structure 710 and the first segment 721 are at least partially located within the clearance opening 801.

[0120] Optionally, the gate structure 700 may be spaced apart from the source metal 800, so that the source metal 800 is less likely to be short-circuited with the gate structure 700.

[0121] Optionally, part of the second region A2 may be located on one side of the first region A1 in the third direction D3, and part of the second region A2 may be located on both sides of the first region A1 in the second direction D2. That is, the second region A2 as a whole may be in the shape of a "U", and the first region A1 may be surrounded by the second region A2 in the shape of a "U".

[0122] In the above embodiments, by providing a clearance opening 801 for the source metal 800 and at least partially placing the gate bonding structure 710 and the first segment 721 within the clearance opening 801, the first region A1 can be at least partially embedded in the second region A2. This facilitates the connection between the gate structure 700 and the unit cell structure, and helps to improve the overall integration of the semiconductor device 10. It can also significantly improve the structural compactness of the semiconductor device 10, enabling the integration of the RC network circuit without increasing the size too much.

[0123] In some embodiments, the semiconductor device 10 further has a third region A3, which is located on the same side of the second region A2 on the third direction D3 as the first region A1. The gate trace 720 further includes a third segment 723 located in the third region A3, and the first segment 721 and the second segment 722 are electrically connected through the third segment 723.

[0124] Optionally, the third region A3 may be located on at least one side of the first region A1 in the second direction D2.

[0125] Optionally, the third segment 723 may extend along the second direction D2, that is, the length direction of the third segment 723 may be the second direction D2, so that the third segment 723 can be connected with the first segment 721 and the second segment 722.

[0126] In some embodiments, the semiconductor device 10 also has a fourth region A4, which may surround the first region A1, the second region A2 and the third region A3, and the semiconductor device 10 may also include a terminal 900 disposed in the fourth region A4.

[0127] In some embodiments of this application, based on the structure of the semiconductor device 10 provided in the foregoing embodiments, there are various methods for fabricating the semiconductor device 10.

[0128] As an example, after the fabrication of the first well region 320 and the second well region 330 of the epitaxial layer 300 in the semiconductor device 10 is completed, the material of the epitaxial layer 300 can be etched at the corresponding positions of the first region A1 and the second region A2 using a mask to form trenches 301. Subsequently, a dielectric structure 400, a resistive structure S1, a conductive structure S2 and a semiconductor structure 600 can be formed by a deposition process. Then, after depositing the material of the insulating layer 500, the material of the insulating layer 500 can be subjected to an opening process to form various openings and apertures on the insulating layer 500. Finally, a gate structure 700 and a source metal 800 can be formed by depositing metal material.

[0129] In some embodiments of this application, when the orthogonal projection size of the gate bonding structure 710 on the substrate 200 is 300μm × 500μm, the adjustable range of the resistance element R in the RC network circuit of the semiconductor device 10 is 10 kΩ to 50 kΩ. By setting the resistance of the resistance element R in the RC network circuit to be not less than 10 kΩ, the gate leakage current can be effectively suppressed to the 100μA level under a working voltage of 5V. When the material of the resistor structure S1 includes polysilicon, based on the conductivity of polysilicon and process consistency, the resistance of the resistance element R in the RC network circuit should not be greater than 50kΩ.

[0130] In the RC network circuit of semiconductor device 10, the capacitance of capacitor element C can be controlled within a range of no more than 1 nF. The larger the capacitance of capacitor element C, the better its filtering and EMI suppression performance. However, its size is limited by the thickness of dielectric structure 400. Taking silicon nitride (Si3N4) as an example, to ensure that the breakdown voltage of dielectric structure 400 is higher than the device operating voltage of 5V, the thickness of dielectric structure 400 must be no less than 10 nm.

[0131] Figure 11 This is a parameter simulation diagram of an RC network circuit provided in an embodiment of this application. Figure 12 This is a parameter simulation diagram of an RC network circuit provided in another embodiment of this application.

[0132] As an example, the trench 301 has a depth of 0.7 μm, a width of 0.5 μm, a dielectric structure 400 made of Si3N4 material, a thickness of not less than 10 nm, and polysilicon in the first trench 301a and the second trench 301b is N-type with a doping concentration controlled at 2 × 10¹. 7 cm⁻³~3×10¹ 9 Under the condition of cm⁻³", the simulation results of the RC network circuit parameters can be obtained as follows: Figure 11 and Figure 12 As shown.

[0133] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A semiconductor device, characterized in that, The semiconductor device has a first region, the semiconductor device comprising: Substrate; An epitaxial layer is disposed on one side of the substrate in a first direction, and a trench is formed on the side of the epitaxial layer opposite to the substrate. The trench includes a first trench located in the first region, and the first trench extends along a second direction, which intersects with the second direction. A resistor structure is disposed within the first trench; An insulating layer is disposed on the side of the epitaxial layer opposite to the substrate; A gate structure is disposed on the side of the insulating layer opposite to the substrate. The gate structure includes a gate bonding structure and a gate trace. The gate trace includes a first segment located within the first region. The gate bonding structure is located within the first region and spaced apart from the first segment in the second direction. The insulating layer has a first via and a second via. The gate bonding structure is connected to the resistor structure in the first trench through the first via. The first segment is connected to the resistor structure in the first trench through the second via. The orthographic projection of the resistor structure in a single first trench on the substrate overlaps with the orthographic projection of the gate bonding structure and the first segment on the substrate. At least one first via and at least one second via are located on the side of the same resistor structure away from the substrate.

2. The semiconductor device according to claim 1, characterized in that, The trench further includes a second trench located within the first region, the second trench extending along the second direction, the first trench and the second trench being spaced apart in a third direction, and the first direction, the second direction and the third direction intersecting each other. The semiconductor device further includes a conductive structure and a dielectric structure. The conductive structure is disposed within the second trench. The orthographic projection of the conductive structure within a single second trench onto the substrate overlaps with the orthographic projection of the gate bonding structure and the first segment onto the substrate. The dielectric structure is at least partially disposed within the second trench and between the conductive structure and the epitaxial layer. The epitaxial layer includes a first well region located within a first region and at least adjacent to the second trench. The insulating layer has a third via and a fourth via. The gate bonding structure is connected to the conductive structure in the second trench through the third via. The first segment is connected to the first well region through the fourth via.

3. The semiconductor device according to claim 2, characterized in that, The minimum distance between the orthographic projection of the first via on the substrate and the orthographic projection of the first segment on the substrate is the first distance, and the minimum distance between the orthographic projection of the third via on the substrate and the orthographic projection of the first segment on the substrate is the second distance, wherein the first distance is less than the second distance.

4. The semiconductor device according to claim 2, characterized in that, The size of the first via in the second direction is smaller than the size of the third via in the second direction.

5. The semiconductor device according to claim 2, characterized in that, The number of the fourth vias is multiple, and the multiple fourth vias are spaced apart on the third side. The orthogonal projection of the conductive structure on the substrate is located between the orthogonal projections of adjacent fourth vias on the substrate.

6. The semiconductor device according to claim 2, characterized in that, There are multiple second grooves, which are respectively located on both sides of the first groove in the third direction.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, The semiconductor device further includes a second region, and further includes a semiconductor structure disposed on the side of the insulating layer near the substrate, a drain metal disposed on the side of the substrate away from the epitaxial layer, and a source metal disposed on the side of the insulating layer away from the substrate. The gate trace includes a second segment electrically connected to the first segment and located in the second region. The epitaxial layer includes an epitaxial region, a second well region, a channel region, and a source region. The source metal, the semiconductor structure, the second well region, the channel region, and the source region are all located in the second region. The second well region is located on the side of the epitaxial region facing away from the substrate. The source region is at least partially located on the side of the second well region facing away from the substrate. The channel region is adjacent to the source region and located on the side of the second well region closer to the semiconductor structure. The insulating layer also has a first functional opening and a second functional opening located in the second region. The source metal is connected to the source region through the first functional opening, and the second segment is connected to the semiconductor structure through the second functional opening.

8. The semiconductor device according to claim 7, characterized in that, The second region includes a first sub-region and a second sub-region. The second sub-region is located on at least one side of the first sub-region in the second direction. The second segment is located within the second sub-region. The source metal is located within the first sub-region and is spaced apart from the second segment.

9. The semiconductor device according to claim 7, characterized in that, The source metal has a clearance opening on the third-side upward, and the gate bonding structure and the first segment are at least partially located within the clearance opening.

10. The semiconductor device according to claim 7, characterized in that, The semiconductor device further has a third region located on the same side of the second region in a third direction as the first region, and the gate trace further includes a third segment located within the third region, the first segment and the second segment being electrically connected through the third segment.

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