Semiconductor device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, and discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate layer; the epitaxial layer is located on the substrate layer and comprises a terminal region and a scribing channel region surrounding the terminal region; the doped region is located in the scribing channel region and extends into a part of the terminal region, and the doped region comprises a first doped region and a second doped region; the first doped region and the second doped region have the same conduction type and different doping concentrations; the substrate layer and the epitaxial layer have the same conductive type and are opposite to the conductive type of the first doped region. The total concentration of the first doped region and the second doped region is higher than the concentration of one doped region, the potential of the surface of the scribing channel region can be further reduced, and the effect of avoiding failure of the semiconductor device is optimal.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] With the development of power electronics technology, power semiconductor devices need to handle increasingly higher voltages. To overcome the problem of electric field concentration at the edges of power semiconductor devices limiting their voltage withstand capability, termination structures have emerged. Common termination structures include planar termination structures, vertical termination structures, and composite termination structures. Termination structures improve the voltage withstand capability of power semiconductor devices by altering the electric field distribution and reducing the electric field strength at the device edges.

[0003] Although power semiconductor devices are protected by termination structures, in certain scenarios (such as wafer-level evaluation, substrate-level evaluation, or encapsulation without insulating adhesive), a high voltage is applied to the drain on the back side of the power semiconductor device. Since the scribe line in the power semiconductor device is not effectively protected and the exposed scribe line has the same potential as the drain, the high voltage at the drain can creep through the scribe line to the source on the front side of the power semiconductor device. Creepage breakdown will occur between the drain and the source, which will lead to the failure of the power semiconductor device. Summary of the Invention

[0004] The purpose of this invention is to provide at least one semiconductor device and its fabrication method, which can at least solve the problem of creepage breakdown effect between the drain and source, leading to semiconductor device failure.

[0005] To address the aforementioned technical problems, the present invention provides a semiconductor device comprising: a substrate layer; an epitaxial layer located on the substrate layer, the epitaxial layer including a termination region and a scribe line region surrounding the termination region; a doped region located in the scribe line region and extending into a portion of the termination region, the doped region including a first doped region and a second doped region; the first doped region and the second doped region having the same conductivity type but different doping concentrations; the substrate layer and the epitaxial layer having the same conductivity type but opposite to the conductivity type of the first doped region.

[0006] The semiconductor device provided by this invention, by placing a doped region in the scribe line region and extending it into a portion of the terminal region, and utilizing the depletion layer withstand voltage in reverse voltage application of the PN junction formed between the doped region and the surrounding epitaxial layer, can effectively shield the electric field on the surface of the scribe line region, reduce the potential of the scribe line region surface, and prevent reverse voltage from creeping from the back electrode of the semiconductor device through the scribe line region to the front electrode of the semiconductor device. Simultaneously, the doped region includes a first doped region and a second doped region, which have the same conductivity type but different doping concentrations. The total concentration of the first and second doped regions is higher than that of a single doped region, further reducing the potential of the scribe line region surface and enhancing the ability to prevent reverse voltage from creeping from the back electrode of the semiconductor device through the scribe line region to the front electrode of the semiconductor device. This achieves optimal semiconductor device failure prevention.

[0007] In addition, the doped region has a ring structure.

[0008] In addition, the first doped region and the second doped region are spaced apart along a direction parallel to the surface of the substrate layer, and the first doped region or the second doped region near the terminal region extends into part of the terminal region.

[0009] In addition, at least a portion of the second doped region is located within the first doped region; wherein the first doped region and / or the second doped region extends into a portion of the terminal region.

[0010] In addition, there are multiple first doped regions, which are spaced apart along a direction parallel to the surface of the substrate layer; at least a portion of the second doped region is located in the first doped region, and the second doped region also extends between adjacent first doped regions.

[0011] Additionally, it includes: a cutoff region located in the terminal region, the cutoff region being in contact with a doped region extending into a portion of the terminal region; or, the cutoff region and the doped region extending into a portion of the terminal region being spaced apart; the cutoff region and the epitaxial layer having the same conductivity type, and the doping concentration of the cutoff region being greater than the doping concentration of the epitaxial layer.

[0012] In addition, the epitaxial layer also includes an active region, which is surrounded by a terminal region. The active region includes a well region and a source region located within the well region. The well region and the first doped region have the same conductivity type, doping concentration, and depth. The source region and the second doped region also have the same conductivity type, doping concentration, and depth. The well region and the first doped region use the same ion implantation process, and the source region and the second doped region use the same ion implantation process, which helps to reduce process complexity.

[0013] In addition, the doping concentration of the first doped region is less than that of the second doped region, and the depth of the first doped region is greater than that of the second doped region.

[0014] The present invention also provides a method for fabricating a semiconductor device, comprising: forming an epitaxial layer on a substrate layer, the epitaxial layer including a termination region and a dicing region surrounding the termination region; forming a doped region in the dicing region and a portion of the termination region, wherein forming the doped region includes: forming a first doped region and a second doped region in the dicing region and a portion of the termination region respectively; the first doped region and the second doped region have the same conductivity type but different doping concentrations; the substrate layer and the epitaxial layer have the same conductivity type but opposite conductivity type to the first doped region.

[0015] Additionally, it includes: forming a cutoff region in the terminal region; the cutoff region and the doped region extending into the partial terminal region being in contact; or, the cutoff region and the doped region extending into the partial terminal region being spaced apart; the cutoff region and the epitaxial layer having the same conductivity type, and the doping concentration of the cutoff region being greater than the doping concentration of the epitaxial layer.

[0016] In addition, the epitaxial layer also includes an active region, which is surrounded by a termination region. The semiconductor device fabrication method further includes: forming a well region in the active region; during the formation of the well region, forming a first doped region in the dicing channel region and a portion of the termination region; and forming a source region in the well region; during the formation of the source region, forming a second doped region in the dicing channel region and a portion of the termination region. The well region and the first doped region employ the same ion implantation process, and the source region and the second doped region employ the same ion implantation process, which helps reduce process complexity. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0018] Figure 1 This is a schematic cross-sectional view of a semiconductor device provided in an embodiment of the present invention;

[0019] Figure 2 This is another cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present invention;

[0020] Figure 3 This is a top view of an epitaxial layer in a semiconductor device according to an embodiment of the present invention;

[0021] Figure 4 A schematic flowchart of a method for fabricating a semiconductor device according to another embodiment of the present invention;

[0022] Figures 5 to 12 This is a schematic diagram of the fabrication process of a semiconductor device according to another embodiment of the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present invention to enable the reader to better understand the present invention. However, the technical solutions claimed in the present invention can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0024] Reference Figure 1 and Figure 2 The present invention provides a semiconductor device comprising: a substrate layer 1; an epitaxial layer 2 located on the substrate layer 1, the epitaxial layer 2 including a terminal region A and a scribe line region B surrounding the terminal region A; a doped region 3 located in the scribe line region B and extending into a portion of the terminal region A, the doped region 3 including a first doped region 3a and a second doped region 3b; the first doped region 3a and the second doped region 3b have the same conductivity type but different doping concentrations; the substrate layer 1 and the epitaxial layer 2 have the same conductivity type but opposite conductivity type to the first doped region 3a.

[0025] In this embodiment, by setting the doped region 3 in the scribe line region B and extending it into part of the terminal region A, the PN junction formed between the doped region 3 and the surrounding epitaxial layer 2 utilizes the depletion layer withstand voltage during reverse voltage application. This effectively shields the electric field on the surface of the scribe line region B, reduces the potential of the scribe line region B, and prevents reverse voltage from creeping from the back electrode of the semiconductor device through the scribe line region B to the front electrode of the semiconductor device. Simultaneously, the doped region 3 includes a first doped region 3a and a second doped region 3b. The first doped region 3a and the second doped region 3b have the same conductivity type but different doping concentrations. The total concentration of the first doped region 3a and the second doped region 3b is higher than that of a single doped region, further reducing the potential of the scribe line region B and enhancing the ability to prevent reverse voltage from creeping from the back electrode of the semiconductor device through the scribe line region to the front electrode of the semiconductor device. This achieves optimal results in preventing semiconductor device failure.

[0026] The doped region 3 extends into a portion of the terminal region A. This can be because the first doped region 3a extends into a portion of the terminal region A while the second doped region 3b does not extend into the terminal region A; or the second doped region 3b extends into a portion of the terminal region A while the first doped region 3a does not extend into the terminal region A; or both the first doped region 3a and the second doped region 3b extend into a portion of the terminal region A.

[0027] In one embodiment, the first doped region 3a and the second doped region 3b are spaced apart along a direction parallel to the surface of the substrate layer 1, and the first doped region 3a or the second doped region 3b near the terminal region A extends into a portion of the terminal region A (not shown).

[0028] In another embodiment, at least a portion of the second doped region 3b is located within the first doped region 3a; wherein the first doped region 3a and / or the second doped region 3b extends into a portion of the terminal region A.

[0029] At least a portion of the second doped region 3b is located in the first doped region 3a. This can be either a portion of the second doped region 3b is located in the first doped region 3a and a portion is located in the epitaxial layer 2 outside the first doped region 3a, or all of the second doped region 3b is located in the first doped region 3a.

[0030] Figure 1 and Figure 2 In this illustration, at least a portion of the second doped region 3b is located within the first doped region 3a, and both the first doped region 3a and the second doped region 3b extend into a portion of the terminal region A. Adjustments can be made according to actual needs, and this application does not impose any limitations.

[0031] Continue to refer to Figure 1 There are multiple first doped regions 3a, which are spaced apart along a direction parallel to the surface of the substrate layer 1. At least a portion of the second doped region 3b is located within the first doped regions 3a, and the second doped region 3b extends between adjacent first doped regions 3a. Specifically, a portion of the second doped region 3b is located within the first doped regions 3a, a portion is located in the epitaxial layer 2 between adjacent first doped regions 3a, and a portion is located in the epitaxial layer 2 on the side of the first doped region 3a closest to the terminal region A along a direction parallel to the substrate layer 1 towards the terminal region A. When there are multiple first doped regions 3a, the first doped region 3a closest to the terminal region A extends into a portion of the terminal region A. The width dimensions of the multiple first doped regions 3a along the surface parallel to the substrate layer 1 can be the same or different; the distance between adjacent first doped regions 3a can be the same or different.

[0032] Continue to refer to Figure 2 The number of first doped regions 3a is one. Among them, part of the second doped region 3b is located in the first doped region 3a and part of it is located in the epitaxial layer 2 of the first doped region 3a along the direction parallel to the substrate layer 1 towards the terminal region A.

[0033] In this embodiment, the number of second doped regions 3b is one.

[0034] In other embodiments, there may be multiple second doped regions 3b, which are spaced apart along a direction parallel to the surface of the substrate layer 1; the second doped regions 3b and the first doped region 3a are spaced apart, or at least a portion of the second doped regions 3b are located within the first doped region 3a. When there are multiple second doped regions 3b and the second doped regions 3b extend into a portion of the terminal region A, the second doped region 3b closest to the terminal region A extends into the portion of the terminal region A. The width dimensions of the multiple second doped regions 3b along the surface parallel to the substrate layer 1 may be the same or different; the distances between adjacent second doped regions 3b may be the same or different.

[0035] refer to Figure 3 , Figure 3 This is a top view of a semiconductor device. Figure 1 and Figure 2 All along Figure 3 A schematic diagram of the cross-section obtained from the mid-section line MM'. Figure 3 The term "zone B surrounds terminal area A" specifically means that zone B encircles terminal area A.

[0036] In one embodiment, the doped region 3 has a ring structure. In this embodiment, the first doped region 3a has a ring structure, and the second doped region 3b has a ring structure.

[0037] In one embodiment, the semiconductor device further includes: a cutoff region 4 located in the terminal region A, the cutoff region 4 being in contact with a doped region 3 extending into a portion of the terminal region A; or, the cutoff region 4 and the doped region 3 extending into a portion of the terminal region A are spaced apart; the cutoff region 4 and the epitaxial layer 2 have the same conductivity type, and the doping concentration of the cutoff region 4 is greater than the doping concentration of the epitaxial layer 2.

[0038] In this embodiment, the cutoff region 4 has a ring structure and the doped region 3 surrounds the cutoff region 4.

[0039] When the first doped region 3a extends into part of the terminal region A and the second doped region 3b does not extend into part of the terminal region A, the cutoff region 4 is in contact with or spaced apart from the first doped region 3a; when the second doped region 3b extends into part of the terminal region A and the first doped region 3a does not extend into part of the terminal region A, the cutoff region 4 is in contact with or spaced apart from the second doped region 3b; when both the first doped region 3a and the second doped region 3b extend into part of the terminal region A, the cutoff region 4 may be in contact with both the first doped region 3a and the second doped region 3b, or the cutoff region 4 may be spaced apart from both the first doped region 3a and the second doped region 3b, or the cutoff region 4 may be in contact with one of the first doped region 3a and the second doped region 3b and spaced apart from the other.

[0040] Figure 1 and Figure 2In the illustration, the cutoff region 4 is spaced apart from the first doped region 3a and is in contact with the second doped region 3b. Other embodiments are not limited to this.

[0041] In this embodiment, the depth of the cutoff region 4 is equal to the depth of the second doped region 3b. In other embodiments, the depth of the cutoff region is greater than or less than the depth of the second doped region.

[0042] In one embodiment, the substrate 1 has an N-type conductivity and is made of N-type silicon carbide; the epitaxial layer 2 has an N-type conductivity and is made of N-type silicon carbide. In other embodiments, the substrate and the epitaxial layer have P-type conductivity, and the materials of the substrate and the epitaxial layer are not limited.

[0043] In one embodiment, the doping concentration of epitaxial layer 2 is lower than that of substrate layer 1. In a specific embodiment, the doping concentration of epitaxial layer 2 is 1E14cm⁻¹. -3 ~5E16cm -3 For example, 1E14cm -3 2E15cm -3 4E15cm -3 Or 5E16cm -3 In other embodiments, the doping concentration of the epitaxial layer is not limited.

[0044] Continue to refer to Figure 1 and Figure 2 The semiconductor device also includes a buffer layer 5 located between the substrate layer 1 and the epitaxial layer 2. The buffer layer 5 and the epitaxial layer 2 have the same conductivity type, and the doping concentration of the buffer layer 5 is less than that of the substrate layer 1 but greater than that of the epitaxial layer 2.

[0045] In one embodiment, the buffer layer 5 has an N-type conductivity and is made of an N-type silicon carbide epitaxial layer. In other embodiments, the buffer layer has a P-type conductivity, and the material of the buffer layer is not limited.

[0046] In one embodiment, the doping concentration of the buffer layer 5 is 5E17cm. -3 ~5E18cm -3 For example, 5E17cm -3 Or 5E18cm -3 In other embodiments, the doping concentration of the buffer layer is not limited.

[0047] In one embodiment, the conductivity type of the cutoff region 4 is N-type, and the doping concentration of the cutoff region 4 is greater than 5E18cm. -3 In other embodiments, the conductivity type of the cutoff region is P-type, and there is no limitation on the doping concentration of the cutoff region.

[0048] In one embodiment, the epitaxial layer 2 further includes an active region C, which is surrounded by a terminal region A. The active region C includes a well region 6 and a source region 7 located within the well region 6. The well region 6 and the first doped region 3a have the same conductivity type, doping concentration, and depth. The source region 7 and the second doped region 3b have the same conductivity type, doping concentration, and depth. The well region 6 and the first doped region 3a employ the same ion implantation process, and the source region 7 and the second doped region 3b employ the same ion implantation process, which helps to reduce process complexity.

[0049] In one embodiment, the doping concentration of the first doped region 3a is less than the doping concentration of the second doped region 3b, and the depth of the first doped region 3a is greater than the depth of the second doped region 3b. It is known that the doping concentration of the well region 6 is less than the doping concentration of the source region 7, and the depth of the well region 6 is greater than the depth of the source region 7. In other embodiments, the doping concentration of the first doped region may be greater than the doping concentration of the second doped region, ensuring that the doping concentrations of the first and second doped regions are different; the depth of the first doped region may also be less than or equal to the depth of the second doped region, in which case the first and second doped regions are formed independently using two ion implantation processes.

[0050] In one embodiment, the conductivity type of the well region 6 is P-type, and the doping concentration of both the well region 6 and the first doped region 3a is 1E16cm⁻¹. -3 ~5E18cm -3 For example, 1E16cm -3 3E16cm -3 4E17cm -3 Or 5E18cm -3 The conductivity type of source region 7 is P-type, and the doping concentration of both source region 7 and the second doped region 3b is greater than 5E18cm⁻¹. -3 In other embodiments, the conductivity type of the well region is N-type, the conductivity type of the source region is N-type, and there are no restrictions on the doping concentration and depth of the well region, the first doped region, the source region, and the second doped region.

[0051] In one embodiment, the terminal region A further includes a terminal ion implantation region 8 located between the cutoff region 4 and the active region C. The terminal ion implantation region 8 includes a first terminal ion implantation region 8a and a second terminal ion implantation region 8b spaced apart. The first terminal ion implantation region 8a has the same conductivity type, doping concentration, and depth as the well region 6 and the first doped region 3a. The second terminal ion implantation region 8b has the same conductivity type, doping concentration, and depth as the source region 7 and the second doped region 3b. The first terminal ion implantation region 8a uses the same ion implantation process as the well region 6 and the first doped region 3a, and the second terminal ion implantation region 8b uses the same ion implantation process as the source region 7 and the second doped region 3b, which helps to further reduce process complexity.

[0052] In one embodiment, the doping concentration of the first terminal ion implantation region 8a is less than the doping concentration of the second terminal ion implantation region 8b, and the depth of the first terminal ion implantation region 8a is greater than the depth of the second terminal ion implantation region 8b. In other embodiments, this is not the only limitation.

[0053] Figure 3 The diagram illustrates that the terminal region A surrounds the active region C, specifically meaning that the terminal region A encircles the active region C. That is, the terminal ion implantation region 8 surrounds the trap region 6 and the source region 7. In this embodiment, the terminal ion implantation region 8 has a ring structure, the first terminal ion implantation region 8a has a ring structure, and the second terminal ion implantation region 8b has a ring structure.

[0054] In one embodiment, the first terminal ion implantation region 8a is located between the second terminal ion implantation region 8b and the cutoff region 4, and the first terminal ion implantation region 8a and the cutoff region 4 are spaced apart; the second terminal ion implantation region 8b is located between the trap region 7 and the second terminal ion implantation region 8b, and the second terminal ion implantation region 8b is in contact with the trap region 7.

[0055] In this embodiment, the first terminal ion implantation region 8a is the main junction, and the second terminal ion implantation region 8b is the terminal structure. The first terminal ion implantation region 8a and the second terminal ion implantation region 8b are structures known in the art. Figure 1 and Figure 2 In the illustration, the second terminal ion implantation region 8b includes several spaced field confinement rings. In other embodiments, the second terminal ion implantation region may employ other terminal structures.

[0056] In one embodiment, the semiconductor device further includes: a passivation layer 9 located on the side surface of a portion of the terminal region A away from the substrate layer 1, the passivation layer 9 covering the terminal ion implantation region 8, the cutoff region 4 and the portion of the doped region 3; and a protective layer 10 covering the side surface of the passivation layer 9 away from the substrate layer 1 and the side surface of the passivation layer 9.

[0057] In one embodiment, the passivation layer 9 is made of an insulating material, and the protective layer 10 includes a polyimide layer.

[0058] In one embodiment, the semiconductor device further includes: a front electrode 11, at least a portion of which is located on the side surface of the source region 7 away from the substrate layer 1; and a back electrode 12, located on the side surface of the substrate layer 1 away from the epitaxial layer 2.

[0059] In this embodiment, the front electrode 11 is the source electrode and the back electrode 12 is the drain electrode.

[0060] In one embodiment, the semiconductor device includes a power semiconductor device, such as a silicon carbide metal-oxide-semiconductor field-effect transistor.

[0061] refer to Figure 4 Another embodiment of the present invention provides a method for fabricating a semiconductor device, comprising:

[0062] S1: An epitaxial layer is formed on the substrate layer, the epitaxial layer including a termination region and a scribe line region surrounding the termination region;

[0063] S2: Forming doped regions in the dicing channel region and part of the terminal region, wherein forming doped regions includes: forming a first doped region and a second doped region in the dicing channel region and part of the terminal region respectively; the first doped region and the second doped region have the same conductivity type but different doping concentrations; the substrate layer and the epitaxial layer have the same conductivity type but opposite conductivity type to the first doped region.

[0064] The method for fabricating a semiconductor device further includes: forming a cutoff region in a terminal region; the cutoff region and a doped region extending into a portion of the terminal region being in contact; or, the cutoff region and the doped region extending into the portion of the terminal region being spaced apart; the cutoff region and the epitaxial layer having the same conductivity type, and the doping concentration of the cutoff region being greater than the doping concentration of the epitaxial layer.

[0065] The epitaxial layer also includes an active region, and the terminal region surrounds the active region; the method for fabricating the semiconductor device further includes: forming a well region in the active region, and during the formation of the well region, forming a first doped region in the dicing channel region and a portion of the terminal region; and forming a source region in the well region, and during the formation of the source region, forming a second doped region in the dicing channel region and a portion of the terminal region.

[0066] The following is for reference. Figures 5 to 12 It provides a detailed introduction to the fabrication process of semiconductor devices.

[0067] refer to Figure 5 An epitaxial layer 2 is formed on the substrate layer 1. The epitaxial layer 2 includes a termination region A and a scribe line region B surrounding the termination region A. Specifically, the scribe line region B surrounds the termination region A.

[0068] In this embodiment, the epitaxial layer 2 further includes an active region C, and a terminal region A surrounds the active region C. Specifically, the terminal region A surrounds the active region C.

[0069] The conductivity type of substrate layer 1, the conductivity type of epitaxial layer 2, and the doping concentration are described in the foregoing embodiments.

[0070] In this embodiment, before forming the epitaxial layer 2 on the substrate layer 1, a buffer layer 5 is further formed on the substrate layer 1. In other embodiments, the buffer layer may not be formed.

[0071] The conductivity type and doping concentration of buffer layer 5 are described in the foregoing embodiments.

[0072] Reference Figures 6 to 9A doped region 3 is formed in the dicing region B and part of the terminal region A; a terminal ion implantation region 8 is formed in the terminal region A; and a well region 6 is formed in the active region C, and a source region 7 is formed in the well region 6.

[0073] In one embodiment, forming a doped region 3 in the dicing region B and a portion of the terminal region A includes forming a first doped region 3a and a second doped region 3b in the dicing region B and the portion of the terminal region A, respectively; the first doped region 3a and the second doped region 3b have the same conductivity type but different doping concentrations. The relationship between the doping concentrations and depths of the first doped region 3a and the second doped region 3b is described in the foregoing embodiments.

[0074] In this embodiment, forming a doped region 3 in the dicing region B and a portion of the terminal region A includes: forming a first doped region 3a in the dicing region B and a portion of the terminal region A, followed by forming a second doped region 3b in the dicing region B and a portion of the terminal region A. In other embodiments, the second doped region may be formed first, followed by the formation of the first doped region.

[0075] In one embodiment, forming a terminal ion implantation region 8 in the terminal region A includes forming a first terminal ion implantation region 8a and a second terminal ion implantation region 8b in the terminal region A. The second terminal ion implantation region 8b is located between the well region 7 and the second terminal ion implantation region 8b, and the second terminal ion implantation region 8b is in contact with the well region 7. The relationship between the doping concentration and depth of the first terminal ion implantation region 8a and the second terminal ion implantation region 8b is described in the foregoing embodiments.

[0076] In this embodiment, forming a terminal ion implantation region 8 in terminal region A includes: forming a first terminal ion implantation region 8a in terminal region A, and then forming a second terminal ion implantation region 8b in terminal region A. In other embodiments, the second terminal ion implantation region may be formed first, followed by the formation of the first terminal ion implantation region.

[0077] For details, please refer to Figure 6 A patterned first mask 100 is formed on the epitaxial layer 2, exposing a portion of the surface of the epitaxial layer 2; using the patterned first mask 100 as a mask, an ion implantation process is performed on the surface of the epitaxial layer 2 to form a first doped region 3a in the dicing region B and a portion of the terminal region A.

[0078] Figure 6 In this embodiment, there are multiple first doped regions 3a, which are spaced apart along a direction parallel to the surface of the substrate layer 1. The first doped region 3a closest to the terminal region A extends into a portion of the terminal region A. In other embodiments, there is only one first doped region 3a.

[0079] In this embodiment, we continue to refer to Figure 6 Simultaneously, a first terminal ion implantation region 8a is formed in the terminal region A, and a well region 6 is formed in the active region C. The first terminal ion implantation region 8a has the same conductivity type, doping concentration, and depth as the well region 6 and the first doped region 3a. This helps reduce process complexity. In other embodiments, the order of forming the first doped region, the first terminal ion implantation region, and the well region is not limited.

[0080] In this embodiment, the first terminal ion implantation region 8a is the main junction.

[0081] refer to Figure 7 Remove the patterned first mask 100.

[0082] refer to Figure 8 A patterned second mask 200 is formed on the epitaxial layer 2. The patterned second mask 200 covers the first terminal ion implantation region 8a and part of the well region 6, and exposes part of the surface of the epitaxial layer 2, part of the surface of the well region 6, and the surface of the first doped region 3a. Using the patterned second mask 200 as a mask, an ion implantation process is performed on the surface of the first doped region 3a and part of the epitaxial layer 2 to form a second doped region 3b in the first doped region 3a and part of the epitaxial layer 2. Part of the second doped region 3b is located in the first doped region 3a and part of it extends outside the first doped region 3a in the epitaxial layer 2. Specifically, part of the second doped region 3b is located in the first doped region 3a, part of it is located in the epitaxial layer 2 between adjacent first doped regions 3a, and part of it is located in the epitaxial layer 2 on the side of the first doped region 3a closest to the terminal region A along a direction parallel to the substrate layer 1 toward the terminal region A.

[0083] In other embodiments, the first doped region may be formed only in the dicing channel region, without forming the first doped region in the partial terminal region; alternatively, the second doped region may be formed only in the dicing channel region, without forming the second doped region in the partial terminal region. At least one of the first and second doped regions may extend into the partial terminal region.

[0084] In other embodiments, the first doped region and the second doped region are spaced apart along a direction parallel to the surface of the substrate. The first or second doped region near the termination region extends into a portion of the termination region.

[0085] In one embodiment, the number of second doped regions 3b can be one or more, and the multiple second doped regions 3b are spaced apart along a direction parallel to the surface of the substrate layer 1.

[0086] The descriptions of the doping concentration relationship, depth relationship, structure, size, and other positional relationships of the first doped region 3a and the second doped region 3b are all based on the descriptions in the foregoing embodiments.

[0087] In this embodiment, we continue to refer to Figure 8 Simultaneously, a second terminal ion implantation region 8b is formed in the terminal region A, and a source region 7 is formed in the well region 6. The second terminal ion implantation region 8b has the same conductivity type, doping concentration, and depth as the well region 6 and the second doped region 3b. This helps reduce process complexity. In other embodiments, the order of forming the second doped region, the second terminal ion implantation region, and the source region is not limited.

[0088] In this embodiment, the second terminal ion implantation region 8b includes a plurality of spaced field confinement rings. In other embodiments, the second terminal ion implantation region may employ other terminal structures.

[0089] refer to Figure 9 Remove the patterned second mask 200.

[0090] Reference Figure 10 and Figure 11 A cutoff region 4 is formed in the terminal region A. The cutoff region 4 is located between the doped region 3 and the terminal ion implantation region 8. Specifically, the first terminal ion implantation region 8a is located between the second terminal ion implantation region 8b and the cutoff region 4, and the first terminal ion implantation region 8a and the cutoff region 4 are spaced apart.

[0091] Specifically, refer to Figure 10 A patterned third mask 300 is formed on the epitaxial layer 2. The patterned third mask 300 covers the first terminal ion implantation region 8a, the second terminal ion implantation region 8b, the trap region 6, the source region 7, the first doped region 3a, and the second doped region 3b, and exposes part of the surface of the epitaxial layer 2. Using the patterned third mask 300 as a mask, an ion implantation process is performed on the surface of the epitaxial layer 2 to form a cutoff region 4 in the terminal region A.

[0092] In one embodiment, the cutoff region 4 and the doped region 3 extending into the partial terminal region A are in contact; or, the cutoff region 4 and the doped region 3 extending into the partial terminal region A are spaced apart.

[0093] For a description of the structure, conductivity type, doping concentration, and depth of the cutoff region 4, please refer to the description in the foregoing embodiments.

[0094] In this embodiment, the first doped region 3a closest to the terminal region A extends into a portion of the terminal region A and is spaced apart from the cutoff region 4. The second doped region 3b is located in the epitaxial layer 2 of the first doped region 3a closest to the terminal region A, which is parallel to the substrate layer 1 and faces the terminal region A, and is in contact with the second doped region 3b.

[0095] refer to Figure 11 Remove the patterned third mask 300.

[0096] refer to Figure 12 A passivation layer 9 is formed on the side surface of the terminal region A opposite to the substrate layer 1; a protective layer 10 is formed on the side surface of the passivation layer 9 opposite to the substrate layer 1 and on the side surface of the passivation layer 9; a front electrode 11 is formed on the side surface of the source region 7 opposite to the substrate layer 1; and a back electrode 12 is formed on the side surface of the substrate layer 1 opposite to the epitaxial layer 2.

[0097] The passivation layer 9 covers the terminal ion implantation region 8, the cutoff region 4, and the partially doped region 3. In this embodiment, the front electrode 11 is the source electrode, and the back electrode 12 is the drain electrode.

[0098] In this embodiment, the front electrode 11 can be formed after the passivation layer 9 and the protective layer 10 are formed sequentially; and the back electrode 12 can be formed after the front electrode 11 is formed. Alternatively, the passivation layer 9 and the protective layer 10 can be formed sequentially after the front electrode 11 is formed; and the back electrode 12 can be formed after the passivation layer 9 and the protective layer 10 are formed sequentially. There is no limitation on the process order of the passivation layer 9, the protective layer 10, the back electrode 12, and the front electrode 11.

[0099] It should be understood that the terms "mechanism," "device," "component," etc., used in this application are merely one method of distinguishing different components, elements, parts, sections, or assemblies at different levels. However, if other terms can achieve the same purpose, they can be replaced by other expressions.

[0100] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention. In practical applications, the technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification, and various changes can be made to them in form and detail without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized by, Comprising: a substrate layer; an epitaxial layer on the substrate layer, the epitaxial layer comprising a termination region and a scribe lane region surrounding the termination region; a doped region in the scribe lane region and extending into part of the termination region, the doped region comprising a first doped region and a second doped region; the first doped region and the second doped region being of the same conductivity type and different doping concentration; the substrate layer and the epitaxial layer being of the same conductivity type and opposite to the conductivity type of the first doped region.

2. The semiconductor device according to claim 1, wherein The doped region is a ring structure.

3. The semiconductor device of claim 1, wherein The first doped region and the second doped region are spaced apart along a direction parallel to a surface of the substrate layer, the first doped region or the second doped region near the termination region extending into part of the termination region.

4. The semiconductor device of claim 1, wherein At least part of the second doped region is in the first doped region; wherein the first doped region and / or the second doped region extends into part of the termination region.

5. The semiconductor device according to claim 4, wherein The number of the first doped regions is multiple, and the multiple first doped regions are spaced apart along a direction parallel to a surface of the substrate layer; At least part of the second doped region is in the first doped region, and the second doped region also extends between adjacent first doped regions.

6. The semiconductor device of claim 1, wherein Further comprising: a cutoff region in the termination region, the cutoff region being in contact with the doped region extending into part of the termination region; or, the cutoff region being spaced apart from the doped region extending into part of the termination region; the cutoff region and the epitaxial layer being of the same conductivity type, and the cutoff region having a doping concentration greater than a doping concentration of the epitaxial layer.

7. The semiconductor device of claim 1, wherein The epitaxial layer further comprises an active region, the termination region surrounding the active region, the active region comprising a well region and a source region in the well region, the well region and the first doped region being of the same conductivity type, doping concentration and depth, and the source region and the second doped region being of the same conductivity type, doping concentration and depth.

8. The semiconductor device according to any one of claims 1 to 7, wherein The doping concentration of the first doped region is less than the doping concentration of the second doped region, and the depth of the first doped region is greater than the depth of the second doped region.

9. A method of manufacturing a semiconductor device, characterized by, Comprising: forming an epitaxial layer on a substrate layer, the epitaxial layer comprising a termination region and a scribe lane region surrounding the termination region; forming a doped region in the scribe lane region and part of the termination region, wherein forming the doped region comprises: forming a first doped region and a second doped region in the scribe lane region and part of the termination region, respectively; the first doped region and the second doped region being of the same conductivity type and different doping concentration; the substrate layer and the epitaxial layer being of the same conductivity type and opposite to the conductivity type of the first doped region.

10. The method of producing a semiconductor device according to Claim 9, wherein Further comprising: forming a cutoff region in the termination region; the cutoff region being in contact with the doped region extending into part of the termination region; or, the cutoff region being spaced apart from the doped region extending into part of the termination region; the cutoff region and the epitaxial layer being of the same conductivity type, and the cutoff region having a doping concentration greater than a doping concentration of the epitaxial layer.

11. The method of producing a semiconductor device according to Claim 9, wherein The epitaxial layer further comprises an active region, the termination region surrounding the active region; The method for manufacturing a semiconductor device further includes: forming a well region in the active region, in the process of forming the well region, forming a first doped region in the scribe lane region and in part of the termination region; and forming a source region in the well region, in the process of forming the source region, forming a second doped region in the scribe lane region and in part of the termination region.

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