Pseudo gate forming method and semiconductor device forming method

Abstract

The invention discloses a dummy gate forming method and a semiconductor device forming method, and the dummy gate forming method comprises the steps: providing a substrate, forming an isolation structure in the substrate, and forming a stacked structure for forming a dummy gate on the isolation structure; etching off the part, located below the side wall of the stacked structure, of the surface of the isolation structure to form a groove; and forming a pseudo gate side wall covering the side wall of the laminated structure on the substrate, wherein the groove is filled with the pseudo gate side wall. The structure on the surface of the isolation structure can be effectively protected through the part, filled in the groove, of the dummy gate side wall.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a dummy gate and a method for forming a semiconductor device. Background Technology

[0002] As the feature size of semiconductor devices continues to decrease according to Moore's Law, when the process node is below 28nm, the gate of semiconductor devices is usually made of high-k metal (HKMG). The HKMG is formed by a gate replacement process. One type of gate replacement process is the "high-k first" method, which involves forming a high-k dielectric layer in the gate formation region on the substrate surface before forming the dummy gate.

[0003] Figures la to Id The diagram shown illustrates the result of some steps in the pseudo-gate formation process in the prior art. Figure la As shown, the pseudo-gate formation process includes: forming a stacked structure 130 for constituting the pseudo-gate on a high-k dielectric layer 121, wherein the stacked structure 130 can be formed as follows: Figure la The structure shown includes a polysilicon layer 131, a silicon nitride layer 132, and a silicon oxide layer 133. To protect the stacked structure 130 from damage, the dummy gate formation process is as follows: Figure lb The diagram includes: forming a pseudo-gate sidewall 150, the pseudo-gate sidewall 150 covering the sidewall of the high-K dielectric layer 121 and the sidewall of the stacked structure 130.

[0004] However, in some semiconductor devices, the gate formation region is partially located on the isolation structure 111 included in the semiconductor substrate, such as... Figure lc As shown, the lateral etching by hydrogen fluoride (HF) in the subsequent cleaning process will cause the high-k dielectric layer 121 on the surface of the isolation structure 111 to be exposed from the location indicated by the arrow. In this way, the sulfuric acid in the subsequent cleaning process will react with the exposed high-k dielectric layer 121, thereby causing the high-k dielectric layer 121 to... Figure Id As shown, it was gradually hollowed out. Summary of the Invention

[0005] In view of the above problems, this application provides a method for forming a dummy gate and a method for forming a semiconductor device, aiming to effectively protect the structure on the surface of the isolation structure by improving the manufacturing process of the dummy gate.

[0006] According to a first aspect of the present invention, a method for forming a pseudo-gate is provided, comprising: A substrate is provided, wherein an isolation structure is formed therein, and a stacked structure for constituting a pseudo gate is formed on the isolation structure; The portion of the surface of the isolation structure located below the sidewall of the stacked structure is etched away to form a groove; A pseudo-gate sidewall is formed on the substrate, covering the sidewalls of the stacked structure, and the pseudo-gate sidewall fills the groove; The pseudo-gate sidewall includes a first portion covering the sidewall of the stacked structure and a second portion filling the groove. The thickness of the second portion is greater than the thickness of the first portion, and the thickness of the second portion is the width of the subsequent lateral etching of the isolation structure.

[0007] Optionally, a high-k dielectric layer is further formed on the isolation structure, the high-k dielectric layer being located between the isolation structure and the stacked structure.

[0008] Optionally, the pseudo-gate formation method further includes: etching away the portion of the high-K dielectric layer located below the sidewall of the stacked structure, and forming the groove after etching away the respective portions of the high-K dielectric layer and the isolation structure surface located below the sidewall of the stacked structure.

[0009] Optionally, a barrier layer is further formed on the isolation structure, the barrier layer being located between the high-k dielectric layer and the stacked structure.

[0010] Optionally, the pseudo-gate formation method further includes: etching away the portions of the barrier layer and the high-K dielectric layer located below the sidewalls of the stacked structure, and forming the groove after etching away the portions of the barrier layer, the high-K dielectric layer and the isolation structure surface located below the sidewalls of the stacked structure.

[0011] Optionally, the isolation structure is made of silicon oxide, the high-K dielectric layer is made of hafnium oxide, and the barrier layer is made of titanium nitride. The portions of the barrier layer, the high-K dielectric layer, and the surface of the isolation structure located below the sidewall of the stacked structure are etched away by a dry etching process, wherein the etching gases used in the dry etching process are boron trichloride gas and chlorine gas.

[0012] Optionally, etching away the portion of the surface of the isolation structure located below the sidewall of the stacked structure includes: etching away the portion of the surface of the isolation structure near the stacked structure, and then laterally etching away the portion of the surface of the isolation structure covered by the stacked structure until the portion of the surface of the isolation structure located below the sidewall of the stacked structure is etched away.

[0013] Optionally, a pseudo-gate sidewall is formed on the substrate to cover the sidewalls of the stacked structure, including: A protective layer is deposited on the substrate, the protective layer covering the sidewalls of the stacked structure, filling the grooves, and covering the surface of the isolation structure; The protective layer is etched so that, after the portion of the protective layer covering the surface of the isolation structure is removed, the portion of the protective layer covering the sidewalls of the stacked structure and filling the groove forms the pseudo-gate sidewall.

[0014] Optionally, the protective layer is made of silicon nitride.

[0015] According to a second aspect of the present invention, a method for forming a semiconductor device is provided, comprising: A pseudo-gate is formed by any of the pseudo-gate forming methods described in the first aspect; Source and drain regions are formed in the substrates on both sides of the dummy gate using an ion implantation process. An interlayer dielectric layer with its top flush with the dummy gate is formed on the substrates on both sides of the dummy gate; The dummy gate is removed to form a gate recess in the interlayer dielectric layer, and a metal gate replacing the dummy gate is formed in the gate recess.

[0016] The unexpected technical effect of this application is: The dummy gate formation method provided in this application involves forming a stacked structure on an isolation structure included in a substrate, then etching away the portion of the isolation structure surface located below the sidewall of the stacked structure to form a groove, and then forming a dummy gate sidewall on the substrate that covers the sidewall of the stacked structure and fills the groove. In this way, the portion of the dummy gate sidewall recessed into the groove can resist the lateral etching of hydrogen fluoride, thereby protecting the structure on the surface of the isolation structure.

[0017] Furthermore, when a high-K dielectric layer is formed on the isolation structure, the high-K dielectric layer located between the isolation structure and the stacked structure serves as a structure on the surface of the isolation structure, and can be protected from the portion of the dummy gate sidewall that is recessed into the groove formed by the isolation structure. In addition, when a barrier layer is also formed on the isolation structure, the barrier layer located between the high-K dielectric layer and the stacked structure serves as a structure on the surface of the isolation structure along with the high-K dielectric layer, and can also be protected from the portion of the dummy gate sidewall that is recessed into the groove formed by the isolation structure along with the high-K dielectric layer. Attached Figure Description

[0018] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which: Figure la A schematic cross-sectional view is shown after the formation of the laminated structure according to the prior art; Figure lb A schematic cross-sectional view is shown after the pseudo-gate sidewall is formed according to the prior art; Figure lc A schematic cross-sectional view of a pseudo-gate formed by prior art after the isolation structure has been laterally etched is shown; Figure Id This diagram shows a schematic cross-sectional view of a pseudogate formed by prior art after a portion of the high-k dielectric layer is hollowed out by the reaction with sulfuric acid; Figure 2 This document shows a flowchart illustrating a pseudo-gate formation method according to an embodiment of this application. Figure 3a A schematic cross-sectional view is shown after the groove is formed according to an embodiment of this application; Figure 3b A schematic cross-sectional view showing the groove after it has been filled according to an embodiment of this application; Figure 3c A schematic cross-sectional view is shown after the pseudo-grid sidewall is formed according to an embodiment of this application; Figure 3d This shows a schematic cross-sectional view of the pseudo-gate formed in the embodiments of this application after the isolation structure has been laterally etched; Figure 4 This shows a cross-sectional view of a groove formed according to an embodiment of the present application; Figure 5 A flowchart illustrating a method for forming a semiconductor device according to another embodiment of this application is shown.

[0019] Explanation of reference numerals in the attached figures: 111-Isolation structure; 121-High-K dielectric layer; 130-Layered structure; 131-Polysilicon layer; 132-Silicon nitride layer; 133-Silicon oxide layer; 140-Protective layer; 150-Dummy gate sidewall; 160-Improved dummy gate sidewall. Detailed Implementation

[0020] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0021] This application may be presented in various forms, some of which will be described below.

[0022] In the rapid development of semiconductor manufacturing technology, the thickness of the gate oxide layer in semiconductor devices has been continuously decreasing. Insufficient gate oxide thickness can cause significant carrier tunneling, a problem addressed by high-dielectric metal gates. High-dielectric metal gates use a high-dielectric-constant dielectric material instead of conventional silicon oxide as the gate dielectric layer in semiconductor devices, thus avoiding the carrier tunneling effect caused by the reduced gate dielectric layer thickness. Simultaneously, due to the Fermi level pinning effect between the high-dielectric-constant dielectric material and the semiconductor substrate, a metal material is needed instead of conventional polycrystalline silicon as the gate electrode layer in semiconductor devices. In this application, the gate dielectric layer formed by the high-dielectric-constant dielectric material is also called a high-k dielectric layer, and the gate electrode layer formed by the metal material is also called a metal gate.

[0023] In the fabrication of semiconductor devices, a high-k dielectric metal gate can be formed in the gate formation region through a gate replacement process. In the "high-k first" method, which is a gate replacement process, a high-k dielectric gate is first formed in the gate formation region on the substrate surface. Figure la The high-K dielectric layer 121 shown is then used to form a dummy gate. After the dummy gate is formed, source and drain regions are formed in the substrate on both sides of the dummy gate by ion implantation. An interlayer dielectric layer with the top of the dummy gate is formed on the substrate on both sides of the dummy gate. Then the dummy gate is removed and a groove is formed in the interlayer dielectric layer. Then the groove is filled with a metal material to form a metal gate that replaces the dummy gate in the groove.

[0024] Pseudo-gates typically include, for example: Figure lb The layered structure 130 and dummy gate sidewall 150 are shown. In some semiconductor devices, the gate formation region is partially on the isolation structure 111 included in the semiconductor substrate, such as high-voltage metal-oxide-semiconductor (HVMOS) devices. The isolation structure 111 mentioned above is, for example, a shallow trench isolation structure (STI). To illustrate the effect of the isolation structure on the high-dielectric metal gate, Figures la to Id And afterwards Figures 3a to 3d The gate formation region is entirely located on the isolation structure 111. It should be understood that this does not imply a limitation on the structure of the semiconductor device.

[0025] Semiconductor device fabrication typically requires multiple cleaning processes to remove unwanted impurities. These cleaning processes involve the sequential use of hydrogen fluoride and sulfuric acid. Hydrogen fluoride has isotropic etching capabilities on silicon oxide, and the isolation structure 111 made of silicon oxide will... Figure lcAs shown, the surface of the isolation structure 111 is laterally etched with hydrogen fluoride, which exposes the bottom of the high-k dielectric layer 121. During subsequent cleaning with sulfuric acid, the exposed high-k dielectric layer 121 reacts with the sulfuric acid, thereby causing the high-k dielectric layer 121 to... Figure Id As shown, the metal is gradually hollowed out, and the resulting semiconductor device cannot have a high-dielectric metal gate that meets the requirements, resulting in a significant decrease in product yield.

[0026] For the reasons mentioned above, this application provides a method for forming a pseudo-gate. Figure 2 The diagram shown is a flowchart of a pseudo-gate formation method provided in an embodiment of this application. Figure 2 As shown, the method for forming a pseudo-gate includes: Step S110: A substrate is provided, an isolation structure is formed in the substrate, and a stacked structure for forming a pseudo gate is formed on the isolation structure.

[0027] Step S120: The portion of the surface of the isolation structure located below the sidewall of the stacked structure is etched away to form a groove.

[0028] In step S130, a pseudo gate sidewall is formed on the substrate to cover the sidewalls of the stacked structure, and the pseudo gate sidewall fills the groove.

[0029] It should be noted that the pseudo-gate sidewall, as part of the pseudo-gate, protects the stacked structure from the side. Therefore, the material used for the pseudo-gate sidewall must ensure that it will not be damaged by hydrogen fluoride. In this way, after the groove formed by the isolation structure is filled by the pseudo-gate sidewall, the layer on the surface of the isolation structure that is flush with the groove will also not be damaged by hydrogen fluoride, thus effectively protecting the structure on the surface of the isolation structure.

[0030] The following is combined with Figures 3a to 3d The pseudo-gate formation method provided in the embodiments of this application will be described in detail. Figures 3a to 3d Zhongyu Figures la to Id The parts with the same structure shown will not be repeated in the following description unless necessary.

[0031] like Figure 3a As shown, an isolation structure 111 is formed within the substrate, and a stacked structure 130 is formed on the isolation structure 111. In some examples, the stacked structure 130 may be located indirectly on the surface of the isolation structure 111 without contacting it, for example, in the "high-K first" method, it is formed on the isolation structure 111. Figure 3a The high-K dielectric layer 121 shown is then used to form a pseudo-gate. The high-K dielectric layer 121 is located between the isolation structure 111 and the stacked structure 130. Therefore, as a structure on the surface of the isolation structure 111, the high-K dielectric layer 121 can be protected by the portion of the pseudo-gate sidewall that is recessed into the groove formed by the isolation structure 111.

[0032] In the case where a high-K dielectric layer 121 is also formed on the isolation structure 111, the dummy gate formation method provided in this application embodiment may further include: etching away the portion of the high-K dielectric layer 121 located under the sidewall of the stacked structure 130. After the portions of the high-K dielectric layer 121 and the isolation structure 111 located under the sidewall of the stacked structure 130 are etched away, a groove filled by the dummy gate sidewall 150 is formed. In this way, the etchant used in the groove formation process allows the isolation structure 111 and the high-K dielectric layer 121 to be etched simultaneously. The etchant only needs to avoid etching the polysilicon layer 131 included in the stacked structure 130 during the groove formation process.

[0033] Furthermore, a barrier layer can also be formed on the isolation structure 111, the barrier layer being located on... Figure 3a The high-k dielectric layer 121 and the stacked structure 130 shown are used to block the diffusion of the metal material forming the metal gate into the high-k dielectric layer 121 after the high-k metal gate is formed, so the blocking layer is not removed during the removal of the dummy gate. Figure 3a The barrier layer is not shown, but it should be understood that the barrier layer is located in Figure 3a The high-K dielectric layer 121 and the stacked structure 130 shown are together, and thus together with the high-K dielectric layer 121, as a structure on the surface of the isolation structure 111, can be protected together with the high-K dielectric layer 121 from the portion of the pseudo-gate sidewall recessed into the groove formed by the isolation structure 111.

[0034] In the case where a barrier layer is also formed on the isolation structure 111, the dummy gate formation method provided in this application embodiment may further include: etching away the portion of the barrier layer located below the sidewall of the stacked structure 130. After the portions of the barrier layer, the high-K dielectric layer 121 and the isolation structure 111 located below the sidewall of the stacked structure 130 are etched away, a groove filled by the dummy gate sidewall 150 is formed. In this way, the etchant used in the groove formation process allows the isolation structure 111, the high-K dielectric layer 121 and the barrier layer to be etched simultaneously. The etchant only needs to avoid etching the polysilicon layer 131 included in the stacked structure 130 during the groove formation process.

[0035] When the isolation structure 111 is made of silicon oxide (SiO2), the high-K dielectric layer 121 is made of hafnium oxide (HfO2), and the barrier layer is made of titanium nitride (TiN), the portions of the barrier layer, the high-K dielectric layer 121, and the isolation structure 111 located below the sidewalls of the stacked structure 130 are etched away using a dry etching process. The etching gases used in the dry etching process are boron trichloride (BCl3) and chlorine (Cl2). It should be noted that a mixture of boron trichloride and chlorine is used in the etching process of the high-K dielectric layer 121 because pure chlorine does not react with hafnium oxide. However, when boron trichloride is mixed with chlorine, chlorine can react with hafnium oxide. This is because boron trichloride can form an intermediate with the oxygen atoms in hafnium oxide, making it easier for the oxygen atoms in hafnium oxide to be replaced by chlorine atoms in chlorine to form chlorides.

[0036] Furthermore, by setting the concentration ratio of chlorine in the chlorine-boron trichloride mixture, the mixture exhibits high selectivity for silicon oxide, hafnium oxide, and silicon nitride. Therefore, the polycrystalline silicon layer 131 is not damaged during the removal of the portions of the barrier layer (TiN), the high-k dielectric layer 121 (hafnium oxide), and the isolation structure 111 (silicon oxide) located below the sidewalls of the stacked structure 130. In one embodiment, the chlorine concentration ratio {chlorine / (chlorine + boron trichloride)} in the chlorine-boron trichloride mixture is 20% to 45%.

[0037] Specifically, the etching away of the portion of the surface of the isolation structure 111 located below the sidewall of the stacked structure 130 is performed after the formation of the trench dummy gate stacked structure 130, as shown above. Figure 3a The process involves etching away a portion of the surface of the isolation structure 111 at a height of h near the stacked structure 130, followed by lateral etching of the portion of the surface of the isolation structure 111 covered by the stacked structure at a height of h, until the portion of the surface of the isolation structure 111 located below the sidewall of the stacked structure 130 is etched away, thereby forming a groove with a height of h and a width of d on the isolation structure 111. Dry etching has strong directionality. In the process of using dry etching to remove the portion of the surface of the isolation structure 111 located below the sidewall of the stacked structure 130, the portion of the surface of the isolation structure 111 near the stacked structure 130 can be etched away first using downward dry etching, and then the portion of the surface of the isolation structure 111 located below the sidewall of the stacked structure 130 can be etched away using lateral dry etching. In an example where the barrier layer and high-K dielectric layer 121 need to be etched, the portions of the barrier layer, high-K dielectric layer 121, and isolation structure 111 located under the sidewalls of the stacked structure 130 are etched away in one piece by lateral dry etching to form a groove.

[0038] Reference Figure 3bThe aforementioned formation of a pseudo-gate sidewall covering the sidewalls of the stacked structure 130 on the substrate may include: depositing a protective layer 140 on the substrate, the protective layer 140 covering the sidewalls of the stacked structure 130, filling the grooves, and covering the surface of the isolation structure 111; see reference. Figure 3c The aforementioned formation of a pseudo-gate sidewall covering the sidewalls of the stacked structure 130 on the substrate further includes: etching a protective layer 140 such that, after a portion of the protective layer 140 covering the surface of the isolation structure 111 is removed, the sidewalls of the stacked structure 130 and the portion filling the groove are formed by the protective layer 140 covering the sidewalls of the stacked structure 130 and the portion filling the groove. Figure 3c The improved pseudo-gate sidewall 160 is shown. The protective layer 140 is made of, for example, silicon nitride.

[0039] Furthermore, Figure 3c The dummy gate sidewall 160 shown includes a first portion covering the sidewall of the stacked structure 130 and a second portion filling the groove, wherein the first portion has a first thickness w1, the second portion has a second thickness w2, and the second thickness w2 is greater than the first thickness w1.

[0040] Even after the improved pseudo-gate sidewall 160 with the aforementioned filling groove is formed, hydrogen fluoride will still etch it during the subsequent cleaning process. Figure 3c The middle isolation structure 111 is located on the surface of the outer portion of the improved pseudo-gate sidewall 160, specifically as follows: Figure 3d The diagram shows that after the surface of the isolation structure 111 outside the improved dummy gate sidewall 160 is etched, the portion of the isolation structure 111 below the improved dummy gate sidewall 160 is etched. It should be noted that the cleaning process duration and the amount of hydrogen fluoride used are limited, thus the width of the hydrogen fluoride lateral etching of the isolation structure 111 during the cleaning process is limited. Therefore, as long as the thickness w2 of the second portion is greater than the width w3 of the hydrogen fluoride lateral etching of the isolation structure 111, the structure on the surface of the isolation structure 111 will not be damaged.

[0041] Reference Figure 3dAfter step S120 is performed, the groove formed on the isolation structure 111 is filled with a portion of the improved dummy gate sidewall 160, which can be considered as forming an isolation layer at the corner of the bottom of the stacked structure 130. This isolation layer protects the structure on the surface of the isolation structure 111 during the subsequent cleaning process, preventing the structure on the surface of the isolation structure 111 from contacting sulfuric acid and thus preventing it from being hollowed out due to reaction with sulfuric acid. In some examples where a high-k dielectric layer 121 or even a barrier layer is also formed on the surface of the isolation structure 111, the portions of the high-k dielectric layer 121 and the barrier layer located under the sidewall of the stacked structure 130 are not etched away to form the groove that fills a portion of the improved dummy gate sidewall 160, and the high-k dielectric layer 121 and the barrier layer are also effectively protected. As the gate dielectric layer of the high-k metal gate of the semiconductor device formed later, the high-k dielectric layer 121 can be effectively protected without etching away a portion of it, which is of great significance for improving the quality of the high-k metal gate of the semiconductor device. The barrier layer, as an important structure in high-dielectric metal gates, prevents the diffusion of the metal material of the gate electrode layer into the gate dielectric layer. It can be effectively protected without etching away a portion of it, and is of great significance for improving the quality of high-dielectric metal gates in semiconductor devices.

[0042] Figure 4 The image shown is a cross-sectional view of a groove formed according to an embodiment of this application. The thick black horizontal lines in the cross-sectional view represent a barrier layer, and above the barrier layer is... Figure 3a The schematic layered structure 130 shows a barrier layer below which is an adjacent layer on the bottom surface of the barrier layer. Figure 3a The diagram illustrates a high-k dielectric layer 121 and an isolation structure 111 below the high-k dielectric layer 121, with a width greater than that of the high-k dielectric layer 121. (See diagram for reference.) Figure 4 As shown, the portions of the barrier layer, high-K dielectric layer 121 and isolation structure 111 located below the sidewall of the stacked structure 130 are etched away to form a groove with a width of d, while the stacked structure 130 still maintains a vertical sidewall, that is, the original morphology of the stacked structure 130 is not changed because the portion of the underlying structure below the sidewall of the stacked structure 130 is etched away.

[0043] Corresponding to the pseudo-gate formation method provided in the above embodiments, another embodiment of this application also provides a method for forming a semiconductor device. Figure 5 The diagram shown is a flowchart of an exemplary method for forming a semiconductor device according to an embodiment of this application. Figure 5 As shown, the method for forming the semiconductor device includes: A pseudo-gate is formed through steps S110 to S130; Step S140: Source and drain regions are formed in the substrate on both sides of the dummy gate by ion implantation. Step S150: An interlayer dielectric layer with its top flush with the dummy gate is formed on the substrates on both sides of the dummy gate. Step S160: Remove the dummy gate and form a gate trench in the interlayer dielectric layer, and form a metal gate in the gate trench to replace the dummy gate.

[0044] For a detailed description of steps S110 to S160, please refer to the above description of the pseudo-gate formation method, which will not be repeated here.

[0045] The semiconductor device formation method provided in this application embodiment includes an improved dummy gate sidewall 160 formed by steps S110 to S130. The improved dummy gate sidewall 160 fills the groove on the surface of the isolation structure 111 located under the sidewall of the stacked structure 130. Therefore, the structure on the surface of the isolation structure 111 can be effectively protected, thereby allowing the high-k dielectric layer 121 and the barrier layer on the surface of the isolation structure 111 to be not etched to ensure that the high-k dielectric layer 121 and the barrier layer are not hollowed out. Furthermore, the shape of the stacked structure 130 constituting the dummy gate is not affected during the dummy gate formation process. Therefore, the semiconductor device finally formed has a high-quality high-dielectric metal gate, the semiconductor device yield is high, and the electrical performance of the semiconductor device is not adversely affected.

[0046] As described above, these embodiments of this application do not exhaustively cover all details, nor do they limit the application to merely the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A method for forming a pseudo-gate, comprising: A substrate is provided, wherein an isolation structure is formed therein, and a stacked structure for constituting a pseudo gate is formed on the isolation structure; The portion of the surface of the isolation structure located below the sidewall of the stacked structure is etched away to form a groove; A pseudo-gate sidewall is formed on the substrate, covering the sidewalls of the stacked structure, and the pseudo-gate sidewall fills the groove; The pseudo-gate sidewall includes a first portion covering the sidewall of the stacked structure and a second portion filling the groove. The thickness of the second portion is greater than the thickness of the first portion, and the thickness of the second portion is the width of the subsequent lateral etching of the isolation structure.

2. The method for forming a pseudo-gate according to claim 1, wherein, A high-k dielectric layer is also formed on the isolation structure, and the high-k dielectric layer is located between the isolation structure and the stacked structure.

3. The pseudo-gate formation method according to claim 2 further includes: The groove is formed by etching away the portion of the high-K dielectric layer located below the sidewall of the stacked structure, and the portions of the high-K dielectric layer and the isolation structure surface located below the sidewall of the stacked structure.

4. The method for forming a pseudo-gate according to claim 2, wherein, A barrier layer is also formed on the isolation structure, and the barrier layer is located between the high-k dielectric layer and the stacked structure.

5. The pseudo-gate formation method according to claim 4 further includes: The portion of the barrier layer and the high-K dielectric layer located below the sidewall of the stacked structure is etched away, and the groove is formed after the portion of the barrier layer, the high-K dielectric layer and the isolation structure surface located below the sidewall of the stacked structure is etched away.

6. The method for forming a pseudo-gate according to claim 5, wherein, The isolation structure is made of silicon oxide, the high-K dielectric layer is made of hafnium oxide, and the barrier layer is made of titanium nitride. The portions of the barrier layer, the high-K dielectric layer, and the surface of the isolation structure located below the sidewall of the stacked structure are etched away by a dry etching process, wherein the etching gases used in the dry etching process are boron trichloride gas and chlorine gas.

7. The method for forming a pseudo-gate according to claim 1, wherein, Etching away the portion of the surface of the isolation structure located below the sidewall of the stacked structure includes: etching away the portion of the surface of the isolation structure near the stacked structure, and then laterally etching away the portion of the surface of the isolation structure covered by the stacked structure until the portion of the surface of the isolation structure located below the sidewall of the stacked structure is etched away.

8. The method for forming a pseudo-gate according to claim 7, wherein, Forming a pseudo-gate sidewall covering the sidewalls of the stacked structure on the substrate includes: A protective layer is deposited on the substrate, the protective layer covering the sidewalls of the stacked structure, filling the grooves, and covering the surface of the isolation structure; The protective layer is etched so that, after the portion of the protective layer covering the surface of the isolation structure is removed, the portion of the protective layer covering the sidewalls of the stacked structure and filling the groove forms the pseudo-gate sidewall.

9. The method for forming a pseudo-gate according to claim 8, wherein, The protective layer is made of silicon nitride.

10. A method for forming a semiconductor device, comprising: A pseudo-gate is formed by the pseudo-gate forming method according to any one of claims 1-9; Source and drain regions are formed in the substrates on both sides of the dummy gate using an ion implantation process. An interlayer dielectric layer with its top flush with the dummy gate is formed on the substrates on both sides of the dummy gate; The dummy gate is removed to form a gate recess in the interlayer dielectric layer, and a metal gate replacing the dummy gate is formed in the gate recess.

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