Semiconductor device and method of forming image sensor on substrate

Abstract

A semiconductor device and a method of forming an image sensor on a substrate are provided, and systems, apparatus, and methods are described that protect isolation trench structures from charge damage during plasma-based BEOL deposition and etch steps. Apparatus and methods may include an image sensor having an array isolation trench in an array portion of an image sensor substrate including an array of pixels. The peripheral portion of the substrate may include an isolation trench coupled with the metallization layer at a front side of the substrate. The peripheral portion may also include a contact between the substrate section and the metallization layer. The substrate and the peripheral trench are maintained at the same potential during BEOL processing, thereby reducing the risk of charge damage to the isolation trench. In some embodiments, the peripheral trenches may remain isolated from the array trenches until BEOL processing is completed, such as coupled by conductive material after backside thinning. The array trenches may be coupled through the peripheral portion for biasing in a completed image sensor.

Description

Technical Field

[0001] This application generally relates to image sensors, more specifically to image sensors having trench isolation structures inserted between adjacent pixels, and particularly to a semiconductor device and a method for forming an image sensor on a substrate. Background Technology

[0002] Image sensors are used in many electronic devices, such as cameras, smartphones, and computers, to capture images and / or video, as well as other potential functions. Image sensors typically comprise an array of image pixels arranged in rows and columns. Each pixel may contain a photodiode that generates an electrical charge in response to an incident photon. The pixel array may include isolation structures between each pixel to prevent electrical crosstalk, prevent light leakage, improve internal reflections, etc.

[0003] The pixel array may be covered by a color filter array. Various circuits may be coupled to each pixel, pixel column, and / or pixel row to store generated charges, transfer such charges, convert the charges into a digital representation, and / or for other readout and processing purposes. Therefore, one or more conductive signal lines (also referred to herein as metal wiring layers or metal layers) may be connected to various structures of each pixel and / or the pixel array. The conductive signal lines may extend both inside and outside the array (referred to herein as the periphery of the sensor, or simply the periphery). In some cases, isolation structures may be biased to reduce dark current.

[0004] A back-side image sensor (BSI) may initially have processing steps performed from the front side (FS) of the image sensor's substrate. These processing steps may include forming various pixel structures (such as photodiodes, transfer transistors, and other functional components) and isolation structures within the substrate. Front-side processing may also include forming various structures, circuits, etc., in the periphery, as well as one or more metal wiring layers for the image sensor.

[0005] Various plasma processes can be used to perform the etching, deposition, and other processes required to form image sensors, particularly during the formation of metal wiring layers. However, plasma processes can charge various metal layers and interconnect structures. For image sensors with bias isolation structures, the isolation structures can be contacted from the front side, but excess charge from the plasma process can accumulate within the isolation structures. Excess charge can generate electric fields that can affect surrounding materials. Dielectric materials such as silicon dioxide or low-k dielectrics may be susceptible to damage from these electric fields. For example, high electric fields can cause dielectric breakdown and can lead to the formation of undesirable defects such as pinholes and voids. Back-side isolation structures can be formed after the front-side processing to avoid charge damage, but the formation of back-side trenches and back-side contacts with the trenches can be expensive.

[0006] Therefore, it is desirable to provide improved apparatus and methods for image sensors with bias isolation structures. Summary of the Invention

[0007] Various implementations relate to systems, apparatus, and methods for protecting bias array trenches from charge damage during the manufacture of image sensors or other devices.

[0008] In various embodiments, a semiconductor device may include: a substrate including an array portion and a peripheral portion; a plurality of substrate segments defined by a plurality of array trenches in the substrate, the plurality of substrate segments including a first substrate segment in the peripheral portion; a first array trench in the plurality of array trenches, wherein the first array trench traverses the array portion and the peripheral portion; a second array trench in the array portion of the plurality of array trenches, wherein the first array trench intersects with the second array trench in the array portion; a first trench contact coupled to the first array trench in the peripheral portion; a first substrate contact coupled to the first substrate segment; and a conductive signal line, wherein the conductive signal line electrically couples the first trench contact and the first substrate contact.

[0009] In various embodiments, a semiconductor device may include: a substrate including an array portion and a peripheral portion; a plurality of array trenches including: a first array trench traversing both the array portion and the peripheral portion; and a second array trench in the array portion, wherein the first array trench intersects and is electrically coupled to the second array trench; a peripheral trench in the peripheral portion, wherein the peripheral trench does not intersect with any of the plurality of array trenches; trench contacts coupled to the peripheral trenches in the peripheral portion, wherein the trench contacts are located on the front side of the substrate; and a conductive layer on the back side of the substrate, wherein the conductive layer couples the peripheral trenches to the first array trenches at the peripheral portion.

[0010] In various embodiments, a method of forming an image sensor on a substrate may include: forming a plurality of deep trenches from the front side of the substrate during a front-end process (FEOL) process, wherein the plurality of deep trenches are formed in an array portion and a peripheral portion of the substrate; and a first trench among the plurality of deep trenches includes an array trench traversing the array portion and the peripheral portion; forming substrate contacts of the substrate adjacent to the first trenches in the peripheral portion at the front side of the substrate during a back-end process (BEOL) process; forming electrical contacts of the first trenches in the peripheral portion; and thinning the substrate from the back side of the substrate after the BEOL process.

[0011] These and other examples are described in more detail below. Attached Figure Description

[0012] Figure 1 This is a schematic diagram illustrating an exemplary device including an image sensor according to various embodiments.

[0013] Figure 2A This is a plan view of a first exemplary arrangement of isolation trenches for an image sensor according to various embodiments.

[0014] Figure 2B It is along Figure 2A The image shows a cross-sectional side view taken along line 1-1 and in the direction of that line, illustrating the isolation trench after BEOL treatment according to various embodiments.

[0015] Figure 2C It is along Figure 2A The image shows a cross-sectional side view taken along line 1-1 and in the direction of that line, illustrating the isolation trench after thinning on the back side according to various embodiments.

[0016] Figure 3A This is a plan view of a second exemplary arrangement of isolation trenches for an image sensor according to various embodiments.

[0017] Figure 3B It is along Figure 3A The image shows a cross-sectional side view taken along line 2-2 and in the direction of that line, illustrating the isolation trench after BEOL treatment according to various embodiments.

[0018] Figure 3C It is along Figure 3A The image shows a cross-sectional side view taken along line 2-2, which illustrates the isolation trench after thinning on the back side according to various embodiments.

[0019] Figure 4A This is a cross-sectional side view showing a third exemplary arrangement of an isolation trench after BEOL treatment according to various embodiments.

[0020] Figure 4B This is a cross-sectional side view showing a third exemplary arrangement of an isolation trench after thinning on the back side according to various embodiments.

[0021] Figure 5A This is a plan view of a fourth exemplary arrangement of isolation trenches for an image sensor according to various embodiments.

[0022] Figure 5B It is along Figure 5A The cross-sectional side view taken along line 3-3 shows the isolation trench after thinning on the back side according to various embodiments.

[0023] Figure 6A This is a plan view of a fifth exemplary arrangement of isolation trenches for an image sensor according to various embodiments.

[0024] Figure 6B It is along Figure 6A The cross-sectional side view taken along line 4-4 shows the isolation trench after thinning on the back side according to various embodiments.

[0025] Figure 6C It is along Figure 6A The cross-sectional side view taken along line 4-4 shows an isolation trench coupled for biasing on the back side of an image sensor according to various embodiments.

[0026] Figure 7A This is a plan view of a sixth exemplary arrangement of isolation trenches for an image sensor according to various embodiments.

[0027] Figure 7B It is along Figure 7A The cross-sectional side view taken along line 5-5 shows an isolation trench coupled for biasing on the back side of an image sensor according to various embodiments.

[0028] Figure 8A This is a plan view of a seventh exemplary arrangement of isolation trenches for an image sensor according to various embodiments.

[0029] Figure 8B It is along Figure 8A The cross-sectional side view taken along line 6-6 shows an isolation trench coupled for biasing on the back side of an image sensor according to various embodiments.

[0030] Figure 9A This is a plan view of an eighth exemplary arrangement of isolation trenches for an image sensor according to various embodiments.

[0031] Figure 9B It is along Figure 9A The cross-sectional side view taken along line 7-7 shows an isolation trench coupled for biasing on the back side of an image sensor according to various embodiments.

[0032] Figure 10A It is a plan view of the first arrangement of the array portion and multiple peripheral portions according to various implementation schemes.

[0033] Figure 10B It is a plan view of the second arrangement of the array portion and multiple peripheral portions according to various implementation schemes.

[0034] Figure 11 This is a simplified flowchart illustrating methods for protecting array trenches during manufacturing according to various embodiments. Detailed Implementation

[0035] The following detailed description is intended to provide several examples illustrating the broader concepts set forth herein, but is not intended to limit the invention or its application and use. Furthermore, one is not expected to be bound by any theory presented in the foregoing background or the following detailed description.

[0036] Embodiments of the present invention reduce charge damage to deep trench structures (e.g., those used in pixel arrays of image sensors) caused by the BEOL process. According to various embodiments, the array isolation trench structure forming the pixel array of the image sensor can be coupled to metal wiring for biasing after the BEOL process. The array trench can be coupled to trenches or other biasing structures in the peripheral portion of the image sensor via back-side connections. According to various embodiments, the array trench can extend to the peripheral portion, wherein the trenches in the peripheral portion and the substrate are electrically shorted to the same potential during the BEOL process via metal wiring or other conductive material.

[0037] Various embodiments provide array trenches that can be biased via electrical coupling in the peripheral portion of the image sensor. The substrate in the array portion can be isolated from the trenches and substrate in the peripheral portion after BEOL processing and can be biased separately from the substrate in the peripheral portion (e.g., grounded) during image sensor operation. In some embodiments, the substrate in the peripheral portion can be biased to the same voltage (e.g., -4V) as the trench in the periphery. Some embodiments provide stacked via contacts with the trenches, these stacked via contacts having a minimized area to minimize the metal antenna ratio. Some embodiments may provide a protection diode in the substrate adjacent to the trench in the peripheral portion.

[0038] Advantageously, the systems, apparatus, and methods according to this specification provide an improved trench isolation structure that can be biased during operation of the image sensor 14. Due to fewer defects and damage caused by the BEOL process, the improved trench isolation structure can have improved performance, and it can be implemented with relatively inexpensive process steps.

[0039] Figure 1 An electronic device 10 having a camera module, such as that described herein, is illustrated. The camera module 12 (sometimes referred to as an imaging device or imaging system) may include one or more image sensors 14 and one or more lenses 28. During operation, the lenses 28 focus light onto the image sensor 14. The image sensor 14 includes a photosensitive element, such as a photodiode, that converts incident photons into electrical charges. The image sensor may have any number (e.g., hundreds, thousands, millions, or more) of pixels, each including a photosensitive element. The image sensor 14 may include bias circuitry, sample-and-hold circuitry, correlated double sampling (CDS) circuitry, amplifier circuitry, analog-to-digital converter (ADC) circuitry, data output circuitry, memory circuitry, address circuitry, etc.

[0040] Still image data and video image data from image sensor 14 can be provided to image processing circuit 16 via communication path 26. Image processing circuit 16 can be used to perform image processing functions such as autofocus, depth sensing, data formatting, white balance and exposure adjustment, video image stabilization, face detection, etc. Image processing circuit 16 can also be used to compress raw camera image files as needed (e.g., compress to Joint Image Experts Group format or JPEG format).

[0041] In some arrangements (sometimes referred to as a system-on-a-chip (SOC) arrangement), the image sensor 14 and the image processing circuitry 16 are implemented on a common integrated circuit. In other arrangements, the image sensor 14 and the image processing circuitry 16 may be implemented using separate integrated circuits. For example, the image sensor 14 and the image processing circuitry 16 may be formed on separate, stacked substrates.

[0042] In some arrangements, the image sensor 14 may include a bonded substrate. For example, in a back-illuminated (BSI) image sensor, the pixel array, peripheral structures, circuitry, and metal wiring layers may be formed from the front side of the first substrate before the first substrate is flipped for additional processing (such as back-side thinning, passivation, color filter arrays, and microlens formation). The metal wiring layers may be used to connect various components of the pixels (such as photodiodes and readout circuitry) to control and data processing circuitry or other related circuitry or structures elsewhere on the image sensor 14. The front side of the first substrate may be bonded to a second substrate, for example, containing additional pixel control and / or storage structures, readout circuitry, and / or other control and processing circuitry.

[0043] Camera module 12 can transmit acquired image data to host subsystem 20 via communication path 18. For example, image processing circuitry 16 can transmit image data to subsystem 20. Electronic device 10 can provide users with many advanced functions. For example, in a computer or smartphone, it can provide the user with the ability to run user applications. To implement these functions, host subsystem 20 of electronic device 10 may include storage and processing circuitry 24 and input / output devices 22, such as keypads, input / output ports, joysticks, and displays. Storage and processing circuitry 24 may include volatile and / or non-volatile memory. Storage and processing circuitry 24 may also include microprocessors, microcontrollers, digital signal processors, application-specific integrated circuits (ASICs), or other processing circuitry.

[0044] Figure 2AA top view of an exemplary image sensor 14 with a bias isolation structure according to various embodiments is shown. The image sensor includes a semiconductor substrate 254, such as silicon. The image sensor 14 may have an array portion 220 and a peripheral portion 210. The array portion 220 may include an array of pixels 222 arranged in rows and columns. The peripheral portion 210 may be located outside the array portion 220, for example, adjacent to the array portion 220, and may include other support circuitry and structures. The peripheral portion 210 need not include the entire portion of the substrate 254 located outside the array portion 220. The isolation structure of the pixel portion 220 may be biased from the peripheral portion 210.

[0045] In some embodiments, the peripheral portion 210 includes structures configured to protect the array portion 220 from charge damage during processing and to provide appropriate bias during operation of the image sensor 14. In some embodiments, the peripheral portion 210 may also include other structures supporting the functionality and operation of the image sensor 14. For example, these structures may include input / output (I / O) circuitry, analog and / or digital signal processing circuitry, control logic, clock generation and distribution, power distribution, etc. The peripheral portion may also include structures related to the boundaries of the pixel array, such as row address decoders and column address decoders for accessing individual pixels.

[0046] For clarity, in Figures 2A to 2C A simplified subset of array portion 220 and peripheral portion 210 is shown. In many embodiments, the actual number of trench structures, pixels, substrates, and trench connections can be much higher. Furthermore, because various trench structures can be electrically coupled throughout array portion 220 and / or peripheral portion 210, some embodiments may include only a subset of the various trench structures and / or substrate portions, each having trench and / or substrate connections.

[0047] Image sensor 14 may include an arrangement of array trench isolation structures 230. Array trenches 230 are those trenches that extend laterally along substrate 254 through array portion 220 and are positioned between adjacent pixels of the pixel array to act as isolation structures. In some embodiments, array trenches 230 may also extend into peripheral portion 210. Array trenches 230 may include full trench (FT) trenches, deep trench (DT) trenches, and / or any other suitable trench isolation structures. In some embodiments, array trenches 230 may include deep trench isolation (DTI) structures, such as front-side deep trench isolation (FDTI) and / or rear-side deep trench isolation (BDTI).

[0048] Reference Figure 2BIn some embodiments, the array trench 230 can be formed by etching trenches in the front surface 256 (also referred to as the front side or FS) of the substrate 254 of the image sensor 14. The array trench 230 can be partially etched through the substrate 254 in both the array portion 220 and the peripheral portion 210, such that the array trench 230 does not intersect with the rear surface 258 of the substrate and the substrate maintains electrical integrity throughout the array portion 220 and the peripheral portion 210, for example as... Figure 2B As shown in the diagram. The trench may be lined with an insulating material 234, such as silicon dioxide, silicon nitride, other high-k or low-k dielectrics, etc. The insulating material 234 may be selected based on electrical properties, optical properties, or other desired characteristics and / or functions.

[0049] The array trench 230 can then be filled with a conductive filler 232, such as polysilicon, metal, and / or other materials suitable for biasing. In some embodiments, the conductive filler 232 may comprise tungsten and / or doped polysilicon. The array trench 230 of the array portion 220 and the peripheral portion 210 can be electrically coupled, for example, through the conductive filler 232, such that they are maintained at the same potential. For example, the array trench 230 can be positively biased, negatively biased, or grounded as needed during operation of the image sensor 14.

[0050] The formation of the array trench 230 can be performed during the front-end process (FEOL) of the image sensor 14, for example, along with the formation of other semiconductor structures such as pixels and control logic. Therefore, in some embodiments, at the end of the FEOL process, the substrate remains electrically intact or is otherwise configured to maintain a consistent potential throughout the peripheral portion 210 and the array portion 220.

[0051] One or more trench contacts 270 may be formed into one or more arrayed trenches 230 in the peripheral portion 210. One or more substrate contacts 272 may be formed into one or more segments of the substrate 254 in the peripheral portion 210. The substrate segments 254 may be those portions of the substrate located between consecutive trenches. The trench contacts 270 and substrate contacts 272 may be formed as needed during or after the FEOL process. In some embodiments, the trench contacts 270 and / or substrate contacts 272 include conductive vias.

[0052] One or more metal wiring layers may be formed at the front side 256 of substrate 254 during back-end process (BEOL) processing. The metal wiring layers may alternate with insulating material layers such as various oxides. Vias may extend through one or more insulating layers to connect multiple metal layers. Various insulating layers are not shown for clarity. The FS passivation layer 252 (e.g., oxide) at the front side 256 may be part of a first insulating layer (not shown) between substrate 254 and the first metal layer 260. Trench contacts 270 and substrate contacts 272 may extend through passivation layer 252 to be electrically coupled to trench segments and substrate 254 segments, respectively.

[0053] The first metal layer 260 may be formed during the BEOL process. In some embodiments, the first metal layer 260 may be electrically coupled to the trench contact 270 and the substrate contact 272. Through the first metal layer 260, the substrate segment 254 in the peripheral portion 210 and the array trench 230 will be at substantially the same potential. Because the continuous metal filler 232 extends in both the peripheral portion 210 and the array portion 220, the array trench 230 in the peripheral portion 210 and the array portion 220 will be at substantially the same potential. Because the electrically intact portion of the substrate extends along the back surface 258 (also referred to herein as the back side or BS) in both the peripheral portion 210 and the array portion 220, the substrate segment 254 in the peripheral portion 210 and the array portion 220 will be at substantially the same potential.

[0054] Therefore, in some exemplary embodiments, the substrate 254 and the array trench in both the peripheral portion 210 and the array portion 220 can be maintained at substantially the same potential during BEOL processing. If various plasma processes performed during BEOL generate excess charge on one or more metal layers, the array trench 230 and the substrate 254 segment will remain at an equivalent potential, thereby minimizing or otherwise reducing the electric field between the array trench 230 and the surrounding substrate 254. This significantly reduces the risk of charge damage during plasma processes or other processes that induce charge in the image sensor 14 structure.

[0055] After the BEOL treatment from the FS256 is completed, there is likely almost no additional risk of charge damage from further processing steps. (Refer to...) Figure 2C After BEOL processing from FS256, the substrate can be flipped, for example, attached to a carrier wafer, and further processed from BS258. In some embodiments, the substrate 254 segment of pixel portion 220 can be electrically decoupled from the substrate 254 of the peripheral portion after BEOL processing, thus allowing the array trench 230 to be biased independently of the substrate 254 segment of array portion 220 during operation of image sensor 14.

[0056] In some embodiments, substrate 254 can be thinned from BS258, for example, using grinding and / or etching. Substrate 254 can be thinned to at least array trench 230 such that one or more segments of substrate 254 are no longer electrically connected. For example, after thinning, segments of substrate 254 in array portion 220 can be electrically isolated from segments of substrate 254 in peripheral portion 210. Segments of substrate 254 in peripheral portion 210 can be electrically isolated from substrates 254 in other portions of image sensor 14 located outside array portion 220. In some embodiments, substrate 254 is thinned such that segments of substrate 254 for each pixel in array portion 220 become physically and / or electrically isolated from each other, based on the desired performance and functionality of each pixel. Segments of substrate 254 in peripheral portion 210 can be electrically coupled to array trench 230 via trench contacts 270 and substrate contacts 272 at FS256.

[0057] In some embodiments, after thinning, a passivation region 240 may be formed on the BS258. The passivation region 240 may include an anti-reflective coating (ARC), a chemical passivation layer, an electrically insulating layer (such as a high-k or low-k dielectric), etc. For example, the passivation region 240 may include an insulating layer 238 (e.g., silicon dioxide or silicon nitride) and a high-k dielectric layer 236. Additional processing from the BS258 may include forming color filter arrays, microlenses, and / or other desired structures (not shown).

[0058] Advantageously, according to various embodiments, charge damage to the array trench 230 during BEOL processing can be prevented, and bias can be provided to the array trench 230 during operation of the image sensor 14 using only the FS256 contacts with the substrate 254 and / or the array trench 230. In other words, the apparatus and methods according to various exemplary embodiments can be implemented without the corresponding BS258 contacts.

[0059] Reference Figure 3A In some exemplary embodiments, the array trenches 230 form a broken or otherwise incomplete grid in the peripheral portion 210, and / or may not be individually coupled to the first metal layer 260 via trench contacts 270. However, the array trenches 230 may be fully electrically coupled by intersecting with other array trenches 230 in the peripheral portion 210 and / or array portion 220. The number and placement of the substrate contacts 272 and trench contacts 270 may be selected based on the required protection during or after BEOL processing, the required performance based on various process parameters and / or requirements, the required functionality during operation of the image sensor 14, and / or any other suitable criteria.

[0060] Reference Figure 3BThe image sensor 14 is shown after back-side thinning. In some embodiments, the substrate 254 in the peripheral portion 210 may include a heavily doped region 354 formed and positioned near the FS 256 and aligned with the substrate contact 272 to provide improved electrical coupling with the substrate contact 272. For example, the lightly doped p-type substrate 254 in the peripheral portion 210 may include a heavily doped p-type region 354 for landing of the substrate contact 272. The heavily doped region 354 may provide an improved discharge path through the substrate 254 during various plasma processes or other charge-generating processes.

[0061] In some implementations, array contacts 270 and / or substrate contacts 272 can be coupled to a higher-level metal wiring layer spanning a larger portion of peripheral portion 210 via one or more reduced-area metal wiring layers. The relatively small metal area can be used to further protect substrate 254 and array trench 230 from charge damage, as charge can accumulate on the larger area of ​​the metal structure.

[0062] For example, the number of substrate contacts 272 and array contacts 270 can be reduced as described above, thereby allowing the use of short segments of the first metal layer 260 to couple adjacent contacts 270, 272. The first metal layer 260 can be coupled to a larger area fourth metal layer 266 via conductive vias 274 and the second and third metal layers 262 and 264 (each having a small area). The fourth metal layer 266 can span a large portion of the peripheral portion 210 and can be coupled to multiple shorter segments of the first metal layer 260, and can receive more charge generated during various plasma processes. The fourth metal layer 266 can be further coupled to additional metal layers, such as a fifth metal layer 268, as needed via conductive vias 274.

[0063] Reference Figure 3C The image sensor 14 is shown after back-side thinning. In some embodiments, a protection diode may be formed in the substrate 254 to protect the array trench 230 during BEOL processing. In some embodiments, a highly doped region 354 may be formed in a well 450 that is doped opposite to the substrate 254. For example, a highly doped p-type region 354 may be formed in an n-type well 450, wherein the highly doped p-type region 354 forms the anode of the protection diode. Substrate contacts 272 may be coupled to the anode of the protection diode. In other embodiments, a region doped opposite to the substrate 254 may be used to form the diode. For example, the diode may be formed from a highly doped n-type region in a p-type substrate.

[0064] During the process that generates charge on metal layers 260, 262, 264, 266, and 268, the protection diode can be forward biased due to charging, allowing the formation of a path for charge flow into the substrate. The forward biasing of the protection diode can occur simultaneously with the inflow of charge into the array trench 230, and thus the potentials of the array trench 230 and the substrate 254 segment remain substantially equal.

[0065] The substrate 254 segment in the peripheral portion 210 is substantially electrically isolated from the array trench 230 by a protection diode during normal operation of the image sensor 14. In some embodiments, biasing the array trench 230 to a negative value (e.g., about -4V) also reverse biases the protection diode and substantially prevents the substrate 254 from acquiring the same potential as the array trench 230.

[0066] Advantageously, an embodiment having a protective diode for the connection between substrate contact 272 and substrate 254 may not require back-side thinning to isolate substrate 254 in peripheral portion 210 from other portions of substrate 254 in image sensor 14. Therefore, in some embodiments, various trenches may retain partial depth trenches after all back-side thinning (not shown), thereby allowing substrate 254 to remain electrically intact after back-side 258 processing is complete.

[0067] Figure 4A An exemplary image sensor 14 after FEOL processing is shown. In some embodiments, spacer etching may be performed on the insulating material 234 lining the array trench 230 during FEOL processing before filling the conductive material 232. Spacer etching may open the insulating material 234 at the bottom surface of the array trench 230. The opening exposes the bottom of the array trench 230 to the substrate 254, thereby allowing the conductive material 232 to subsequently be conductively coupled to the substrate 254 through the opening. During BEOL processing, excess charge may drain through the conductive material 232 and into the substrate 254 at the bottom of the array trench 230.

[0068] The substrate 254 and the array trench 230 can be maintained at substantially the same potential through conductive coupling at the bottom of the array trench 230. In some embodiments, one or more substrate contacts 272 may be provided in the peripheral portion 210 as needed to further facilitate potential equalization between the substrate 254 and the array trench 230.

[0069] Reference Figure 4BAfter the BEOL process, the substrate 254 can be flipped and BS258 thinning is performed, as described above. BS258 thinning removes the bottom portion of the array trenches having openings in the insulating material 234. BS258 thinning thus electrically isolates each segment of the substrate 254 from the conductive material 232 of the array trenches 230. Advantageously, the image sensor 14 formed according to various such embodiments can protect the array trenches 230 from charge damage during the BEOL process using only the structure and processing of FS256. For example, the image sensor 14 according to various such embodiments does not require BS258 contacts for protecting or biasing the array trenches 230.

[0070] Reference Figure 5A In some embodiments, the substrate 254 in the peripheral portion 210 may be electrically isolated from the array trench 230. For example, the peripheral portion 210 may not have any substrate contacts 272. By forming a high stack of vias and metal layers with a small cross-sectional area and remaining unconnected for trench biasing until the BEOL process is complete, the array trench 230 can be protected from charge damage from the BEOL process.

[0071] In some implementation schemes, refer to Figure 5B The trench contact 270 can be coupled via a plurality of vias 274 and regions of two or more metal layers 260, 262, 264, 266, 268 having small cross-sectional areas. For example, the corresponding vias and metal layers can be the minimum dimensions required to form electrical connections with lower and / or upper layers, for example, based on various process design rules. In an exemplary embodiment, during BEOL processing, the trench contact 270 is coupled to small regions of the first metal layer 260, the second metal layer 262, the third metal layer 264, and the fourth metal layer 566-1. As described above, the small cross-sectional area reduces the risk of charge damage.

[0072] During BEOL processing, a large region of metal layer other than the uppermost metal layer can also be formed, which can be configured to couple to other image sensor 14 circuitry to ultimately provide trench bias during the operation of image sensor 14. For example, a large region 566-2 of a fourth metal layer 566-2 can be formed and configured to bias the array trench 230. The large region 566-2 can receive excess charge during BEOL processing but remains unconnected to the array trench 230 until the BEOL processing is complete. Therefore, the risk of charge damage to the array trench 230 and surrounding structures during BEOL processing is significantly reduced.

[0073] At the end of the BEOL process, the large region 566-2 and the small region 566-1 of the non-topmost metal layer can be coupled to the topmost metal layer, such as the fifth metal layer 268, via additional vias. Coupling these regions 566-1, 566-2 via the topmost metal layer provides a path for biasing the array trench 230 during operation of the image sensor 14. Since the topmost metal layer is formed at the end of the BEOL process, the array trench 230 is less susceptible to charge damage. It should be appreciated that some embodiments may include substrate contacts 272 in the peripheral portion 210 as needed. It should be further appreciated that vias of various metal layers and other arrangements of conductive signal lines can be used to couple the array trench 230 and / or the substrate 254, wherein large conductive signal lines remain unconnected until the end of the BEOL process.

[0074] Figure 6A A top view of an exemplary image sensor 14 with array isolation structures according to various embodiments is shown. These array isolation structures are disconnected during BEOL processing and coupled from BS258 after BEOL processing to enable biasing of the array isolation structures during operation of the image sensor 14. (See also: Regarding...) Figures 2A to 2C The image sensor 14 may have an array portion 220 and a peripheral portion 210. The peripheral portion 210 need not include the entire portion of the substrate 254 located outside the array portion 220. After BEOL processing, the isolation structure for the pixel portion 220 can be biased via the BS258 connection in the peripheral portion 210.

[0075] For clarity, in Figures 6A to 6C A simplified subset of array portion 220 and peripheral portion 210 is shown. In many embodiments, the actual number of trench structures, pixels, substrates, and trench connections can be much higher. Furthermore, because various trench structures can be electrically coupled throughout array portion 220 and / or peripheral portion 210, some embodiments may include only a subset of the various trench structures and / or substrate portions, each having trench connections and / or substrate connections.

[0076] Image sensor 14 may include an arrangement of array trench 230 and peripheral trench 630. Array trench 230 may be as described above. Peripheral trench 630 may include trenches extending laterally along substrate 254 through peripheral portion 210 but not through array portion 230. Peripheral trench 630 does not intersect with array trench 230 and therefore is not directly electrically coupled to array trench 230 through the intersection of various trenches.

[0077] The peripheral trench 630 may include a full trench (FT) trench, a deep trench (DT) trench, and / or any other suitable trench isolation structure. In some embodiments, the peripheral trench 630 may include a deep trench isolation (DTI) structure, such as front deep trench isolation (FDTI) and / or rear deep trench isolation (BDTI). In some embodiments, the peripheral trench 630 is formed simultaneously with and using the same process as the array trench 230.

[0078] Reference Figure 6B In some embodiments, the array trench 230 and the peripheral trench 630 can be formed by etching trenches in the FS256 of the substrate 254 of the image sensor 14. In some embodiments, the array trench 230 and the peripheral trench 630 can be partially etched through the substrate 254 in both the array portion 220 and the peripheral portion 210, such that the substrate 254 maintains electrical integrity throughout the array portion 220 and the peripheral portion 210, for example as... Figure 2B As shown in the figure. In some embodiments, the array trench 230 and the peripheral trench 630 may be completely etched through the substrate 254 in both the array portion 220 and the peripheral portion 210, such that the substrate 254 in the peripheral portion 210 is isolated from the substrate 254 in the array portion 220.

[0079] As described above, the array trench 230 and the peripheral trench 630 may be lined with an insulating material 234. As described above, the array trench 230 and the peripheral trench 630 may then be filled with a conductive material filler 232. The array trench 230 of the array portion 220 and the peripheral portion 210 may be electrically coupled, for example, through the conductive filler 232, such that they are maintained at the same potential. The array trench 230 may be electrically isolated from the peripheral trench 630 during FEOL processing.

[0080] The formation of the array trench 230 and the peripheral trench 630 can be performed during the FEOL processing of the image sensor 14. In embodiments with the array trench 230 and the peripheral trench 630 formed only partially through the substrate 254, at the end of the FEOL processing, the substrate 254 remains electrically intact or is otherwise configured to maintain a consistent potential throughout the peripheral portion 210 and the array portion 220. In embodiments with the array trench 230 and the peripheral trench 630 formed completely through the substrate 254, at the end of the FEOL processing, the substrate 254 in the peripheral portion 210 is electrically isolated from the substrate 254 in the array portion 220.

[0081] One or more trench contacts 270 may be formed into one or more peripheral trenches 630 in the peripheral portion 210. One or more substrate contacts 272 may be formed into one or more segments of the substrate 254 in the peripheral portion 210. In some embodiments, FS contacts with the array trench 230 are not formed during or after the FEOL process, thereby electrically isolating the array trench 230 from the peripheral trenches 630 and the segments of the substrate 254 in the peripheral portion 210. The trench contacts 270 and substrate contacts 272 may be formed as needed during or after the FEOL process.

[0082] As described above, one or more metal wiring layers may be formed at the front side 256 of the substrate 254 during back-end process (BEOL) processing. The FS passivation layer 252 (e.g., oxide) at the front side 256 may be part of a first insulating layer (not shown) between the substrate 254 and the first metal layer 260. Trench contacts 270 and substrate contacts 272 may pass through the passivation layer 252 to be electrically coupled to the peripheral trench 630 and the substrate 254 segment, respectively.

[0083] The first metal layer 260 may be formed during the BEOL process. In some embodiments, the first metal layer 260 may be electrically coupled to the trench contact 270 and the substrate contact 272. Through the first metal layer 260, the substrate segment 254 in the peripheral portion 210 and the peripheral trench 630 will be at substantially the same potential. In other words, the first metal layer 260 can electrically short-circuit the substrate segment 254 and the peripheral trench 630.

[0084] During BEOL processing, the array trench 230 in the peripheral portion 210 and the array portion 220 remains isolated from the peripheral trench 630 and the substrate 254 segment. In some embodiments, such as those with a trench isolation structure that does not fully extend through the substrate 254, the substrate 254 segment in the peripheral portion 210 and the array portion 220 will be at substantially the same potential due to the electrically intact portion of the substrate extending along BS258 in both the peripheral portion 210 and the array portion 220.

[0085] Therefore, in some exemplary embodiments, the substrate 254 and the peripheral trench 630 in the peripheral portion 210 can be maintained at substantially the same potential during BEOL processing. If various plasma processes performed during BEOL processing generate excess charge on one or more metal layers, the peripheral trench 630 and the substrate 254 segment will remain at an equivalent potential, thereby minimizing or otherwise reducing the electric field between the peripheral trench 630 and the surrounding substrate 254. Furthermore, the array trench 230 remains isolated from the metal wiring layers during BEOL processing and will remain isolated from any charge accumulation. This significantly reduces the risk of charge damage to the substrate 254 and the various trenches 230, 630 of the image sensor 14 during BEOL processing.

[0086] After BEOL processing from FS256, the substrate can be flipped, for example, attached to a carrier wafer, and further processed from BS258. If desired, for example in embodiments including trench isolation structures formed not entirely through the substrate 254, the substrate 254 can be thinned from BS258 to at least the array trench 230, such that one or more segments of the substrate 254 are no longer electrically connected. In some embodiments, the substrate 254 can be thinned from BS258 to remove insulating material 234 from the bottom of the array trench 230 and the peripheral trench 630, thereby exposing conductive filler 232. In some embodiments, passivation regions 240 can be formed on BS258.

[0087] Therefore, as Figure 6B As shown, the substrate 254 segment in array portion 220 is electrically isolated from the substrate 254 segment in peripheral portion 210. The substrate 254 segment in peripheral portion 210 is electrically isolated from the substrate 254 in other portions of image sensor 14 located outside array portion 220. Due to BS258 thinning and / or full-depth trench formation, the substrate 254 segments for each pixel in array portion 220 are physically and / or electrically isolated from each other. The substrate 254 segments in peripheral portion 210 are electrically coupled to peripheral trench 630 via trench contacts 270 and substrate contacts 272.

[0088] Reference Figure 6C The array trench 230 can be electrically coupled to the peripheral trench 630 after BEOL treatment. In some embodiments, a large backside region 640 (e.g., spanning at least one array trench 230 and one peripheral trench 630) can be opened in the passivation region 240 in the peripheral portion 210. The open large backside region 640 can expose the conductive filler 232 of the array trench 230 and the peripheral trench 630.

[0089] A back-side conductive layer 642 can be formed, for example, by deposition within the opening of the large back-side region 640. In some embodiments, the back-side conductive layer 642 may also extend over the passivation region 240 surrounding the opening of the large back-side region 640. In some embodiments, the back-side conductive layer 642 may be formed simultaneously with and / or made of the same material as the metal layer in the array portion 220, but electrically isolated from the metal layer. For example, the back-side conductive layer 642 may be formed of tungsten during the same processing steps as the formation of the tungsten light-shielding layer in the pixel array. In some embodiments, the light-shielding layer in the pixel array may be grounded, and the back-side conductive layer 642 may receive a negative voltage through the peripheral trench 630 to bias the array trench 230.

[0090] The back-side conductive layer 642 can electrically couple the array trench 230 to the peripheral trench 630 in the peripheral portion 210. In some embodiments, a substrate 254 segment in the peripheral portion 210 is also electrically coupled to the array trench 230 and the peripheral trench 630 via the back-side conductive layer 642. In some embodiments, the back-side conductive layer 642 may comprise a metal, such as tungsten. The array trench 230 can be biased during operation of the image sensor 14 via the electrical coupling of the back-side conductive layer 642, the peripheral trench 630, the trench contact 270, the first metal layer 260, and other suitable circuitry of the image sensor 14.

[0091] Advantageously, according to various embodiments, the array trench 230 can be isolated from charge damage during BEOL processing and can be electrically coupled to the peripheral trench 630 via the conductive layer 642 on the BS258 to provide bias to the array trench 230 during operation of the image sensor 14. The conductive layer 642 coupling the peripheral trench 630 to the array trench 230 can be a relatively low-cost contact due to its relatively large size.

[0092] In some implementation schemes, refer to Figure 7A and Figure 7B The FS256 substrate contact 272 in the substrate 254 section from the first metal layer 260 to the peripheral portion 210 can be omitted. Except for omitting the substrate contact 272, the formation of the structure of the peripheral portion 210 and the array portion 220 can remain consistent with... Figure 6B and Figure 6C The description is the same.

[0093] During BEOL processing, due to the presence of trench contacts 270 and the omission of substrate contacts 272, the peripheral trench 630 may accumulate charge and may not maintain the same potential as the surrounding substrate 254 segment. Charge damage may occur in or around the peripheral trench 630, and the damage may be limited to the peripheral portion 220, which is acceptable. Additionally, the back-side conductive layer 642 can electrically couple the peripheral trench 630 and the substrate 254 segment in the peripheral portion 210 after BEOL processing, thereby reducing the effects of any charge damage that may have occurred in the peripheral trench 630.

[0094] As described above, the array trench 230 is electrically coupled to the peripheral trench 630 via the back-side conductive layer 642 after BEOL treatment and is not subject to charge damage from the BEOL treatment. Various embodiments omitting the substrate contact 272 can be provided otherwise as described above. Figures 6A to 6C The same advantages and functionality described.

[0095] In some implementation schemes, refer to Figure 8A and Figure 8B Instead of opening the large backside region 640, or otherwise, one or more small backside regions 840 may be opened in the passivation region 240. The openings of the small backside regions 840 may be aligned with the conductive material filler 232 of the array trench 230 and the peripheral trench 630 in the peripheral portion 210, and may avoid opening the passivation region 240 at the substrate 254 segment. The open small backside regions 840 may expose the conductive filler 232 of the array trench 230 and the peripheral trench 630. The openings of the small backside regions 840 allow the array trench 230 and the peripheral trench 630 to be electrically coupled through the backside conductive layer 642, while avoiding electrical coupling with the substrate 254.

[0096] In some embodiments, as described above, substrate contact 272 may be omitted. Therefore, if desired, substrate 254 may remain isolated from peripheral trench 630 and array trench 230 and their respective biases during operation of image sensor 14. In some alternative embodiments, FS256 substrate contact 272 may be included to electrically couple array trench 230, peripheral trench 630, and the substrate 254 segment in peripheral portion 210.

[0097] As described above, the array trench 230 is electrically coupled to the peripheral trench 630 via the back-side conductive layer 642 after the BEOL treatment and is not subject to charge damage from the BEOL treatment. Various embodiments having a small back-side region 840 opened in the passivation region 240 and omitting the opening of the large back-side region 640 can be provided otherwise as described above. Figures 6A to 6C The same advantages and functionality described.

[0098] In some implementation schemes, refer to Figure 9A and Figure 9B The array trench 230 can be electrically coupled after BEOL treatment for biasing via the back-side conductive layer 642. The back-side conductive layer 642 can be formed in a large back-side region 940 opened in the passivation region 240 in the peripheral portion 210. The large back-side region 940 can span at least one array trench 230 and at least one adjacent substrate 254 segment in the peripheral portion 210. In some embodiments, the large back-side region 940 spans multiple array trenches 230 and multiple substrate 254 segments. One or more of the substrate 254 segments spanned by the large back-side region 940 can be coupled to a substrate contact 272 from FS 256.

[0099] Figure 9B A simplified cross-section of pixel 222 and peripheral portion 210 is shown. Pixel 222 may include a photodiode 910 formed in substrate 254. Pixel 222 may also include one or more substrate contacts 272 and other structures to perform reset, readout, and other pixel functions. For example, transistor gate 920 may form part of a transfer transistor (not shown) to transfer charge generated by incident photons and may be controlled via substrate contacts 272.

[0100] In the peripheral portion, the substrate 254 adjacent to the array trench 230 may be highly doped 930 to increase the conductivity of the substrate 254 from FS256 to BS258. The substrate 254 may be doped during the formation of the array trench 230 (e.g., before filling with conductive material 232 and / or lining with insulating material 234). The substrate 254 adjacent to the array trench 230 in the array portion 220 may also be doped during the same process step.

[0101] The doped portion of substrate 254 in the peripheral portion can be coupled to substrate contact 272. Trench contact 270 can be omitted. During BEOL processing, array trench 230 can thus remain isolated from any metal wiring layer and not exposed to charge damage. After BEOL processing and any BS258 thinning (as described above), a large backside region 940 can be opened in passivation region 240. Backside conductive layer 642 can then be formed, which can electrically couple one or more segments of substrate 254 to one or more array trenches 230 in peripheral portion 210.

[0102] The array trench is electrically coupled to be biased via the back-side conductive layer 642, the highly doped substrate 930 adjacent to the array trench 230, and the substrate contact 272 in the peripheral portion 210. The same type of contact used in the pixel 222 (e.g., substrate contact 272) can be used to bias the substrate 254 segment in the peripheral portion. Therefore, advantageously, both the peripheral portion 210 and the array portion 220 require only one type of FS256 contact to protect the array trench 230 from charge damage while providing bias to the array trench 230 during operation of the image sensor 14.

[0103] Figure 10A and Figure 10B This is a simplified block diagram illustrating an exemplary arrangement of array portion 220 and peripheral portion 210. As described above, image sensor 14 may include other areas on substrate 254 besides peripheral portion 210 and array portion 220, and such other areas are not shown for clarity. Peripheral portion 210 may be arranged in any suitable manner near array portion 220. Therefore, it should be appreciated that embodiments according to this disclosure are not limited to those embodiments shown in the several figures contained herein.

[0104] Reference Figure 10A The peripheral portion 210 may include one or more substrate regions substantially disposed at one or more corners of the array portion 220 (e.g., at the four corners of the pixel array). The peripheral portion 210 may be substantially centered at the corners of the array portion 220, for example, forming an "L" shape with sides of equal length. The length of the peripheral portion 210 along each side of the array portion 220 may be minimized to minimize the metal area connected to the array trench 230, peripheral trench 630, and / or other structures during BEOL processing. Minimizing the connected metal area reduces the risk of charge damage.

[0105] Reference Figure 10B The peripheral portion 220 may include one or more substrate regions arranged along one or more sides of the array portion 220. For example, the image sensor 14 may include two peripheral portions 210, each arranged on opposite sides of the array portion 220. As another example, the image sensor 14 may include four peripheral portions 210, each arranged on one side of the array portion 220 (and, for example, not around the corners of the array portion 220). The peripheral portions 210 extending along one or more sides of the array portion 220 can provide more connections to the array trench 230, the peripheral trench 630, and / or other structures, and may therefore reduce the resistance to the array trench 230 in the array portion 230.

[0106] Figure 11A simplified process flow is shown for a method 1100 for protecting an array trench structure during the formation of an image sensor, for example, according to various embodiments described herein. The method may include step 1102 of forming one or more array trenches in a substrate during FEOL processing, wherein the array trenches traverse an array portion and a peripheral portion of the substrate. The trenches may include deep trenches, such as front-side deep trenches. At step 1106, substrate contacts may be formed on the front side of the substrate in the peripheral portion during BEOL processing. The substrate contacts may be formed to the substrate adjacent to the array trenches. In some embodiments, the formation of substrate contacts may be omitted from method 1100.

[0107] At step 1108, electrical contacts for an array of trenches may be formed in the peripheral portion. In some embodiments, the electrical contacts may include trench contacts formed on the front side of the substrate during the BEOL process. At step 1112, for example after the BEOL process, the substrate may be thinned from the back side. In some embodiments, at step 1112, the substrate may be thinned down to at least the bottom surface of the array of trenches. At step 1114, for example after the thinning in step 1112, a passivation region may be formed on the back side of the substrate.

[0108] Some implementations include a separate peripheral trench coupled to the array trench after the BEOL treatment. In some such implementations, one or more peripheral trenches may be formed during the FEOL treatment at step 1104. The peripheral trenches may remain isolated from the array trenches during the FEOL treatment. In some such implementations, at step 1110, front-side trench contacts may be formed to one or more peripheral trenches during the BEOL treatment. Furthermore, at step 1108, the electrical contacts of the array trenches may include a conductive layer formed on the back side of the substrate.

[0109] The back-side electrical contact can be formed during step 1108 after the thinning in step 1112. For example, the contact can be formed after step 1116, which forms one or more openings in the passivation regions at the array trench and the peripheral trench. The openings may include large openings spanning the array trench and the peripheral trench, separate openings at each of the array trench and the peripheral trench, etc. The array trench may be coupled to the peripheral trench via a conductive layer at the opening in the passivation region.

[0110] Therefore, the steps of the exemplary methods described herein can be performed in any suitable order, and the order of the steps used to form the various structures described herein can be rearranged without departing from the scope of the invention.

[0111] Therefore, various embodiments provide array trench isolation in the pixel array, which is biased at the peripheral portion of the image sensor. Various embodiments provide several arrangements for biasing the array trenches from the periphery while protecting the array trenches from damage during BEOL processing. The systems, apparatuses, and methods described herein provide improved charge handling during BEOL processing.

[0112] Advantageously, the systems, apparatus, and methods described herein offer the following advantages: reduced dark current using biased array trenches; improved yield due to minimized charge damage; and reduced cost through the use of large back-side structures and / or standard front-side contacts. While the various trenches and other structures described herein may be referred to as being associated with FS256 or BS258, it should be recognized that the structures and processes described herein are suitably adapted for use on alternative BS258 or FS256. Various trenches, contacts, and other structures can be distributed in the substrate 254 in any suitable manner, and different embodiments can organize the processing of various features in any number of different ways.

[0113] The general concepts set forth herein are applicable to any number of alternative but equivalent embodiments. The term “exemplary” is used herein to indicate an example, illustration, or description that may have any number of alternatives. Any specific embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other specific embodiments, nor is it intended as a model that must be replicated in other specific embodiments. While several exemplary embodiments have been presented in the foregoing detailed description, it should be understood that numerous alternative but equivalent variations exist, and the examples presented herein are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, various changes may be made to the function and arrangement of the described elements and the order of steps without departing from the scope of the claims and their legal equivalents.

Claims

1. A semiconductor device, characterized by, include: The substrate includes an array portion and a peripheral portion; Multiple substrate segments defined by a plurality of arrayed trenches in the substrate, the plurality of substrate segments including a first substrate segment in the peripheral portion; The first array trench in the plurality of array trenches, wherein the first array trench traverses the array portion and the peripheral portion; The second array trench in the array portion of the plurality of array trenches, wherein the first array trench intersects with the second array trench in the array portion; A first groove contact is coupled to the first array groove in the peripheral portion; The first substrate contact coupled to the first substrate segment; and A conductive signal line, wherein the conductive signal line is electrically coupled to the first trench contact and the first substrate contact.

2. The semiconductor device of claim 1, wherein, The peripheral portion is adjacent to the array portion.

3. The semiconductor device according to claim 2, wherein, The peripheral portion includes multiple substrate regions; and Each substrate region is located at the corner of the peripheral portion.

4. The semiconductor device of claim 1, wherein, The first substrate segment is adjacent to the first array trench.

5. The semiconductor device of claim 1, wherein, The first trench contact and the first substrate contact are located on the front side of the substrate.

6. The semiconductor device of claim 1, wherein, The plurality of arrayed trenches extend from the front side of the substrate to the back side of the substrate.

7. The semiconductor device of claim 1, wherein, The plurality of arrayed trenches extend from the front side of the substrate and do not intersect with the back side of the substrate.

8. The semiconductor device of claim 1, wherein, The first substrate contact is coupled to the protection diode in the first substrate segment.

9. The semiconductor device of claim 1, wherein, The first array trench includes: Insulating material lining; and Conductive material filler, wherein, The insulating lining has an opening at the bottom surface of the first array trench; and The conductive material filler is coupled to the substrate through an opening in the insulating material liner.

10. A semiconductor device, characterized by comprising: include: The substrate includes an array portion and a peripheral portion; Multiple array trenches, the multiple array trenches including: A first array trench traversing both the array portion and the peripheral portion; and The second array trench in the array portion, wherein the first array trench intersects and is electrically coupled to the second array trench; The peripheral trench in the peripheral portion, wherein the peripheral trench does not intersect with any of the plurality of array trenches; Trench contacts coupled to the peripheral trench in the peripheral portion, wherein the trench contacts are located on the front side of the substrate; and A conductive layer on the back side of the substrate, wherein the conductive layer couples the peripheral trench to the first array trench at the peripheral portion.

11. The semiconductor device according to claim 10, wherein, The substrate includes a plurality of substrate segments defined by the peripheral trench and the first array trench, wherein the semiconductor device further includes: A substrate contact, wherein the substrate contact is coupled to at least one of the plurality of substrate segments at the front side of the peripheral portion, wherein the trench contact and the substrate contact are electrically coupled via a conductive signal line.

12. The semiconductor device of claim 10, further comprising: The passivation region on the back side of the substrate, wherein the conductive layer is coupled to the peripheral trench and the first array trench through a large opening in the passivation region.

13. The semiconductor device of claim 10, further comprising: The passivation region on the back side of the substrate, wherein, The conductive layer is coupled to the peripheral trench and the first array trench through a first small opening in the passivation region at the peripheral trench and a second small opening in the passivation region at the first array trench; and The conductive layer is not coupled to the substrate between the peripheral trench and the first array trench.

14. The semiconductor device according to claim 10, wherein, The plurality of array trenches and the peripheral trenches extend from the front side of the substrate to the back side of the substrate.

15. The semiconductor device according to claim 10, wherein, The array portion includes multiple pixels; and The plurality of array trenches define the plurality of pixels.

16. A method for forming an image sensor on a substrate, characterized in that, include: During the front-end process FEOL treatment, multiple deep trenches are formed from the front side of the substrate, wherein, The plurality of deep trenches are formed in the array portion of the substrate and the peripheral portion of the substrate; and The first trench of the plurality of deep trenches includes an array trench that traverses the array portion and the peripheral portion; during the back-end process BEOL, a substrate contact of the substrate adjacent to the first trench is formed on the front side of the substrate in the peripheral portion; Electrical contacts forming the first trench in the peripheral portion; and The substrate is thinned from the back side after BEOL treatment.

17. The method according to claim 16, wherein, The electrical contacts include trench contacts formed on the front side of the substrate during BEOL processing.

18. The method according to claim 16, wherein, The thinning includes thinning the substrate to the bottom surface of at least the plurality of deep trenches.

19. The method of claim 16, wherein, The second trench in the plurality of deep trenches includes a peripheral trench isolated from the first trench during FEOL processing, and the method further includes: A trench contact of the second trench in the peripheral portion is formed at the front side of the substrate, wherein, The electrical contact includes a conductive layer on the back side of the substrate; and The conductive layer couples the first trench to the second trench at the peripheral portion.

20. The method according to claim 19, further comprising: After the thinning, a passivation region is formed on the back side of the substrate; as well as One or more openings are formed in the passivation regions at the first trench and the second trench, wherein the conductive layer couples the first trench and the second trench through the one or more openings.

Images