Central processor-based process interruption method, apparatus, device and readable medium

Abstract

Embodiments of the present disclosure disclose a central processor-based process interruption method, device, equipment and readable medium. A specific embodiment of the method comprises: obtaining a historical running data sequence of a target processor; performing data preprocessing on the historical running data sequence to generate a preprocessed historical running data sequence; performing segmentation processing on each preprocessed historical running data in the preprocessed historical running data sequence to generate a segmented historical data group set; determining a confidence interval corresponding to the segmented historical data group; for each determined confidence interval, performing an interval merging algorithm to generate at least one merged confidence interval as a utilization safety baseline set; and performing a process interruption operation on at least one process running on the target processor. The embodiment avoids data loss and the situation that the process carried by the processor cannot run, thereby reducing the waste of processor resources.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of computer technology, and more particularly to a process interruption method, apparatus, device, and readable medium based on a central processing unit. Background Technology

[0002] With the rapid development of network technology, central processing units (CPUs) often perform heavy process execution tasks. When there are many processes running, the processor may overheat, causing the processes to malfunction or even rendering the processor unusable. Currently, the common method to determine whether a processor is operating normally is to set a fixed processor utilization threshold and determine whether the current processor utilization exceeds the set threshold.

[0003] However, when using the above method to determine whether the processor is operating normally, the following technical problems often arise:

[0004] When judging whether the processor is abnormal by setting a fixed threshold, the instantaneous fluctuation of the processor utilization may cause important processes to be interrupted, resulting in data loss. Furthermore, the judgment by using a fixed threshold has a high false positive rate, which may lead to the failure to detect abnormal processors in time, causing the processes carried by the processor to malfunction or even rendering the processor unusable.

[0005] The information disclosed in this background section is only intended to enhance the understanding of the background of the inventive concept, and therefore may contain information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The summary portion of this disclosure is intended to provide a brief overview of the concepts, which will be described in detail in the detailed description portion. This summary portion is not intended to identify key or essential features of the claimed technical solutions, nor is it intended to limit the scope of the claimed technical solutions.

[0007] Some embodiments of this disclosure provide a process interruption method, apparatus, electronic device, and computer-readable medium based on a central processing unit to solve one or more of the technical problems mentioned in the background section above.

[0008] In a first aspect, some embodiments of this disclosure provide a process interruption method based on a central processing unit (CPU). The method includes: in response to detecting that the utilization rate of a target processor is greater than or equal to a preset utilization rate, acquiring a historical running data sequence of the target processor; performing data preprocessing on the historical running data sequence to generate a preprocessed historical running data sequence; segmenting each preprocessed historical running data in the preprocessed historical running data sequence to generate a segmented historical data set; for each segmented historical data set in the segmented historical data set, determining a confidence interval corresponding to the segmented historical data set; for each determined confidence interval, executing an interval merging algorithm to generate at least one merged confidence interval as a utilization safety baseline set; and in response to the processor utilization rate at the current time point being greater than or equal to the corresponding utilization safety baseline, performing a process interruption operation on at least one process running on the target processor.

[0009] Secondly, some embodiments of this disclosure provide a process interruption device based on a central processing unit (CPU). The device includes: an acquisition unit configured to acquire a historical running data sequence of the target processor in response to detecting that the utilization rate of the target processor is greater than or equal to a preset utilization rate; a preprocessing unit configured to perform data preprocessing on the historical running data sequence to generate a preprocessed historical running data sequence; a segmentation unit configured to segment each preprocessed historical running data in the preprocessed historical running data sequence to generate a segmented historical data set; a determination unit configured to determine a confidence interval corresponding to each segmented historical data set in the segmented historical data set; an execution unit configured to execute an interval merging algorithm for each determined confidence interval to generate at least one merged confidence interval as a utilization safety baseline set; and a process interruption unit configured to perform a process interruption operation on at least one process running on the target processor in response to the processor utilization rate at the current time point being greater than or equal to the corresponding utilization safety baseline.

[0010] Thirdly, some embodiments of this disclosure provide an electronic device, including: one or more processors; and a storage device having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the method described in any implementation of the first aspect above.

[0011] Fourthly, some embodiments of this disclosure provide a computer-readable medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the method described in any of the implementations of the first aspect above.

[0012] The above embodiments of this disclosure have the following beneficial effects: The CPU-based process interruption method of some embodiments of this disclosure avoids data loss and prevents the processes carried by the processor from failing to run, thus reducing the waste of processor resources. Specifically, the reasons for data loss, the inability of the carried processes to run normally, or even processor failure are: when judging whether the processor is abnormal by setting a fixed threshold, the instantaneous fluctuation of the processor utilization may lead to the interruption of important processes, resulting in data loss. Furthermore, judging by a fixed threshold has a high false positive rate, making it impossible to detect abnormal processors in time, causing the processes carried by the processor to fail to run normally or even causing the processor to fail. Based on this, the CPU-based process interruption method of some embodiments of this disclosure firstly, in response to detecting that the utilization of the target processor is greater than or equal to a preset utilization rate, obtains the historical running data sequence of the target processor. Thus, the historical running data of the processor can be obtained. Secondly, the historical running data sequence is preprocessed to generate a preprocessed historical running data sequence. Thus, by denoising and processing outliers in the historical data, data support is provided for subsequent data processing. Then, the preprocessed historical running data in the above-mentioned preprocessed historical running data sequence is segmented to generate a segmented historical data set. This allows the historical running data to be split according to time segments. Next, for each segmented historical data set, a confidence interval is determined; for each determined confidence interval, an interval merging algorithm is executed to generate at least one merged confidence interval, serving as a utilization safety baseline set. This allows the processor utilization safety baseline for different time periods to be determined. Finally, in response to the processor utilization at the current time point being greater than or equal to the corresponding utilization safety baseline, at least one process running on the target processor is interrupted. Thus, when the processor utilization exceeds the safety baseline, the processor is identified as an abnormal processor, and the processes on the processor are interrupted to protect the processor, preventing overheating that could cause the processes running on the processor to fail, and preventing the processor from becoming unusable due to overheating. Attached Figure Description

[0013] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and elements are not necessarily drawn to scale.

[0014] Figure 1 This is a flowchart of some embodiments of the process interruption method based on the central processing unit according to the present disclosure;

[0015] Figure 2 This is a schematic diagram of the structure of some embodiments of the central processing unit-based process interruption device according to the present disclosure;

[0016] Figure 3 This is a schematic diagram of the structure of an electronic device suitable for implementing some embodiments of the present disclosure. Detailed Implementation

[0017] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0018] It should also be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings. Unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other.

[0019] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0020] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0021] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0022] This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0023] Figure 1 A flow 100 of some embodiments of a CPU-based process interruption method according to the present disclosure is shown. This CPU-based process interruption method includes the following steps:

[0024] Step 101: In response to detecting that the utilization rate of the target processor is greater than or equal to the preset utilization rate, obtain the historical running data sequence of the target processor.

[0025] In some embodiments, the execution entity (e.g., a server) of the CPU-based process interruption method may, in response to detecting that the utilization of the target processor is greater than or equal to a preset utilization, acquire a historical running data sequence of the target processor. In practice, the historical running data sequence can be acquired from a target database via a wired or wireless connection. The target processor may be the processor of the process to be terminated. The preset utilization may be a pre-set resource utilization rate of the processor. As an example, the preset utilization may be 50%. The historical running data in the historical running data sequence may be the running data of the target processor within a historical time period. The historical running data may include, but is not limited to, utilization, timestamps, and memory usage. The target database may be a database used to store the historical running data sequence. The historical running data in the historical running data sequence may be sorted according to the included timestamps.

[0026] Step 102: Perform data preprocessing on the historical running data sequence to generate a preprocessed historical running data sequence.

[0027] In some embodiments, the execution entity may perform data preprocessing on the aforementioned historical running data sequence to generate a preprocessed historical running data sequence. This data preprocessing may involve denoising each historical running data point in the aforementioned historical running data sequence.

[0028] In practice, the historical running data sequence can be preprocessed using the following steps to generate a preprocessed historical running data sequence:

[0029] The first step is to perform data cleaning on each historical data point in the aforementioned historical data sequence to generate a cleaned data sequence. In practice, a threshold filtering algorithm can be used to clean the data points in the aforementioned historical data sequence to generate a cleaned data sequence. This allows invalid data (e.g., data with a utilization rate greater than or equal to 100%) to be identified and removed.

[0030] The second step is to impute missing values ​​in each cleaning operation data point in the above cleaning operation data sequence to generate an imputed operation data sequence. In practice, a linear interpolation algorithm can be used to impute missing values ​​in each cleaning operation data point in the above cleaning operation data sequence to generate an imputed operation data sequence.

[0031] The third step is to smooth the padded running data sequence to generate a smoothed padded running data sequence as a preprocessed historical running data sequence. Here, a moving average algorithm can be used to smooth instantaneous fluctuations and reduce the interference of sudden fluctuations.

[0032] Step 103: Segment the preprocessed historical running data in the preprocessed historical running data sequence to generate a segmented historical data set.

[0033] In some embodiments, the execution entity may segment each piece of preprocessed historical running data in the preprocessed historical running data sequence to generate a segmented historical data set.

[0034] In practice, the following steps can be used to segment the preprocessed historical data in the preprocessed historical data sequence to generate segmented historical data sets:

[0035] The first step is to segment each preprocessed historical data set in the aforementioned preprocessed historical data sequence to generate segmented data sets. In practice, the preprocessed historical data can be segmented into sets with a preset duration as a cycle. For example, the preset duration could be one hour.

[0036] The second step involves reconstructing the generated segmented runtime data groups to create a reconstructed runtime data set. This reconstruction process can involve clustering the segmented runtime data representing the same time period to generate the reconstructed runtime data set. For example, the segmented runtime data from 10:00 AM to 11:00 AM on Monday can be combined with the segmented runtime data from 10:00 AM to 11:00 AM on Tuesday to form a reconstructed runtime data set.

[0037] The third step involves reconstructing the runtime data set and performing the following merging steps:

[0038] The first merging step involves determining the utilization distribution values ​​of the first two reconstructed running data groups in the reconstructed running data group set based on a preset algorithm. The preset algorithm can be a dynamic time warping algorithm or a variance formula.

[0039] The second merging step involves merging the first two reconstructed operation data sets in response to the difference between the two determined utilization rate distribution values ​​being less than or equal to a preset threshold, to generate a merged data set. The preset threshold can be a pre-defined threshold for the difference between the two utilization rate distribution values. For example, the merging process could merge the data from 10:00 to 11:00 and the data from 11:00 to 12:00 into the data from 10:00 to 12:00.

[0040] The third merging step involves updating the reconstructed runtime data set based on the merged data set to generate an updated runtime data set. In practice, the first two reconstructed runtime data sets in the reconstructed runtime data set can be replaced with the merged data set.

[0041] In the fourth merging step, in response to the fact that the number of update running data groups included in the aforementioned update running data set is less than or equal to a preset number, the aforementioned update running data set is determined as a segmented historical data set. The preset number can be a pre-defined number of update running data groups included in the update running data set. As an example, the preset number can be 2.

[0042] Optionally, after the fourth merging step, in response to the difference between the two determined utilization distribution values ​​being greater than a preset threshold, the above-mentioned reconstructed running data set is determined as the updated running data set.

[0043] Optionally, after the third step, in response to the fact that the number of updated running data groups included in the updated running data group set is greater than the preset number, the updated running data group set is used as the reconstructed running data group set, and the above merging step is performed again.

[0044] Step 104: For each segmented historical data group in the segmented historical data set, determine the confidence interval corresponding to the segmented historical data group.

[0045] In some embodiments, the execution entity may determine the confidence interval corresponding to each segmented historical data group in the segmented historical data group set.

[0046] In addressing the technical problems mentioned in the background section, and considering the application scenario in modern automobiles, where steering and braking commands are transmitted via electrical signals, calculated by the CPU under real-time operating system scheduling, and ultimately drive the motors, the CPU is the core of the control chain. However, this presents the following technical problem: during vehicle operation, the determined confidence interval for the CPU is affected by fluctuations in historical data (e.g., historical data collected under extreme conditions), leading to deviations in the determined confidence interval. This makes it impossible to accurately determine whether processor utilization is abnormal, resulting in tail latency in CPU response time and reduced vehicle driving safety. To meet the following requirements for this application scenario—accurately identifying abnormal processors—we have decided to adopt the following solution:

[0047] In some optional implementations of certain embodiments, the aforementioned execution entity may determine the confidence interval corresponding to each segmented historical data group in the segmented historical data group set through the following steps:

[0048] The first step, for each segmented historical data group in the above-mentioned segmented historical data group set, is to perform the following determination steps:

[0049] The first determination step involves determining a first confidence parameter and a second confidence parameter for each segment of historical data included in the aforementioned segmented historical data set. The first confidence parameter can be the mean of the aforementioned segmented historical data set. The second confidence parameter can be the standard deviation of the aforementioned segmented historical data set.

[0050] The second determination step involves generating an initial confidence interval corresponding to the aforementioned segmented historical data group, based on the first and second confidence parameters. In practice, firstly, the number of segmented historical data included in the aforementioned segmented historical data group can be determined as the target number. Secondly, the target number, the first and second confidence parameters are input into the standard normal distribution formula to determine the upper and lower limits of the aforementioned initial confidence interval.

[0051] The third step is to determine the skewness and kurtosis values ​​of the aforementioned segmented historical data sets. In practice, the skewness and kurtosis values ​​of the aforementioned segmented historical data sets can be determined using skewness and kurtosis formulas.

[0052] The fourth step involves determining the interval offset direction corresponding to the aforementioned segmented historical data group based on the skewness values. Here, the interval offset direction can be determined based on the sign of the skewness values. For example, if the sign of the skewness value is positive, the interval offset direction is the upper limit. If the sign of the skewness value is negative, the interval offset direction is the lower limit.

[0053] The fifth determination step involves performing a first correction process on the initial confidence interval based on the aforementioned skewness value and the aforementioned interval offset direction to generate a first confidence interval. Here, in response to the aforementioned interval offset direction being an upper limit, the sum of the upper limit of the initial confidence interval and the product of the upper limit and a preset skewness factor can be determined as the correction upper limit. In response to the aforementioned interval offset direction being a lower limit, the difference between the lower limit of the initial confidence interval and the product of the lower limit and a preset skewness factor can be determined as the correction lower limit. The preset skewness factor can be a pre-set constant factor.

[0054] The sixth determination step involves generating a correction width value corresponding to the first confidence interval based on the aforementioned kurtosis value. In practice, firstly, the difference between the aforementioned kurtosis value and the standard normal distribution can be determined as the contraction value. Secondly, the correction width value can be determined as the product of the width of the initial confidence interval and the preset kurtosis factor of the contraction value.

[0055] The seventh step involves performing a second correction process on the first confidence interval based on the aforementioned correction width value to generate a second confidence interval. In practice, the upper and lower limits of the first confidence interval can be respectively determined as the sum of the upper and lower limits of the first confidence interval and half of the aforementioned correction width value, which are then used as the upper and lower limits of the second confidence interval.

[0056] The aforementioned first to seventh determination steps, as an inventive point of this disclosure, combined with step "step 106" below, solve the technical problem: "During vehicle operation, the determined confidence interval of the CPU is affected by fluctuations in historical data (e.g., historical data was collected in extreme environments), resulting in a deviation in the determined confidence interval. This makes it impossible to accurately determine whether the processor utilization is abnormal, leading to a tail delay in CPU response time and lower vehicle driving safety." The reason for the lower vehicle driving safety is as follows: During vehicle operation, the determined confidence interval of the CPU is affected by fluctuations in historical data (e.g., historical data was collected in extreme environments), resulting in a deviation in the determined confidence interval. This makes it impossible to accurately determine whether the processor utilization is abnormal, leading to a tail delay in CPU response time and lower vehicle driving safety. If the above factors are resolved, the effect of improving vehicle driving safety can be achieved. To achieve this effect, this disclosure, firstly, for each segmented historical data group in the aforementioned segmented historical data group set, performs the following determination steps: First, determine the first confidence parameter and the second confidence parameter of each segmented historical data included in the aforementioned segmented historical data group. Therefore, the mean and standard deviation of each segment of historical data can be determined. Second, based on the first and second confidence parameters, an initial confidence interval corresponding to the segmented historical data group is generated. This allows for the generation of initial confidence intervals. Third, the skewness and kurtosis values ​​of the segmented historical data group are determined; based on the skewness value, the interval offset direction corresponding to the segmented historical data group is determined. This allows the offset direction of the interval to be determined by the skewness value, providing data support for subsequent correction. Fourth, based on the skewness value and the interval offset direction, a first correction process is performed on the initial confidence interval to generate a first confidence interval; based on the kurtosis value, a correction width value corresponding to the first confidence interval is generated; based on the correction width value, a second correction process is performed on the first confidence interval to generate a second confidence interval as the confidence interval. This allows for the correction of the confidence interval using the skewness and kurtosis values. In conjunction with "step 106," in response to the processor utilization rate at the current time point being greater than or equal to the corresponding safe utilization baseline, a process interruption operation is performed on at least one process running on the target processor. This avoids deviations in the confidence interval due to data fluctuations, thereby interrupting processes in the processor, preventing tail delays, and improving vehicle driving safety.

[0057] Step 105: For each determined confidence interval, execute the interval merging algorithm to generate at least one merged confidence interval as a set of utilization safety baselines.

[0058] In some embodiments, the aforementioned execution entity may perform an interval merging algorithm on each determined confidence interval to generate at least one merged confidence interval as a set of utilization safety baselines.

[0059] In practice, the following steps can be used to execute an interval merging algorithm on each determined confidence interval to generate at least one merged confidence interval as a safe baseline set for utilization:

[0060] The first step is to sort the determined confidence intervals to generate a confidence interval sequence. Here, the confidence intervals can be sorted sequentially according to time.

[0061] The second step involves performing the following processing steps on every two adjacent confidence intervals in the above confidence interval sequence:

[0062] The first processing step is to determine the interval parameter set for the two adjacent confidence intervals. The interval parameter set includes one of the following: the difference between the upper and lower limits of the interval. The difference between the upper and lower limits can be the difference between the upper limits of two adjacent confidence intervals. The difference between the lower and lower limits of the intervals can be the difference between the lower limits of two adjacent confidence intervals.

[0063] The second processing step involves merging the two adjacent confidence intervals in response to the condition that the upper limit difference of the aforementioned intervals is less than or equal to a first preset upper limit difference. The first preset upper limit difference can be a pre-defined upper limit difference of the intervals. For example, the first preset upper limit difference can be 0.5 hours.

[0064] The third processing step involves merging the two adjacent confidence intervals in response to the condition that the upper limit difference of the interval is less than or equal to a second preset upper limit difference, is greater than the first preset upper limit difference, and the lower limit difference of the interval is less than or equal to a preset lower limit difference. The second preset upper limit difference can be a pre-set upper limit difference that is greater than the first preset upper limit difference. For example, the second preset upper limit difference could be 0.75 hours.

[0065] The third step is to perform a merge traversal on the merged confidence interval sequence to generate a merge traversal result. This merge traversal can be achieved by performing the above processing steps on the merged confidence interval sequence again.

[0066] The fourth step is to determine the number of confidence intervals included in the merged confidence interval sequence in response to the above merged traversal result indicating that merging is not possible. This number is used as the interval count.

[0067] Fifth, in response to the fact that the number of intervals is less than the preset number of intervals, the merged confidence interval sequence is rolled back to generate a rolled-back confidence interval sequence as a utilization safety baseline set. The preset number of intervals can be a pre-defined number of confidence intervals included in the confidence interval sequence. The rollback process can be to roll back the confidence interval sequence to a point before the last processing step.

[0068] Step 106: In response to the processor utilization rate at the current time point being greater than or equal to the corresponding utilization safety baseline, perform a process interruption operation on at least one process running on the target processor.

[0069] In some embodiments, the execution entity may perform a process interruption operation on at least one process running on the target processor in response to the processor utilization rate at the current time being greater than or equal to the corresponding utilization safety baseline.

[0070] In addressing the technical problems mentioned in the background section, and considering the specific application scenario where a process tree, due to a vulnerability or design flaw, consumes processor resources and cannot be interrupted by a termination command, the following technical problem arises: Because the process and its child processes indefinitely consume processor resources, the processor's Out of Memory (OOM) mechanism is triggered, leading to random interruptions of other processes and system crashes. Given the following requirements for this application scenario—avoiding memory overflow—we have decided to adopt the following solution:

[0071] In some optional implementations of certain embodiments, the aforementioned execution entity may perform a process interruption operation on at least one process running on the target processor in response to the processor utilization rate at the current time being greater than or equal to the corresponding safe utilization baseline:

[0072] The first step is to obtain the processor utilization rate at the current time point.

[0073] The second step is to determine at least one safe utilization baseline corresponding to the current time point, and select a safe utilization baseline that meets preset conditions from the at least one safe utilization baseline as the target safe utilization baseline. The preset conditions can be the safe utilization baseline with the smallest corresponding time unit. For example, given that the safe utilization baselines corresponding to the processor utilization are 11:00 to 12:00 and Monday to Tuesday, the safe utilization baseline corresponding to 11:00 to 12:00 is selected as the target safe utilization baseline.

[0074] The third step is to identify the target processor as an abnormal processor in response to the processor utilization rate being greater than or equal to the target utilization safety baseline.

[0075] The fourth step is to determine, based on the preset sampling period, whether the processor utilization of the above-mentioned abnormal processors meets the preset utilization conditions within the preset number of periods.

[0076] Fifth, in response to the abnormal processor's processor utilization meeting the preset utilization condition within a preset number of cycles, the processes running by the abnormal processor are sorted in descending order according to their corresponding resource usage to generate a process sequence. The preset utilization condition can be that the processor utilization corresponding to the abnormal processor is greater than or equal to a safe utilization baseline within the preset number of cycles. The preset number of cycles can be a pre-defined number of time periods. The time period can be 1 minute.

[0077] Step 6: Based on the above process sequence, select at least one process from the sequence as the interrupt process to obtain the sequence of processes to be interrupted. In practice, a predetermined number of non-core processes can be selected from the above process sequence as the sequence of processes to be interrupted. The non-core processes can be processes that support the processor or the system hosted by the processor. As an example, the non-core processes can be processes other than kernel threads and virtualization drivers.

[0078] Step 7: Interrupt each process in the interruptible process sequence and its corresponding child process in turn, and monitor the processor utilization of the abnormal processor in real time.

[0079] Step 8: In response to the processor utilization being less than or equal to the target security baseline, stop the remaining uninterrupted processes on the terminal.

[0080] Steps one through eight above, as an inventive point of this disclosure, solve the technical problem: "When a process and its child processes infinitely consume processor resources, the processor's OOM (Out of Memory Killer) mechanism is triggered, leading to random interruption of other processes and causing system crashes." The cause of the system crash is as follows: When a process and its child processes infinitely consume processor resources, the processor's OOM mechanism is triggered, leading to random interruption of other processes and causing system crashes. Solving the above factors can prevent system crashes. To achieve this effect, this disclosure first obtains the processor utilization rate at the current time point. This allows the determination of the processor utilization rate at the current time. Second, it determines at least one safe utilization baseline at the current time point, and selects a safe utilization baseline that meets preset conditions from the at least one safe utilization baseline as the target safe utilization baseline. This allows the selection of the closest safe baseline. Third, in response to the processor utilization rate being greater than or equal to the target utilization safety baseline, the target processor is identified as an abnormal processor. Based on a preset sampling period, it is determined whether the processor utilization rate of the abnormal processor meets a preset utilization condition within a preset number of periods. In response to the abnormal processor's processor utilization rate meeting the preset utilization condition within a preset number of periods, the processes running on the abnormal processor are sorted in descending order according to their corresponding resource usage to generate a process sequence. Thus, processes can be sorted according to resource utilization. Fourth, based on the process sequence, at least one process is selected as an interrupt process to obtain a sequence of processes to be interrupted. Thus, non-core processes that can be terminated can be selected. Fifth, each process in the sequence of processes to be interrupted, as well as its corresponding child processes, are interrupted sequentially, and the processor utilization rate of the abnormal processor is monitored in real time. In response to the processor utilization rate being less than or equal to the target safety baseline, the remaining processes to be interrupted are stopped. Thus, each process and its child processes can be forcibly interrupted, thereby promptly preventing system crashes caused by abnormal processes.

[0081] The above embodiments of this disclosure have the following beneficial effects: The CPU-based process interruption method of some embodiments of this disclosure avoids data loss and prevents the processes carried by the processor from failing to run, thus reducing the waste of processor resources. Specifically, the reasons for data loss, the inability of the carried processes to run normally, or even processor failure are: when judging whether the processor is abnormal by setting a fixed threshold, the instantaneous fluctuation of the processor utilization may lead to the interruption of important processes, resulting in data loss. Furthermore, judging by a fixed threshold has a high false positive rate, making it impossible to detect abnormal processors in time, causing the processes carried by the processor to fail to run normally or even causing the processor to fail. Based on this, the CPU-based process interruption method of some embodiments of this disclosure firstly, in response to detecting that the utilization of the target processor is greater than or equal to a preset utilization rate, obtains the historical running data sequence of the target processor. Thus, the historical running data of the processor can be obtained. Secondly, the historical running data sequence is preprocessed to generate a preprocessed historical running data sequence. Thus, by denoising and processing outliers in the historical data, data support is provided for subsequent data processing. Then, the preprocessed historical running data in the above-mentioned preprocessed historical running data sequence is segmented to generate a segmented historical data set. This allows the historical running data to be split according to time segments. Next, for each segmented historical data set, a confidence interval is determined; for each determined confidence interval, an interval merging algorithm is executed to generate at least one merged confidence interval, serving as a utilization safety baseline set. This allows the processor utilization safety baseline for different time periods to be determined. Finally, in response to the processor utilization at the current time point being greater than or equal to the corresponding utilization safety baseline, at least one process running on the target processor is interrupted. Thus, when the processor utilization exceeds the safety baseline, the processor is identified as an abnormal processor, and the processes on the processor are interrupted to protect the processor, preventing overheating that could cause the processes running on the processor to fail, and preventing the processor from becoming unusable due to overheating.

[0082] Further reference Figure 2 As an implementation of the methods shown in the above figures, this disclosure provides some embodiments of a process interruption device based on a central processing unit. These device embodiments are similar to... Figure 1 Corresponding to the method embodiments shown, this central processing unit-based process interruption device can be specifically applied to various electronic devices.

[0083] like Figure 2As shown, some embodiments of the central processing unit-based process interruption device 200 include: an acquisition unit 201, a preprocessing unit 202, a segmentation unit 203, a determination unit 204, an execution unit 205, and a process interruption unit 206. The acquisition unit 201 is configured to acquire the historical running data sequence of the target processor in response to detecting that the utilization rate of the target processor is greater than or equal to a preset utilization rate; the preprocessing unit 202 is configured to perform data preprocessing on the historical running data sequence to generate a preprocessed historical running data sequence; the segmentation unit 203 is configured to segment each preprocessed historical running data in the preprocessed historical running data sequence to generate a segmented historical data set; the determination unit 204 is configured to determine the confidence interval corresponding to each segmented historical data set in the segmented historical data set; the execution unit 205 is configured to execute an interval merging algorithm for each determined confidence interval to generate at least one merged confidence interval as a utilization safety baseline set; and the process interruption unit 206 is configured to perform a process interruption operation on at least one process running on the target processor in response to the processor utilization rate at the current time point being greater than or equal to the corresponding utilization safety baseline.

[0084] It is understandable that the units described in the central processing unit-based process interrupt device 200 and the reference Figure 1 The steps in the described method correspond to each other. Therefore, the operations, features, and beneficial effects described above for the method also apply to the central processing unit-based process interrupt device 200 and the units contained therein, and will not be repeated here.

[0085] The following is for reference. Figure 3 This document illustrates a structural schematic of an electronic device 300 suitable for implementing some embodiments of the present disclosure. The electronic devices in some embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 3 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments of this disclosure.

[0086] like Figure 3As shown, the electronic device 300 may include a processing unit 301 (e.g., a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 302 or a program loaded from a storage device 308 into a random access memory (RAM) 303. The RAM 303 also stores various programs and data required for the operation of the electronic device 300. The processing unit 301, ROM 302, and RAM 303 are interconnected via a bus 304. An input / output (I / O) interface 305 is also connected to the bus 304.

[0087] Typically, the following devices can be connected to I / O interface 305: input devices 306 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 307 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 308 including, for example, magnetic tapes, hard disks, etc.; and communication devices 309. Communication device 309 allows electronic device 300 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 3 An electronic device 300 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively. Figure 3 Each box shown can represent a device or multiple devices as needed.

[0088] In particular, according to some embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, some embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication device 309, or installed from storage device 308, or installed from ROM 302. When the computer program is executed by processing device 301, it performs the functions defined in the methods of some embodiments of this disclosure.

[0089] It should be noted that, in some embodiments of this disclosure, the computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In some embodiments of this disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In some embodiments of this disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0090] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol) and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.

[0091] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device. The aforementioned computer-readable medium carries one or more programs that, when executed by the electronic device, cause the electronic device to: in response to detecting that the utilization rate of the target processor is greater than or equal to a preset utilization rate, acquire a historical running data sequence of the target processor; preprocess the historical running data sequence to generate a preprocessed historical running data sequence; segment each preprocessed historical running data in the preprocessed historical running data sequence to generate a segmented historical data set; for each segmented historical data set in the segmented historical data set, determine a confidence interval corresponding to the segmented historical data set; for each determined confidence interval, execute an interval merging algorithm to generate at least one merged confidence interval as a utilization safety baseline set; and in response to the processor utilization rate at the current time point being greater than or equal to the corresponding utilization safety baseline, perform a process interruption operation on at least one process running on the target processor.

[0092] Computer program code for performing operations of some embodiments of this disclosure can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0093] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0094] The units described in some embodiments of this disclosure can be implemented in software or hardware. The described units can also be located in a processor; for example, a processor can be described as including an acquisition unit, a preprocessing unit, a segmentation unit, a determination unit, an execution unit, and a process interruption unit. The names of these units do not necessarily limit the unit itself; for example, the acquisition unit can also be described as "a unit that acquires a historical running data sequence of the target processor in response to detecting that the utilization rate of the target processor is greater than or equal to a preset utilization rate."

[0095] The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), and so on.

[0096] The above description is merely a selection of preferred embodiments of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in the embodiments of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in the embodiments of this disclosure.

Claims

1. A process interruption method based on a central processing unit, characterized in that, include: In response to detecting that the utilization rate of the target processor is greater than or equal to a preset utilization rate, the historical operating data sequence of the target processor is obtained; The historical operation data sequence is preprocessed to generate a preprocessed historical operation data sequence; Each preprocessed historical running data in the preprocessed historical running data sequence is segmented to generate a segmented historical data set; For each segmented historical data group in the segmented historical data group set, determine the confidence interval corresponding to the segmented historical data group; For each determined confidence interval, an interval merging algorithm is executed to generate at least one merged confidence interval as a set of utilization safety baselines; Specifically, the step of performing an interval merging algorithm for each determined confidence interval to generate at least one merged confidence interval as a utilization safety baseline set includes: The determined confidence intervals are sorted to generate a confidence interval sequence; For every two adjacent confidence intervals in the confidence interval sequence, the following processing steps are performed: Determine the interval parameter set for the two adjacent confidence intervals, wherein the interval parameter in the interval parameter set is one of the following: upper limit difference of interval, lower limit difference of interval; In response to the upper limit difference of the interval being less than or equal to the first preset upper limit difference, the two adjacent confidence intervals are merged. In response to the interval upper limit difference being less than or equal to the second preset upper limit difference, greater than the first preset upper limit difference, and the interval lower limit difference being less than or equal to the preset lower limit difference, a merging operation is performed on the two adjacent confidence intervals; The merged confidence interval sequence is merged and iterated to generate the merged traversal result; In response to the merge traversal result indicating that merging is not possible, the number of confidence intervals included in the merged confidence interval sequence is determined as the number of intervals; In response to the number of intervals being less than the preset number of intervals, the merged confidence interval sequence is backtracked to generate a backtracked confidence interval sequence as a utilization safety baseline set. In response to the processor utilization rate at the current time being greater than or equal to the corresponding utilization safety baseline, a process interruption operation is performed on at least one process running on the target processor.

2. The method according to claim 1, characterized in that, The step of preprocessing the historical running data sequence to generate a preprocessed historical running data sequence includes: Data cleaning processing is performed on each historical operation data in the historical operation data sequence to generate a cleaned operation data sequence; Missing values ​​are filled in each cleaning operation data in the cleaning operation data sequence to generate a filled operation data sequence; The padded running data sequence is smoothed to generate a smoothed padded running data sequence as a preprocessed historical running data sequence.

3. The method according to claim 1, characterized in that, The step of segmenting each preprocessed historical data in the preprocessed historical data sequence to generate a segmented historical data set includes: For each preprocessed historical running data in the preprocessed historical running data sequence, the preprocessed historical running data is segmented to generate segmented running data groups; The generated segmented running data groups are reconstructed to generate a reconstructed running data group set; Based on the reconstructed runtime data set, the following merging steps are performed: Based on the preset algorithm, the utilization distribution values ​​of the first two reconstructed running data groups in the reconstructed running data group set are determined respectively. In response to the difference between the two determined utilization distribution values ​​being less than or equal to a preset threshold, the first two reconstructed running data groups are merged to generate a merged data group. Based on the merged data set, the reconstructed running data set is updated to generate an updated running data set; In response to the fact that the number of update running data groups included in the update running data set is less than or equal to a preset number, the update running data set is determined as a segmented historical data set.

4. The method according to claim 3, characterized in that, The method further includes: If the number of updated running data groups included in the updated running data set is greater than the preset number, the updated running data set is used as the reconstructed running data set, and the merging step is performed again.

5. The method according to claim 3, characterized in that, After determining the utilization distribution values ​​of the first two reconstructed running data groups in the reconstructed running data group set based on the preset algorithm, the merging step further includes: If the difference between the two determined utilization distribution values ​​is greater than the preset threshold, the reconstructed running data set is determined as the updated running data set.

6. A process interruption device based on a central processing unit, characterized in that, include: The acquisition unit is configured to acquire the historical operating data sequence of the target processor in response to detecting that the utilization rate of the target processor is greater than or equal to a preset utilization rate; A preprocessing unit is configured to preprocess the historical running data sequence to generate a preprocessed historical running data sequence. The segmentation unit is configured to segment each piece of preprocessed historical running data in the preprocessed historical running data sequence to generate a segmented historical data set. The determining unit is configured to determine the confidence interval corresponding to each segmented historical data group in the segmented historical data group set. An execution unit is configured to execute an interval merging algorithm for each determined confidence interval to generate at least one merged confidence interval as a utilization safety baseline set; the execution unit is further configured to: The determined confidence intervals are sorted to generate a confidence interval sequence; For every two adjacent confidence intervals in the confidence interval sequence, the following processing steps are performed: Determine the interval parameter set for the two adjacent confidence intervals, wherein the interval parameter in the interval parameter set is one of the following: upper limit difference of interval, lower limit difference of interval; In response to the upper limit difference of the interval being less than or equal to the first preset upper limit difference, the two adjacent confidence intervals are merged. In response to the interval upper limit difference being less than or equal to the second preset upper limit difference, greater than the first preset upper limit difference, and the interval lower limit difference being less than or equal to the preset lower limit difference, a merging operation is performed on the two adjacent confidence intervals; The merged confidence interval sequence is merged and iterated to generate the merged traversal result; In response to the merge traversal result indicating that merging is not possible, the number of confidence intervals included in the merged confidence interval sequence is determined as the number of intervals; In response to the number of intervals being less than the preset number of intervals, the merged confidence interval sequence is backtracked to generate a backtracked confidence interval sequence as a utilization safety baseline set. The process interruption unit is configured to perform a process interruption operation on at least one process running on the target processor in response to the processor utilization rate at the current time being greater than or equal to the corresponding utilization safety baseline.

7. An electronic device, characterized in that, include: One or more processors; A storage device on which one or more programs are stored; When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any one of claims 1 to 5.

8. A computer-readable medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 5.

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