Verification system of FSMC multi-memory interface based on UVM

Abstract

The invention discloses a verification system of an FSMC multi-memory interface based on a UVM, and belongs to the technical field of chip verification. The verification system of the FSMC multi-memory interface based on the UVM comprises a test layer, a simulation instruction definition layer, an AHB bus interface component, an assertion inspection component and an external memory interface component. The problems that in the prior art, a single memory is mainly connected for verification, only a single protocol can be verified, the verification means is limited, and the efficiency and the coverage rate are not high are solved, the transmission type of the AHB is defined in the environment configuration component, therefore, the verification diversity is improved, the verification requirements for verifying different memory interfaces are well met, and the verification efficiency is improved. According to the interface protocol verification method and device, the randomized excitation and self-checking function conforming to the protocol can be generated, the verification comprehensiveness is greatly improved, the pertinence and correctness of the verified module are greatly improved, the verification efficiency is improved, the code cost is reduced, and the accuracy of interface protocol verification is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip verification technical field, specifically to a verification system of FSMC multi-memory interface based on UVM. BACKGROUND

[0002] FSMC as a multi-memory interface controller module is very important in the microcontroller, and the module can realize various memory interface protocols.

[0003] The Chinese patent with publication number CN217360777U discloses a verification circuit for microcontroller FSMC multiplexing function, which comprises a CPU, an external latch chip and an FSMC memory interface, the NADV port between the CPU and the external latch chip is connected through an inverter realized by N-MOS, so as to realize the time-sharing transmission of the data line and the address line of the microcontroller to the FSMC memory, through the verification circuit, the data line and the address line of the microcontroller can be time-sharing transmitted to the FSMC memory, and the time delay is very low, which will not affect the control of the memory.

[0004] The above-mentioned patent mainly connects a single memory for verification in actual use, can only verify a single protocol, and the verification means is limited, the efficiency and the coverage rate are not high, therefore, it does not meet the existing demand, for this, we propose a verification system of FSMC multi-memory interface based on UVM. SUMMARY

[0005] The present application relates to the chip verification technical field, specifically to a verification system of FSMC multi-memory interface based on UVM.

[0006] To achieve the above-mentioned purpose, the present application provides the following technical scheme: a verification system of FSMC multi-memory interface based on UVM, comprising a simulation top layer based on a UVM verification methodology, which is used for initializing the verification system and starting a test case, the simulation top layer comprises: a test layer, which is used for AHB protocol communication with the FSMC to be verified, simulates a real CPU host to initiate access to the external memory to the FSMC according to the test case, and monitors whether the memory protocol timing generated by the FSMC is correct. a simulation instruction definition layer, which is used to define the connection relationship between the FSMC interface and the commercial memory module, and to realize the real external memory read and write operation by adding an option in the simulation instruction to connect a specific external memory; an AHB bus interface component, which is used to drive and detect the interface of the AHB bus; an assertion check component, which is used to make assertion check on the interface signal in the external memory interface component, and to detect whether the timing protocol output by the FSMC is correct; an external memory interface component, which is used to connect the external memory interface of the FSMC to be tested.

[0007] Preferably, the test layer comprises: a test environment configuration, which comprises an AHB configuration and a memory configuration, the AHB configuration is used to select the AHB access parameter and is transmitted to the test case in the test sequence library, and the memory configuration is used to configure the components of the memory required for testing; a register model, which is used to transmit the configuration result to the sequence management component of the AHB host agent layer in the environment layer, to configure the register of the FSMC, and to drive to the AHB bus interface of the FSMC through the stimulus driving component; an environment layer, which is used to configure the environment of the AHB, the type of the external memory and the related test parameters, the reference model is used to simulate the basic function of the FSMC according to the test case, to compare the expected data in the comparison test process with the actually transmitted data, to configure the register of the FSMC, and to store and manage the verification sequence; a test sequence library, which is used to store the test case.

[0008] Preferably, the memory configuration comprises: the AHB access parameter is selected by the AHB configuration in the test environment configuration and is transmitted to the test case in the test sequence library; the configuration result is transmitted to the sequence management component of the AHB host agent layer in the environment layer through the register model; the components of the memory required for testing are configured by the memory configuration in the test environment configuration, which is transmitted to the memory slave agent layer and the reference model in the environment layer, and is driven to the AHB bus interface of the FSMC through the stimulus driving component.

[0009] Preferably, the specific process of the test layer comprises: the memory type used for testing is added by the simulation instruction definition layer; the FSMC and the instruction defined memory are connected, and the verification system of the multi-memory interface of the FSMC is initialized; The AHB configuration selects AHB access parameters and passes them to the test case in the test sequence library, and configures the memory components required for testing; The configuration result is passed to the sequence management component of the AHB host agent layer, the registers of the FSMC are configured, and the AHB bus interface of the FSMC is driven through the stimulus driving component; The reference model simulates the basic functions of the FSMC according to the test case, compares the expected data in the test process with the actually transmitted data, and if the comparison is successful, the verification passes, the FSMC function is normal, otherwise the verification fails, the FSMC function is abnormal and needs to be checked.

[0010] Preferably, the test result meets the verification requirement, and the FSMC is verified, specifically including: Starting a virtual test sequence, starting the test cases of all memory interface protocols supported by the FSMC in the sequence; According to the test function points of all memory interface protocols supported by the FSMC, the AHB access type and the memory type are determined, and the test data is prepared; The FSMC function is configured by writing in the FSMC register through the AHB host agent layer, the access operation to the external memory is started, and the verification process of the FSMC is completed.

[0011] Preferably, the environment layer comprises: The reference model is used to simulate the basic functions of the FSMC according to the test case, and will process the signals from the monitoring components in the AHB host agent layer and the memory slave agent layer according to the test environment configuration, and will transmit the processed data to the score board for comparison, the reference model is written based on the functions of the FSMC, and supports multiple memory timing protocols; The score board is used to compare the expected data in the test process with the actually transmitted data; The verification sequence library is used to store and manage the verification sequence; The AHB host agent layer is used to access the registers and memories of the FSMC; The memory slave agent layer is used to simulate the external memory to receive and process the signals of the FSMC.

[0012] Preferably, the AHB host agent layer comprises a register access component and a memory access component, and the memory slave agent layer comprises an external memory access component, and the register access component, the memory access component and the external memory access component all comprise a sequence management component, a stimulus driving component and a detection component, which are used for test sequence transmission, sending and signal detection.

[0013] Preferably, the simulation definition layer comprises `ifdef, `elsif and `endif, which are used to connect different commercial memory interface and external memory interface components, and +define+ is added in the instruction of VCS to select the required memory interface, and the commercial memory module comprises SRAM, PSRAM, NOR flash and NAND flash.

[0014] Preferably, the working process of the simulation definition layer specifically comprises the following steps. According to the functions of the memory interface protocols supported by the FSMC, the function points of different protocols are decomposed, and corresponding configuration data packets are generated; According to the types of the memory interface protocols supported by the FSMC, the test cases and the simulation definition layer are configured, and the corresponding memories are selected for simulation.

[0015] Preferably, one end of the AHB bus interface component is connected with the AHB interface of the FSMC to be tested, the external memory interface of the FSMC to be tested is connected with the external memory interface component, the other end of the AHB bus interface component is connected with the excitation driving component and the monitoring component in the register access component and the memory access component of the AHB master agent layer in the environment layer, and the external memory interface component is connected with the excitation driving component and the monitoring component in the external memory access component of the memory slave agent layer.

[0016] Compared with the prior art, the present application has the following beneficial effects: The present application can compile corresponding functional cases according to different functions of the FSMC, configure the overall test environment, define the transmission type of the AHB in the environment configuration component through the transmission of handles, define the type of the external memory in the memory configuration, thereby improving the diversity of verification, well meeting the verification requirements of different memory interfaces, introducing commercial VIP in the AHB bus component to generate randomized excitation and self-checking functions in accordance with the protocol, greatly improving the comprehensiveness of verification, adding commercial IP in the standard memory component to greatly improve the pertinence and correctness of the verified module, thereby improving the efficiency of verification and reducing the code cost, and improving the accuracy of interface protocol verification. BRIEF DESCRIPTION OF DRAWINGS

[0017] Fig. 1 It is a schematic diagram of the FSMC multi-memory interface verification system based on UVM of the present application; Fig. 2 It is a simulation flowchart of the FSMC multi-memory interface verification system based on UVM of the present application. DETAILED DESCRIPTION

[0018] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments of the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative work are within the protection scope of the present application.

[0019] In order to solve the problems in the prior art that the single memory is connected for verification, only a single protocol can be verified, the verification means is limited, and the efficiency and coverage are not high, please refer to Figs. 1-2 The embodiment provides the following technical solutions: The verification system of the FSMC multi-memory interface based on UVM includes a simulation top layer based on a UVM verification methodology, which is used for initializing the verification system and starting a test case, the simulation top layer includes: A test layer, which is used for communicating with the FSMC to be verified in an AHB protocol, simulating a real CPU host to initiate an access to an external memory to the FSMC according to a test case, and monitoring whether a memory protocol timing generated by the FSMC is correct; A simulation instruction definition layer, which is used for defining a connection relationship of the FSMC interface and a commercial memory module, and connecting a specific external memory by adding an option in the simulation instruction, so as to realize a real external memory read-write operation; An AHB bus interface component, which is used for AHB bus driving excitation and detection interface; An assertion checking component, which is used for making assertion checking on interface signals in the external memory interface component, and detecting whether a timing protocol output by the FSMC is correct; An external memory interface component, which is used for connecting an external memory interface of the FSMC to be tested.

[0020] The test layer includes: A test environment configuration, the test environment configuration includes AHB configuration and memory configuration, the AHB configuration is used for selecting AHB access parameters and transmitting the AHB access parameters to a test case in a test sequence library, and the memory configuration is used for configuring components of a memory required for testing; A register model, which is used for transmitting a configuration result to a sequence management component of an AHB host agent layer in an environment layer, configuring registers of the FSMC, and driving to an AHB bus interface of the FSMC through an excitation driving component; An environment layer is configured to configure the environment of the AHB, the external memory type and the related test parameters, the reference model simulates the basic function of the FSMC according to the test case, compares the expected data in the test process with the actually transmitted data, configures the register of the FSMC, and stores and manages the verification sequence; the test environment configuration includes the memory configuration and the AHB configuration; the memory configuration is used to configure the memory of the test case; and the AHB configuration is used to configure the AHB of the test case A test sequence library is configured to store the test case.

[0021] The environment layer includes: The reference model is configured to simulate the basic function of the FSMC according to the test case, to process the signals from the monitoring components in the AHB host agent layer and the memory slave agent layer according to the test environment configuration, and to transmit the processed data to the score board for comparison, the reference model is written based on the function of the FSMC, and supports multiple memory timing protocols; The score board is configured to compare the expected data in the test process with the actually transmitted data; The verification sequence library is configured to store and manage the verification sequence; The AHB host agent layer is configured to access the register and the memory of the FSMC; The memory slave agent layer is configured to simulate the external memory to receive and process the signals of the FSMC.

[0022] The AHB host agent layer includes the register access component and the memory access component, the memory slave agent layer includes the external memory access component, and the register access component, the memory access component and the external memory access component all include the sequence management component, the stimulus driving component and the detection component, which are used for the transmission, sending and signal detection of the test sequence.

[0023] The simulation definition layer includes `ifdef, `elsif and `endif, which are used to connect different commercial memory interfaces and external memory interface components, and add +define+ in the instructions of the VCS to select the required memory interface, and the commercial memory modules include SRAM, PSRAM, NOR flash and NAND flash.

[0024] One end of the AHB bus interface component is connected with the AHB interface of the FSMC to be tested, the external memory interface of the FSMC to be tested is connected with the external memory interface component, and the other end of the AHB bus interface component is connected with the stimulus driving component and the monitoring component in the register access component and the memory access component of the AHB host agent layer in the environment layer, and the external memory interface component is connected with the stimulus driving component and the monitoring component in the external memory access component of the memory slave agent layer.

[0025] Test layer, comprising specifically: Adding memory type for test by using simulation instruction definition layer; Connecting FSMC and instruction defined memory, and initializing verification system of FSMC multi-memory interface; Selecting AHB access parameters by using AHB configuration, and transferring to test case of test sequence library, and configuring memory components required for test; Transferring configuration result to sequence management component of AHB host agent layer, configuring registers of FSMC, and driving to AHB bus interface of FSMC through stimulus driving component; Referencing model simulating basic functions of FSMC according to test case, comparing expected data in test process with actually transmitted data, if comparison is successful, verification passes, FSMC functions normally, otherwise, verification fails, FSMC functions abnormally, and checking is required.

[0026] Memory configuration, comprising specifically: Selecting AHB access parameters by using AHB configuration in test environment configuration, and transferring to test case of test sequence library; Transferring configuration result to sequence management component of AHB host agent layer in environment layer through register model; Transferring memory configuration in test environment configuration to memory slave agent layer and reference model in environment layer through stimulus driving component driven to AHB bus interface of FSMC, and configuring components of memory required for test.

[0027] Working process of simulation definition layer, comprising specifically: Decomposing function points of different protocols for test according to functions of memory interface protocols supported by FSMC, and generating corresponding configuration data packet; Configuring test case and simulation definition layer according to memory interface protocol types supported by FSMC, and selecting corresponding memory for simulation.

[0028] Verifying FSMC when test result meets verification requirement, comprising specifically: Starting a virtual test sequence, and starting test cases of all memory interface protocols supported by FSMC in the sequence; Determining AHB access type and memory type according to test function points of all memory interface protocols supported by FSMC, and preparing test data; Configuring FSMC functions by writing in registers of FSMC through AHB host agent layer, starting access operation to external memory, and completing verification process of FSMC.

[0029] Working principle: in the use of the FSMC multi-memory interface verification system based on UVM of the application, reference Fig. 1 , specifically includes: In the test layer based on UVM and the simulation instruction definition layer containing commercial memory module are added respectively, the specific memory module is selected by adding simulation instruction definition, the module under test is connected, and the AHB and memory related parameters in the test case of the sequence library in the test layer are configured, which is used for configuring the components of the environment platform, preparing the corresponding test data to meet the test requirements; The AHB interface of the FSMC under test and the one end of the AHB bus interface component are connected, and the external memory interface of the FSMC under test and the external memory interface component are connected; The other end of the AHB bus interface component is connected with the stimulus driving component and the monitoring component in the register access component and the memory access component of the AHB host agent layer respectively, and the external memory interface component is connected with the stimulus driving component and the monitoring component in the external memory access component of the memory slave agent layer; The `ifdef, `elsif and `endif are added in the simulation definition layer, the different commercial memory interfaces and external memory interface components are connected, and the +define+ is added in the instruction of VCS to select the required memory interface; The AHB configuration in the test environment configuration is used to select the AHB access parameters, which are transmitted to the test case of the test sequence library, the configuration results are transmitted to the sequence management component of the AHB host agent layer through the register model, and are driven to the AHB bus interface of the FSMC through the stimulus driving component, and the memory configuration in the test environment configuration is transmitted to the memory slave agent layer and the reference model in the environment layer, so as to configure the components of the required memory for testing; The reference model processes the signals from the monitoring components in the AHB host agent layer and the memory slave agent layer according to the test environment configuration, and transmits the processed data to the score board for comparison, the AHB access data and the data through the reference model are compared in the score board, and the simulation information is collected and printed; The sequence management components in the AHB host agent layer and the memory slave agent layer transmit the received test sequence to the stimulus driving component, and complete the driving and feedback of the stimulus.

[0030] The simulation flow is described, as shown in Fig. 2 According to the functions of the memory interface protocols supported by FSMC, the function points of different protocols are decomposed, and the corresponding configuration data packets are generated; ​Configure the test cases and simulation definition layer according to the memory interface protocol types supported by FSMC, and select the corresponding memory for simulation; Initialize the FSMC verification system with the required test configuration, initialize the FSMC verification system through configuration, connect the components of the verification system, and start the configuration data package corresponding to the test case; After connecting to the components of the verification system, start the configuration data package corresponding to the test case and perform verification testing on the FSMC under test; Start a virtual test sequence, which includes test sequences for different memory interface protocol function points, thereby starting test cases for all memory interface protocols supported by FSMC.

[0031] Determine the AHB access type and memory type based on the test function points of all memory interface protocols supported by FSMC, and prepare the test data; The FSMC function is configured by writing to the FSMC register through the AHB host agent layer, enabling access to external memory and completing the FSMC verification process.

[0032] In summary, the UVM-based FSMC multi-memory interface verification system of this invention, based on different functions of FSMC, writes corresponding functional cases and configures the overall test environment. Through handle transfer, it defines the AHB transfer type in the environment configuration component and the external memory type in the memory configuration, thereby improving the diversity of verification and well meeting the verification needs of different memory interfaces. By introducing commercial VIPs into the AHB bus component, it can generate protocol-compliant randomized stimuli and self-checking functions, greatly improving the comprehensiveness of verification. By adding commercial IP to the standard memory component, it greatly improves the relevance and correctness of the verified modules. Compared with traditional FSMC verification technology, it designs and builds a highly automated and reusable verification environment and a complete verification process. By modifying the control parameters of the verification platform's bus access to external memory, verification can be performed directly, improving verification efficiency and reducing code costs. It can provide a verification environment for multiple memory interface protocols, improving the completeness of FSMC verification, and can also connect to commercial memory modules to improve the accuracy of interface protocol verification.

[0033] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0034] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention.

Claims

1. A verification system for a UVM-based FSMC multi-memory interface, comprising a simulation top-level layer based on the UVM verification methodology for initializing the verification system and initiating test cases, characterized in that, The simulation top layer includes: The test layer is used to communicate with the FSMC to be verified via the AHB protocol. Based on the test cases, it simulates the real CPU host to initiate access to external memory to the FSMC and monitors whether the memory protocol timing generated by the FSMC is correct. The simulation instruction definition layer is used to define the connection relationship between the FSMC interface and the commercial memory module, and to connect to specific external memory by adding options to the simulation instructions to realize real external memory read and write operations. AHB bus interface component, used for AHB bus driver excitation and detection interface; The assertion checking component is used to perform assertion checks on the interface signals in the external memory interface component and to check whether the timing protocol output by the FSMC is correct. External memory interface component, used to connect to the external memory interface of the FSMC under test.

2. The verification system for the UVM-based FSMC multi-memory interface according to claim 1, characterized in that: The test layer includes: Test environment configuration includes AHB configuration and memory configuration. AHB configuration is used to select AHB access parameters and pass them to the test cases in the test sequence library. Memory configuration is used to configure the memory components required for testing. The register model is used to pass the configuration results to the sequence management component of the AHB host agent layer in the environment layer, configure the registers of the FSMC, and drive them to the AHB bus interface of the FSMC through the excitation driver component. The environment layer is used to configure the AHB environment, external memory type, and related test parameters. The reference model simulates the basic functions of the FSMC based on the test cases, compares the expected data with the actual transmitted data during the test, configures the FSMC registers, and stores and manages the verification sequence. A test sequence library for storing test cases.

3. The verification system for the UVM-based FSMC multi-memory interface according to claim 2, characterized in that: The memory configuration includes: Select the AHB access parameters using the AHB configuration in the test environment configuration and pass them to the test cases in the test sequence library; The configuration results are passed to the sequence management component of the AHB host agent layer in the environment layer via a register model. The excitation driver component drives the AHB bus interface of the FSMC, and the memory configuration in the test environment configuration is passed to the memory slave agent layer and reference model in the environment layer to configure the memory components required for the test.

4. The verification system for the UVM-based FSMC multi-memory interface according to claim 1, characterized in that: The specific process of the test layer includes: Add the memory type used for testing using the simulation instruction definition layer; A verification system that connects the FSMC and the instruction-defined memory, and initializes the FSMC multi-memory interface; The AHB configuration selects the AHB access parameters and passes them to the test cases in the test sequence library, and configures the memory components required for the test. The configuration results are passed to the sequence management component of the AHB host agent layer to configure the FSMC registers and drive them to the AHB bus interface of the FSMC through the excitation driver component. The reference model simulates the basic functions of FSMC based on test cases. It compares the expected data with the actual transmitted data during the test. If the comparison is successful, the verification is passed and the FSMC function is normal. Otherwise, the verification fails and the FSMC function is abnormal, requiring investigation.

5. The verification system for the UVM-based FSMC multi-memory interface according to claim 4, characterized in that: If the test results meet the verification requirements, the FSMC will be verified, specifically including: Start a virtual test sequence, in which test cases for all memory interface protocols supported by FSMC are launched; Determine the AHB access type and memory type based on the test function points of all memory interface protocols supported by FSMC, and prepare the test data; The FSMC function is configured by writing to the FSMC register through the AHB host agent layer, enabling access to external memory and completing the FSMC verification process.

6. The verification system for the UVM-based FSMC multi-memory interface according to claim 1, characterized in that: The environment layer includes: The reference model is used to simulate the basic functions of FSMC according to test cases. It will process signals from monitoring components in the AHB host agent layer and memory slave agent layer according to the test environment configuration, and transmit the processed data to the scoring board for comparison. The reference model is written based on the functions of FSMC and supports multiple memory timing protocols. A scoreboard is used to compare the expected data with the actual data transmitted during the test. A verification sequence library for storing and managing verification sequences; The AHB host proxy layer is used for host access to FSMC registers and memory; The memory slave agent layer is used to simulate external memory to receive and process signals from the FSMC.

7. The verification system for the UVM-based FSMC multi-memory interface according to claim 6, characterized in that: The AHB host agent layer includes a register access component and a memory access component, and the memory slave agent layer includes an external memory access component. The register access component, memory access component, and external memory access component all include a sequence management component, a stimulus driving component, and a detection component, which are used for the transmission, sending, and signal detection of test sequences.

8. The verification system for the UVM-based FSMC multi-memory interface according to claim 1, characterized in that: The simulation definition layer includes `ifdef`, `elsif`, and `endif`, which are used to connect different commercial memory interfaces and external memory interface components. The +define+ instruction in VCS is added to select the required memory interface. Commercial memory modules include SRAM, PSRAM, NOR flash, and NAND flash.

9. The verification system for the UVM-based FSMC multi-memory interface according to claim 8, characterized in that: The working process of the simulation definition layer specifically includes: Based on the functionality of the memory interface protocols supported by FSMC, the functional points of different protocols are broken down for testing, and corresponding configuration data packets are generated. Configure the test cases and simulation definition layer according to the memory interface protocol types supported by FSMC, and select the corresponding memory for simulation.

10. The verification system for the UVM-based FSMC multi-memory interface according to claim 1, characterized in that: One end of the AHB bus interface component is connected to the AHB interface of the FSMC under test. The external memory interface of the FSMC under test is connected to the external memory interface component. The other end of the AHB bus interface component is connected to the register access component and the excitation drive component and the monitoring component in the memory access component of the AHB host agent layer in the environment layer, respectively. The external memory interface component is connected to the excitation drive component and the monitoring component in the external memory access component of the memory slave agent layer.

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